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Copyright 1999, Texas Instruments Incorporated POST OFFICE 655303
Top Searches for this datasheetCD54/74AC540, -541, CD54/74ACT540, -541 octal buffer/line drivers ADVANCED CMOS technology. CD54/74AC/ACT540 inverting 3-state buffers having active-LOW output enables. CD54/74AC/ACT541 non-inverting 3-state buffers having active-LOW output enables. CD74AC540, -541, CD74ACT540, -541 supplied 20-lead dual-in-line plastic packages suffix) 20-lead dual-in-line small-outline plastic packages suffix). Both package types operable over following temperature ranges: Industrial (-40 +85°C) Extended Industrial/Military (-55 +125°C). CD54AC540, -541, CD54ACT540, -541, available chip form suffix), operable over +125°C temperature range. Copyright 1999, Texas Instruments Incorporated POST OFFICE 655303 DALLAS, TEXAS 75265 MAXIMUM RATINGS, Absolute-Maximum Values: SUPPLY-VOLTAGE (VCC) -0.5 INPUT DIODE CURRENT, (for -0.5 OUTPUT DIODE CURRENT, (for -0.5 OUTPUT SOURCE SINK CURRENT Output Pin, (for -0.5 GROUND CURRENT (ICC IGND) ±100 PACKAGE THERMAL IMPEDANCE, (see Note package 69°C/W package 58°C/W STORAGE TEMPERATURE (Tstg) +150°C LEAD TEMPERATURE (DURING SOLDERING): distance 1/16 1/32 (1.59 0.79 from case maximum +265°C Unit inserted into board min. thickness 1/16 (1.59 with solder contacting lead tips only +300°C outputs device: each additional output. NOTE package thermal impedance calculated accordance with JESD POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 655303 DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device CD54AC541F3A CD54ACT540F3A CD54ACT541F3A CD74AC540M CD74AC541E CD74AC541M CD74AC541M96 CD74AC541SM CD74AC541SM96 CD74ACT540E CD74ACT540M CD74ACT540M96 CD74ACT541E CD74ACT541M CD74ACT541M96 CD74ACT541SM CD74ACT541SM96 Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE Package Type CDIP CDIP CDIP SOIC PDIP SOIC SOIC SSOP SSOP PDIP SOIC SOIC PDIP SOIC SOIC SSOP SSOP Package Drawing Pins Package Plan 2000 2000 2000 2000 2000 None None None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) None Pb-Free (RoHS) Lead/Ball Finish Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call NIPDAU Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Call Level-2-260C-1 YEAR/ Level-1-235C-UNLIM marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device. Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight. MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that Addendum-Page PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis. Addendum-Page IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. 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