Military Temperature Range -55°C 125°C 100-ns 80-ns Instruction C
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
Military Temperature Range
-55°C 125°C 100-ns 80-ns Instruction Cycle Times Words Programmable On-Chip Data Words On-Chip Program 128K Words Data/Program Space Input Output Channels 16-Bit Parallel Interface Directly Accessible External Data Memory Space Global Data Memory Interface 16-Bit Instruction Data Words 16-Bit Multiplier With 32-Bit Product 32-Bit Accumulator Single-Cycle Multiply/Accumulate Instructions 16-Bit Scaling Shifter Manipulation Logical Instructions Instruction Support Floating-Point Operations, Adaptive Filtering, Extended-Precision Arithmetic Block Moves Data/Program Management Repeat Instructions Efficient Program Space Eight Auxiliary Registers Dedicated Arithmetic Unit Indirect Addressing Serial Port Direct Code Interface Synchronization Input Synchronous Multiprocessor Configurations Wait States Communication Slow-Off-Chip Memories/Peripherals On-Chip Timer Control Operations Three External Maskable User Interrupts Input Polled Software Branch Instruction 1.6-µm CMOS Technology Programmable Output Signaling External Devices
Single Supply On-Chip Clock Generator Packaging:
68-Pin Leaded Ceramic Chip Carrier Suffix) 68-Pin Ceramic Grid Array Suffix) 68-Pin Leadless Ceramic Chip Carrier Suffix)
68-Pin Packages (Top View)
READY CLKR CLKX IACK CLKOUT1 CLKOUT2 HOLDA CLKIN STRB SYNC INT0 INT1 INT2
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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68-Pin Package (Top View)
Copyright 2001, Texas Instruments Incorporated
products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
description
This data sheet provides design documentation SMJ320C25 SMJ320C25-50 digital signal processor (DSP) devices SMJ320 family VLSI digital signal processors peripherals. SMJ320 family supports wide range digital signal processing applications such tactical communications, guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, other computation-intensive applications. Differences between SMJ320C25 SMJ320C25-50 specifically identified, following paragraph parameter tables pages through this data sheet. When specifically differentiated, term SMJ320C25 used describe both devices. SMJ320C25 100-ns instruction cycle time. SMJ320C25-50 80-ns instruction cycle time. With these fast instruction cycle times their innovative memory configurations, these devices perform operations necessary many real-time digital signal processing algorithms. Since most instructions require only cycle, SMJ320C25 capable executing 12.5 million instructions second. On-chip data 16-bit words, on-chip program words, direct addressing words external data memory space words external program memory space, multiprocessor interface features sharing global memory minimize unnecessary data transfers take full advantage capabilities instruction set. Table PGA/CLCC/LCCC Assignments
FUNCTION K1/26 K2/28 L3/29 K3/30 L4/31 K4/32 L5/33 K5/34 K6/36 L7/37 K7/38 L8/39 FUNCTION CLKOUT1 CLKOUT2 CLKR CLKX K8/40 L9/41 K9/42 L10/43 B7/68 G11/50 C11/58 D10/57 B9/64 A9/63 F1/18 E2/17 FUNCTION E1/16 D2/15 D1/14 C2/13 C1/12 B2/11 A2/9 B3/8 A3/7 B4/6 A4/5 85/4 FUNCTION HOLD HOLDA IACK INT0 INT1 A5/3 B6/2 J1/24 K10/45 E11/54 J2/25 F10/53 A7/67 E10/55 B11/60 G1/20 G2/21 FUNCTION INT2 MP/MC READY STRB SYNC H1/22 J11/46 A6/1 C10/59 J10/47 B8/66 A8/65 H11/48 H10/49 F2/19 A10/61 B10/62 FUNCTION X2/CLKIN H2/23 L6/35 B1/10 K11/44 L2/27 D11/56 G10/51 F11/52
SMJ320 trademark Texas Instruments Incorporated.
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Terminal Functions
SIGNALS X2/CLKIN CLKOUT1 CLKOUT2 D15-D0 A15-A0 PS,DS,IS STRB INT2-INT0 MP/MC IACK READY HOLD HOLDA SYNC CLKR CLKX I/O/Z I/O/Z I/O/Z supply pins Ground pins Output from internal oscillator crystal Input internal oscillator from crystal external clock Master clock output (crystal CLKIN frequency/4) second clock output signal 16-bit data (MSB) through (LSB). Multiplexed between program, data, spaces. 16-bit address (MSB) through (LSB) Program, data, space select signals Read write signal Strobe signal Reset input External user interrupt inputs Microprocessor/microcomputer mode select Microstate complete signal Interrupt acknowledge signal Data ready input. Asserted external logic when using slower devices indicate that current transaction complete. request signal. Asserted when SMJ320C25 requires access external global data memory space. External flag output (latched software-programmable signal) Hold input. When asserted, SMJ320C25 goes into idle mode places data, address, control lines high-impedance state. Hold acknowledge signal Synchronization input Branch control input. Polled BIOZ instruction Serial data receive input Clock receive input serial port Frame synchronization pulse receive input Serial data transmit output Clock transmit output serial port DEFINITION
Frame synchronization pulse transmit. Configurable either input output. I/O/Z denotes input/output/high-impedance state.
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block diagram
X2/CLKIN CLKOUT1 CLKOUT2 SYNC STRB READY HOLD HOLDA IACK MP/MC INT(2-0) A15-A0 Program
PFC(16)
QIR(16) IR(16) STO(16) ST1(16) RPTC(8) IFR(6) CLKR CLKX RSR(16) XSR(16)
Controller
MCS(16) PC(16)
Address Program ROM/ EPROM (4096 Instruction
Stack
DRR(16) DXR(16) TIM(16) PRD(16) IMR(6) GREG(8)
D15-D0
Data AR0(16) ARP(3) AR1(16) AR2(16) AR3(16) AR4(16) AR5(16) AR6(16) AR7(16) ARB(3) ARAU(16) Block Data Block (256 Data DATA/PROG (256 Block Shifter(0-16) DP(9) From
Program
TR(16)
Multiplier
PR(32) Shifter(-6,
ALU(32) ACCH(16) Shifters (0-7) ACCL(16)
LEGEND: ACCH ACCL ARAU
Accumulator high Accumulator Arithmetic logic unit Auxiliary register arithmetic unit Auxiliary register pointer buffer Auxiliary register pointer Data memory page pointer Serial port data receive register Serial port data transmit register
Interrupt flag register Interrupt mask register Instruction register Microcall stack Queue instruction register Product register Period register timer Timer Temporary register
RPTC GREG AR0-AR7 ST0,
Program counter Prefetch counter Repeat instruction counter Global memory allocation register Serial port receive shift register Serial port transmit shift register Auxiliary registers Status registers Carry
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
architecture
SMJ320C25 increases performance algorithms through innovative additions SMJ320 architecture. Increased throughput SMJ320C25 many applications accomplished means single-cycle multiply/accumulate instructions with data move option, eight auxiliary registers with dedicated arithmetic unit, faster necessary data-intensive signal processing. architectural design SMJ320C25 emphasizes overall speed, communication, flexibility processor configuration. Control signals instructions provide floating-point support, block-memory transfers, communication slower off-chip devices, multiprocessing implementations. large on-chip blocks, configurable either separate program data spaces contiguous data blocks, provide increased flexibility system design. Programs words masked into internal program ROM. remainder 64K-word program memory space located externally. Large programs execute full speed from this memory space. Programs also downloaded from slow external memory high-speed on-chip RAM. total data memory address space included facilitate implementation algorithms. VLSI implementation SMJ320C25 incorporates these features well many others, such hardware timer, serial port, block data transfer capabilities. 32-bit ALU/accumulator SMJ320C25 32-bit arithmetic logic unit (ALU) accumulator perform wide range arithmetic logical instructions, majority which execute single clock cycle. executes variety branch instructions dependent status single word. These instruction provide following capabilities:
Branch address specified accumulator Normalize fixed-point numbers contained accumulator Test specified word data memory.
input always provided from accumulator, other input provided from product register (PA) multiplier input scaling shifter which fetched data from data bus. After performed arithmetic logical operations, result stored accumulator. 32-bit accumulator split into 16-bit segments storage data memory. Additional shifters output accumulator perform shifts while data being transferred data storage. contents accumulator remain unchanged. scaling shifter SMJ320C25 scaling shifter 16-bit input connected data 32-bit output connected ALU. scaling shifter produces left shift bits input data, programmed instruction. LSBs output filled with zeroes, MSBs either filled with zeroes sign-extended, depending upon status programmed into (sign-extension mode) status register ST1. 16-bit parallel multiplier SMJ320C25 16-bit hardware multiplier, which capable computing signed unsigned 32-bit product single machine cycle. multiplier following associated registers:
16-bit temporary register (TR) that holds operands multiplier, 32-bit product register (PR) that holds product.
Incorporated into SMJ320C25 instruction single-cycle multiply/accumulate instruction that allow both operands processed simultaneously. data these operations reside anywhere internal external memory transferred multiplier each cycle program data buses.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
16-bit parallel multiplier (continued) Four product shift modes available product register (PR) output that useful when performing multiply/accumulate operations, fractional arithmetic, justifying fractional products. timer SMJ320C25 provides memory-mapped 16-bit timer control operations. on-chip timer (TIM) register down counter that continuously clocked CLKOUT1. timer interrupt (TINT) generated every time timer decrements zero. timer reloaded with value contained period (PRD) register within next cycle after reaches zero that interrupts programmed occur regular intervals cycles CLKOUT1. memory control SMJ320C25 provides total 16-bit words on-chip data RAM, divided into three separate blocks (B0, B2). words, words (blocks always data memory, words (block programmable either data program memory. data memory size words allows SMJ320C25 handle data array words (256 words on-chip used program memory), while still leaving locations intermediate storage. When using block program memory, instructions downloaded from external program memory into on-chip then executed. When using on-chip program RAM, ROM, high-speed external program memory, SMJ320C25 runs full speed without wait states. However, READY line used interface SMJ320C25 slower, less-expensive external memory. Downloading programs from slow off-chip memory on-chip program speeds processing while cutting system costs. SMJ320C25 provides three separate address states program memory, data memory, I/O. on-chip memory mapped into either 64K-word data memory program memory space, depending upon memory configuration. CNF0 (configure block data memory) CNFP (configure block program memory) instruction allow dynamic configuration memory maps through software. Regardless configuration, user still execute from external program memory. SMJ320C25 registers which mapped into data memory space: serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, global memory allocation register.
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memory control (continued)
Program
0(0000h) Interrupts Reserved (External) 31(001Fh) 32(0020h 31(001Fh) 32(0020h 4015(0FAFh) 4016(0FB0h) 0(0000h)
Program
Interrupts Reserved (On-Chip ROM/EPROM) 0(0000h)
Data
On-Chip Memory-Mapped Registers 5(0005h) 6(0006h) Reserved 95(005Fh) 96(0060h 127(007Fh) 128(0080h) On-Chip Block Page
On-Chip ROM/EPROM
Reserved 4095(0FFFh) 4096(1000h)
Reserved 511(01FFh) 512(0200h)
Pages
External 767(02FFh) 768(0300h) External 1023(03FFh) 1024(0400h)
On-Chip Block On-Chip Block
Pages
Pages
External
Pages -511
65,535(FFFFh) MP/MC (Microprocessor Mode)
65,535(0FFFFh) MP/MC (Microcomputer Mode)
65,535(0FFFFh)
Memory Maps After CNFD Instruction Program
0(0000h) Interrupts Reserved (External) 0(0000h)
Program
Interrupts Reserved (On-Chip ROM/EPROM) On-Chip ROM/EPROM Reserved 0(0000h)
Data
On-Chip Memory-Mapped Registers 5(0005h) 6(0006h) Reserved 95(005Fh) 96(0060h On-Chip Block Page
31(001Fh) 32(0020h
31(001Fh) 32(0020h 4015(0FAFh) 4016(0FB0h) 4095(0FFFh) 4096(1000h)
127(007Fh) 128(0080h) Reserved Pages
External
511(01FFh) 512(0200h) Does Exist External 767(02FFh) 768(0300h) On-Chip Block 1023(03FFh) 1024(0400h) Pages Pages
65,279(0FEFFh) 65,280(0FF00h) On-Chip Block 65,535(0FFFFh) MP/MC (Microprocessor Mode)
65,279(0FEFFh) 65,280(0FF00h) On-Chip Block 65,535(0FFFFh) MP/MC (Microcomputer Mode) 65,535(0FFFFh)
External
Pages -511
Memory Maps After CNFP Instruction
Figure Memory Maps
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
interrupts subroutines SMJ320C25 three external maskable user interrupts INT2-INT0, available external devices that interrupt processor. Internal interrupts generated serial port (RINT XINT), timer (TINT), software interrupt (TRAP) instruction. Interrupts prioritized with reset (RS) having highest priority serial port transmit interrupt (XINT) having lowest priority. interrupt locations two-word boundaries that branch instruction accommodated those locations desired. built-in mechanism protects multicycle instructions from interrupts. interrupt occurs during multicycle instruction, interrupt processed until instruction completed. This mechanism applies both instructions that repeated become multicycle READY signal. external interface SMJ320C25 supports wide range system interfacing requirements. Program, data, address spaces provide interface memory I/O. thus maximizing system throughout. design simplified having treated same memory. devices mapped into address space using processor's external address data buses same manner memory-mapped devices. Interface memory devices varying speeds accomplished using READY line. When transitions made with slower devices, SMJ320C25 processor waits until other device completes function signals processor READY line. Then, SMJ320C25 continues execution. full-duplex serial port provides communication with serial devices, such codecs, serial converters, other serial systems. interface signals compatible with codecs many other serial devices with minimum external hardware. serial port also used intercommunication between processors multiprocessing applications. serial port memory-mapped registers: data transmit register (DXR) data receive register (DRR). Both registers operate either byte mode 16-bit word mode, accessed same manner other data memory location. Each register external clock, framing synchronization pulse, associated shift registers. method multiprocessing implemented programming device transmit while others receive mode. multiprocessing flexibility SMJ320C25 allows configurations satisfy wide range system requirements. SMJ320C25 used follows:
standalone processor multiprocessor with devices parallel slave/host multiprocessor with global memory space peripheral processor interfaced processor-controlled signals another device.
multiprocessing applications, SMJ320C25 capability allocating global data memory space communicating with that space (bus request) READY control signals. Global memory data memory shared more than processor. Global data memory access must arbitrated. 8-bit memory-mapped GREG (global memory allocation register) specifies part SMJ320C25s data memory global external memory. contents register determine size global memory space. current instruction addresses operand within that space, asserted request control bus. length memory cycle controlled READY line. SMJ320C25 supports (direct memory access) external program/data memory using HOLD HOLDA signals. Another processor take complete control SMJ320C25s external memory asserting HOLD low. This causes SMJ320C25 place address, data, control lines high-impedance state, assert HOLDA. Program execution from on-chip memory proceed concurrently while device hold mode.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
instruction
SMJ320C25 microprocessor implements comprehensive instruction that supports both numeric-intensive signal processing operations well general-purpose applications, such multiprocessing high-speed control. maximum throughput, next instruction prefetched while current being executed. Since same data lines used communicate external data/program space, number cycles vary depending upon whether next data operand fetch from internal external program memory. Highest throughput achieved maintaining data memory on-chip using either internal fast external program memory. addressing modes SMJ320C25 instruction provides three memory addressing modes: direct, indirect, immediate addressing. Both direct indirect addressing used access data memory. direct addressing, seven bits instruction word concatenated with nine bits data memory page pointer form 16-bit data memory address. Indirect addressing accesses data memory through eight auxiliary registers. immediate addressing, data based portion instruction word(s). direct memory addressing, instruction word contains lower seven bits data memory address. This field concatenated with nine bits data memory page pointer form full 16-bit address. Thus, memory paged direct addressing mode with total pages, each page containing words. Eight auxiliary register (AR0-AR7) provide flexible powerful indirect addressing. select specific auxiliary register, Auxiliary Register Pointer (ARP) loaded with value from through AR0-AR7, respectively. There seven types indirect addressing: auto-increment auto-decrement, post-indexing either adding subtracting contents AR0, single indirect addressing with increment decrement bit-reversal addressing (used FFTs) with increment decrement. operations performed current auxiliary register same cycle original instruction, followed anew value being loaded. repeat feature repeat feature, used with instructions such multiply/accumulates, block moves, transfers, table read/writes, allows single instruction performed times. repeat counter (RPTC) loaded with either data memory value (RPT instruction) immediate value (RPTK instruction) .The value this operand less than number times that next instruction executed. Those instructions that normally multicycle pipelined when using repeat feature, effectively become single-cycle instructions. instruction summary Table lists symbols abbreviations used Table instruction summary, Table consists primarily single-cycle,single-word instructions. Infrequently used branch, I/O, CALL instructions multicycle. instruction summary arranged according function alphabetized within each functional grouping.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
instruction summary (continued)
Table Instruction Symbols
SYMBOL 4-bit field specifying code 2-bit field specifying compare mode Data memory address field Format status Addressing mode Immediate operand field Port address (PA0-PA15 predefined assembler symbols equal through respectively) 2-bit field specifying register output shift code 3-bit operand field specifying auxiliary register 4-bit left-shift code 3-bit accumulator left-shift field MEANING
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
Table SMJ320C25 Instruction Summary
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC DESCRIPTION WORDS ADDC ADDH ADDK ADDS ADDT ADLK ANDK CMPL LACK LACT LALK NORM SACH SACL SBLK SUBB SUBC SUBH SUBK SUBS Absolute value accumulator accumulator with shift accumulator with carry high accumulator accumulator short immediate accumulator with sign extension suppressed accumulator with shift specified register accumulator long immediate with shift with accumulator immediate with accumulator with shift Complement accumulator Load accumulator with shift Load accumulator immediate short Load accumulator with shift specified register Load accumulator long immediate with shift Negate accumulator Normalize contents accumulator with accumulator immediate with accumulator with shift Rotate accumulator left Rotate accumulator right Store high accumulator with shift Store low-order accumulator with shift Subtract from accumulator long immediate with shift Shift accumulator left Shift accumulator right Subtract from accumulator with shift Subtract from accumulator with borrow Conditional subtract Subtract from high accumulator Subtract from accumulator short immediate Subtract from accumulator with sign extension suppressed INSTRUCTION CODE
These instructions included TMS320C1x instruction set. These instructions included TMS32020 instruction set.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
Table SMJ320C25 Instruction Summary (continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC DESCRIPTION WORDS SUBT XORK ZALH ZALR ZALS Subtract from accumulator with shift specified register Exclusive-OR with accumulator Exclusive-OR immediate with accumulator with shift Zero accumulator Zero accumulator load high accumulator Zero accumulator load high accumulator with rounding Zero accumulator load accumulator with sign extension suppressed INSTRUCTION CODE
AUXILIARY REGISTERS DATA PAGE POINTER INSTRUCTIONS MNEMONIC ADRK CMPR LARK LARP LDPK LRLK SBRK DESCRIPTION WORDS auxiliary register short immediate Compare auxiliary register with auxiliary register Load auxiliary register Load auxiliary register short immediate Load auxiliary register pointer Load data memory page pointer Load data memory page pointer immediate Load auxiliary register long immediate Modify auxiliary register Store auxiliary register Subtract from auxiliary register short immediate INSTRUCTION CODE
These instructions included TMS320C1x instruction set. These instructions included TMS32020 instruction set.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
Table SMJ320C25 Instruction Summary (continued)
REGISTER, REGISTER, MULTIPLY INSTRUCTIONS MNEMONIC APAC MACD MPYA MPYK MPYS MPYU SPAC SQRA SQRS DESCRIPTION WORDS register accumulator Load high register Load register Load register accumulate previous product Load register, accumulate previous product, move data Load register store register accumulator Load register subtract previous product Multiply accumulate Multiply accumulate with data move Multiply (with register, store product register) Multiply accumulate previous product Multiply immediate Multiply subtract previous product Multiply unsigned Load accumulator with register Subtract register from accumulator Store high register Store register register output shift mode Square accumulate Square subtract previous product INSTRUCTION CODE
These instructions included TMS320C1x instruction set. These instructions included TMS32020 instruction set.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
Table SMJ320C25 Instruction Summary (continued)
BRANCH/CALL INSTRUCTIONS WORDS BACC BANZ BBNZ BGEZ BIOZ BLEZ CALA CALL Branch unconditionally Branch address specified accumulator Branch auxiliary register zero Branch Branch Branch carry Branch accumulator Branch accumulator Branch status Branch accumulator Branch accumulator Branch carry Branch overflow Branch accumulator Branch overflow Branch accumulator Call subroutine indirect Call subroutine Return from subroutine INSTRUCTION CODE
MNEMONIC
DESCRIPTION
DATA MEMORY OPERATIONS WORDS BLKD BLKP DMOV FORT RFSM RTXM SFSM STXM TBLR TBLW Block move from data memory data memory Block move from program memory data memory Data move data memory Format serial port registers Input data from port Output data port Reset serial port frame synchronization mode Reset serial port transmit mode Reset external flag serial port frame synchronization mode serial port transmit mode external flag Table read Table write INSTRUCTION CODE
MNEMONIC
DESCRIPTION
These instructions included TMS320C1x instruction set. These instructions included TMS32020 instruction set.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
Table SMJ320C25 Instruction Summary (concluded)
CONTROL INSTRUCTIONS MNEMONIC BITT CNFD CNFP DINT EINT IDLE LST1 POPD PSHD PUSH ROVM RPTK RSXM SOVM SST1 SSXM TRAP Test Test specified register Configure block data memory Configure block program memory Disable interrupt Enable interrupt Idle until interrupt Load status register Load status register operation stack accumulator stack data memory Push data memory value onto stack Push accumulator onto stack Reset carry Reset hold mode Reset overflow mode Repeat instruction specified data memory value Repeat instruction specified immediate value Reset sign-extension mode Reset test/control flag carry hold mode overflow mode Store status register Store status register sign-extension mode test/control flag Software interrupt DESCRIPTION WORDS INSTRUCTION CODE
These instructions included TMS320C1x instruction set. These instructions included TMS32020 instruction set.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
development systems software support
Texas Instruments offers concentrated development support complete documentation designing SMJ320C25-based microprocessor system. When developing application, tools provided evaluate performance processor, develop algorithm implementation, fully integrate design's software hardware modules. When questions arise, additional support obtained calling nearest Texas Instruments Regional Technology Center (RTC). Sophisticated development operations performed with SMJ320C25 Macro Assembler/linker, Simulator, Emulator (XDS). macro assembler linker used translate program modules into object code link them together. This puts program modules into form which loaded into SMJ320C25 Simulator Emulator. simulator provides quick means initially debugging SMJ320C25 software while emulator provides real-time in-circuit emulation necessary perform system level debug efficiently. Table gives complete list SMJ320C25 software hardware development tools. Table SMJ/SMJ320C25 Software Hardware Support
MACRO ASSEMBLERS/LINKERS Host Computer DECVAX TI/IBM Operating System MS/PC-DOS SIMULATORS Host Computer DECVAX TI/IBM Operating System MS/PC-DOS EMULATORS Model XDS/22 Power Supply Included Part Number TMDS3262221 Part Number TMDS3242211-08 TMDS3242811-02 Part Number TMDS324210-08 TMDS3242810-02
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, -0.3 Input voltage range -0.3 Output voltage range -0.3 Continuous power dissipation Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltage values with respect VSS.
recommended operating conditions
SMJ320C25-50 Supply voltage Supply voltage READY D15-D0 High-level input oltage High voltage CLKR, CLKX CLKIN others D15-D0, FSX, CLKIN, CLKR, CLKX level input Low-level voltage High-level output current Low-level output current HOLD others 3.00 2.20 2.20 3.50 4.00 3.00 0.80 0.70 0.80 4.75 2.35 2.20 2.30 3.50 3.50 3.00 0.80 0.70 0.70 5.25 SMJ320C25 UNIT
Operating case temperature maximum rated operating conditions point case initial (time zero) power
This device contains circuits protect inputs outputs against damage high static voltages electrostatic fields. These circuits have been qualified protect this device against electrostatic discharges (ESD) according MIL-STD-883C, Method 3015; however, advised that precautions taken avoid application voltage higher than maximum-rated voltages these high-impedance circuits. During storage handling, device leads should shorted together device should placed conductive foam. circuit, unused inputs should always connected appropriated logic voltage level, preferably either ground. Specific guidelines handling devices this type contained publication Guidelines Handling (ESDS) Devices Assemblies available from Texas Instruments.
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
electrical characteristics over specified free-air temperature range (unless otherwise noted)
PARAMETER High-level output voltage Low-level output voltage Three-state current X2/CLKIN Input current Supply current rrent Input capacitance other pins Normal Idle/R5L5 MAX, TEST CONDITIONS MIN, MIN, SMJ320C25, SMJ320C25-50 UNIT
Output capacitance typical values 25°C
CLOCK CHARACTERISTICS TIMING
SMJ320C25 either internal oscillator external frequency source clock.
internal clock option
internal oscillator enabled connecting crystal across X2/CLKIN (see Figure frequency CLKOUT1 one-fourth crystal fundamental frequency. crystal should either fundamental overtone mode, parallel resonant, with effective series resistance power dissipation specified load capacitance Note that overtone crystals require additional tuned circuit (see application report, Hardware Interfacing TMS320C25).
SMJ320C25-50 PARAMETER TEST CONDITIONS Input clock frequency 55°C 125°C These values derived from characterization data tested. 50.0 SMJ320C25 40.0 UNIT
X2/CLKIN Crystal
Figure Internal Clock Options
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
external clock option
external frequency source used injecting frequency directly into X2/CLKIN with left unconnected. external frequency injected must conform specifications listed following table.
switching characteristics over recommended operating conditions (see Note
PARAMETER tc(C) td(CIH-C) td(C1-C2) tf(C) tr(C) Cycle time, CLKOUT1/CLKOUT2 Delay time, CLKIN high CLKOUT1/CLKOUT2/STRB high/low Delay time, CLKOUT1 high CLKOUT2 low, Delay time, CLKOUT2 high CLKOUT1 high, etc. Fall time, CLKOUT1/CLKOUT2/STRB Rise time, CLKOUT1/CLKOUT2/STRB SMJ320C25-50 SMJ320C25 UNIT
tw(CL) Pulse duration, CLKOUT1/CLKOUT2 tw(CH) Pulse duration, CLKOUT1/CLKOUT2 high .This parameter production tested NOTE 1/4tc(C)
timing requirements over recommended operating conditions (see Note
SMJ320C25-50 tc(CI) tw(CIL) tw(CIH) tsu(S) Cycle time, CLKIN Pulse duration, CLKIN low, tc(CI) (see Note Pulse duration, CLKIN high, tc(CI) (see Note Setup time, SYNC before CLKIN SMJ320C25 UNIT
th(S) Hold time, SYNC from CLKIN NOTES: 1/4tc(C) Rise fall times, assuming 40-60% duty cycle, incorporated within this specification CLKIN rise fall times must less than
Figure Test Load Circuit
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1.88 0.92 0.80 Input
(Min) (Max)
Output
(Min) (Max)
Figure Voltage Reference Levels
switching characteristics over recommended operating conditions (see Note
PARAMETER td(C1-S) STRB from CLKOUT1 STRB present) td(C2-S) CLKOUT2 STRB STRB present) tsu(A) th(A) tw(SL) tw(SH) Address setup time before STRB (see Note Address hold time after STRB high (see Note STRB pulse duration wait states, Note STRB high pulse duration (between consecutive cycles, Note SMJ320C25-50 SMJ320C25 UNIT
tsu(D)W Data write setup time before STRB high wait states) th(D)W Data write hold time from STRB high ten(D) tdis(D) Data starts being driven after STRB (write cycle) Data three-state after STRB high (write cycle)
td(MSC) valid from CLKOUT1 These values derived from characterization data tested.
timing requirements over recommended operating conditions (see Note
SMJ320C25-50 ta(A) tsu(D)R th(D)R td(SL-R) td(C2H-R) th(SL-R) th(C2H-R) td(M-R) Access time, read data from address time (read cycle, Notes Setup time, data read before STRB high Hold time, data read from STRB high Delay time, READY valid after STRB wait states) Delay time, READY valid after CLKOUT2 high Hold time, READY after STRB wait states) Hold time, READY after CLKOUT2 high Delay time, READY valid after valid SMJ320C25 UNIT
th(M-R) Hold time, READY after valid NOTES: 1/4tc(C) A15-A0, R/W, timings included timings referenced "address" Delays between CLKOUT1 /CLKOUT2 edges STRB edges track each other, resulting tw(SL) tw(SH) being with wait states. Read data access time defined ta(A) tsu(A) tw(SL) tsu(D)R tr(C).
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
INT, BIO, timing switching characteristics over recommended operating conditions (see Note
PARAMETER td(RS) Delay time, CLKOUT1 reset state entered td(IACK) Delay time, CLKOUT1 IACK valid td(XF) Delay time, valid before falling edge STRB SMJ320C25-50 SMJ320C25 UNIT
timing requirements over recommended operating conditions (see Note
SMJ320C25-50 tsu(IN) th(IN) tw(IN) tw(RS) Setup time, INT/BIO/RS before CLKOUT1 high Hold time, INT/BIO/RS after CLKOUT1 high Pulse duration, INT/BIO Pulse duration, tc(C) 3tc(C) SMJ320C25 tc(C) 3tc(C) UNIT
switching characteristics over recommended operating conditions (see Note
PARAMETER td(C1L-AL) tdis(AL-A) tdis(C1L-A) td(HH-AH) ten(A-C1L) Delay time, HOLDA after CLKOUT1 Disable time, HOLDA address three-state Disable time, address three-state after CLKOUT1 (HOLD mode, Note Delay time, HOLD high HOLDA high Enable time, address driven before CLKOUT1 (HOLD mode, Note SMJ320C25-50 SMJ320C25 UNIT
timing requirements over recommended operating conditions (see Note
SMJ320C25-50 SMJ320C25 UNIT UNIT
td(C2H-H) Delay time, HOLD valid after CLKOUT2 high These values derived from characterization data tested. NOTES: 1/4tc(C) INT, asynchronous inputs occur time during clock cycle. However, specified setup time met, exact sequence shown timing diagram occurs. INT/BIO fall time must less than A15-A0, STRB, timings included timings referenced '"address".
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
serial port timing switching characteristics over recommended operating conditions (see Note
PARAMETER td(CH-DX) td(FL-DX) td(CH-FS) Delay time, valid after CLKX rising edge (see Note Delay time, valid after falling edge (TXM Note valid after CLKX rising edge (TXM SMJ320C25-50 SMJ320C25 UNIT
timing requirements over recommended operating conditions (see Note
SMJ320C25-50 tc(SCK) tw(SCK1 tw(SCK) tsu(FS) th(FS) tsu(DR) th(DR) Serial port frequency Serial port clock (CLKX/CLKR) cycle time Serial port clock (CLKX/CLKR) pulse duration (see Note Serial port clock (CLKX/CLKR) high pulse duration (see Note FSX/FSR setup time before CLKX/CLKR falling edge (TXM FSX/FSR hold time after CLKX/CLKR falling edge (TXM setup time before CLKR falling edge hold time after CLKR falling edge 1.25 6250 SMJ320C25 1.25 5000 UNIT
NOTES: 1/4tc(C) last occurrence falling CLKX rising. duty cycle serial port clock must within 40-60% .Serial port clock (CLKX/CLKR) rise fall times must less than
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
TIMING DIAGRAMS
Timing measurements referenced from voltage high voltage with exception CLKOUT1, CLKOUT2, STRB timing that referenced from falling edge voltage rising edge voltage
tc(CI) tf(CI) tr(CI) X/2CLKIN th(S) tsu(S) SYNC tc(C) td(CIH-C) CLKOUT1 tw(CH) td(CIH-C) STRB td(CIH-C) tr(C) tf(C) tw(CL) td(CIH-C) tsu(S) tw(CIH) tw(CIL)
tc(C) tw(CL)
CLKOUT2 td(C1-C2) td(C1-C2) td(C1-C2) td(C1-C2) tw(CH) tf(C) tr(C)
Figure Clock Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
td(C1-S) CLKOUT1 td(C1-S) CLKOUT2 td(C2-S) STRB tw(SH) tsu(A) tw(SL) A15-A0, ta(A) td(SL-R) tsu(D)R READY Valid th(A) td(C2-S)
th(SL-R) D15-D0 Data
th(D)R
Figure Memory Read Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1
CLKOUT2
STRB th(A) tsu(A) A15-A0, Valid
READY tsu(D)W
th(D)W
D15-D0
Data
ten(D)
tdis(D)
Figure Memory Write Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1
CLKOUT2
STRB th(C2H-R) A15-A0, td(C2H-R) READY td(M-R) D15-D0 (For Read Operation) D15-D0 (For Write Operation) td(MSC) td(MSC) th(M-R) td(M-R) th(M-R) Data th(C2H-R) Valid td(C2H-R)
Data
Figure Wait-State Memory Access Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1 tsu(IN) td(RS) tsu(IN) th(IN) tw(RS) A15-A0 Valid Fetch Location D15-D0 Valid Begin Program Execution
STRB
Control Signals
IACK
Serial Port Control Control signals R/W, Serial port controls FSX.
Figure Reset Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1
STRB tsu(IN) tw(IN) INT2-INT0 tf(IN) A15-A0 FETCH td(IACK) IACK FETCH td(IACK) FETCH FETCH th(IN)
Figure Interrupt Timing
CLKOUT1
STRB FETCH Branch Address A15-A0 FETCH BIOZ tsu(IN) th(IN) Valid Branch Address FETCH Next Instruction
Figure Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1
STRB td(XF) A15-A0 FETCH SXF/RXF Valid Valid Valid Valid
Figure External Flag Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1
CLKOUT2
STRB td(C2H-H) HOLD
A15-A0
Valid
Valid
tdis(C1L-A) D15-D0 tdis(AL-A) HOLDA td(C1L-AL)
FETCH
EXECUTE HOLD asynchronous input occur time during clock cycle. specified timing met, exact sequence shown occurs; otherwise, delay CLKOUT2 cycle occurs.
Figure HOLD Timing (part
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
CLKOUT1
CLKOUT2 ten(A-C1L) STRB td(C2H-H) HOLD
Valid
D15-D0 td(HH-AH) HOLDA
A15-A0
FETCH
EXECUTE HOLD asynchronous input occur time during clock cycle. specified timing met, exact sequence shown occurs; otherwise, delay CLKOUT2 cycle occurs.
Figure HOLD Timing (part
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
tc(SCK) tr(SCK) tw(SCK) CLKR th(DR) th(FS)
tf(SCK) tw(SCK)
tsu(FS)
tsu(DR)
Figure Serial Port Receive Timing
tc(SCK) tw(SCK) CLKX td(CH-DX) tf(SCK) th(FS) (Input, tsu(FS) td(FL-DX) td(CH-FS) td(CH-DX) 8,16 tw(SCK) tr(SCK)
td(CH-FS) (Output,
Figure Serial Port Transmit Timing
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA
(S-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (28,83) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,33) 0.962 (24,43) 0.064 (1,63) 0.064 (1,63) 0.069 (1,75) 0.082 (2,08) 0.082 (2,08) 0.082 (2,08)
0.080 (2,03) 0.080 (2,03) 0.120 (3,05) 0.120 (3,05) 0.120 (3,05) 0.120 (3,05)
0.095 (2,41) 0.075 (1,91)
1.135 1.165 (28,83) (29,59)
0.025 (0,64) 0.015 (0,38) 0.025 0.050 (0,64 1,27) Places
0.025 (0,64)
0.015 (0,38) 0.003 (0,08) 0.028 (0,71) 0.022 (0,56) 0.015 (0,38) 0.045 (1,14) Places 0.035 (0,89) 0.050 (1,27) 4040136/B 03/95
0.055 (1,40) 0.045 (1,14)
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
(S-CQCC-J**)
PINS SHOWN 0.043 (1,09) 0.033 (0,84)
J-LEADED CERAMIC CHIP CARRIER
Index Mark (Optional)
0.025 (0,64) 0.015 (0,38)
0.058 (1,47) 0.042 (1,07)
0.015 (0,38) 0.025 (0,64) 0.036 (0,89) 0.085 (2,16) 0.065 (1,65) 0.011 (0,28) 0.007 (0,18)
0.050 (1,27) 0.030 (0,76) Places 0.050 (1,27) 0.020 (0,51) 0.010 (0,25) 0.145 (3,68) 0.100 (2,54) 0.641 0.500 0.630 0.080 (2,03) 0.095 (2,41) 0.058 (1,47) 0.072 (1,83) 4040139/C 10/98 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. index mark appear bottom depending package vendor. This package hermetically sealed with metal lid.
PINS
0.700 0.680 0.659
(17,78) (17,27) (16,74) (16,28) (12,70) (16,00) 1.000 (25,40) (24,89) (24,38) (23,88) (20,32) (23,62) 0.980 0.960 0.940 0.800 0.930
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SMJ320C25, SMJ320C25 DIGITAL SIGNAL PROCESSOR
(S-CPGA-P68)
0.970 (24,63) 0.950 (24,13) 0.536 (13,61) 0.524 (13,31)
CERAMIC GRID ARRAY PACKAGE
0.800 (20,32)
0.100 (2,54)
0.088 (2,23) 0.072 (1,83)
0.194 (4,98) 0.166 (4,16)
0.055 (1,39) 0.045 (1,14) 0.050 (1,27) Places 0.018 (0,46) 4040114-14/C 04/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Index mark appear bottom depending vendor. Pins located within 0.010 (0,25) diameter true position relative each other maximum material condition within 0.030 (0,76) diameter relative edges ceramic. This package hermetically sealed with metal lids with ceramic lids using glass frit. pins gold plated solder dipped. Falls within 1835 CMGA1-PN, CMGA13-PN JEDEC MO-067 MO-066 respectively
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device 5962-8861901XA 5962-8861901YA 5962-8861901ZA 5962-8861902XA 5962-8861902ZA SM320C25FJM SM320C25GBM SMJ320C25-50FJM SMJ320C25-50GBM SMJ320C25FDM SMJ320C25FJM SMJ320C25GBM
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CPGA LCCC JLCC CPGA JLCC JLCC CPGA JLCC CPGA LCCC JLCC CPGA
Package Drawing
Pins Package Plan None None None None None None None None None None None None
Lead/Ball Finish Call Call Call Call Call Call Call Call Call Call Call Call
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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