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4LSB Vout nanoDacTM, Buffered, 3V/5V, Preliminary Technical Data
FEATURES Single 16-Bit DAC, inl. Volt Digital Interface Capability Power-On-Reset Zero Volts/Mid Scale Three Power-Down Functions Power Serial Interface with SchmittTriggered Inputs 8-Lead Sot23 Power Operation Fast Settling. Glitch Powerup.
AD5061
APPLICATIONS Process Control Data Acquisition Systems Portable Battery Powered Instruments Digital Gain Offset Adjustment Programmable Voltage Current Sources Programmable Attenuators
AD5061
Part Number Description
nanoDACD/A, 1LSBs INL., Unbuffered, nanoDACD/A, LSBs INL., Unbuffered, uSOIC, uncommitted bi-polar resistors. 14/16 nanoDACD/A, LSBs INL, Buffered, Sot23.
AD5062 AD5063
AD5061, member nanoDACfamily, single 16-bit buffered voltage DAC, available Sot23. AD5061 operated 3V/5V. part utilizes versatile three-wire serial interface that operates clock rates compatible with standard SPITM, QSPITM, MICROWIREand interface standards. reference AD5061 supplied from external pin. reference buffer also provided chip. parts incorporate power-on-reset circuit that ensures that output powers zero volts/ scale remains there until valid write takes place device. parts also contain power-down feature that reduces current consumption device 50nA provides software selectable output loads while power-down mode. part into power-down mode over serial interface. Total unadjusted error part <1mV. These parts also provide very glitch power-up.
GENERAL DESCRIPTION
AD5040/60
PRODUCT HIGHLIGHTS
Available 8-lead SOT23. Accurate, INL. Glitch Power-up. High speed serial interface with clock speeds MHz. Three power down modes available user.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 2004 Analog Devices, Inc. rights reserved.
Rev. Page
AD5061
AD5061-SPECIFICATIONS1
AD5061, 5.5V, Vref =4.096V, RL=5k, 200pF TMIN TMAX; unless otherwise noted.
Preliminary Technical Data
Parameter STATIC PERFORMANCE AD5061 Resolution Relative Accuracy Differential Nonlinearity Offset Code Error Gain Error Offset Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density
Version1
Unit
Test Conditions/Comments
0.65 Vref -150mV 1000
Bits µV/°C FSR/°C V/µs nV/Hz nV/Hz nV-s nV-s
Guaranteed Monotonic Design.
+/-1lsb code=TBD 1kHz code=TBD 10kHz Change Around Major Carry.
Digital-to-Analog Glitch Impulse Digital Feedthrough Output Impedance REFERENCE INPUT/OUPUT Vref Input Range Input Current Input Impedance LOGIC INPUTS Input Current VINL, Input Voltage VINH, Input High Voltage VINL, Input Voltage VINH, Input High Voltage Capacitance POWER REQUIREMENTS (Normal Mode) +2.7 +3.6 (All Power-Down Modes) (Normal Mode) +5.0 +5.5 (All Power-Down Modes)
VDD-100mV
AD5060 Volt Option) Active Excluding Load Current
AD5060 Volt Option) Active Excluding Load Current
Rev. Page
Preliminary Technical Data
Parameter Version1 Unit
AD5040/AD5060
Test Conditions/Comments
(Normal Mode) +2.7 +5.5 (All Power-Down Modes)
AD5040 Active Excluding Load Current
PSSR
NOTES 1Temperature ranges follows: Version: -40°C +125°C, typical 25°C. 2Guaranteed design characterization, production tested. Linearity calculated using reduced code range 480-64716. Specifications subject change without notice.
Rev. Page
AD5061
TIMING CHARACTERISTICS
(VDD 2.7-5.5 specifications TMIN TMAX unless otherwise noted)
Preliminary Technical Data
Parameter
Limit1
Unit
Test Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Time SYNC SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge SYNC Rising Edge Minimum SYNC High Time SYNC Rising Edge next SCLK Fall Ignore
NOTES 1All input signals specified with ns/V (10% VDD) timed from voltage level (VIL VIH)/2. 2See Figure 3Maximum SCLK frequency MHz. Specifications subject change without notice.
Figure Timing DiagramAD506. AD5040 same timing specs with Word.
Rev. Page
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings 25°C unless otherwise noted)
AD5040/AD5060
Parameter Digital Input Voltage VOUT GND1 Operating Temperature Range Industrial Version) Storage Temperature Range Maximum Junction Temperature SOT23 Package Power Dissipation Thermal Impedance Thermal Impedance
Rating -0.3 -0.3 -0.3 -40°C +125°C -65°C +150°C 150°C Max-Ta)/ 229.6°C/W 91.99°C/W
Lead Temperature, Soldering Vapour Phase Sec) Infrared Sec)
300°C 220°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device high performance integrated circuit with rating sensitive. Proper precautions should taken handling assembly.
Model AD5061BRJ-1 AD5061BRJ-2 AD5061BRJ-3
Temperature Range -40OC -40OC
Description Buffered SOT-23, Reset Zero Buffered SOT-23, Reset Buffered SOT-23, Reset Zero
Package Options
Rev. Page
AD5061 CONFIGURATION FUNCTION DESCRIPTION
Preliminary Technical Data
Figure AD5063 SOT23
Table Function Descriptions
Mnemonic DacGND VOUT SYNC
Function Power Supply Input. These parts operated from +2.5 +5.5 should decoupled GND. Reference Voltage Input. Ground input DAC. Analog output voltage from DAC. Level triggered control input (active low). This frame synchronization signal input data. When SYNC goes low, enables input shift register data transferred falling edges following clocks. updated following 16th clock cycle unless SYNC taken high before this edge which case rising edge SYNC acts interrupt write sequence ignored DAC. Serial Clock Input. Data clocked into input shift register falling edge serial clock input. Data transferred rates MHz. Serial Data Input. This device shift register. Data clocked into register falling edge serial clock input. Ground reference point Analog circuitry part.
SCLK AGND
Rev. Page
Preliminary Technical Data
Gain Error TERMINOLOGY Relative Accuracy
DAC, relative accuracy Integral Nonlinearity (INL) measure maximum deviation, LSBs, from straight line passing through endpoints transfer function. typical code plot seen Figure
AD5040/AD5060
This measure span error DAC. deviation slope transfer characteristic from ideal expressed percent full-scale range.
Total Unadjusted Error
Total Unadjusted Error (TUE) measure output error taking various errors into account. typical code plot seen Figure
Differential Nonlinearity
Differential Nonlinearity (DNL) difference between measured change ideal change between adjacent codes. specified differential nonlinearity maximum ensures monotonicity. This guaranteed monotonic design. typical code plot seen Figure
Zero-Code Error Drift
This measure change zero-code error with change temperature. expressed µV/°C.
Gain Error Drift
This measure change gain error with changes temperature. expressed (ppm full-scale range)/°C.
Zero-Code Error
Zero-code error measure output error when zero code (0000Hex) loaded register. Ideally output should zero-code error always positive AD5061 because output cannot below combination offset errors output amplifier. Zero-code error expressed plot zero-code error temperature seen Figure
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse impulse injected into analog output when input code register changes state. normally specified area glitch secs measured when digital input code changed major carry transition (7FFF 8000 Hex). Figure
Full-Scale Error
Full-scale error measure output error when full-scale code (FFFF Hex) loaded register. Ideally output should LSB. Full-scale error expressed percent full-scale range. plot full-scale error temperature seen Figure
Digital Feedthrough
Digital feedthrough measure impulse injected into analog output from digital inputs measured when output updated. specified secs measured with full-scale code change data bus, i.e., from vice versa.
Rev. Page
AD5061
Linearity Plot
Preliminary Technical Data
Linearity Plot
Code
Figure Typical Plot
-0.2 -0.6
-0.2 -0.6 Code
Figure Typical PloT.
Figure Total Unadjusted Error Polt. Figure DNLvs Supply
Figure Zero Scale Error Full Scale Error Temperature
Figure Histogram Vdd=3/5 Volts.
Rev. Page
Preliminary Technical Data
AD5040/AD5060
Figure Source Sink Current Capability
Figure Supply Current Code.
Figure Supply Current Temperature
Figure Supply Current SupplyoVoltage
Figure Half Scale Settling Time Figure Full Scale Settling Time
Rev. Page
AD5061
Preliminary Technical Data
Figure Power Reset Volts.
Figure Exiting Power-Down
Figure Digital Analog Glitch Impulse
Figure Harmonic Distortion igitally Generated Waveform.
Figure Output Spectral Density 100k Bandwidth
Figure Noise Plot
Rev. Page
Preliminary Technical Data
AD5040/AD5060
Figure Offset Error Distribution Figure PowerUp Transient
Figure Gain Error Distribution Figure Glitch Energy
Rev. Page
AD5061
GENERAL DESCRIPTION
AD5061 single 16-bit, serial input, voltage output DACs. AD5061 operates from either supply. Data written AD50461in 24-bit word format. AD5061 incorporates power-on reset circuit, which ensures that output powers mid-scale. device also software power-down mode pin, which reduces typical current consumption 50nA
Preliminary Technical Data
reference core
SERIAL INTERFACE
AD5061 word write) three-wire serial interface (SYNC, SCLK DIN), which compatible with SPI, QSPI MICROWIRE interface standards well most DSPs. Figure timing diagram typical write sequence. write sequence begins bringing SYNC line low. Data from line clocked into 24-bit shift register falling edge SCLK. serial clock frequency high MHz, making these parts compatible with high speed DSPs. falling clock edge, last data clocked programmed function executed (i.e., change register contents and/or change mode operation). this stage, SYNC line kept brought high. either case, must brought high minimum before next write sequence that falling edge SYNC initiate next write sequence. Since SYNC buffer draws more current when than does when SYNC should idled between write sequences even lower power operation part. mentioned above, however, must brought high again just before next write sequence.
Architecture
architecture AD5061 consists matched sections. simplifed circuit diagram shown Figure four MSBs 16-bit data word decoded drive switches, E15. Each these switches connects matched resistors either AGND VREF. remaining bits thedata word drive switches 12-bit voltage modeR-2R ladder network.
Input Shift Register
input shift register bits wide (see Figure 22/23). D23D16 zero normal operation. D17, control bits that control which mode operation part (normal mode three power-down modes). There more complete description various modes PowerDown Modes section. next sixteen bits data bits. These transferred register 24th falling edge SCLK.
Figure Ladder Structure
Reference Buffer
AD5061 operates with external reference. reference input (REFIN) input range Vdd. This input voltage then used provide buffered
Figure AD5060 Input Register Contents
Rev. Page
Preliminary Technical Data
AD5040/AD5060
Figure AD5040 Input Register Contents
SYNC Interrupt
normal write sequence, SYNC line kept least falling edges SCLK updated 24th falling edge. However, SYNC brought high before 24th falling edge this acts interrupt write sequence. shift register reset write sequence seen invalid. Neither update register contents change operating mode occurs-see Figure
Table Modes Operation AD5061
Operating Mode Normal Operation Power-Down Mode TRI-STATE
Power-On-Reset
AD5061 contains power-on-reset circuit that controls output voltage during power-up. register filled with zeros output voltage zero volts/mid-scale. remains there until valid write sequence made DAC. This useful applications where important know state output while process powering When both bits part works normally with normal power consumption. However, three powerdown modes, supply current falls only does supply current fall output stage also internally switched from output amplifier resistor network known values. This advantage that output impedance part known while part power-down mode. There three different options. output connected internally through resistor, resistor left open-circuited (Three-State). output stage illustrated Figure
Software Reset.
AD5061 into software reset setting register one. This includes writing ones bits D23D16, which normal mode operation. Note:
SYNC Interrupt command cannot performed software reset command started.
Power-Down Modes
AD5061 contains three separate modes operation. These modes software-programmable setting bits (PD1 PD0) control register. Table shows state bits corresponds mode operation device.
Figure Output Stage During Power-Down bias generator, output amplifier, other associated linear circuitry shut down when power-down mode activated. However, contents register unaffected when power-down. time exit power-down typically Figure plot.
Rev. Page
AD5061
MICROPROCESSOR INTERFACING AD5061 ADSP-2101/ADSP-2103 Interface
Figure shows serial interface between AD5061 ADSP-2101/ADSP-2103. ADSP-2101/ADSP-2103 should operate SPORT Transmit Alternate Framing Mode. ADSP-2101/ADSP-2103 SPORT programmed through SPORT control register should configured follows: Internal Clock Operation, Active Framing, 16Bit Word Length. Transmission initiated writing word register after SPORT been enabled.
Preliminary Technical Data
Figure AD5061 ADSP-2101/ADSP-2103 Interface
SCLK
SYNC
DB23
DB23
INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES 24TH FALLING EDGE
Figure SYNC Interrupt Facility AD5060.
AD5061 68HC11/68L11 Interface
Figure shows serial interface between AD5060 68HC11/68L11 microcontroller. 68HC11/68L11 drives SCLK AD5060, while MOSI output drives serial data line DAC. SYNC signal derived from port line (PC7). setup conditions correct operation this interface follows: 68HC11/68L11 should configured that CPOL CPHA When data being transmitted DAC, SYNC line taken (PC7). When 68HC11/68L11 configured above, data appearing MOSI output valid falling edge SCK. Serial data from 68HC11/68L11 transmitted 8-bit bytes with only eight falling clock edges occurring transmit cycle. Data transmitted first. order load data AD5061, left after first eight bits transferred, second serial write operation performed taken high this procedure.
AD5061 Blackfin ADSP-BF53X Interface
Figure shows serial interface between AD5641 Blackfin ADSP-53X microprocessor. ADSP-BF53X processor family incorporates dual-channel synchronous serial ports, SPORT1 SPORT0 serial multiprocessor communications. Using SPORT0 connect AD5062/63, setup interface follows. DT0PRI drives SDIN AD5062/63, while TSCLK0 drives SCLK part. SYNC driven from TFS0.
Figure AD5061 Blackfin ADSP-BF53X Interface
AD5061 80C51/80L51 Interface
Figure shows serial interface between AD5061 80C51/80L51 microcontroller. setup interface follows: 80C51/80L51 drives SCLK AD5061, while drives serial data line part. SYNC signal again derived from programmable port. this case port line P3.3 used. When data transmitted AD5061, P3.3 taken low. 80C51/80L51 transmits data only 8-bit bytes; thus only eight falling clock edges occur transmit cycle. load data DAC, P3.3 left
Rev. Page
Figure AD5061 68HC11/68L11 Interface
Preliminary Technical Data
after first eight bits transmitted, second write cycle initiated transmit second byte data. P3.3 taken high following completion this cycle. 80C51/80L51 outputs serial data format which first. AD5061 requires data with first received. 80C51/80L51 transmit routine should take this into account.
AD5040/AD5060
Figure ADR425 Reference AD5040. ADR420 used AD5060. Long term drift measure much reference drifts over time. reference with tight long term drift specification ensures that overall solution remains relatively stable during entire lifetime. temperature co-efficient references output voltage affect INL,DNL TUE. reference with tight temperature coefficient specification should chosen reduce temperatue dependence output voltage ambient conditions. high accuracy applications, which have relatively noise budget, reference output voltage noise needs considered. Choosing reference with output noise voltage practical system noise resolution required important. Precision voltage references such ADR435 produce output noise 0.1-10Hz region. Examples some recommended precision references supply AD5060 shown figure below.
Figure AD5061 80C51/80L51 Interface
AD5061 Microwire Interface
Figure shows interface between AD5061 microwire compatible device. Serial data shifted falling edge serial clock clocked into AD5061 rising edge
Figure AD5061 MICROWIRE Interface
APPLICATIONS Choosing Reference AD5061.
achieve optimum performance from AD5060, thought should given choice precision voltage reference. AD5061 have just reference input, REFIN. voltage reference input used supply positive input Therefore error reference will reflected Dac. There possible sources error when choosing voltage reference high accuracy applications; initial accuracy, drift, long term drift output voltage noise. Initial accuracy output voltage will lead full scale error Dac. minimize these errors, reference with high initial accuracy preferred. Also, choosing reference with output trim adjustment, such ADR425 allow system designer trim system errors setting reference voltage voltage other than nominal. trim adjustment also used temperature trim error.
Part list precision references with AD5061.
Part
ADR420 ADR425 ADR02 ADR392
Initial Accuracy max) +/-6 +/-6 +/-5 +/-6
Temp Drift (ppm max)
0.1-10Hz Noise typ)
1.75
Bipolar Operation Using AD5061
AD5061 been designed single-supply operation bipolar output range also possible using circuit Figure circuit below will give output voltage range Rail-to-rail operation amplifier output achievable using AD820 OP295 output amplifier. output voltage input code calculated follows:
Rev. Page
AD5061
POWER
Preliminary Technical Data
REGULATOR 0.1.
where represents input code decimal (0-65535). With
SCLK
SCLK
ADMu103x
This output voltage range with 0000Hex corresponding output 3FFF corresponding output.
VOUT
DATA
Figure AD5061 with Opto-Isolated Interface
Power Supply Bypassing Grounding
When accuracy important circuit helpful carefully consider power supply ground return layout board. printed circuit board containing AD5061 should have separate analog digital sections, each having area board. AD5061 system where other devices require AGND DGND connection, connection should made point only. This ground point should close possible AD5061. power supply AD5061 should bypassed with capacitors. capacitors should physically close possible device with capacitor ideally right against device. capacitors tantalum bead type. important that capacitor Effective Series Resistance (ESR) Effective Series Inductance (ESI), e.g., common ceramic types capacitors. This capacitor provides impedance path ground high frequencies caused transient currents internal logic switching. power supply line itself should have large trace possible provide impedance path reduce glitch effects supply line. Clocks other fast switching digital signals should shielded from other parts board digital ground. Avoid crossover digital analog signals possible. When traces cross opposite sides board, ensure that they right angles each other reduce feedthrough effects through board. best board layout technique microstrip technique where component side board dedicated ground plane only signal traces placed solder side. However, this always possible with two-layer board.
Figure Bipolar Operation with AD5061
Using AD5061 with Opto-Isolated Interface Chip.
process-control applications industrial environments often necessary opto-isolated interface protect isolate controlling circuitry from hazardous commonmode voltages that occur area where functioning. Because AD5061 uses three-wire serial logic interface, ADuM130Xifamily ideal provide digital isolation interface. ADuM130x isolators provide three independent isolation channels variety channel configurations data rates. They operate across full range from 2.7V 5.5V, providing compatibility with lower voltage systems well enabling voltage translation functionality across isolation barrier. Figure power supply part also needs isolated. This done using transformer. side transformer, regulator provides supply required AD5061.
Rev. Page
Preliminary Technical Data
AD5040/AD5060
Outline Dimensions Dimensions shown inches
SOT23
2004Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective companies.
PR04762-0-9/04(PrB).
Rev. Page

FEATURES Single 16-Bit DAC, inl. Volt Digital Interface Capability Pow

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