1-kb High Speed Microwire Serial EEPROM FEATURES High speed opera

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1-kb High Speed Microwire Serial EEPROM FEATURES High speed opera

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CAT93HC46
1-kb High Speed Microwire Serial EEPROM FEATURES
High speed operation: volt operation Selectable word organization Sequential Read Software write protection Power-up inadvertent write protection power CMOS technology 1,000,000 program/erase cycles year data retention
E
Industrial extended temperature ranges 8-Lead PDIP, SOIC, MSOP TSSOP
packages
DESCRIPTION
CAT93HC46 1-kb Serial EEPROM memory device which configured registers either bits (ORG VCC) bits (ORG GND). Each register written read) serially using pin. CAT93HC46 manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. device designed endure 1,000,000 program/erase cycles data retention years. CAT93HC46 available 8-pin DIP, SOIC, MSOP TSSOP packages.
CONFIGURATION
Package
FUNCTIONAL SYMBOL
SOIC Package
CAT93HC46
SOIC Package MSOP Package
FUNCTIONS
TSSOP Package
Name
Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization Connection
Note: When connected VCC, organization selected. When connected ground, selected. left unconnected, then internal pullup device will select organization.
2004 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. 1008,Rev.
CAT93HC46 ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C with Respect Ground(1) -2.0 with Respect Ground -2.0 Lead Soldering Temperature secs) 300°C Output Short Circuit Current(2) RELIABILITY CHARACTERISTICS
Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 1,000,000 2000 Units Cycles/Byte Years Volts
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
D.C. OPERATING CHARACTERISTICS Industrial Temperature Range (-40°C 85°C)
Symbol ICC1 ICC2 ISB1 ISB2(5) VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Standby Supply Current (x8) Standby Supply Current (x16) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage -0.1 Limits Units Test Conditions MHz, MHz, GND, ORG=GND GND, Float VCC, VOUT VCC, 1.8V -400
-100
Note: minimum input voltage -0.5 During transitions, inputs undershoot -2.0 periods less than Maximum voltage output pins which overshoot periods less than Output shorted more than second. This parameter tested initially after design process change that affects parameter. Latch-up protection provided stresses pins from Standby Current (ISB2) (<900 nA).
Doc. 1008, Rev.
CAT93HC46
POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up Read Operation Power-up Write Operation Units
A.C. CHARACTERISTICS Industrial Temperature Range (-40°C 85°C) Symbol SKMAX tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tCSMIN tSKHI tSKLOW Parameter Maximum Clock Frequency Setup Time Hold Time Setup Time Hold Time Output Delay Output Delay Output Delay High-Z Minimum Time Minimum High Time Minimum Time Output Delay Status Valid Program/Erase Pulse Width Units Test Conditions
NOTE: This parameter tested initially after design process change that affects parameter. tPUR tPUW delays required from time stable until specified operation initiated. input levels timing reference points shown Test Conditions" table.
A.C. TEST CONDITIONS Input Rise Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages
Doc. 1008, Rev.
CAT93HC46 DEVICE OPERATION
CAT93HC46 1024-bit nonvolatile memory intended with industry standard microprocessors. CAT93HC46 organized registers either bits bits. When organized X16, seven 9-bit instructions control reading, writing erase operations device. When organized seven 10-bit instructions control operation device. CAT93HC46 operates single power supply will generate chip high voltage required during write operation. Instructions, addresses, data clocked into rising edge clock (SK). normally high impedance state, except when reading data from device, when checking ready/busy status after write operation. ready/busy status determined after start write operation selecting device high) polling pin; indicates that write operation completed, while high indicates that device ready next instruction. necessary, placed back into high impedance state shifting dummy into pin. will enter high impedance state falling edge clock (SK). Placing into high impedance state recommended applications where tied together form common DI/O pin. format instructions sent device logical start bit, 2-bit 4-bit) opcode, 6-bit byte/ word address additional when organized write operations 16-bit data field (8-bit organization).
INSTRUCTION
Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL
Start Opcode
Address A5-A0 A5-A0 A5-A0
11XXXX 00XXXX 10XXXX 01XXXX
Data Comments Read Address AN-A0 Clear Address AN-A0 D7-D0 D15-D0 Write Address AN-A0 Write Enable Write Disable Clear Addresses D7-D0 D15-D0 Write Addresses
A6-A0 A6-A0 A6-A0
11XXXXX 00XXXXX 10XXXXX 01XXXXX
Figure Sychronous Data Timing
tSKHI tDIS tCSS tDIS tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW
Doc. 1008, Rev.
CAT93HC46
Read Upon receiving READ command address (clocked into pin), CAT93HC46 will come high impedance state; after initial dummy zero bit, data will shifted out, first. output will toggle rising edge clock will stable after specified time delay (tPD0 tPD1) After data word been shifted remains asserted with clock continuing toggle, CAT93HC46 will automatically increment next address shift next data word. long continuously asserted continues toggle, device will keep incrementing next address automatically until reaches address space, then loops back address sequential READ mode, only initial data word preceeded dummy zero bit; subsequent data words will follow without dummy zero bit.
Write After receiving WRITE command, address data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self-timed clear data store cycle into specified memory location. clocking necessary after device entered self-timed mode. (Note ready/busy status CAT93HC46 determined selecting device polling pin. Since this device features Auto-Clear before write, necessary erase memory location before written into. Erase Upon receiving ERASE command address, (Chip Select) must deasserted minimum tCSMIN. falling edge will start self-timed clear cycle selected memory location. clocking necessary after device entered self-timed mode. (Note ready/busy status CAT93HC46 determined selecting device polling pin. Once cleared, content cleared location returns logical state.
Figure Read Instruction Timing
STANDBY HIGH-Z AN-1
HIGH-Z
tPD0
Figure Sequential Read Instruction Timing
Don't Care AN-1
HIGH-Z
Dummy
Address
Address
Address
Doc. 1008, Rev.
CAT93HC46
Erase/Write Enable Disable CAT93HC46 powers write disable state. writing after power-up after EWDS (write disable) instruction must first preceded EWEN (write enable) instruction. Once write enabled, will remain enabled until power device removed, EWDS instruction sent. EWDS instruction used disable CAT93HC46 write clear instructions, will prevent accidental writing clearing device. Data read normally from device regardless write enable/disable status. Erase Upon receiving ERAL command, (Chip Select) must deselected minimum tCSMIN. falling edge will start self-timed clear cycle memory locations device. clocking necessary after device entered self-timed mode. (Note ready/busy status CAT93HC46 determined selecting device polling pin. Once cleared, contents memory locations will return logical state. Figure Write Instruction Timing
HIGH-Z BUSY READY HIGH-Z AN-1 STATUS VERIFY STANDBY
Write Upon receiving WRAL command data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self-timed data write memory locations device. clocking necessary after device entered self-timed mode. ready/busy status CAT93HC46 determined selecting device polling pin. necessary memory locations cleared before WRAL command executed. Once written, contents memory locations will return logical state. Note After last data been sampled, Chip Select (CS) must brought before next rising edge clock (SK) order start self-timed high voltage cycle. This important because brought before after this specific frame window, addressed location will programmed erased.
Figure Erase Instruction Timing
HIGH-Z AN-1
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
Doc. 1008, Rev.
CAT93HC46
Figure EWEN/EWDS Instruction Timing
STANDBY
ENABLE=11 DISABLE=00
Figure ERAL Instruction Timing
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
HIGH-Z
Figure WRAL Instruction Timing
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
Doc. 1008, Rev.
CAT93HC46 ORDERING INFORMATION
Prefix Device 93HC46 Suffix -1.8 TE13 H(2)
Optional Company
Product Number 93HC46:
Temperature Range Blank Commercial Industrial Automotive Extended Package PDIP SOIC (JEDEC) SOIC (JEDEC) TSSOP
Tape Reel TE13: 2000/Reel
Revision
Operating Voltage Blank (Vcc=2.5 6.0V) (Vcc=1.8 6.0V)
available upon request
Notes: device used above example 93HC46SI-TE13 (SOIC, Industrial Temperature,Tape Reel). Product revision letter marked package suffix production date code (e.g., AYWWH.) additional information, please contact your Catalyst sales office.
Doc. 1008, Rev.
REVISION HISTORY
Date 11/11/2003 Rev. Reason Updated Features Eliminated Commercial temperature range Updated Operating Characteristics Updated Characteristics Updated Ordering Information 11/14/2003 7/27/2004 Updated Operating Characteristics revision Ordering Information
Copyrights, Trademarks Patents Trademarks registered trademarks Catalyst Semiconductor include each following:
Catalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. complete list patents issued Catalyst Semiconductor contact Company's corporate office 408.542.1000.
CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES.
Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication Revison: Issue date: Type:
1008 7/27/04 Final

1-kb High Speed Microwire Serial EEPROM FEATURES High speed opera

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