High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker Des

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High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker Des

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CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker
Description
'HC280 'HCT280 9-bit odd/even parity, generator checker devices. Both even parity outputs available checking generating parity words nine bits long. Even parity indicated output high) when even number data inputs high. parity indicated output high) when number data inputs high. Parity checking words larger than bits accomplished tying output input additional HC/HCT280 parity checker.
Features /Title (CD74 HC280 CD74 HCT28 /Subject (High Speed CMOS Logic 9-Bit Odd/E Parity
Typical Propagation Delay 17ns 15pF, 25oC Replaces LS180 Types Easily Cascadable Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC280F3A CD54HCT280F3A CD74HC280E CD74HC280MT CD74HC280M96 CD74HCT280E TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC PDIP
NOTE: When ordering, entire part number. suffix denotes tape reel. suffix denotes small-quantity reel 250.
Pinout
CD54HC280, CD54HCT280 (CERDIP) CD74HC280 (PDIP, SOIC) CD74HCT280 (PDIP) VIEW
Functional Diagram
EVEN
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±25mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Thermal Resistance (Typical, Note1) (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Specifications table, e.g., 360µA 25oC.
Switching Specifications
Input 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay, Input
SYMBOL
TEST CONDITIONS
tPLH, tPHL
50pF
15pF Propagation Delay, Input tPLH, tPHL 50pF
15pF
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
Switching Specifications
Input (Continued) 25oC Input Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay, Input Propagation Delay, Input Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes NOTES: used determine dynamic power consumption, package. VCC2 (CPD where Input Frequency, Output Frequency, Output Load Capacitance, Supply Voltage. tPLH, tPHL 50pF 15pF tPLH, tPHL 50pF 15pF tTLH, tTHL 50pF -40oC 85oC -55oC 125oC UNITS
PARAMETER Output Transition Time
SYMBOL tTLH, tTHL
TEST CONDITIONS 50pF
Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device 8607701CA CD54HC280F3A CD54HCT280F3A CD74HC280E CD74HC280M96 CD74HC280MT CD74HCT280E
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP CDIP PDIP SOIC SOIC PDIP
Package Drawing
Pins Package Plan 2500 None None None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker Des

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