August 1997 Revised September 2003 High-Speed CMOS Logic Triple 3

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August 1997 Revised September 2003 High-Speed CMOS Logic Triple 3

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CD54HC27, CD74HC27, CD54HCT27, CD74HCT27
August 1997 Revised September 2003
High-Speed CMOS Logic Triple 3-Input Gate
Description
'HC27 'HCT27 logic gates utilize silicon gate CMOS technology achieve operating speeds similar LSTTL gates with power consumption standard CMOS integrated circuits. devices have ability drive LSTTL loads. logic family functionally compatible with standard logic family.
Features
Buffered Inputs
/Title (CD74 HC27, CD74 HCT27 /Subject (High Speed CMOS Logic
Typical Propagation Delay: 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC27F3A CD54HCT27F3A CD74HC27E CD74HC27M CD74HC27MT CD74HC27M96 CD74HCT27E CD74HCT27M CD74HCT27MT CD74HCT27M96 TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC
NOTE: When ordering, entire part number. suffix denotes tape reel. suffix denotes small-quantity reel 250.
Pinout
CD54HC27, CD54HCT27 (CERDIP) CD74HC27, CD74HCT27 (PDIP, SOIC) VIEW
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC27, CD74HC27, CD54HCT27, CD74HCT27 Functional Diagram
TRUTH TABLE INPUTS OUTPUT
High Voltage Level, Voltage Level
Logic Symbol
CD54HC27, CD74HC27, CD54HCT27, CD74HCT27
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (PDIP) Package (SOIC) Package. Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC27, CD74HC27, CD54HCT27, CD74HCT27
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. -2.1 -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
(Note
Input Loading Table
INPUT UNIT LOADS
NOTE: Unit Load limit specified Electrical Specifications table, e.g. 360µA 25oC.
Switching Specifications Input
PARAMETER TYPES Propagation Delay, Input Output (Figure tPLH, tPHL 50pF Propagation Delay, Data Input Output tPLH, tPHL 15pF SYMBOL TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC27, CD74HC27, CD54HCT27, CD74HCT27
Switching Specifications Input
PARAMETER Transition Times (Figure SYMBOL tTLH, tTHL (Continued) Input Capacitance Power Dissipation Capacitance (Notes TYPES Propagation Delay, Input Output (Figure Propagation Delay, Data Input Output Transition Times (Figure Input Capacitance Power Dissipation Capacitance (Notes NOTES: used determine dynamic power consumption, gate. VCC2 (CPD where input frequency, output load capacitance, supply voltage. tPLH, tPHL tPLH, tPHL tTLH, tTHL 50pF 15pF 50pF 25oC -40oC 85oC -55oC 125oC UNITS
TEST CONDITIONS 50pF
Test Circuits Waveforms
INPUT
INPUT 2.7V 1.3V 0.3V
tTLH
tTHL
tTLH tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device 5962-8970301CA CD54HC27F3A CD54HCT27F3A CD74HC27E CD74HC27M CD74HC27M96 CD74HC27MT CD74HCT27E CD74HCT27M CD74HCT27M96 CD74HCT27MT
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP CDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC
Package Drawing
Pins Package Plan 2500 2500 None None None Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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August 1997 Revised September 2003 High-Speed CMOS Logic Triple 3

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