October 1997 Revised August 2004 High-Speed CMOS Logic 8-Line Dec
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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
October 1997 Revised August 2004
High-Speed CMOS Logic 8-Line Decoder/ Demultiplexer Inverting Noninverting
Ordering Information
PART NUMBER CD54HC138F3A CD54HC238F3A CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138M CD74HC138MT CD74HC138M96 CD74HC238E CD74HC238M CD74HC238MT CD74HC238M96 CD74HC238NSR CD74HC238PW CD74HC238PWR CD74HC238PWT CD74HCT138E CD74HCT138M CD74HCT138MT CD74HCT138M96 CD74HCT238E CD74HCT238M CD74HCT238M96 TEMP. RANGE (oC) PACKAGE CERDIP CERDIP CERDIP CERDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC TSSOP TSSOP TSSOP PDIP SOIC SOIC SOIC PDIP SOIC SOIC
Features
Select Eight Data Outputs Active 138, Active High
/Title (CD74 HC138 CD74 HCT13 CD74 HC238 CD74 HCT23 /Subject (High Speed
Port Memory Selector Three Enable Inputs Simplify Cascading Typical Propagation Delay 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5-V 5.5-V Operation Direct LSTTL Input Logic Compatibility, VIL= (Max), (Min) CMOS Input Compatibility, VOL,
Description
'HC138, 'HC238, 'HCT138, 'HCT238 high-speed silicon-gate CMOS decoders well suited memory address decoding data-routing applications. Both circuits feature power consumption usually associated with CMOS circuitry, have speeds comparable low-power Schottky logic. Both circuits have three binary select inputs (A0, A2). device enabled, these inputs determine which eight normally high outputs HC/HCT138 series which normally outputs HC/HCT238 series high. active active high enables (E1, provided ease cascading decoders. decoder's eight outputs drive low-power Schottky equivalent loads.
NOTE: When ordering, entire part number. suffixes denote tape reel. suffix denotes small-quantity reel 250.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2004, Texas Instruments Incorporated
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Pinout
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238 (CERDIP) CD74HC138, CD74HCT138, CD74HCT238 (PDIP, SOIC) CD74HC238 (PDIP, SOIC, SOP, TSSOP) VIEW
(Y7) (Y0) (Y1) (Y2) (Y3) (Y4) (Y5) (Y6)
Functional Diagram
HC/HCT HC/HCT
Signal names parentheses 'HC138 'HCT138. TRUTH TABLE 'HC138, 'HCT138 INPUTS ENABLE ADDRESS OUTPUTS
High Voltage Level, Voltage Level, Don't Care TRUTH TABLE 'HC238, 'HCT238 INPUTS ENABLE ADDRESS OUTPUTS
High Voltage Level, Voltage Level, Don't Care
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Package Thermal Impedance, (see Note (PDIP) Package 67oC/W (SOIC) Package. 73oC/W (SOP) Package 64oC/W (TSSOP) Package 108oC/W Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating, operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems, theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT A0-A2 UNIT LOADS 1.25
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
Switching Specifications Input
TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay Address Output
SYMBOL
tPLH, tPHL 50pF
15pF 50pF
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Switching Specifications Input
(Continued) 25oC Output Transition Time (Figure tTLH, tTHL 50pF Power Dissipation Capacitance (Notes Input Capacitance TYPES Propagation Delay Address Output tPLH, tPHL 50pF 15pF Enable Output HC/HCT138 Enable Output HC/HCT238 Output Transition Time (Figure Power Dissipation Capacitance (Notes Input Capacitance NOTES: used determine dynamic power consumption, gate. VCC2 (CPD where Input Frequency, Output Load Capacitance, Supply Voltage. tPLH, tPHL 50pF tPLH, tPHL 15pF tTLH, tTHL 50pF 15pF 15pF -40oC 85oC -55oC 125oC UNITS
PARAMETER Enable Output HC/HCT138
SYMBOL
TEST CONDITIONS
tPLH, tPHL 50pF
Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2005
PACKAGING INFORMATION
Orderable Device 5962-8688401EA CD54HC138F CD54HC138F3A CD54HC238F3A CD54HCT138F CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138M CD74HC138M96 CD74HC138MT CD74HC238E CD74HC238M CD74HC238M96 CD74HC238MT CD74HC238NSR CD74HC238PW CD74HC238PWR CD74HC238PWT CD74HCT138E CD74HCT138M CD74HCT138M96 CD74HCT138MT CD74HCT238E CD74HCT238M CD74HCT238M96 CD74HCT238PW CD74HCT238PWR Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP CDIP CDIP CDIP CDIP CDIP PDIP SOIC SOIC SOIC PDIP SOIC SOIC SOIC TSSOP TSSOP TSSOP PDIP SOIC SOIC SOIC PDIP SOIC SOIC TSSOP TSSOP Package Drawing Pins Package Plan None None None None None None None Pb-Free (RoHS) Green (RoHS Sb/Br) Lead/Ball Finish Call Call Call Call Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM Level-1-250C-UNLIM
2500 Green (RoHS Sb/Br) 2500 2000 2000 2500 2500 2000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2005
Orderable Device
Status
Package Type
Package Drawing
Pins Package Plan (RoHS)
Lead/Ball Finish
Peak Temp
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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