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TVP5146

NTSC / PAL / SECAM 4x10 Bit Digital Video Decoder With Macrovision Detection, YPbPr / RGB Inputs, 5 Line Comb Filter and SCART Support

TVP5146
NTSC / PAL / SECAM 4x10 Bit Digital Video Decoder With Macrovision Detection, YPbPr / RGB Inputs, 5 Line Comb Filter and SCART Support
Data Manual
November 2004
HPA Digital Audio Video
SLES084A
Contents
List of Illustrations
List of Tables
1 Introduction
Macrovision copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection) 3.3-V tolerant digital I / O ports
1.1 Detailed Functionality
HSYNC / VSYNC outputs with programmable position, polarity, and width, and FID (field ID) output Component video processing - - - Gain (contrast) and offset (brightness) adjustments Automatic component video detection (525 / 625) Color space conversion from RGB to YCbCr
Composite and S-video processing - - - - - - - - Adaptive 2-D, 5-line, adaptive comb filter for composite video inputs chroma trap available Automatic video standard detection (NTSC / PAL / SECAM) and switching Luma-peaking with programmable gain Patented CTI circuit Patented architecture for locking to weak, noisy, or unstable signals Single 14.31818-MHz reference crystal for all standards (ITU-R.BT601 and square pixel) Line-locked internal pixel sampling clock generation with horizontal- and vertical-lock signal outputs Genlock output real-time control (RTC format) for downstream video encoder synchronization
Certified Macrovision copy protection detection
Macrovision is a trademark of Macrovision Corporation. Other trademarks are the property of their respective owners.
I2C host port interface Reduced power consumption: 1.8-V digital core, 3.3-V for digital I / O, and 1.8-V analog core with power-save and power-down modes 80-terminal TQFP PowerPAD package
1.2 Applications
· · · · · · · Digital TV LCD TV / monitors DVD-R PVR PC video cards Video capture / video editing Video conferencing
1.3 Related Products
· TVP5150A / TVP5150AM1 Ultralow Power NTSC / PAL / SECAM Video Decoder With Robust Sync Detector, (SLES098)
1.4 Ordering Information
PACKAGED DEVICES TA 0°C to 70°C 80-TERMINAL PLASTIC FLAT-PACK PowerPAD TVP5146PFP
Gemstar is a trademark of Gemstar-TV Guide International. PowerPAD is a trademark of Texas Instruments.
1.5 Functional Block Diagram
YCbCr Y9:0 C9:0 FSS
Gain / Offset
GPIO Sampling Clock Timing Processor With Sync Detector
Host Interface
XTAL1
XTAL2
VS / VBLK
DATACLK
Figure 1-1. Functional Block Diagram
RESETB
1.6 Terminal Assignments
PFP PACKAGE (TOP VIEW)
Figure 1-2. Terminal Assignments Diagram
1.7 Terminal Functions
Table 1-1. Terminal Functions
Table 1-1. Terminal Functions (Continued)
Analog 1.8-V return
Analog power. Connect to 1.8 V.
Analog 3.3-V return
Analog power. Connect to 3.3 V.
Digital return Digital power. Connect to 1.8 V. Digital power return Digital power. Connect to 3.3 V or less for reduced noise. Analog power return Analog power. Connect to 1.8 V.
2 Functional Description
2.1 Analog Processing and A / D Converters
Figure 2-1 shows a functional diagram of the analog processors and ADCs. This block provides the analog interface to all video inputs. It accepts up to 10 inputs and performs source selection, video clamping, video amplification, A / D conversion, and gain and offset adjustments to center the digitized video signal.
TVP5146 Analog Front End
Clamp
10-Bit ADC
Clamp
10-Bit ADC
Line-Locked Sampling Clock
Clamp
10-Bit ADC
Clamp
10-Bit ADC
Figure 2-1. Analog Processors and A / D Converters
Video Input Switch Control
The TVP5146 decoder has 4 analog channels that accept up to 10 video inputs. The user can configure the internal analog video switches via the I2C interface. The 10 analog video inputs can be used for different input configurations, some of which are: · · · · Up to 10 selectable individual composite video inputs Up to four selectable S-video inputs Up to three selectable analog YPbPr / RGB video inputs and one CVBS input Up to two selectable analog YPbPr / RGB video inputs, two S-video inputs, and two CVBS inputs
The input selection is performed by the input select register at I2C subaddress 00h (see Section 2.11.1).
Analog Input Clamping
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection between bottom and mid clamp is performed automatically by the TVP5146 decoder.
Automatic Gain Control
The TVP5146 decoder uses four programmable gain amplifiers (PGAs), one per channel. The PGA can scale a signal with a voltage-input compliance of 0.5-VPP to 2-VPP to a full-scale 10-bit A / D output code range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain corresponds to a code 0x0 (2-VPP full-scale input, -6-dB gain) while maximum gain corresponds to code 0xF (0.5 VPP full scale, +6-dB gain). The TVP5146 decoder also has 12-bit fine gain controls for each channel and applies independently to coarse gain controls. For composite video, the input video signal amplitude can vary significantly from the nominal level of 1 VPP. The TVP5146 decoder can adjust its PGA setting automatically: an AGC can be enabled and can adjust the signal amplitude such that the maximum range of the ADC is reached without clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the TVP5146 decoder can read the gain currently being used. The TVP5146 AGC comprises the front-end AGC before Y / C separation and the back-end AGC after Y / C separation. The back-end AGC restores the optimum system gain whenever an amplitude reference such as the composite peak (which is only relevant before Y / C separation) forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references: sync height, color burst amplitude, composite peak, and luma peak. The specific amplitude references being used by the front-end and back-end AGC algorithms can be independently controlled using the AGC white peak processing register located at subaddress 74h. The TVP5146 gain increment speed and gain increment delay can be controlled using the AGC increment speed register located at subaddress 78h and the AGC increment delay register located at subaddress 79h, respectively.
A / D Converters
All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A / D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All ADC reference voltages are generated internally.
2.2 Digital Video Processing
Figure 2-2 is a block diagram of the TVP5146 digital video decoder processor. This processor receives digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs, YCbCr signal enhancements for CVBS and S-video inputs, and YPbPr / RGB processing for component video inputs. It also generates horizontal and vertical syncs and other output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide field identification, horizontal and vertical lock, vertical blanking, and active video window indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with external syncs or 10-bit 4:2:2 with embedded / separate syncs. The circuit detects pseudosync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material. Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO and / or registers for retrieval via the host port interface.
Copy Protection Detector
VBI Data Processor
Slice VBI Data Y9:0 Output Formatter C9:0 FSS
2y Decimation 2y Decimation 2y Decimation 2y Decimation XTAL1 XTAL2 RESETB PWDN DATACLK
CVBS / Y / G CVBS / Y Composite Processor YCbCr
Y / G Pb / B Pr / R Component Processor YCbCr
FID VS / VBLK Timing Processor HS / CS GLCO AVID Host Interface SCL SDA
Figure 2-2. Digital Video Processor Block Diagram
2y Decimation Filter
Composite Processor
Figure 2-3 is a block diagram of the TVP5146 digital composite video processing circuit. This circuit receives a digitized composite or S-video signal from the ADCs and performs Y / C separation (bypassed for S-video input), chroma demodulation for PAL / NTSC and SECAM, and YUV signal enhancements. The 10-bit composite video is multiplied by the subcarrier signals in the quadrature demodulator to generate color difference signals U and V. The U and V signals are then sent to low-pass filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the unique property of color phase shifts from line to line. The chroma is remodulated through a quadrature modulator and subtracted from line-delayed composite video to generate luma. This form of Y / C separation is completely complementary, thus there is no loss of information. However, in some applications, it is desirable to limit the U / V bandwidth to avoid crosstalk. In that case, notch filters can be turned on. To accommodate some viewing preferences, a peaking filter is also available in the luma path. Contrast, brightness, sharpness, hue, and saturation controls are programmable through the host port.
CVBS / Y Line Delay -
Peaking
Delay
SECAM Luma
NTSC / PAL Remodulation Contrast Brightness Saturation Adjust Notch Filter
SECAM Color Demodulation
Color LPF 2
Notch Filter
Burst Accumulator (U)
Burst Accumulator (V)
5-Line Adaptive Comb Filter Notch Filter Notch Filter Delay U
V CVBS / C NTSC / PAL Demodulation
Color LPF 2
Delay
Figure 2-3. Composite and S-Video Processor Block Diagram
2.2.2.1 Color Low-Pass Filter
High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for video sources that have asymmetrical U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters. Figure 2-4 through Figure 2-7 represent the frequency responses of the wideband color low-pass filters.
10 0 -10 Amplitude - dB -20 -30 -40 -50 -60 -70 0.0 NTSC SQP -3 dB @ 1.29 MHz ITU-R BT.601 -3 dB @ 1.42 MHz PAL SQP -3 dB @ 1.55 MHz Amplitude - dB
10 0 -10 -20 -30 -40 -50 -60 -70 0.0 Filter 1 -3 dB @ 936 kHz Filter 2 -3 dB @ 767 kHz Filter 0 -3 dB @ 1.29 MHz Filter 3 -3 dB @ 504 kHz
f - Frequency - MHz
Figure 2-4. Color Low-Pass Filter Frequency Response
Figure 2-5. Color Low-Pass Filter With Filter Frequency Response, NTSC Square Pixel Sampling
10 Filter 2 -3 dB @ 922 kHz Filter 0 -3 dB @ 1.55 MHz Filter 3 -3 dB @ 605 kHz Filter 1 -3 dB @ 1.13 MHz
10 0 -10 Amplitude - dB -20 -30 -40 -50 -60 -70 0.0 Filter 2 -3 dB @ 844 kHz Filter 0 -3 dB @ 1.41 MHz Filter 3 -3 dB @ 554 kHz Filter 1 -3 dB @ 1.03 MHz
0 -10 Amplitude - dB 4.0 -20 -30 -40 -50 -60 -70 0.0
f - Frequency - MHz
Figure 2-6. Color Low-Pass Filter With Filter Characteristics, NTSC / PAL ITU-R BT.601 Sampling
Figure 2-7. Color Low-Pass Filter With Filter Characteristics, PAL Square Pixel Sampling
2.2.2.2 Y / C Separation
10 5 0 -5 Amplitude - dB Amplitude - dB -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 f - Frequency - MHz No Notch Filter Notch 1 Filter Notch 3 Filter Notch 2 Filter 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 f - Frequency - MHz No Notch Filter Notch 1 Filter Notch 2 Filter Notch 3 Filter
Figure 2-8. Chroma Trap Filter Frequency Response, NTSC Square Pixel Sampling
10 5 0 -5 Amplitude - dB -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 f - Frequency - MHz No Notch Filter Notch 1 Filter Amplitude - dB Notch 3 Filter
Figure 2-9. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling
10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 f - Frequency - MHz No Notch Filter Notch 1 Filter Notch 3 Filter
Notch 2 Filter
Figure 2-10. Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling
Figure 2-11. Chroma Trap Filter Frequency Response, PAL Square Pixel Sampling
Luminance Processing
The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2-12 illustrates the basic functions of the luminance data path. In the case of S-video, the luminance signal bypasses the comb filter or chroma trap filter and is fed directly to the circuit. High-frequency components of the luminance signal are enhanced by a peaking filter (sharpness). Figure 2-13, Figure 2-14, and Figure 2-15 show the characteristics of the peaking filter at four different gain settings that are programmable via the host port.
Peak Detector
Bandpass Filter
Peaking Filter
Delay
Figure 2-12. Luminance Edge-Enhancer Peaking Block Diagram
Figure 2-13. Peaking Filter Response, NTSC Square Pixel Sampling
Figure 2-14. Peaking Filter Response, NTSC / PAL ITU-R BT.601 Sampling
Figure 2-15. Peaking Filter Response, PAL Square Pixel Sampling
2.2.3.1 Color Transient Improvement
Color transient improvement (CTI) enhances horizontal color transients by delay modulation for both color difference signals. The operation must be performed only on YCbCr-formatted data. The color difference signal transition points are maintained, but the edges are enhanced for signals which have bandwidth-limited color components (for example, CVBS and S-video).
Component Video Processor
Offset
Limit
Figure 2-16. Y Component Gain, Offset, Limit
CbCr x Limit CbCr
Figure 2-17. CbCr Component Gain, Offset, Limit
Color Space Conversion
The formulas for RGB to YCbCr conversion are given as:
2.3 Clock Circuits
TVP5146 74 14.31818-MHz Clock
TVP5146 74
14.31818-MHz Crystal CL1
XTAL1
XTAL2
Figure 2-18. Reference Clock Configurations
2.4 Real-Time Control (RTC)
Although the TVP5146 decoder is a line-locked system, the color burst information is used to determine accurately the color subcarrier frequency and phase. This ensures proper operation with nonstandard video signals that do not follow exactly the required frequency multiple between color subcarrier frequency and video line frequency. The frequency control word of the internal color subcarrier PLL and the subcarrier reset bit are transmitted via terminal 37 (GLCO) for optional use in an end system (for example, by a video encoder). The frequency control word is a 23-bit binary number. The instantaneous frequency of the color subcarrier can be calculated from the following equation: F PLL + F ctrl 2 23 F sclk
where FPLL is the frequency of the subcarrier PLL, Fctrl is the 23-bit PLL frequency control word, and Fsclk is two times the pixel frequency. Figure 2-19 shows the detailed timing diagram.
Valid Sample Reserved RTC
Invalid Sample
128 CLK
18 CLK 1 CLK
45 CLK 23-Bit Fsc PLL Increment
Figure 2-19. RTC Timing
2.5 Output Formatter
The output formatter sets how the data is formatted for output on the TVP5146 output buses. Table 2-1 shows the available output modes. Table 2-1. Output Format
Table 2-2. Summary of Line Frequencies, Data Rates, and Pixel / Line Counts
Fast Switches for SCART
The TVP5146 decoder supports the SCART interface used in European audio / video end equipment to carry composite video, S-video, and RGB video on the same cable. In the event that composite video and RGB video are present simultaneously on the video terminals assigned to a SCART interface, the TVP5146 decoder assumes they are pixel synchronous to each other. The timing for both composite video and RGB video is obtained from the composite source, and its derived clock is used to sample RGB video as well. The fast-switch input terminal allows switching between these two input video sources on a pixel-by-pixel basis. The fast switch is a hard switch there is no alpha blending between both sources.
Separate Syncs
525-Line 525 First Field Video 1 2 3 4 5 6 7 8 9 10 11 21 22
VS VS Start CS FID VS Stop
VBLK Start
VBLK Stop
262 Second Field Video
VS VS Start CS FID VS Stop
VBLK Start NOTE: Line numbering conforms to ITU-R BT.470
VBLK Stop
Figure 2-20. Vertical Synchronization Signals for 525-Line System
625-Line 622 First Field Video 623 624 625 1 2 3 4 5 6 7 8 23 24 25
VS VS Start CS FID VS Stop
VBLK Start
VBLK Stop
310 Second Field Video
VS VS Start CS FID VS Stop
VBLK Start NOTE: Line numbering conforms to ITU-R BT.470
VBLK Stop
Figure 2-21. Vertical Synchronization Signals for 625-Line System
DATACLK
Horizontal Blanking
SAV SAV SAV SAV Cb0 1 2 3 4
HS Start HS A B
HS Stop
Figure 2-22. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
DATACLK
Horizontal Blanking
CbCr9:0
Horizontal Blanking
Cb0 Cr0 Cb1 Cr1
HS Start HS A B D AVID
HS Stop
AVID Start
Figure 2-23. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
Pixel Clock) H / 2 858 864 780 944
Pixel Clock) H / 2 429 432 390 472
Figure 2-24. VSYNC Position With Respect to HSYNC
Embedded Syncs
2.6 I2C Host Interface
Communication with the TVP5146 decoder is via an I2C host interface. The I2C standard consists of two signals, the serial input / output data (SDA) line and the serial input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be multimastered, the TVP5146 decoder functions as a slave device only.
Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. The slave-address select signal, terminal 37 (I2CA), enables the use of two TVP5146 decoders tied to the same I2C bus by controlling the least significant bit of the I2C device address. Table 2-4. I2C Host Interface Terminal Description
SIGNAL I2CA SCL SDA TYPE I I I / O DESCRIPTION Slave address selection Input clock line Input / output data line
Reset and I2C Bus Address Selection
The TVP5146 decoder can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I2CA terminal. The TVP5146 decoder samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures the I2C bus address bit A0. The I2CA terminal has an internal pulldown resistor to pull the terminal low to set a zero. Table 2-5. I2C Address Selection
If terminal 37 is strapped to DVDD via a 2.2-k resistor, I2C device address A0 is set to 1.
I2C Operation
S 1011 1000 ACK Subaddress ACK Send data ACK P
Data transfers occur using the following illustrated formats. Read from I2C control registers
S 1011 1000 ACK Subaddress ACK S 1011 1001 ACK Receive data NAK P
VBUS Access
The TVP5146 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2-25 shows the VBUS registers access.
I2C Registers 00h
VBUS Registers 00 0000h
HOST Processor
CC WSS VITC E0h E1h E8h EAh FFh VBUS Data VBUS23:0 VBUS Address VPS FIFO Line Mode
80 051Ch 80 0520h 80 052Ch 80 0600h
80 0700h 90 1904h FF FFFFh
VBUS Write Single Byte S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
Send Data
Multiple Bytes S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
Send Data
VBUS Read Single Byte S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
Read Data
Multiple Bytes S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
Read Data
Figure 2-25. VBUS Access
I2C Timing Requirements
The TVP5146 decoder requires delays in the I2C accesses to accommodate the internal processor timing. In accordance with I2C specifications, the TVP5146 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length maximum delays are indicated in the following diagram: Normal register
S 1011 1000 ACK Subaddress ACK Send data ACK Wait 64 µs P
2.7 VBI Data Processor
The TVP5146 VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), program delivery control (PDC), vertical interval time code (VITC), video program system (VPS), copy generation management system (CGMS) data, and electronic program guide (Gemstar) 1x / 2x. Table 2-6 shows the supported VBI system. These services are acquired by programming the VDP to enable the reception of one or more VBI data standard(s) in the VBI. The VDP can be programmed on a line-per-line basis to enable simultaneous reception of different VBI formats, one per line. The results are stored in a FIFO and / or registers. Because of its high data bandwidth, the teletext results are stored in FIFO only. The TVP5146 decoder provides fully decoded V-CHIP data to the dedicated registers at subaddresses 800540h-800543h (see Sections 2.12.4 through 2.12.7). Table 2-6. Supported VBI Systems
VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is output on the Y9:2 terminals during the horizontal blanking period. Table 2-7 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of the FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard. Table 2-7. Ancillary Data Format and Sequence
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 : 0 0 0 D7 (MSB) 0 1 1 NEP NEP NEP D6 0 1 1 EP EP EP D5 0 1 1 0 F5 N5 D4 0 1 1 1 F4 N4 Data error D3 0 1 1 0 F3 N3 Match #1 D2 0 1 1 DID2 F2 N2 Match #2 D1 0 1 1 DID1 F1 N1 D0 (LSB) 0 1 1 DID0 F0 N0 Data ID (DID) Secondary data ID (SDID) Number of 32-bit data (NN) Internal data ID0 (IDID0) Video line # 9:8 Internal data ID1 (IDID1) Data byte Data byte Data byte Data byte : Data byte Check sum 0 0 0 0 Fill byte Nth word 1st word Ancillary data preamble DESCRIPTION
Video line # 7:0
1. Data 2. Data 3. Data 4. Data : m. Data CS7:0
EP: DID:
Even parity for D0-D5
NEP: Negated even parity
SDID: NN: IDID0: IDID1:
CS: Fill byte:
VBI Raw Data Output
The TVP5146 decoder can output raw A / D video data at twice the sampling rate for external VBI slicing. This is transmitted as an ancillary data block, although somewhat differently from the way the sliced VBI data is transmitted in the FIFO format as described in Section 2.7.1. The samples are transmitted during the active portion of the line. VBI raw data uses ITU-R BT.656 format having only luma data. The chroma samples are replaced by luma samples. The TVP5146 decoder inserts a four-byte preamble 000h 3FFh 3FFh 180h before data start. There are no checksum bytes and fill bytes in this mode. Table 2-8. VBI Raw Data Output Format
2.8 Reset and Initialization
Reset is initiated at power up or any time terminal 34 (RESETB) is brought low. Table 2-9 describes the status of the TVP5146 terminals during and immediately after reset. Table 2-9. Reset Sequence
SIGNAL NAME Y9:0, C9:0, DATACLK RESETB, PWDN, SDA, SCL, FSS, AVID, GLCO, HS, VS, FID INTREQ DATACLK DURING RESET Input Input Input Output RESET COMPLETED High-impedance Input Output High-impedance
POWER (3.3 V and 1.8 V)
1 ms (min)
200 ns (min) Normal Operation
RESETB (Terminal 34)
Reset 1 ms (min)
SDA (Terminal 29)
Invalid I2C Cycle
Valid
Figure 2-26. Reset Timing
STEP 1 2 3 4 5 6 7 8 9 I2C SUBADDRESS 0xE8 0xE9 0xEA 0xE0 0xE8 0xE9 0xEA 0xE0 0xE0 I2C DATA 0x02 0x00 0x80 0x01 0x60 0x00 0xB0 0x01 0x00
Afterward, the user programs the device as usual.
2.9 Adjusting External Syncs
The proper sequence to program the following external syncs is: · To set NTSC, PAL-M, NTSC 443, PAL60 (525-line modes): - - · Set the video standard to NTSC (register 02h) Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h)
To set PAL, PAL-N, SECAM (625-line modes): - - Set the video standard to PAL (register 02h) Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h)
For autoswitch, set the video standard to autoswitch (register 02h)
2.10 Internal Control Registers
The TVP5146 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire decoder. Communication between the external controller and the TVP5146 decoder is through a standard I2C host port interface, as described earlier. Table 2-10 shows the summary of these registers. Detailed programming information for each register is described in the following sections. Additional registers are accessible through an indirect procedure involving access to an internal 24-bit address wide VBUS. Table 2-11 shows the summary of the VBUS registers. NOTE: Do not write to reserved registers. Reserved bits in any defined register must be written with 0s, unless otherwise noted.
Table 2-10. Register Summary
Table 2-10. Registers Summary (Continued)
I2C SUBADDRESS 26h-27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh-30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch-3Dh 3Eh 3Fh 40h 41h 42h-43h 44h-45h 46h 47h 48h 49h 4Ah-4Bh 4Ch-4Dh 4Eh-4Fh 50h-51h 52h-6Fh 70h 71h-73h 74h 75h-77h
DEFAULT CCh 00h 00h 00h 00h 05h 00h 40h 00h FFh FFh FFh FFh 00h
20h 20h 20h 20h 900h 900h 900h 900h
Table 2-10. Registers Summary (Continued)
I2C SUBADDRESS 78h 79h 7Ah-7Fh 80h 81h 82h-B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h-C3h C4h-D5h D6h D7h D8h D9h DAh DBh-DFh E0h E1h E2h E3h-E7h E8h-E9h EBh-EFh F0h F1h
DEFAULT 05h 1Eh
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 80h 00h 00h 00h 01Eh 06h 1Bh FFh 00h FFh 00h 00h
00 0000h
Table 2-10. Registers Summary (Continued)
Table 2-11. VBUS Register Summary
REGISTER NAME Reserved VDP closed caption data VDP WSS data Reserved VDP VITC data Reserved VDP V-Chip data Reserved VDP general line mode and line address Reserved VDP VPS / Gemstar data Reserved VDP FIFO read Reserved Interrupt configuration Reserved I2C SUBADDRESS 00 0000h-80 051Bh 80 051Ch-80 051Fh 80 0520h-80 0526h 80 0527h-80 052Bh 80 052Ch-80 0534h 80 0535h-80 053Fh 80 0540h-80 0543h 80 0544h-80 05FFh 80 0600h-80 0611h 80 0612h-80 06FFh 80 0700h-80 070Ch 80 070Dh-90 1903h 90 1904h 90 1905h-B0 005Fh B0 0060h B0 0061h-FF FFFFh 00h R / W R R 00h, FFh R / W R R R R DEFAULT R / W
NOTE: Writing any value to a reserved register may cause erroneous operation of the TVP5146 decoder. It is recommended not to access any data to / from reserved registers.
2.11 Register Definitions
2.11.1 Input Select Register
Subaddress Default 7 00h 00h 6 5 4 3 2 1 0
Input select 7:0
Table 2-12. Analog Channel and Video Mode Selection
Ten input terminals can be configured to support composite, S-video, and component YPbPr / RGB or SCART as listed in Table 2-12. Users must follow this table properly for S-video and component applications because only the terminal configurations listed in Table 2-12 are supported.
2.11.2 AFE Gain Control Register
Subaddress Default 7 01h 0Fh 6 Reserved 5 4 3 1 2 1 1 AGC chroma 0 AGC luma
2.11.3 Video Standard Register
Subaddress Default 7 02h 00h 6 5 Reserved 4 3 2 1 Video standard 2:0 0
NOTE: PAL60 is not included in autoswitch mode. With the autoswitch code running, the user can force the decoder to operate in a particular video standard mode by writing the appropriate value into this register. Changing these bits causes the register settings to be reinitialized. NOTE: Sampling rate (either square pixel or ITU-R BT.601) can be set by bit 7 (sampling rate) in the output formatter 1 register at I2C subaddress 33h (see Section 2.11.35).
2.11.4 Operation Mode Register
Subaddress Default 7 03h 00h 6 5 4 Reserved 3 2 1 0 Power save
2.11.5 Autoswitch Mask Register
Subaddress Default 7 Reserved 04h 23h 6 5 SECAM 4 NTSC 4.43 3 (Nc) PAL 2 (M) PAL 1 PAL 0 (M, J) NTSC
2.11.6 Color Killer Register
Subaddress Default 7 Reserved 05h 10h 6 5 4 3 2 Color killer threshold 4:0 1 0
Automatic color killer
2.11.7 Luminance Processing Control 1 Register
Subaddress Default 7 Reserved 06h 00h 6 Pedestal not present 5 Reserved 4 VBI raw 3 2 1 0
Luminance signal delay 3:0
2.11.8 Luminance Processing Control 2 Register
Subaddress Default 7 07h 00h 6 5 Reserved 4 3 2 1 Reserved 0
Luma filter select 1:0
Peaking gain (sharpness) 1:0
2.11.9 Luminance Processing Control 3 Register
Subaddress Default 7 08h 02h 6 5 Reserved 4 3 2 1 0
Trap filter select 1:0
2.11.10 Luminance Brightness Register
Subaddress Default 7 09h 80h 6 5 4 Brightness 7:0 3 2 1 0
2.11.11 Luminance Contrast Register
Subaddress Default 7 0Ah 80h 6 5 4 Contrast 7:0 3 2 1 0
2.11.12 Chrominance Saturation Register
Subaddress Default 7 0Bh 80h 6 5 4 Saturation 7:0 3 2 1 0
2.11.13 Chroma Hue Register
Subaddress Default 7 0Ch 00h 6 5 4 Hue 7:0 3 2 1 0
2.11.14 Chrominance Processing Control 1 Register
Subaddress Default 7 0Dh 00h 6 Reserved 5 4 Color PLL reset 3 Chrominance adaptive comb enable 2 Reserved 1 0
Automatic color gain control 1:0
2.11.15 Chrominance Processing Control 2 Register
Subaddress Default 7 0Eh 0Eh 6 Reserved 5 4 3 PAL compensation 2 WCF 1 0
Chrominance filter select 1:0
2.11.16 Component Pr Saturation Register
Subaddress Default 7 10h 80h 6 5 4 3 2 1 0
Pr saturation 7:0
2.11.17 Component Y Contrast Register
Subaddress Default 7 11h 80h 6 5 4 Y contrast 7:0 3 2 1 0
2.11.18 Component Pb Saturation Register
Subaddress Default 7 12h 80h 6 5 4 3 2 1 0
Pb saturation 7:0
2.11.19 Component Y Brightness Register
Subaddress Default 7 14h 80h 6 5 4 3 2 1 0
Y brightness 7:0
2.11.20 AVID Start Pixel Register
Subaddress Default Subaddress 16h 17h Reserved 16h-17h 055h 7 6 5 4 AVID active 3 Reserved 2 1 0
AVID start 7:0 AVID start 9:8
The TVP5146 decoder updates the AVID start only when the AVID start MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets. The AVID start pixel register also controls the position of the SAV code.
2.11.21 AVID Stop Pixel Register
Subaddress Default Subaddress 18h 19h Reserved 18h-19h 325h 7 6 5 4 3 2 1 0
AVID stop 7:0 AVID stop 9:8
AVID stop 9:0: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location from HSYNC start pixel 0. default NTSC 601 805 (325h) NTSC Sqp 726 (2D6h) PAL 601 808 (328h) PAL Sqp 696 (2B8h)
The TVP5146 decoder updates the AVID stop only when the AVID stop MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets. The AVID start pixel register also controls the position of the EAV code.
2.11.22 HSYNC Start Pixel Register
Subaddress Default 1Ah-1Bh 000h
Default (000h)
Subaddress 1Ah 1Bh Reserved 7 6 5 4 3 2 1 0
HSYNC start 7:0 HSYNC start 9:8
HSYNC start pixel 9:0: This is an absolute pixel location from HSYNC start pixel 0. The TVP5146 decoder updates the HSYNC start only when the HSYNC start MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets.
2.11.23 HSYNC Stop Pixel Register
Subaddress Default Subaddress 1Ch 1Dh Reserved 1Ch-1Dh 040h 7 6 5 4 3 2 1 0
HSYNC stop 7:0 HSYNC stop 9:8
HSYNC stop 9:0: This is an absolute pixel location from HSYNC start pixel 0. The TVP5146 decoder updates the HSYNC stop only when the HSYNC Stop MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets.
2.11.24 VSYNC Start Line Register
Subaddress Default Subaddress 1Eh 1Fh Reserved 1Eh-1Fh 004h 7 6 5 4 3 2 1 0
VSYNC start 7:0 VSYNC start 9:8
VSYNC start 9:0: This is an absolute line number. The TVP5146 decoder updates the VSYNC start only when the VSYNC start MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets. NTSC: default 004h, PAL: default 001h
2.11.25 VSYNC Stop Line Register
Subaddress Default Subaddress 20h 21h Reserved 20h-21h 007h 7 6 5 4 3 2 1 0
VSYNC stop 7:0 VSYNC stop 9:8
VSYNC stop 9:0: This is an absolute line number. The TVP5146 decoder updates the VSYNC stop only when the VSYNC stop MSB byte is written to. If the user changes these registers, the TVP5146 decoder retains values in different modes until this decoder resets. NTSC: default 007h, PAL: default 004h
2.11.26 VBLK Start Line Register
Subaddress Default Subaddress 22h 23h Reserved 22h-23h 001h 7 6 5 4 3 2 1 0
VBLK start 7:0 VBLK start 9:8
VBLK start 9:0: This is an absolute line number. The TVP5146 decoder updates the VBLK start line only when the VBLK start MSB byte is written to. If the user changes these registers, the TVP5146 decoder retains values in different modes until this decoder resets. NTSC: default 001h, PAL: default 623 (26Fh)
2.11.27 VBLK Stop Line Register
Subaddress Default Subaddress 24h 25h Reserved 24h-25h 015h 7 6 5 4 3 2 1 0
VBLK stop 7:0 VBLK stop 9:8
VBLK stop 9:0: This is an absolute line number. The TVP5146 decoder updates the VBLK stop only when the VBLK stop MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets. NTSC: default 21 (15h), PAL: default 23 (17h)
2.11.28 Fast-Switch Control Register
Subaddress Default 7 28h CCh 6 Mode 2:0 5 4 Reserved 3 Reserved 2 FSS edge 1 Reserved 0 Polarity FSS
2.11.29 Fast-Switch SCART Delay Register
Subaddress Default 7 2Ah 00h 6 Reserved 5 4 3 2 FSS delay 4:0 1 0
2.11.30 SCART Delay Register
Subaddress Default 7 2Ch 00h 6 Reserved 5 4 3 2 SCART delay 4:0 1 0
2.11.31 CTI Delay Register
Subaddress Default 7 2Dh 00h 6 5 Reserved 4 3 2 1 CTI delay 2:0 0
2.11.32 CTI Control Register
Subaddress Default 7 2Eh 00h 6 CTI coring 3:0 5 4 3 2 CTI gain 3:0 1 0
2.11.33 RTC Register
Subaddress Default 7 31h 05h 6 5 Reserved 4 3 2 1 Genlock 2:0 0
2.11.34 Sync Control Register
Subaddress Default 7 32h 00h 6 Reserved 5 4 Polarity FID 3 Polarity VS 2 Polarity HS 1 VS / VBLK 0 HS / CS
2.11.35 Output Formatter 1 Register
Subaddress Default 7 Sampling rate 33h 40h 6 YCbCr code range 5 CbCr code 4 Reserved 3 2 1 Output format 2:0 0
2.11.36 Output Formatter 2 Register
Subaddress Default 7 34h 00h 6 Reserved 5 4 Y9:0 enable 3 Reserved 2 1 CLK polarity 0 Clock enable
2.11.37 Output Formatter 3 Register
Subaddress Default 7 FSS 1:0 35h FFh 6 5 AVID 1:0 4 3 GLCO 1:0 2 1 FID 1:0 0
2.11.38 Output Formatter 4 Register
2.11.39 Output Formatter 5 Register
2.11.40 Output Formatter 6 Register
2.11.41 Clear Lost Lock Detect Register
Subaddress Default 7 39h 00h 6 5 4 Reserved 3 2 1 0 Clear lost lock detect
2.11.42 Status 1 Register
Subaddress 3Ah
Read only
7 Peak white detect status 6 Line-alternating status 5 Field rate status 4 Lost lock detect 3 Color subcarrier lock status 2 Vertical sync lock status 1 Horizontal sync lock status 0 TV / VCR status
2.11.43 Status 2 Register
Subaddress 3Bh
Read only
7 Reserved 6 Weak signal detection 5 PAL switch polarity 4 Field sequence status 3 Reserved 2 1 0
Macrovision detection 2:0
2.11.44 AGC Gain Status Register
Subaddress 3Ch-3Dh
Read only
Subaddress 3Ch 3Dh Coarse gain 3:0 7 6 5 4 Fine gain 7:0 Fine gain 11:8 3 2 1 0
2.11.45 Video Standard Status Register
Subaddress 3Fh
Read only
7 Autoswitch 6 5 Reserved 4 3 2 1 Video standard 2:0 0
This register contains information about the detected video standard that the decoder is currently operating. When autoswitch code is running, this register must be tested to determine which video standard has been detected.
2.11.46 GPIO Input 1 Register
Subaddress 40h
Read only
2.11.47 GPIO Input 2 Register
Subaddress 41h
Read only
2.11.48 Vertical Line Count Register
Subaddress 42h-43h
Read only
2.11.49 AFE Coarse Gain for CH 1 Register
Subaddress Default 7 46h 20h 6 CGAIN 1 3:0 5 4 3 2 Reserved 1 0
2.11.50 AFE Coarse Gain for CH 2 Register
Subaddress Default 7 47h 20h 6 CGAIN 2 3:0 5 4 3 2 Reserved 1 0
2.11.51 AFE Coarse Gain for CH 3 Register
Subaddress Default 7 48h 20h 6 CGAIN 3 3:0 5 4 3 2 Reserved 1 0
2.11.52 AFE Coarse Gain for CH 4 Register
Subaddress Default 7 49h 20h 6 CGAIN 4 3:0 5 4 3 2 Reserved 1 0
Subaddress Default Subaddress 4Ah 4Bh Reserved 4Ah-4Bh 900h 7 6 5 4 FGAIN 1 7:0 FGAIN 1 11:8 3 2 1 0
Subaddress Default Subaddress 4Ch 4Dh Reserved 4Ch-4Dh 900h 7 6 5 4 FGAIN 2 7:0 FGAIN 2 11:8 3 2 1 0
Subaddress Default Subaddress 4Eh 4Fh Reserved 4Eh-4Fh 900h 7 6 5 4 FGAIN 3 7:0 FGAIN 3 11:8 3 2 1 0
Subaddress Default Subaddress 50h 51h Reserved 50h-51h 900h 7 6 5 4 FGAIN 4 7:0 FGAIN 4 11:8 3 2 1 0
2.11.57 ROM Version Register
Subaddress 70h
Read only
ROM version 7:0
ROM Version 7:0: ROM revision number
2.11.58 AGC White Peak Processing Register
Subaddress Default 7 Luma peak A 74h 00h 6 Reserved 5 Color burst A 4 Sync height A 3 Luma peak B 2 Composite peak 1 Color burst B 0 Sync height B
2.11.59 AGC Increment Speed Register
Subaddress Default 7 78h 06h 6 5 Reserved 4 3 2 1 AGC increment speed 3:0 0
2.11.60 AGC Increment Delay Register
Subaddress Default 7 79h 1Eh 6 5 4 3 2 1 0
AGC increment delay 7:0
2.11.61 Chip ID MSB Register
Subaddress 80h
Read only
Chip ID MSB 7:0
2.11.62 Chip ID LSB Register
Subaddress 81h
Read only
Chip ID LSB 7:0
2.11.63 VDP TTX Filter And Mask Registers
Subaddress Default Subaddress B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh B1h 00h 7 B2h 00h B3h 00h 6 B4h 00h 5 B5h 00h B6h 00h 4 B7h 00h 3 B8h 00h B9h 00h 2 BAh 00h 1 0
Filter 1 mask 1 Filter 1 mask 2 Filter 1 mask 3 Filter 1 mask 4 Filter 1 mask 5 Filter 2 mask 1 Filter 2 mask 2 Filter 2 mask 3 Filter 2 mask 4 Filter 2 mask 5
Filter 1 pattern 1 Filter 1 pattern 2 Filter 1 pattern 3 Filter 1 pattern 4 Filter 1 pattern 5 Filter 2 pattern 1 Filter 2 pattern 2 Filter 2 pattern 3 Filter 2 pattern 4 Filter 2 pattern 5
For an NABTS system, the packet prefix consists of five bytes. Each byte contains 4 data bits (D3:0) interlaced with 4 Hamming protection bits (H3:0):
Only data portion D3:0 from each byte is applied to a teletext filter function with corresponding pattern bits P3:0 and mask bits M3:0 (see Figure 2-27). The filter ignores the Hamming protection bits. For WST system (PAL or NTSC), the packet prefix consists of two bytes. The two bytes contain three bits of magazine number (M2:0) and five bits of row address (R4:0), interlaced with eight Hamming prot