µPD9991 RING TONE GENERATOR (WITH SURROUND SOUND) MOBILE PHONES

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µPD9991 RING TONE GENERATOR (WITH SURROUND SOUND) MOBILE PHONES

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INTEGRATED CIRCUIT
µPD9991
RING TONE GENERATOR (WITH SURROUND SOUND) MOBILE PHONES
DESCRIPTION
PD9991 mobile phone ring tone generator that includes on-chip surround sound function.
FEATURES
sound generation method provides realistic sound reproduction tones played same time, abundant variety tunes generated played Implements ADPCM decode functions. Simultaneous playback with MIDI also enabled. Includes high-performance converter with 16-bit resolution Supports five sampling frequency modes: kHz, kHz, kHz, 44.1 kHz, (ASI only) Provides audio serial interface bits). serial data input frequency variable between (during slave mode). Supported formats right-justified, left-justified, IIS. Includes function mixing sound source output signals audio serial input signals (only sampling supported). Includes surround function that uses real-time processing produce surround effects based real-time processing sources including sound sources audio serial input). Host connected 8-bit parallel interface. Includes output control functions vibrator built-in, various types input clocks supported. power supply voltage: (Digital pins support Power supply voltages: DVDD: 1.425 1.575 EVDD: 1.71 AVDD: 2.85 3.15 AVDD-P: 2.85 3.15 65-pin tape FBGA package body size, ball pitch)
ORDERING INFORMATION
Part number Package 65-pin tape FBGA
µPD9991F9-BA1
information this document subject change without notice. Before using this document, please confirm that this latest version.
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Document S16919EJ1V0DS00 (1st edition) Date Published January 2004 Printed Japan
2004
µPD9991
BLOCK DIAGRAM
RESET_B
AGND-P AVDD-P
CLKIN PLL1 PLL2
RDATA CLK8K TRSCK
INT_B CS_B WR_B RD_B
Lch(A)
Analog volume
Digital volume
interface
Sound source
Selector/mixer
LINEOUT_R
Rch(A)
LINEOUT_L
Lch(B) Vibrator ASIO
Rch(B)
VREF IREF
AVDD AGND
DVDD DGND
EVDD EGND
TM3,
BCLK LRCLK
VREF
Remark
DVX: DiMAGIC Virtualizer
Data Sheet S16919EJ1V0DS
IREF
µPD9991
CONFIGURATION
65-pin tape FBGA
PD9991F9-BA1
(Bottom View) KJHGFEDCBA Index Mark (Top View)
Name
Name
Name
Name
Shorted with LINEOUT_L AGND AVDD LINEOUT_R AGND AGND-P Shorted with IREF VREF AVDD-P
CLKIN RDATA TRSCK CLK8K DGND
EGND CS_B RD_B WR_B LRCLK BCLK DVDD EVDD
RESET_B DVDD Shorted with
DVDD INT_B
DGND Shorted with
Data Sheet S16919EJ1V0DS
µPD9991
NAME
ASI: AVDD: AVDD-P: AGND: AGND-P: BCLK: CS_B: CLK8K: CLKIN: DVDD: DGND: EVDD: EGND: INT_B: Address Audio serial data input Power supply analog block Power supply Ground analog block Ground clock input/output Chip select Sync clock input RDATA Clock input Data Power supply digital block Ground digital block Power supply pins Ground pins Interruption IREF: LED: LINEOUT_L: LINEOUT_R: LRCLK: PO3: RD_B: RDATA: RESET_B: TM2: TM3,TM4: TRSCK: VIB: VREF: WR_B: Current reference control output Line Line Left right clock input/output Peripheral output Parallel serial select Read Record data Reset Test mode input Test mode Clock input RDATA Vibration control output Voltage reference Write
Data Sheet S16919EJ1V0DS
µPD9991
CONTENTS
FUNCTIONS Configuration Explanation Functions Connection Unused Pins Initial State Pins Status.14
GENERAL DESCRIPTION.16 HOST INTERFACE Write Access.18 Read Access AUDIO SERIAL INTERFACE ADPCM INPUT INTERFACE.21 CLK8K TRSCK RDATA.21
5.2.1 Serial recording interface.21
REGISTERS (OTHER THAN SOUND SOURCE REGISTERS).22 Standby Setting (STNBY)
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 STDIG STPLL2 STPLL1 STASI STASO STSYNTH.24 STDAC STREF MCLK1A[6:0] MCLK1B[7:0] MCLK2A[4:0] MCLK2B[7:0] SLSORCE MIX.28 ENSRD[1:0].28 FS[2:0].29 BFS[4:0]
Master Clock Switching (MCLK1A, MCLK1B, MCLK2A, MCLK2B)
6.2.1 6.2.2 6.2.3 6.2.4
Switching/Mixing Surround Block Input Source (SLSORCE)
6.3.1 6.3.2
Surround On/Off Switching (ENSRD).28
6.4.1 6.5.1 6.5.2
Switching BCLK Switching ASIO (SLFS)
ASIO Mode Setting (SLASI).30
6.6.1
Data Sheet S16919EJ1V0DS
µPD9991
6.6.2 6.6.3 6.6.4 ASIM.30 LRCLK DAULGA[4:0] DAURGA[4:0].31 AAULGA[4:0]
Digital Volume Setting (DAULGA).
6.7.1 6.8.1 6.9.1
Digital Volume Setting (DAURGA). Analog Volume Setting (AAULGA)
6.10 Analog Volume Setting (AAURGA)
6.10.1 AAURGA[4:0].32
6.11 Settings (VIB)
6.11.1 6.11.2 VIB.33
6.12 Setting General-Purpose Output Pins (POUT).
6.12.1 POUT0 POUT3.33
6.13 Version (VER)
6.13.1 VER[1:0]
6.14 Surround Coefficient Write Register (for Speaker) (SPSRDW1, SPSRDW2)
6.14.1 SPSRDW1[7:0] 6.14.2 SPSRDW2[7:0]
6.15 Surround Coefficient Write Register (for Headphones) (HPSRDW1, HPSRDW2)
6.15.1 HPSRDW1[7:0].34 6.15.2 HPSRDW2[7:0].34
6.16 Surround Coefficient Read Register (for Speaker) (SPSRDR1, SPSRDR2)
6.16.1 SPSRDR1[7:0].35 6.16.2 SPSRDR2[7:0].35
6.17 Surround Coefficient Read Register (for Headphones) (HPSRDR1, HPSRDR2)
6.17.1 HPSRDR1[7:0] 6.17.2 HPSRDR2[7:0]
6.18 Surround Mode Setting Register (SRDRA).
6.18.1 SRDRA[7:0]
POWER STARTUP PROCEDURE Power Application Sequence Shutdown Sequence POWER SAVING FUNCTION Software Power Saving Function (command-driven) Hardware Power Saving Function powering down power supply). SETTING SEQUENCE Power Application Basic Sequence Switching Among Operation Modes.
9.2.1 9.2.2 9.2.3 9.2.4 Mute Standby switching Path switching.39
Data Sheet S16919EJ1V0DS
µPD9991
9.2.5 9.2.6 9.2.7 Surround switching ASIO mode access Sound source-DAC output.41 Sound source-ASO output.41 ASI-DAC output ASI-ASO output.42
Setting Sequence Example
9.3.1 9.3.2 9.3.3 9.3.4
Relation Between Setting Modes Internal Operations (Relation with Synchronization Clock)
STANDBY MODE 10.1 Clock Supply.44 REFERENCE SCHEMATICS 11.1 Line Pins (LINEOUT_L LINEOUT_R) 11.2 Reference Power Supply Voltage Current Supply Pins (VREF IREF).45 11.3 Power Supply.46 11.4 Outline Schematics ELECTRICAL SPECIFICATIONS 12.1 Absolute Maximum Ratings 12.2 Recommended Operating Conditions 12.3 Capacitance 12.4 Characteristics 12.5 Characteristics
12.5.1 Clock 12.5.2 Reset 12.5.3 Host interface 12.5.4 Audio serial interface
12.6 Analog Characteristics 12.7 Mode-Specific Current Consumption Characteristics PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS.58
Data Sheet S16919EJ1V0DS
µPD9991
FUNCTIONS Configuration
+1.5 +3.0 +1.8 +3.0 +3.0
DVDD Interrupt output
EVDD
AVDD
AVDD-P
INT_B CLKIN CS_B WR_B RD_B TM3, LINEOUT_L LINEOUT_R Line output amp. RESET_B Clock input Reset input
interface
interface switch
PD9991
BCLK LRCLK
Debug interface
Audio serial interface
VREF
Voltage reference analog block
IREF interface TRSCK CLK8K RDATA Vibrator control output control output
Current reference analog block
General output
DGND
EGND
AGND
AGND-P
Data Sheet S16919EJ1V0DS
µPD9991
Explanation Functions
Power supply pins
Name DVDD Function Power supply (1.5 digital block sure connect capacitor between this DGND. DGND EVDD Ground digital block Power supply sure connect capacitor between this EGND. different power supply analog power supply. EGND AVDD Ground Power supply analog sure connect capacitor between this AGND. AGND AVDD-P Ground analog block Power supply sure connect capacitor between this AGND-P. AGND-P VREF Ground block Reference voltage analog block sure connect 0.22 capacitor between this AGND. IREF Reference current analog block sure connect resistor between this AGND.
Clock system control pins
Name CLKIN Serial Input Clock input (2.688 16.128 MHz) This reference clock input that used generate internal master clock. sure input using capacitive coupling (1000 pF). RESET_B Input Hardware reset input signal. This resets PD9991. Registers initialized their initial values after reset. Function
Data Sheet S16919EJ1V0DS
µPD9991
Host interface pins
Name Function Host interface address signal input This input indicates internal register address data during host access. When transferring data When setting address internal register accessed Input Host interface address signal input This input selects access destination register during host access. Sound source block register Other block register CS_B Input Chip select input This input host interface select signal. This active (low) while host accesses host interface register. RD_B Input Host read input This active (low) while host reads host interface register. this WR_B active same time. WR_B Input Host write input This active (low) while host writes host interface register. this RD_B active same time. 10H, 10G, 10F, 8-bit host data When host accesses PD9991, address data performed. When CS_B signal inactive (high), this high impedance. INT_B Output Host interrupt output This interrupt signal transmitted from PD9991 host CPU. This used when requesting transmit/receive signals during data transfer internal status notification. Remark This used only sound source block control.
Data Sheet S16919EJ1V0DS
µPD9991
External LED, motor control output pins
Name Output Function External control output (drive output: 12.4 Characteristics) This port output pin. Settings entered writing values port setting register from host CPU. Leave this open when used. Output External motor control output (drive output: 12.4 Characteristics) This port output pin. Settings entered writing values port setting register from host CPU. Leave this open when used.
Audio serial interface pins
Name BCLK Function synchronization clock audio serial This used input output clock that times sampling frequency kHz, kHz, kHz, 44.1 kHz, kHz) that been clock serial transfers. Connect this when used. LRCLK Audio serial frame synchronization clock This used input output frame sync signal serial transfers. Connect this when used. Output Audio serial data output audio serial data's frame size registers. During master mode, either bits bits selected. During slave mode, selections made 2-bit steps within range from bits. Leave this open when used. Input Audio serial data input audio serial data's frame size registers. During master mode, either bits bits selected. During slave mode, selections made 2-bit steps within range from bits. Leave this open when used. Pull-down performed internally.
ADPCM interface pins
Name TRSCK Input Function Serial clock input ADPCM recording Pull-down performed internally. Leave this open when used. CLK8K Input Synchronization clock input ADPCM recording Pull-down performed internally. Leave this open when used. RDATA Input Data input ADPCM recording Pull-down performed internally. Leave this open when used.
Data Sheet S16919EJ1V0DS
µPD9991
DAC, line output pins
Name LINEOUT_L Output Function Sound source line output This outputs left-channel analog signal PD9991's line function. LINEOUT_R Output Sound source line output This outputs right-channel analog signal PD9991's line function.
General-purpose external output pins
Name Output Function General-purpose external output pins These pins used output control signals peripheral devices.
Test pins
Name Input Input test Leave open connect GND. Pull-down performed internally. TM3, test Leave open. Input Parallel/serial setting input (for testing) This should either left open connected GND. Pull-down performed internally. Function
Data Sheet S16919EJ1V0DS
µPD9991
Connection Unused Pins
recommended connect unused pins shown table below.
Name LRCLK BCLK TM3, TRSCK CLK8K RDATA Output Output Input Output Input Input Input Input Output Leave open. Leave open. Connect GND. Connect GND. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Recommended Connection
Initial State Pins
Name INT_B BCLK LRCLK TM3, Output Output Output Output Output During Reset hold hold High-level output Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z After Reset Low-level output Low-level output High-level output Hi-Z Input Input Low-level output Low-level output Input
Data Sheet S16919EJ1V0DS
µPD9991
Status
PD9991's status table shown below. (1/2)
Analog/ Digital Digital Digital Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Name Standby Status Control Signal LINEOUT_L AGND IREF VREF AVDD LINEOUT_R AGND AGND-P CLKIN AVDD-P DGND DVDD CS_B WR_B RD_B DGND INT_B RESET_B DVDD None None None None None None None None None None None None None None None None None Input Input Input Input Input Input Input Input Input Input Input Output Input Note Note None None None None Input Input None None None RESET_B RESET_B RESET_B RESET_B RESET_B RESET_B RESET_B RESET_B RESET_B None RESET_B RESET_B None None STDAC STREF STERF STDAC STPLL1&2 Hi-Z Note Note Note Note None None Input Input Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z High output Input HOLD HOLD Hi-Z Hi-Z Hi-Z Status Input Input Hi-Z Reset Status (RESET_B Low) Control Signal None None STDAC STREF STERF STDAC STPLL1&2 RESET_B RESET_B RESET_B RESET_B Input Input Input Input Input Input Input Input Input Input Input Input Input High output Input outputNote2 outputNote2 Status Input Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z HOLD HOLD HOLD HOLD Input Input Hi-Z outputNote2 outputNote2 outputNote2 outputNote2 Hi-Z Hi-Z Hi-Z Input Input Hi-Z After Reset
Input Input Output Output Output Output Input Input Input Input Input Output Input Output Output
Notes Differs according register setting. 6.12 Setting General-Purpose Output Pins. Registers reset initial values, signals with levels corresponding initial values output. Differs according register setting. 6.11 Settings.
Data Sheet S16919EJ1V0DS
µPD9991
(2/2)
Analog/ Digital Digital Digital Name Standby Status Control Signal EVDD LRCLK STASI, STASO Digital BCLK STASI, STASO Input Digital STASI, STASO Output Digital STASI, STASO Input Input Input Input Input Digital Digital Digital Digital Digital Digital Digital Digital Digital EGND DVDD TRSCK CLK8K RDATA None None None None STDIG STDIG None Input Input Input Input output output Input None None None None RESET_B RESET_B None Input Input Input Input Hi-Z Hi-Z Input Input Input Input Input output output Input Note RESET_B Hi-Z Hi-Z Note None Input Input Note RESET_B Hi-Z Input Note Status Reset Status (RESET_B Low) Control Signal RESET_B Hi-Z Status Input After Reset
Note description status LRCLK, BCLK, ASI, pins during standby mode, Table 1-1. Table 1-1. Status ASIO Block
Analog/ Digital Input Digital Digital Digital LRCLK BCLK InputNote InputNote Invalid Hi-Z Name (Slave) [STASI, STASO] Input Input Invalid Output Input Input Input Hi-Z Input Input Input Output Fixed Fixed Invalid Hi-Z (Master) [STASI, STASO] Output Output Invalid Output Output Output Input Hi-Z Output Output Input Output
Output Digital
Note Fixed level internally Remarks SLASI register (08H). ASIO Mode Setting. STASI STASO bits STNBY register (00H). Standby Setting.
Data Sheet S16919EJ1V0DS
µPD9991
GENERAL DESCRIPTION
Figure 2-1. Block Diagram
RESET_B
AGND-P AVDD-P
CLKIN PLL1 PLL2
RDATA CLK8K TRSCK
INT_B CS_B WR_B RD_B
Lch(A)
Analog volume
Digital volume
interface
Sound source
Selector/mixer
LINEOUT_R
Rch(A)
LINEOUT_L
Lch(B) Vibrator ASIO
Rch(B)
VREF IREF
AVDD AGND
DVDD DGND
EVDD EGND
TM3,
BCLK LRCLK
VREF
PLL1, PLL2 (CLKIN pin) Clock input range from 2.688 16.128 supported. this block, when clock with frequency this range input, multiplied generate fixed frequency clock that required internally. PLL1 generates clock signals required blocks except sound source block, PLL2 generates clock signal sound source block. interface This connects host 8-bit parallel interface. Vibrator, control output port This output port LEDs vibrator. sound source block sound source generation simultaneous tones chip, along with sequencer. sampling frequency kHz. ADPCM's playback function also chip. sampling frequency options channels, channels, channel.
Data Sheet S16919EJ1V0DS
IREF
µPD9991
Audio serial interface This interface external audio data. Five sampling frequency modes supported: kHz, kHz, kHz, 44.1 kHz, (initial value kHz). serial data input frequency variable between (during slave mode). Selector/mixer This block used switch among sound sources audio serial input. (surround) This block performs real-time surround processing. This block converts digital signals (from sound sources audio serial input) analog signals. This (D/A converter) high-performance stereo with 16-bit resolution.
Data Sheet S16919EJ1V0DS
µPD9991
HOST INTERFACE
access method from host interface described below.
Write Access
During write access, data written µPD9991 from system. write access timing shown Figures 3-2. used distinguish between address write cycles data write cycles. used distinguish between register access sound sources register access other purposes Other than sound source, Sound source). address write cycle, data write address assigned bits Operation based detection rising edge WR_B system clock. Caution sure RD_B high level during address write cycles data write cycles. Figure 3-1. Write Access (Single Access)
tsuAW thAW
CS_B twWR WR_B trcWR
RD_B
tsuD1 thD1 Write data Next address
Write address
Address write cycle
Data write cycle
Figure 3-2. Write Access (Continuous Access)
CS_B
WR_B
RD_B
Write address
Write data
Write address
Write data
Write data
Write access
Continuous write access
Remark
CS_B level during write period. necessary always CS_B level during continuous write access. D.C: Don't care
Data Sheet S16919EJ1V0DS
µPD9991
Read Access
During read access, data read from system PD9991. read access timing shown below. used distinguish between address write cycles data read cycles. used distinguish between register access sound sources register access other purposes Other than sound source, Sound source). Operation based detection rising edge WR_B RD_B system clock. address write cycle, data write address assigned bits Figure 3-3. Read Access (Single Access)
tsuAR thAR
CS_B
WR_B twRD RD_B taccDO Read address tdDO Read data Next address trcRD
Address write cycle
Data read cycle
Figure 3-4. Read Access (Continuous Access)
CS_B
WR_B
RD_B
Read address
Read data
Read address
Read data
Read data
Read access
Continuous read access
Remark
CS_B level during read period. necessary always CS_B level during continuous read access. D.C: Don't care
Data Sheet S16919EJ1V0DS
µPD9991
AUDIO SERIAL INTERFACE
When LRCLK SLASI register (08H), L-ch data assigned during high-level period LRCLK R-ch data assigned during low-level period LRCLK. format, this reversed, which case LRCLK should set. Within each these periods, format switched among right-justified, left-justified, format. Selection master mode slave mode also enabled. number data bits frame BFS[4:0] bits SFSL register (07H). serial input/output timing shown Figures 4-3. Figure 4-1. Right-justified Format
1/fs LRCLK BCLK
Figure 4-2. Left-justified Format
1/fs LRCLK BCLK
Figure 4-3. Format
1/fs LRCLK BCLK
Remarks format left-justified with empty sets L-ch level R-ch high level. specify other settings when selecting mode (ASIM SLASI register (08H)). When selecting mode (ASIM SLASI register (08H)), left right justification selected combination with normal reversed left-right format. number data bits frame BFS[4:0] bits SFSL register (07H). During master mode, either bits bits selected. During slave mode, value between bits bits selected two-bit increments. After reset cleared, default frame configuration setting bits total bits L-ch bits R-ch).
Data Sheet S16919EJ1V0DS
µPD9991
ADPCM INPUT INTERFACE CLK8K
This input clock signal used external synchronization when recording. During playback, this clock signal generated based signal generated PD9991, during recording this signal generated based clock signal input from external source. Caution synchronization clock signal being input from external source during recording, recorded data cannot saved. Figure 5-1. Synchronization During ADPCM Recording
signal
Internal signal Standby signal Synchronization
signal auto-generated according clock control settings
TRSCK RDATA
ADPCM input interface external synchronous serial interface used input output linear data. 5.2.1 Serial recording interface timing external synchronous serial interface shown below. Figure 5-2. Timing External Synchronous Serial Interface
TRSCK (256 kHz) CLK8K kHz) RDATA (min.) (min.) I_CLK8K's falling edge "don't care"
Start (I_CLK8K) detected during system clock cycles
Internal data latched during system clock cycles
Transfer ADPCM recorded data performed synchronization with external sync signal external serial clock. Latching data performed falling edge serial clock data latched first 16-bit segments. case 16-bit linear data (two's complement format), bits valid, case µ-law 8-bit data, higher bits ignored only lower bits contain valid data. Caution Input CLK8K detected only rising edge.
Data Sheet S16919EJ1V0DS
µPD9991
REGISTERS (OTHER THAN SOUND SOURCE REGISTERS)
Registers other than sound source registers described below. Caution Information sound source registers will disclosed only parties that have signed (Non Disclosure Agreement). Table 6-1. List Control Registers
Address Initial Value MCLK2B[7:0] SLSORCE STDIG STPLL2 STPLL1 STASI STASO STSYNTH STDAC MCLK1A[6:0] MCLK1B[7:0] MCLK2A[4:0] STREF standby setting Master clock setting Master clock setting Master clock setting Master clock setting Source input mixing settings BFS[4:0] ENSRD[1:0] FS[2:0] Surround Frequency switching ASIO BCLK setting POUT3 DAULGA[4:0] DAURGA[4:0] AAULGA[4:0] AAURGA[4:0] POUT2 POUT1 POUT0 ASIM LRCLK Note setting Digital Volume value Digital Volume value SLASI DAULGA DAURGA ENSRD SLFS Control Description Register Name STNBY MCLK1A MCLK1B MCLK2A MCLK2B SLSORCE
Analog Volume value AAULGA Analog Volume value AAURGA output settings User port output setting version POUT SPSRDW1 SPSRDW2 HPSRDW1 HPSRDW2 SPSRDR1 SPSRDR2 HPSRDR1 HPSRDR2 SRDRA
VER[1:0]
SPSRDW1[7:0] SPSRDW2[7:0] HPSRDW1[7:0] HPSRDW2[7:0] SPSRDR1[7:0] SPSRDR2[7:0] HPSRDR1[7:0] HPSRDR2[7:0] SRDRA[7:0]
Undefined surround coefficient Undefined surround coefficient Undefined surround coefficient Undefined surround coefficient surround coefficient surround coefficient surround coefficient surround coefficient Surround mode setting
Note
Differs according version. Bits marked with "don't care" bits.
Remark
Data Sheet S16919EJ1V0DS
µPD9991
Standby Setting (STNBY)
This register sets standby mode. Address: 00H, register name: STNBY, block: general, access: R/W, initial value:
STDIG STPLL2 STPLL1 STASI STASO STSYNTH STDAC STREF
6.1.1 STDIG
Data Mode Standby Initial Value Standby digital block Normal operation Description
6.1.2 STPLL2
Data Mode Standby Initial Value Standby PLL2 Normal operation Description
Remark
During PLL2 standby mode (power down), PLL2 output clock stopped.
6.1.3 STPLL1
Data Mode Standby Initial Value Standby PLL1 Normal operation Description
Remark 6.1.4 STASI
Data
During PLL1 standby mode (power down), PLL1 output clock stopped.
Mode Standby
Initial Value
Description Standby audio serial interface input (ASI) Normal operation
6.1.5 STASO
Data Mode Standby Initial Value Description Standby audio serial interface output (ASO) Normal operation
Caution LRCLK BCLK operate standby mode only when both STASI STASO bits have been standby. details, Table 1-1. Status ASIO Block.
Data Sheet S16919EJ1V0DS
µPD9991
6.1.6 STSYNTH
Data Mode Standby Initial Value Description Standby sound source block (Synthesizer) Normal operation
6.1.7 STDAC
Data Mode Standby Initial Value Standby blockNote Normal operation Description
Note
This standby signal shared analog block analog volume function.
6.1.8 STREF
Data Mode Standby Initial Value Description Standby voltage/current reference blockNote Normal operation
Note
This standby signal analog block's voltage reference current reference sources.
Data Sheet S16919EJ1V0DS
µPD9991
Master Clock Switching (MCLK1A, MCLK1B, MCLK2A, MCLK2B)
These registers master clock master clock Address: 01H, register name: MCLK1A, block: PLL1, access: R/W, initial value:
MCLK1A[6:0]
Address: 02H, register name: MCLK1B, block: PLL1, access: R/W, initial value:
MCLK1B[7:0]
Address: 03H, register name: MCLK2A, block: PLL2, access: R/W, initial value:
MCLK2A[4:0]
Address: 04H, register name: MCLK2B, block: PLL2, access: R/W, initial value:
MCLK2B[7:0]
6.2.1 MCLK1A[6:0]
Data MCLK1A[6:0] Mode Initial Value Description Sets PLL1, used generate audio master clock.
6.2.2 MCLK1B[7:0]
Data MCLK1B[7:0] Mode Initial Value Description Sets PLL1, used generate audio master clock.
6.2.3 MCLK2A[4:0]
Data MCLK2A[4:0] Mode Initial Value Description Sets PLL2, used generate sound source master clock.
6.2.4 MCLK2B[7:0]
Data MCLK2B[7:0] Mode Initial Value Description Sets PLL2, used generate sound source master clock.
Master clock setting examples shown below.
Data Sheet S16919EJ1V0DS
µPD9991
Audio master clock setting This sets clock frequency supplied blocks except sound source block. sure MCLK1A MCLK1B registers according input clock frequency sampling frequency. input clock signal first divided value MCLK1A register then multiplied value MCLK1B register.
CLKIN Input Frequency [MHz] 2.688 5.376 12.000 12.600 13.000 14.400 16.128 2.688 5.376 12.000 12.600 13.000 14.400 16.128 2.688 5.376 12.000 12.600 13.000 14.400 16.128 2.688 5.376 12.000 12.600 13.000 14.400 16.128 2.688 5.376 12.000 12.600 13.000 14.400 16.128 MCLK1A (Dec) (HEX) MCLK1B (Dec) (HEX) Sampling Frequency [kHz] 44.1 44.1 44.1 44.1 44.1 44.1 44.1 Internal Sampling Frequency [kHz] 44.1000 44.1000 44.0995 44.1051 44.0995 44.1000 44.1000 48.0000 48.0000 48.0091 48.0035 48.0042 48.0000 48.0000 32.0000 32.0000 32.0060 32.0023 32.0028 32.0000 32.0000 8.0000 8.0000 8.0015 8.0006 8.0007 8.0000 8.0000 16.0000 16.0000 16.0030 16.0012 16.0014 16.0000 16.0000 Error Master Clock Frequency Audio [MHz] 22.57920 22.57920 22.57895 22.58182 22.57895 22.57920 22.57920 24.57600 24.57600 24.58065 24.57778 24.57813 24.57600 24.57600 24.57600 24.57600 24.58065 24.57778 24.57813 24.57600 24.57600 24.57600 24.57600 24.58065 24.57778 24.57813 24.57600 24.57600 24.57600 24.57600 24.58065 24.57778 24.57813 24.57600 24.57600
[Hz]
0.00 0.00 -0.49 5.11 -0.49 0.00 0.00 0.00 0.00 9.07 3.47 4.15 0.00 0.00 0.00 0.00 6.05 2.31 2.77 0.00 0.00 0.00 0.00 1.51 0.58 0.69 0.00 0.00 0.00 0.00 3.02 1.16 1.38 0.00 0.00
0.0000 0.0000 -0.0011 0.0116 -0.0011 0.0000 0.0000 0.0000 0.0000 0.0189 0.0072 0.0086 0.0000 0.0000 0.0000 0.0000 0.0189 0.0072 0.0086 0.0000 0.0000 0.0000 0.0000 0.0189 0.0072 0.0086 0.0000 0.0000 0.0000 0.0000 0.0189 0.0072 0.0086 0.0000 0.0000
Data Sheet S16919EJ1V0DS
µPD9991
Sound source master clock setting This sets frequency clock supplied sound source block. sure values MCLK2A MCLK2B registers according input clock frequency. input clock signal first divided value MCLK2A register then multiplied value MCLK2B register.
CLKIN Input Frequency [MHz] 2.688 5.376 12.000 12.600 13.000 14.400 16.128 MCLK2A MCLK2B Sampling Frequency [kHz] Internal Sampling Frequency [kHz] 32.0000 32.0000 32.0000 32.0092 32.0047 32.0000 32.0000 Error Master clock frequency sound source [MHz] 55.10400 55.10400 55.20000 55.44000 54.60000 55.20000 55.10400
(Dec)
(HEX)
(Dec)
(HEX)
[Hz]
0.00 0.00 0.00 9.24 4.69 0.00 0.00
0.0000 0.0000 0.0000 0.0289 0.0147 0.0000 0.0000
Data Sheet S16919EJ1V0DS
µPD9991
Switching/Mixing Surround Block Input Source (SLSORCE)
This register used switching mixing surround block's input source. Address: 05H, register name: SLSORCE, block: Selector, access: R/W, initial value:
SLSORCE
6.3.1 SLSORCE
Data Mode SYNTH Initial Value Description Select input from sound source (synthesizer) Select input from audio serial interface input (ASI)
6.3.2
Data Mode Path selection Initial Value Description Only path used output from either sound source (set SLSORCE). Mixing Mixes sound source signals (SLSORCE setting invalid).
Cautions Mixing mode supported only when sampling frequency kHz. Consequently, when setting sure FS[2:0] bits SLFS register (07H) 000B (see Switching BCLK Switching ASIO (SLFS)). sound source signal exceeds full scale, output signal will clipped. When setting while ASIO slave mode SLASI register (08H)), sure STASI SLASI register (08H) input BCLK LRCLK. When stopping input using sound source only, retain settings STASI SLSORCE
Surround On/Off Switching (ENSRD)
This switches surround function off. Address: 06H, register name: ENSRD, block: DVX, access: R/W, initial value:
ENSRD[1:0]
6.4.1 ENSRD[1:0]
Data Mode Initial Value Description Surround processing performed. coefficient SP's coefficient setting registers (addresses 41H) used perform surround processing. coefficient HP's coefficient setting registers (addresses 43H) used perform surround processing. Setting prohibited
Caution Reading writing surround coefficient enabled only when ENSRD[1:0] 00B.
Data Sheet S16919EJ1V0DS
µPD9991
Switching BCLK Switching ASIO (SLFS)
This sets ASI's sampling rate frequency BCLK. Address: 07H, register name: SLFS, block: ASIO, access: R/W, initial value:
BFS[4:0] FS[2:0]
6.5.1 FS[2:0]
Data 000B 001B 010B 100B 101B Mode 44.1 Initial Value 000B Description Sets ASIO's sampling rate kHz. Sets ASIO's sampling rate 44.1 kHz. Sets ASIO's sampling rate kHz. Sets ASIO's sampling rate kHz. Sets ASIO's sampling rate kHz.
Caution sure this tandem with master clock setting (set each sampling frequency). data that shown above. When setting sampling rate kHz, also data address F3H. 6.5.2 BFS[4:0]
Data Mode Initial Value Description Sets BCLK frequency (can during master mode). Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency. Sets BCLK frequency (can during master mode).
Caution During master mode only (00H) (10H) set. other value set, (the initial value) will selected. During slave mode sampling frequency from increments.
Data Sheet S16919EJ1V0DS
µPD9991
ASIO Mode Setting (SLASI)
This specifies setting shown below. Address: 08H, register name: SLASI, block: ASIO, access: R/W, initial value:
ASIM LRCLK
6.6.1
Data Mode Initial Value Right-justified format Left-justified format Description
6.6.2
Data Mode SLAVE MASTER Initial Value Slave mode Master mode Description
Caution During slave mode, external clock input required. description status ASIO block during various modes, Status. 6.6.3 ASIM
Data Mode Initial Value mode mode this case, "don't care" bit). Description
6.6.4 LRCLK
Data Mode Initial Value Description When LRCLK high level, this specifies channel data. When LRCLK high level, this specifies channel data.
Caution sure LRCLK when mode selected.
Data Sheet S16919EJ1V0DS
µPD9991
Digital Volume Setting (DAULGA)
This sets channel's digital gain. Address: 09H, register name: DAULGA, block: Digital Volume, access: R/W, initial value:
DAULGA[4:0]
6.7.1 DAULGA[4:0]
Data DAULGA[4:0] Mode Initial Value Sets digital gain Description
Digital Volume Setting (DAURGA)
This sets channel's digital gain. Address: 0AH, register name: DAURGA, block: Digital Volume, access: R/W, initial value:
DAURGA[4:0]
6.8.1 DAURGA[4:0]
Data DAURGA[4:0] Mode Initial Value Sets digital gain Description
Table 6-1. Digital Volume (5-Bit Non-Linear)
Gain DAULGA[4:0]/ DAURGA[4:0] (Initial value) Mute Gain DAULGA[4:0]/ DAURGA[4:0]
Data Sheet S16919EJ1V0DS
µPD9991
Analog Volume Setting (AAULGA)
This sets channel's analog gain. Address: 0BH, register name: AAULGA, block: Analog Volume, access: R/W, initial value:
AAULGA[4:0]
6.9.1 AAULGA[4:0]
Data AAULGA[4:0] Mode Initial Value Sets analog gain Description
6.10 Analog Volume Setting (AAURGA)
This sets channel's analog gain. Address: 0CH, register name: AAURGA, block: Analog Volume, access: R/W, initial value:
AAURGA[4:0]
6.10.1 AAURGA[4:0]
Data AAURGA[4:0] Mode Initial Value Sets analog gain Description
Table 6-2. Analog Volume (5-Bit Linear)
Gain AAULGA[4:0] AAURGA[4:0] -1.5 -4.5 -7.5 -10.5 -13.5 -16.5 -19.5 -22.5 -25.5 -28.5 -31.5 -34.5 -37.5 -40.5 -43.5 Mute Gain AAULGA[4:0] AAURGA[4:0] (Initial value)
Data Sheet S16919EJ1V0DS
µPD9991
6.11 Settings (VIB)
This register used control output port vibrator LED. Address: 0DH, register name: VIB, block: Analog Volume, access: R/W, initial value:
6.11.1
Data Mode Initial Value Low-level output from High-level output from Description
6.11.2
Data Mode Initial Value Low-level output from High-level output from Description
Caution both VIB, register value output PD9991's pins.
6.12 Setting General-Purpose Output Pins (POUT)
This sets output level general-purpose output pins (pins PO3). Address: 0EH, register name: POUT, block: access: R/W, initial value:
POUT3 POUT2 POUT1 POUT0
6.12.1 POUT0 POUT3
Data Mode HIGH Initial Value Description Low-level output from corresponding pins PO3. High-level output from corresponding pins PO3.
Caution When digital block standby mode (address 00H, STDIG output from pins held level POUT0 POUT3. details, Table Status ASIO Block Status.
6.13 Version (VER)
This displays LSI's version information. Address: 3FH, register name: VER, block: other, access: initial value: differs depending version
VER[1:0]
6.13.1 VER[1:0]
Data VER[1:0] Mode Initial Value version Description
Data Sheet S16919EJ1V0DS
µPD9991
6.14 Surround Coefficient Write Register (for Speaker) (SPSRDW1, SPSRDW2)
This register used write surround coefficient speaker. Address: 40H, register name: SPSRDW1, block: DVX, access: initial value: undefined
SPSRDW1[7:0]
Address: 41H, register name: SPSRDW2, block: DVX, access: initial value: undefined
SPSRDW2[7:0]
6.14.1 SPSRDW1[7:0]
Data SPSRDW1[7:0] Mode Initial Value Undefined Description Surround coefficient setting register (for speaker)
6.14.2 SPSRDW2[7:0]
Data SPSRDW2[7:0] Mode Initial Value Undefined Description Surround coefficient setting register (for speaker)
6.15 Surround Coefficient Write Register (for Headphones) (HPSRDW1, HPSRDW2)
This register used write surround coefficient headphones. Address: 42H, register name: HPSRDW1, block: DVX, access: initial value: undefined
HPSRDW1[7:0]
Address: 43H, register name: HPSRDW2, block: DVX, access: initial value: undefined
HPSRDW2[7:0]
6.15.1 HPSRDW1[7:0]
Data HPSRDW1[7:0] Mode Initial Value Undefined Description Surround coefficient setting register (for headphones)
6.15.2 HPSRDW2[7:0]
Data HPSRDW2[7:0] Mode Initial Value Undefined Description Surround coefficient setting register (for headphones)
Cautions access surround coefficient write registers (40H, 41H, 42H, 43H), first write surround address setting register, then continuously write data times. Writing data times sets values that stores internal surround coefficients. surround coefficient must written using continuous write access. Even CS_B goes high level during continuous write operation control switches another device, surround coefficient written without problem accessed following previous write operation when CS_B goes level. interrupt (INT_B) occurs while data being written continuously, start over writing surround address setting register again. Reading writing surround coefficients enabled only when ENSRD[1:0] 00B.
Data Sheet S16919EJ1V0DS
µPD9991
6.16 Surround Coefficient Read Register (for Speaker) (SPSRDR1, SPSRDR2)
This register used read surround coefficient speaker. Address: 44H, register name: SPSRDR1, block: DVX, access: initial value:
SPSRDR1[7:0]
Address: 45H, register name: SPSRDR2, block: DVX, access: initial value:
SPSRDR2[7:0]
6.16.1 SPSRDR1[7:0]
Data SPSRDR1[7:0] Mode Initial Value Description Surround coefficient setting register (for speaker)
6.16.2 SPSRDR2[7:0]
Data SPSRDR2[7:0] Mode Initial Value Description Surround coefficient setting register (for speaker)
6.17 Surround Coefficient Read Register (for Headphones) (HPSRDR1, HPSRDR2)
This register used read surround coefficient headphones. Address: 46H, register name: HPSRDR1, block: DVX, access: initial value:
HPSRDR1[7:0]
Address: 47H, register name: HPSRDR2, block: DVX, access: initial value:
HPSRDR2[7:0]
6.17.1 HPSRDR1[7:0]
Data HPSRDR1[7:0] Mode Initial Value Description Surround coefficient setting register (for headphones)
6.17.2 HPSRDR2[7:0]
Data HPSRDR2[7:0] Mode Initial Value Description Surround coefficient setting register (for headphones)
Cautions access surround coefficient read registers (44H, 45H, 46H, 47H), first write surround address setting register, then continuously read data times. Reading data times sets values that stores internal surround coefficients. surround coefficient must read using continuous read access. Even CS_B goes high level during continuous read operation control switches another device, surround coefficient read without problem accessed following previous read operation when CS_B goes level. interrupt (INT_B) occurs while data being read continuously, start over writing surround address setting register again. Reading writing surround coefficients enabled only when ENSRD[1:0] 00B.
Data Sheet S16919EJ1V0DS
µPD9991
6.18 Surround Mode Setting Register (SRDRA)
This register sets mode reading/writing surround coefficients. Address: 48H, register name: SRDRA, block: DVX, access: R/W, initial value:
SRDRA[7:0]
6.18.1 SRDRA[7:0]
Data SRDRA[7:0] Mode Initial Value Sets access surround register Description
Caution SRDRA[7:0] 00H.
Data Sheet S16919EJ1V0DS
µPD9991
POWER STARTUP PROCEDURE
PD9991 includes four power supply units: internal digital logic block power supply (DVDD), PLL1/PLL2 power supply (AVDD-P), internal analog circuit's power supply (AVDD), circuit's power supply (EVDD).
Power Application Sequence
With RESET_B level, turn power supply units (DVDD, AVDD, AVDD-P, EVDD). recommend turning four these units same time. Wait until power supply voltage reaches specified voltage value. Cancel hardware reset. cancel, RESET_B high level.
Shutdown Sequence
With RESET_B level, turn power supply units (DVDD, AVDD, AVDD-P, EVDD). recommend turning four these units same time. After power-down, status RESET_B undefined.
POWER SAVING FUNCTION Software Power Saving Function (command-driven)
PD9991 includes power saving function (standby mode) that controlled command input. details, Standby Setting.
Hardware Power Saving Function powering down power supply)
addition software power saving function, hardware power saving function available. such cases, note with caution that data written registers memory will deleted sure rewrite this data after canceling power saving operation). Follow steps described below when setting hardware power saving. With RESET_B level, turn DVDD, AVDD, AVDD-P. Continue supplying EVDD since used protect line. sure RESET_B level during hardware power saving operation. Follow steps described below cancel hardware power saving. With RESET_B level, turn DVDD, AVDD, AVDD-P. RESET_B high level.
Data Sheet S16919EJ1V0DS
µPD9991
SETTING SEQUENCE Power Application
Steps Items Cancel hardware reset sampling frequency Cancel standby Cancel standby Internal clock valid Target Register, etc. RESET_B (low high) MCLK1A, MCLK1B, MCLK2A, MCLK2B STPLL1, STPLL2, STREF STSYNTH, STDIG, STASI, STASO, STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed.
Basic Sequence Switching Among Operation Modes
Steps Items Lower analog volume step step (recommended) analog volume mute standby mode AAULGA, AAURGA STPLL1, STPLL2, STREF, STSYNTH, STDIG, STASI, STASO, STDAC Switch sound source/audio path Switching surround on/off setting sampling frequency ASIO mode Cancel standby Cancel standby Internal clock valid SLSORCE ENSRD ASIM, LRCLK, STPLL1, STPLL2, STREF STSYNTH, STDIG, STASI, STASO, STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed. Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
Remarks During slave mode, input LRCLK BCLK required. Setting mute after using analog volume control lower volume step step raise volume after canceling mute setting performed order eliminate audible change sound that occur single-frame operation errors digital data that generated while switching. example raising lowering volume step step shown below. Example STEP (minimum unit) Cycle (time step) raising lowering step These values merely example from company's evaluations. Adjustments each should made determined manufacturer. STDIG signal also used reset operations such digital filter operations, required when switching modes.
Data Sheet S16919EJ1V0DS
µPD9991
9.2.1 Mute
Steps Items Lower analog volume step step (recommended) analog volume mute AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
9.2.2 Standby
Steps Items Lower analog volume step step (recommended) analog volume mute standby mode Cancel standby Cancel standby Internal clock valid Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA STPLL1, STPLL2, STREF, STSYNTH, STDIG, STASI, STASO, STDAC STPLL1, STPLL2, STREF STSYNTH, STDIG, STASI, STASO, STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed. AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
9.2.3 switching
Steps Items Lower analog volume step step (recommended) analog volume mute standby mode sampling frequency Cancel standby Cancel standby Internal clock valid Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA STPLL1, STPLL2, STREF, STSYNTH, STDIG, STASI, STASO, STDAC STPLL1, STPLL2, STREF STSYNTH, STDIG, STASI, STASO, STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed. AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
9.2.4 Path switching
Steps Items Lower analog volume step step (recommended) analog volume mute Switch sound source/audio path Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA SLSORCE AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
Caution Data incorrect frame.
Data Sheet S16919EJ1V0DS
µPD9991
9.2.5 Surround switching
Steps Items Lower analog volume step step (recommended) analog volume mute Switching surround on/off setting Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA ENSRD AAULGA, AAURGA AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
Caution Data incorrect frame. 9.2.6 ASIO mode
Steps Items Lower analog volume step step (recommended) analog volume mute standby mode AAULGA, AAURGA STPLL1, STPLL2, STREF, STSYNTH, STDIG, STASI, STASO, STDAC ASIO mode Cancel standby Cancel standby Internal clock valid ASIM, LRCLK, STPLL1, STPLL2, STREF STSYNTH, STDIG, STASI, STASO, STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed. Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
Caution Data incorrect frame. 9.2.7 access
Steps Items After power application Address specification Data transfer Target Register, etc. RESET_B (See Power Application.) Address specification Data transfer
Data Sheet S16919EJ1V0DS
µPD9991
Setting Sequence Example
9.3.1 Sound source-DAC output Power application
Steps Items Cancel hardware reset sampling frequency Sound source/audio path switching Cancel standby Cancel standby Internal clock valid Target Register, etc. RESET_B (low high) MCLK1A, MCLK1B, MCLK2A, MCLK2B SLSORCE STPLL1 STPLL2 STREF STDIG STSYNTH STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed.
Sound source setting Sound source data transfer Volume
Steps Items Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
9.3.2 Sound source-ASO output Power application
Steps Items Cancel hardware reset sampling frequency Sound source/audio path switching ASIO mode Cancel standby Cancel standby Internal clock valid Target Register, etc. RESET_B (low high) MCLK1A, MCLK1B, MCLK2A, MCLK2B SLSORCE ASIM, LRCLK, STPLL1 STPLL2 STREF STDIG STSYNTH STDAC After canceling standby STDIG STSYNTH, normal operation begins after least have elapsed.
Sound source setting Sound source data transfer
Data Sheet S16919EJ1V0DS
µPD9991
9.3.3 ASI-DAC output Power application
Steps Items Cancel hardware reset sampling frequency Sound source/audio path switching ASIO mode Cancel standby Cancel standby Internal clock valid Target Register, etc. RESET_B (low high) MCLK1A, MCLK1B, MCLK2A, MCLK2B kHz, 44.1 kHz, SLSORCE ASIM, LRCLK, STPLL1 STREF STDIG STDAC After canceling standby STDIG, normal operation begins after least have elapsed.
Music data transmission Volume
Steps Items Cancel analog volume mute Raise analog volume step step (recommended) AAULGA, AAURGA AAULGA, AAURGA Target Register, etc.
9.3.4 ASI-ASO output Power application
Steps Items Cancel hardware reset sampling frequency Sound source/audio path switching ASIO mode Cancel standby Cancel standby Internal clock valid Target Register, etc. RESET_B (low high) MCLK1A, MCLK1B, MCLK2A, MCLK2B kHz, 44.1 kHz, SLSORCE ASIM, LRCLK, STPLL1 STREF STDIG STDAC After canceling standby STDIG, normal operation begins after least have elapsed.
Music data transmission
Data Sheet S16919EJ1V0DS
µPD9991
Relation Between Setting Modes Internal Operations (Relation with Synchronization Clock)
Table 9-1. Relation Between Setting Modes Internal Operations (Relation with Synchronization Clock)
Function Register SLSORCE STASI STASO LRCLK, BCLK (Signal) Status Sync. Clock sync_lr Slave mode, sound source path, standby during Slave mode, sound source path, standby, output slave synth Signal input External Invalid Sound sourceASO Uses external synchronization clock. external LRCLK signal been input, outputs stopped. Slave mode, audio path, input, standby slave audio Signal input External Hi-Z ASI-DAC Uses external synchronization clock. external LRCLK signal been input, outputs stopped. Slave mode, audio path, input, output slave audio Signal input External ASI-ASO Uses external synchronization clock. external LRCLK signal been input, outputs stopped. Master mode, sound source path, standby during Master mode, sound source path, standby, output Master mode, audio path, input, standby Master mode, audio path, input, output master audio Signal output Internal ASI-ASO internal clock operates. master audio Signal output Internal Hi-Z ASI-DAC internal clock operates. master synth Signal output Internal Invalid Sound sourceASO internal clock operates. master synth output Internal Invalid Hi-Z Sound sourceDAC internal clock operates. slave synth Input/ internal Internal Invalid Hi-Z Sound sourceDAC Even though slave mode been set, internal clock operates. LINE_OUT (DAC) Actual Remark
Remark
operations Table apply operations mixing mode (address 05H, Therefore, when setting mixing (MIX while ASIO slave mode (address 08H, sure STASI input BCLK LRCLK. When stopping input using sound source only, retain settings STASI SLSORCE
Data Sheet S16919EJ1V0DS
µPD9991
STANDBY MODE
Standby mode various blocks
10.1 Clock Supply
During standby mode PLL1 PLL2, access enabled only standby register address 00H, master clock setting registers addresses 01H, 02H, 03H, 04H, general-purpose output setting register address 0EH. DVX, ASIO, PLL1 standby mode must canceled. sound source logic block, PLL2 standby mode must canceled. supply clock signals from various blocks illustrated Figure 10-1. Figure 10-1. Destination Clocks Supplied from PLL1 PLL2
CLKIN
PLL1 PLL2 PLL2
µPD9991
PLL1
PLL1
Sound source logic block
PLL1 ASIO VREF/IREF
Data Sheet S16919EJ1V0DS
µPD9991
REFERENCE SCHEMATICS 11.1 Line Pins (LINEOUT_L LINEOUT_R)
Figure 11-1. Example Connection Line
PD9991
LINEOUT_L
4.7µF Stereo output
LINEOUT_R
4.7µF
11.2 Reference Power Supply Voltage Current Supply Pins (VREF IREF)
Figure 11-2. Handling VREF IREF Pins
PD9991
IREF Band reference
VREF 0.22
VREF IREF blocks include following functions. Reference voltage generated using band reference current generated using this reference voltage external resistance, supplied analog circuits. VREF IREF blocks operates when STREF STNBY register. Normal mode within after this STREF Cautions sure connect resistor between IREF AGND. connect other resistors IREF pin. sure connect 0.22 (±20%) capacitor between VREF AGND. connect other capacitors VREF pin.
Data Sheet S16919EJ1V0DS
µPD9991
11.3 Power Supply
Whenever possible, avoid placing decoupling capacitor close PD9991's pins. Figure 11-3. Placement Decoupling Capacitor
AVDD DVDD
PD9991
AVDD AGND
DVDD DGND EVDD
DGND AVDD-P AGND-P EGND EVDD
AGND EGND
pairing pins between power supply (with decoupling capacitor) follows (pin numbers indicated parentheses). AVDD (1E) AGND (1D) AVDD-P (2G) AGND-P (1H) DVDD (9K) DGND (5K) DVDD (10D) DGND (10J) EVDD (9C) EGND (6A) DVDD (9A) EGND (6A) Caution EVDD used digital operations. Therefore, recommended different power supply analog power supplies (AVDD AVDD-P) avoid affecting analog characteristics.
Data Sheet S16919EJ1V0DS
µPD9991
11.4 Outline Schematics
Input TM4, PO3, CS_B, WR_B, RD_B, RESET_B, LRCLK, BCLK, ASI, TRSCK, CLK8K, RDATA Output TM3, TM4, PO3, INT_B, VIB, LED, LRCLK, BCLK, Outline Schematic
EVDD
Input
Output
EGND
IREF, VREF
IREF, VREF, LINEOUT_L, LINEOUT_R
AVDD
Input
Output
AGND
CLKIN
AVDD-P
Input
Output
AGND-P
Data Sheet S16919EJ1V0DS
µPD9991
ELECTRICAL SPECIFICATIONS 12.1 Absolute Maximum Ratings
Parameter Supply voltage Symbol DVDD EVDD AVDD AVDD-P Input voltage Output voltage Power dissipation Storage temperature Tstg Conditions digital ports pins analog ports VI/VO EVDD Rating -0.3 +2.0 -0.3 +4.0 -0.3 +4.0 -0.3 +4.0 -0.3 +4.0 -0.3 +4.0 +125 Unit
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
12.2 Recommended Operating Conditions
Parameter Operating voltage Symbol DVDD EVDD AVDD AVDD-P Input voltage Operating ambient temperature +85°C Conditions MIN. 1.425 1.71 2.85 2.85 TYP. MAX. 1.575 3.15 3.15 EVDD Unit
12.3 Capacitance
+25°C, DVDD EVDD
Parameter Input capacitance Output capacitance capacitance Symbol Conditions MHz, pins other than those tested: MIN. TYP. MAX. Unit
Data Sheet S16919EJ1V0DS
µPD9991
12.4 Characteristics
+85°C, with DVDD EVDD within recommended operating condition range)
Parameter Input voltage, high Input voltage, Output voltage, high Symbol VIHN VILN VOH3 EVDD (LED, VOH18 EVDD (LED, -1.5 Output voltage, VOL3 EVDD (LED, VOL18 EVDD (LED, +1.5 Input leakage current, high Input leakage current, ILLN High-impedance leakage current EVDD ILHN EVDD EVDD EVDD EVDD Conditions MIN. EVDD EVDD TYP. MAX. EVDD EVDD Unit
Common ratings switching characteristics
EVDD EVDD EVDD EVDD EVDD EVDD
Input
Test points
Output
EVDD
Test points
EVDD
Data Sheet S16919EJ1V0DS
µPD9991
12.5 Characteristics
(Unless otherwise specified, +85°C, with EVDD within recommended operating condition range) 12.5.1 Clock Timing requirements
Parameter CLKIN input frequency CLKIN input level lockup time Symbol fCLKIN VCLKIN tLPLL VCLKIN 0.5Vp-p fCLKIN 2.688 16.128
Note
Conditions
MIN. 2.688
TYP.
MAX. 16.128 Note
Unit Vp-p
Notes CLKIN input used input should have capacitive coupling (1000 pF). maximum input level CLKIN should exceed power supply (AVDD-P) potential. 12.5.2 Reset Timing requirements (EVDD
Parameter RESET_B low-level width RESET_B recovery time Symbol tw(RL) trec(R) Conditions MIN. TYP. MAX. Unit
Timing requirements (EVDD
Parameter RESET_B low-level width RESET_B recovery time Symbol tw(RL) trec(R) Conditions MIN. TYP. MAX. Unit
Reset timing
tw(RL) RESET_B trec(R)
Data Sheet S16919EJ1V0DS
µPD9991
12.5.3 Host interface
Timing requirements (EVDD
Parameter RD_B width WR_B width RD_B recovery time RD_B recovery time Symbol twRD twWR trcRD trcRD During read access sound source register During read access other than sound source register WR_B recovery time WR_B recovery time trcWR trcWR During write access sound source register During consecutive access write data read data from sound source register WR_B recovery time trcWR During write access other than sound source register Data setup time Data hold time CS_B setup time CS_B hold time CS_B setup time CS_B hold time tsuDI thDI tsuAW thAW tsuAR thAR WR_B WR_B WR_B WR_B RD_B RD_B Conditions MIN. TYP. MAX. Unit
Timing requirements (EVDD
Parameter RD_B width WR_B width RD_B recovery time RD_B recovery time Symbol twRD twWR trcRD trcRD During read access sound source register During read access other than sound source register WR_B recovery time WR_B recovery time trcWR trcWR During write access sound source register During consecutive access write data read data from sound source register WR_B recovery time trcWR During write access other than sound source register Data setup time Data hold time CS_B setup time CS_B hold time CS_B setup time CS_B hold time tsuDI thDI tsuAW thAW tsuAR thAR WR_B WR_B WR_B WR_B RD_B RD_B Conditions MIN. TYP. MAX. Unit
Switching characteristics (EVDD
Parameter Data access time Data hold time Symbol taccDO tdDO Conditions RD_B, Isink RD_B, Isink MIN. TYP. MAX. Unit
Data Sheet S16919EJ1V0DS
µPD9991
Switching characteristics (EVDD
Parameter Data access time Data hold time Symbol taccDO tdDO Conditions RD_B, Isink= RD_B, Isink MIN. TYP. MAX. Unit
Host interface read timing
tsuAR thAR
CS_B
WR_B twRD RD_B taccDO Read address tdDO Read data Next address trcRD
Address write cycle
Data read cycle
Host interface write timing
tsuAW thAW
CS_B twWR WR_B trcWR
RD_B
tsuD1 thD1 Write data Next dddress
Write address
Address write cycle
Data write cycle
Data Sheet S16919EJ1V0DS
µPD9991
12.5.4 Audio serial interface Timing requirements (EVDD
Parameter LRCLK cycle time BCLK cycle time BCLK high-/low-level width BCLK rise/fall time LRCLK rising edge delay time Symbol tcLR tcBC twBC trfBC tdrLRC BCLK BCLK BCLK BCLK When bits frame
Note
Conditions
MIN.
TYP. 1/fs 1/(fs tcBC/2
MAX.
Unit
LRCLK falling edge delay time tdfLRC input setup time input hold time tsuASER thASER
Note
configuration each frame varies according settings BFS[4:0] bits SLFS register (07H).
Timing requirements (EVDD
Parameter LRCLK cycle time BCLK cycle time BCLK high-/low-level width BCLK rise/fall time LRCLK rising edge delay time Symbol tcLR tcBC twBC trfBC tdrLRC BCLK BCLK BCLK BCLK When bits frameNote Conditions MIN. TYP. 1/fs 1/(fs tcBC/2 MAX. Unit
LRCLK falling edge delay time tdfLRC input setup time input hold time tsuASER thASER
Note
configuration each frame varies according settings BFS[4:0] bits SLFS register (07H).
Switching characteristics (EVDD
Parameter LRCLK output delay time output delay time Symbol tdLRC tdASER BCLK BCLK -12.5 Conditions MIN. TYP. MAX. Unit
Switching characteristics (EVDD
Parameter LRCLK output delay time output delay time Symbol tdLRC tdASER BCLK BCLK -37.5 Conditions MIN. TYP. MAX. Unit
Data Sheet S16919EJ1V0DS
µPD9991
Audio serial timing (slave mode)
tdrLRC LRCLK (Input) tcBC twBC BCLK (Input) tsuASER (Input) tdASER (Output) thASER twBC trfBC trfBC tdfLRC
Audio serial timing (master mode)
tdLRC LRCLK (Output) tcBC twBC BCLK (Output) tsuASER (Input) tdASER (Output) thASER twBC trfBC trfBC tdLRC
Data Sheet S16919EJ1V0DS
µPD9991
12.6 Analog Characteristics
propagation characteristics from converter line output described below. Unless otherwise specified, following conditions must met. converter input level INPUT dBFS (D/A converter's full scale input defined dBFS) converter input frequency Sampling frequency Ambient temperature 25°C Power supply voltage AVDD Output load
Parameter Maximum output level Gain error Gain error Symbol GEmax GEmin VOLUME VOLUME Vp-p VOLUME value relative GEmax reference Gain adjustment resolution VOLUME 19.2 Frequency characteristics 19.2 Dynamic range VOLUME INPUT dBm@997 output when used reference VOLUME INPUT dBFS, 19.2 kHz, A-wgt filter Gstep VOLUME When differential error Conditions MIN. TYP. MAX. Unit Vp-p
Data Sheet S16919EJ1V0DS
µPD9991
12.7 Mode-Specific Current Consumption Characteristics
Unless otherwise specified, following conditions must met. Sound source master clock 55.104 Master clock other than sound source master clock 24.576 converter input level INPUT dBFS (D/A converter's full scale input defined dBFS) converter input frequency 1020 Sampling frequency Ambient temperature 25°C Power supply voltage AVDD AVDD-P EVDD DVDD Output load
Parameter Current during output from sound source Symbol IDD1 Conditions AVDD AVDD-P DVDD current when STDIG STPLL2 STPLL1 STSYNTH STDAC STREF SLSORCE sound generator operating normally AVDD AVDD-P DVDD current when STDIG STPLL2 STPLL1 STSYNTH STREF SLSORCE sound generator operating normally AVDD AVDD-P DVDD current when STDIG STPLL1 STDAC STREF SLSORCE Power Supply DVDD AVDD AVDD-P EVDD DVDD AVDD AVDD-P EVDD DVDD AVDD AVDD-P EVDD Current during output from IDD4 AVDD AVDD-P DVDD current when STDIG STPLL1 STREF SLSORCE DVDD AVDD AVDD-P EVDD Standby current (command-driven) ISTB AVDD AVDD-P DVDD current when STDIG STPLL2 STPLL1 STASI STASO STSYNTH STDAC STREF DVDD AVDD AVDD-P EVDD
Note Note Note Note Note
MIN.
TYP.
MAX.
Unit
Current during output from sound source
IDD2
Current during output from
IDD3
Note
EVDD current measured when there load. actual operation µPD9991, EVDD current differs depending external environment such clock rate, load capacitance, load resistance.
Data Sheet S16919EJ1V0DS
µPD9991
PACKAGE DRAWING
65-PIN TAPE FBGA (6x6)
INDEX MARK
ITEM (UNIT:mm) DIMENSIONS 6.00±0.10 6.00±0.10 0.15 0.20 0.50 0.83±0.10 0.18±0.05 0.65 0.32±0.05 0.05 0.08 0.20 0.75 0.75 P65F9-50-BA1
Data Sheet S16919EJ1V0DS
µPD9991
RECOMMENDED SOLDERING CONDITIONS
PD9991 should soldered mounted under following recommended conditions. soldering methods conditions other than those recommended below, contact Electronics sales representative. technical information, following website. Semiconductor Device Mount Manual PD9991F9-BA1: 65-pin tape FBGA
Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 250°C, Time: sec. max. 220°C higher), Count: times less, Exposure limit: days necessary 125°C hours)
Note
IR50-107-2
(after that prebaking
Note
After opening pack, store 25°C less less allowable storage period.
Data Sheet S16919EJ1V0DS
µPD9991
[MEMO]
Data Sheet S16919EJ1V0DS
µPD9991
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S16919EJ1V0DS
µPD9991
Regional Information
Some information contained this document vary from country country. Before using Electronics product your application, pIease contact Electronics office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country. [GLOBAL SUPPORT]
Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782
Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 Sucursal Madrid, Spain Tel: 091-504 Succursale France Tel: 01-30-67 Filiale Italiana Milano, Italy Tel: 02-66 Branch Netherlands Eindhoven, Netherlands Tel: 040-244 Tyskland Filial Taeby, Sweden Tel: 08-63 United Kingdom Branch Milton Keynes, Tel: 01908-691-133
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318
Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-558-3737
Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138
Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311
J03.4
Data Sheet S16919EJ1V0DS
µPD9991
information this document current January, 2004. information subject change without notice. actual design-in, refer latest publications Electronics data sheets data books, etc., most up-to-date specifications Electronics products. products and/or types available every country. Please check with Electronics sales representative availability additional information. part this document copied reproduced form means without prior written consent Electronics. Electronics assumes responsibility errors that appear this document. Electronics does assume liability infringement patents, copyrights other intellectual property rights third parties arising from Electronics products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Electronics others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Electronics assumes responsibility losses incurred customers third parties arising from these circuits, software information. While Electronics endeavors enhance quality, reliability safety Electronics products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects Electronics products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment anti-failure features. Electronics products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only Electronics products developed based customerdesignated "quality assurance program" specific application. recommended applications Electronics product depend quality grade, indicated below. Customers must check quality grade each Electronics product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade Electronics products "Standard" unless otherwise expressly specified Electronics data sheets data books, etc. customers wish Electronics products applications intended Electronics, they must contact Electronics sales representative advance determine Electronics' willingness support given application. (Note) "NEC Electronics" used this statement means Electronics Corporation also includes majority-owned subsidiaries. "NEC Electronics products" means product developed manufactured Electronics defined above).
11-1

µPD9991 RING TONE GENERATOR (WITH SURROUND SOUND) MOBILE PHONES

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