User's Guide Mixed Signal Products SLVU019 IMPORTANT NO

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User's Guide Mixed Signal Products SLVU019 IMPORTANT NO

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Linear Regulator Design Using Universal SOT23
User's Guide
Mixed Signal Products
SLVU019
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Information About Cautions Warnings
Preface
Read This First
About This Manual
This user's guide describes techniques designing dropout voltage linear regulators (LDO) using TI's SLVP125 evaluation modules (EVM) 76933 LDOs.
This Manual
This document contains following chapters:
Chapter Introduction Chapter Adjustments Test Points Chapter Circuit Design Chapter Test Results
Information About Cautions Warnings
This book contain cautions warnings. This example caution statement. caution statement describes situation that could potentially damage your software equipment.
This example warning statement. warning statement describes situation that could potentially cause harm you.
Read This First
Related Documentation From Texas Instruments
information caution warning provided your protection. Please read each caution warning carefully.
Related Documentation From Texas Instruments
TPS760xx, TPS761xx, TPS763xx, TPS764xx, TPS769xx, TPS770xx data sheets (literature numbers SLVS144B, SLVS178A, SLVS181D, SLVS180A, SLVS203B, SLVS210B)
Running Title-Attribute Reference
Contents
Introduction Dropout Voltage Linear Regulator Circuit Operation Design Strategy Schematic Bill Materials Board Layout Adjustments Test Points Adjustment Switch Adjustment Jumper Adjustment Trimmer Adjustment Programming Header Test Setup Circuit Design Adjusting TPS76x01/TPS77001 Output Voltage Temperature Considerations External Capacitor Requirements
Test Results Test Results
Chapter Title-Attribute Reference
Running Title-Attribute Reference
Figures
Typical Application SLVP125 Universal Tester Schematic Diagram Layer Bottom Layer (top view) Assembly Drawing (top assembly) Location Adjustment Parts Test Setup Programming TPS76x01/TPS77001 Resistor Values Calculated Measured Maximum Output Current Input Voltage Without Cooling TPS76933 Test Setup Output Stage With Parasitic Resistances Correlation Different ESRs Their Influence Regulation Vout Load Step From High Output Current Rise Time Function Generator Gate MOSFET (high speed) Rise Time Function Generator Gate MOSFET (low speed) Transient Input (Ch1); Input, Output (Ch2) Load, Cout Delay Time Output High Full Load (100 Load Transition, Vout, Whole Period Full Load (100 Load Transition With Cout Electrolytic Load Full Load (100 Transition With Cout Electrolytic
Tables
Summary Families Their Features SLVP125 Bill Materials Jumper Functions Trimmer Adjustments Timing Equations Exact Resistor Values Resistor Series
Chapter
Introduction
This user's guide describes techniques designing dropout (LDO) voltage linear regulators using TI's SLVP125 evaluation module (EVM) TPS76933 LDO. LDOs provide ideal power supplies rapidly transitioning loads such Texas Instruments TMS320C54x similar processors, fast memory. quiescent current very dropout voltage compared standard LDOs makes TPS76933 particularly suitable battery applications requiring extended lifetime cost. noise power supplies, fast transient response, improved efficiency, component count, easy design make LDOs popular solutions where switched converters noisy standard linear regulators inefficient.
Topic
Page
Dropout Voltage Linear Regulator Circuit Operation Design Strategy Schematic Bill Materials Board Layout
Introduction
Dropout Voltage Linear Regulator Circuit Operation
Dropout Voltage Linear Regulator Circuit Operation
dropout voltage linear regulator topology, PMOS transistor acts pass element that reduces normal 1.5-V 2.5-V collector-to-emitter drop about less. This improvement results lower power dissipation higher efficiency when compared other regulator designs. basic regulator circuit includes output capacitor stabilization. Figure shows circuit typical application.
Figure 1-1. Typical Application
Vout
Control
Load
Vref
application shown Figure 1-1, regulates output voltage Vout. Vout falls below regulation level, controller increases differential PMOS conducts more current, resulting increase Vout. Vout exceeds regulation level, controller decreases differential PMOS conducts less current, resulting decrease Vout. PMOS pass element acts like adjustable resistor. more negative gate becomes versus source, less source-drain resistance becomes, resulting higher current flow through PMOS.
Design Strategy
Design Strategy
SLVP125 provides circuit simultaneously compare performance LDOs SOT23 package. provides proven, demonstrated reference designs test modes choosing evaluating LDOs. programmable high speed transient generator generates either line load transients. transient slew rate, impact transients load/line adjustable. amplifying operational amplifier amp) makes measurements dropout voltages easier more accurate. avoid influencing each other, each powered power supply. Jumpers allow settings minimum/maximum load well device-enable transient impact functions. There enough room evaluate different types output capacitors including behaviors. Many test points allow measuring input, output, dropout voltage. shipped with TPS76933 that provides 3.3-V output voltage. maximum output current mA-output power level reasonable selection criteria powering DSPs battery-supplied applications such mobile phones laptop cards. TPS760xx, TPS761xx, TPS763xx, TPS764xx, TPS769xx, TPS770xx family provides several output currents voltages combined with options like very noise high accuracy. Table summarizes families their features.
Table 1-1. Summary Families Their Features
TPS760xx Maximum input voltage range Maximum output current [mA] Typical quiescent current [µA] Typical dropout voltage [mV] Typical output noise [µVrms] Accuracy over line, load, temperature PSRR kHz, 25°C) Package External SOT23 1.6, 1.8, 2.5, 2.7, 2.8, 3.3, 3.8, 2.5, 2.7, 2.8, 1.2, 1.5, 1.8, 2.5, 2.7, 2.8, 3.3, adj. dropout, ultra quiescent current, high accuracy TPS761xx TPS763xx TPS764xx TPS769xx TPS770xx
(PNP) 2600
(PMOS)
13.5(PMOS)
Available Voltage Option
3.2, 3.3, 3.8,
Performance Advantage
dropout
quiescent current, noise
Introduction
Schematic
Schematic
Figure1-2 shows SLVP125 Universal Tester (3.3 output with TPS76933 schematic diagram.
Figure 1-2. SLVP125 Universal Tester Schematic Diagram
Schematic
Figure 1-2. SLVP125 Universal Tester Schematic Diagram (Continued)
Introduction
Bill Materials
Bill Materials
Table lists materials required SLVP125 EVM.
Table 1-2. SLVP125 Bill Materials
(Alt) (Alt) JP10 JP11 JP12 ECU-V1H104KBW ED1515-ND ED1514-ND ED1515-ND PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN PTC36SAAN Si4410DY Si4410DY ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW GRM235Y5V106Z016A ECU-V1H104KBW 16SA470M 16SP470M ECU-V1H104KBW 16SA470M 16SP470M ECU-V1H104KBW GRM235Y5V106Z016A Description Capacitor, OS-Con, 20-m, Capacitor, OS-Con, 10-m, Capacitor, ceramic, X7R, Capacitor, ceramic, Y5V, -20% +80% Capacitor, user option Capacitor, ceramic, X7R, Capacitor, ceramic, X7R, Capacitor, ceramic, X7R, Capacitor, ceramic, Y5V, -20% +80% Capacitor, ceramic, X7R, Capacitor, OS-Con, 20-m, Capacitor, OS-Con, 10-m, Capacitor, ceramic, X7R, Capacitor, user option Capacitor, ceramic, X7R, Terminal block, 3-pin, Terminal block, 2-pin, Terminal block, 3-pin, Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 3-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 2-pin, 0.100" Header, single-row, straight, 3-pin, 0.100" MOSFET, N-ch, 30-V, 10-A, 13-milliohm MOSFET, N-ch, 30-V, 10-A, 13-milliohm Resistor, Chip, Resistor, Chip, 0.51 Resistor, Chip, user option, Resistor, Chip, user option, Resistor, Chip, 1.00 Resistor, Chip, 1.00 Resistor, Chip, Resistor, Chip, Resistor, Chip, 10.0 Panasonic Sullins Sullins Sullins Sullins Sullins Sullins Sullins Sullins Sullins Sullins Sullins Sullins Silconix Silconix Panasonic Panasonic Panasonic muRata Panasonic Sanyo Sanyo Panasonic Sanyo Sanyo Panasonic muRata Size 1206 1210 1210/1206 1206 1206 1206 1210 1206 1206 1210/1206 1206 3.5mm 3.5mm 3.5mm 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" 0.1" SO-8 SO-8 1206 1206 1206 1206 1206 1206 1206 1206 1206
Bill Materials
Table 1-2. SLVP125 Bill Materials (Continued)
TP10 TP11 TP12 110-99-316-41-001 TLC555CD TPS2812D TLE2021CD TLE2021CD 72-T93YA-10 72-T93YA-50K 72-T93YA-10 72-T93YA-50K EG1218 EG1218 EG1218 EG1218 131-4244-00 131-4244-00 240-345 240-345 240-345 240-333 240-333 240-345 240-345 240-345 131-4244-00 131-4244-00 Description Resistor, Chip, user option, Resistor, chip, 10.0 Trim Pot, cermet, vertical, adjust, Resistor, chip, user option, 1/8-1 Resistor, Trim pot, cermet, vertical, adjust, Resistor, chip, Resistor, chip, user option, Resistor, chip, Resistor, chip, user option, Resistor, chip, Resistor, chip, user option, Resistor, chip, 0.51 Resistor, chip, 1.00 Resistor, chip, 10.0 Resistor, chip, user option, Resistor, chip, 1.00 Resistor, chip, Trim pot, cermet, vertical, adjust, Resistor, chip, user option, 1/8-1 Resistor, chip, 10.0 Resistor, chip, Trim pot, cermet, vertical, adjust, Switch, 1P2T, slide, PC-mount Switch, 1P2T, slide, PC-mount Switch, 1P2T, slide, PC-mount Switch, 1P2T, slide, PC-mount Adaptor, 3.5-mm probe clip 131-5031-00) Adaptor, 3.5-mm probe clip 131-5031-00) Test point, Test point, Test point, Test point, black Test point, black Test point, Test point, Test point, Adaptor, 3.5-mm probe clip 131-5031-00) Adaptor, 3.5-mm probe clip 131-5031-00) LDO, LDO, Socket, 16-pin, frequency programming CMOS timer MOSFET driver, 2-Ch, Noninverting Amp, single-supply, offset Amp, single-supply, offset Vishay E-Switch E-Switch E-Switch E-Switch Tektronix Tektronix Farnell Farnell Farnell Farnell Farnell Farnell Farnell Farnell Tektronix Tektronix Mill-Max Various Various DIP-16 SO-8 SO-8 SO-8 SO-8 Vishay Vishay Vishay Size 1206 1206 0.1" 1206/2512 1206 0.1" 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 1206 0.1" 1206/2512 1206 1206 0.1" 0.1" 0.1" 0.1" 0.1"
Introduction
Board Layout
Board Layout
Figures through show board layout SLVP125 EVM.
Figure 1-3. Layer
Figure 1-4. Bottom Layer (top view)
Board Layout
Figure 1-5. Assembly Drawing (top assembly)
Introduction
1-10
Chapter
Adjustments Test Points
This chapter explains following four adjustment modes:
Adjustment switch Adjustment jumper Adjustment trimmer Adjustment programming header
Figure shows locations adjustment points board.
Topic
Page
Adjustment Switch Adjustment Jumper Adjustment Trimmer Adjustment Programming Header Test Setup
Adjustments Test Points
Adjustment Switch
Adjustment Switch
toggles between high (direction labelling) transient generator frequency. switches transient generator (direction labelling) off. toggles between slower (direction labelling) faster transients. directs transients either DUT1 (direction labelling) DUT2.
Adjustment Jumper
Table lists adjustments that made jumpers.
Table 2-1. Jumper Functions
Function/Device Bypasses input resistor Enables Bypasses emulation minimum load maximum load Toggles between input voltage (direction trimmer) load transient DUT1 DUT2 JP10 JP11 JP12
Adjustment Trimmer
Table lists adjustments that made trimmer.
Table 2-2. Trimmer Adjustments
Function/Device Risetime transient Input voltage spike transient impact DUT1 DUT2
Adjustment Programming Header
programming header used program frequency duty cycle transient generator. Table lists timing equations.
Test Setup
Table 2-3. Timing Equations
Timing Equations With Diode Duty Cycles Timing Equations Without Diode
0.693
0.693 0.693
(2D-1) (1-D)
Note:
0.693
(1-D)
desired load on-time on-time duty cycle total capacitance circuit (CH1 CH2) RH1, Timer resistors value (refer schematics)
Figure 2-1. Location Adjustment Parts
Input voltage transient impact
Input voltage transient impact
Test Setup
Figure shows test setup. Follow these steps initial power SLVP125 Populate test devices board adjust settings jumpers, switches, trimmers test requirements. Also make sure that minimum/maximum load resistors populated matched output current want test, that they handle power dissipation. Connect 12-V power supply 12-V input polarity printed board. current limit should adequate test measure circuit.
Adjustments Test Points
Test Setup
Connect power supply least capable supply connector GND. polarity printed board. Verify that output voltage limit 13.5 that output Turn 12-V supply. Turn second power supply ramp input voltage desired maximum further than 13.5 Verify that output voltage (measured Vout1 Vout2 pins respectively) desired value. Note: With very small loads (<100 will measure small output voltage even with device shutdown. This offset voltages opamps plan insert socket DUT, will have remove jumper wires from socket area. socket internal connections.
Figure 2-2. Test Setup
NOTE: wire pairs should twisted.
Chapter
Circuit Design
This chapter describes circuit design procedure.
Topic
Page
Adjusting TPS76xx01/TPS77001 Output Voltage Temperature Considerations External Capacitor Requirements
Circuit Design
Adjusting TPS76x01/TPS77001 Output Voltage
Adjusting TPS76x01/TPS77001 Output Voltage
voltage regulators TPS76x01/TPS77001 families same internal bandgap voltage, also Figure 1-1. adjustable version, resistors external resistors. virtual short circuit between input pins amp, voltage Vref applies both +input -input pin. Note: TPS76x01/TPS77001 devices except TPS764xx feedback adjustable version. TPS764xx acts bypass external bypass capacitor. This capacitor used further reduce output voltage noise. TPS764xx data sheet details.
Figure 3-1. Programming TPS76x01/TPS77001
Vout
Vref
equation output voltage
Vref
Vout Vref
Vref
resistor ratio function
Vref
Using Figure 3-2, possible quick ratio R1/R2 their maximum value.
Adjusting TPS76x01/TPS77001 Output Voltage
Figure 3-2. Resistor Values
1800 1600 1400 max. Value 1200 1000 10.4 10.8 11.2 11.6 Value R1+R2[k] R1/R2
Output Voltage
Table 3-1. Exact Resistor Values
Vout R1/R2 0.018676 0.103565 0.188455 0.273345 0.358234 0.443124 0.528014 0.612903 0.697793 0.782683 0.867572 0.952462 1.037351 1.122241 1.207131 1.29202 1.37691 1.4618 1.546689 1.631579 1.716469 1.801358 Maximum Value R1+R2[k] 171.429 185.714 200.000 214.286 228.571 242.857 257.143 271.429 285.714 300.000 314.286 328.571 342.857 357.143 371.429 385.714 400.000 414.286 428.571 442.857 457.143 471.429
Circuit Design
Resistor ratio R1/R2
Adjusting TPS76x01/TPS77001 Output Voltage
Table 3-1. Exact Resistor Values(Continued)
Vout 10.5 11.5 R1/R2 1.886248 1.971138 2.056027 2.140917 2.225806 2.310696 2.395586 2.480475 2.565365 2.650255 2.735144 2.820034 2.904924 2.989813 3.074703 3.159593 3.244482 3.66893 4.093379 4.517827 4.942275 5.366723 5.791171 6.21562 6.640068 7.064516 7.488964 7.913413 8.337861 8.762309 9.186757 Maximum Value R1+R2[k] 485.714 500.000 514.286 528.571 542.857 557.143 571.429 585.714 600.000 614.286 628.571 642.857 657.143 671.429 685.714 700.000 714.286 785.714 857.143 928.571 1000.000 1071.429 1142.857 1214.286 1285.714 1357.143 1428.571 1500.000 1571.429 1642.857 1714.286
ensure proper regulation, divider current should maximum resistor value R1+R2 seen Figure Table 3-1. actual values resistor ratio maximum resistor value desired output voltage Figure Table following calculations:
Adjusting TPS76x01/TPS77001 Output Voltage
gets:
1.546689 428.571 1.546689 1.546689 428.571 428.571 168.286 2.546689
Make calculate Derived from equation gets
1.546689
261.39
next value series shown Table error using these resistors
1.544379 Error
1.544379 1.546689
100%
0.149371%
free-ware program called WinResis available Internet help find correct resistor values.
Table 3-2. Resistor Series
series
Circuit Design
Temperature Considerations
Temperature Considerations
protect device assure specifications, maximum junction temperature should exceed 125°C. This restriction limits power dissipation regulator handle given application. ensure junction temperature within acceptable limits, calculate maximum allowable dissipation, PD(max), actual dissipation, which must less than equal PD(max). maximum power dissipation limit determined using following equation:
D(max)
Where
maxJA
TJ,max maximum allowed junction temperature [°C], i.e., 125°C TPS76xxx/TPS77xxx families thermal resistance junction-to-ambient package, i.e., 285°C/W 5-terminal SOT23 ambient temperature regulator dissipation calculated using:
VOUT
maximum output current given temperature calculated
out,max[mA]
Vout
125°C
285°C
1000
Figure shows test results TPS76933 device. Also displayed calculated results.
External Capacitor Requirements
Figure 3-3. Calculated Measured Maximum Output Current Input Voltage Without Cooling TPS76933 Test Setup
Vout Tolerance Area
Current limit
Iout, Input Voltage, calculated Values Iout, Input Voltage, measured Values
[mA]
Vout Iout
External Capacitor Requirements
Besides capacitance, every capacitor also contains parasatic resistances. These parasatic resistances ohmic resistances well inductive impedances. ohmic resistances called equivalent series resistance (ESR), inductive impedances called equivalent series inductance (ESL). designator inductors. equivalent schematic diagram capacitor therefore drawn shown Figure 3-4.
Figure 3-4.
RESR LESL
most cases neglect very small inductive impedance ESL. Therefore following description focuses mainly parasitic resistance ESR. Figure shows output capacitor parasitic resistances typical output stage.
Circuit Design
Vout
Vout Iout,
External Capacitor Requirements
Figure 3-5. Output Stage With Parasitic Resistances
Iout
RESR VESR LESL RLOAD Vout
VCout
Cout
steady state state condition) load supplied (solid arrow) VCout Vout. This means current flowing into Cout branch. Iout suddenly increases, following occurs (see Figure screen shot Chapter Figure 4-7): able supply sudden current need response time Figure 3-6). Therefore capacitor Cout provide current load condition (dashed arrow). Cout acts like battery with internal resistance, ESR. Therefore, depending current demand output, voltage drop will occur RESR LESL. This voltage shown VESR Figure 3-5. internal inductance also causes additional delay (shown Figure 3-6), Cout could immediately supply current load. When Cout finally conducting current load, initial voltage load will Vout VCout VESR. discharge Cout, output voltage Vout will drop continuously until response time reached will resume supplying load. From this point output voltage starts rising again until reaches level directed LDO. This period shown Figure 3-6. figure also shows impact different ESRs output voltage. left brackets show different levels ESRs where number displays lowest number displays highest ESR. Understanding above, draw following conclusions:
higher ESR, bigger spike beginning load transient longer time return steady state. smaller output capacitor, faster discharge time bigger voltage loss during response period (shown Figure 3-6).
Conclusion: higher output current load step differentials, higher requirements Cout with ESR.
External Capacitor Requirements
Figure 3-6. Correlation Different ESRs Their Influence Regulation Vout Load Step From High Output Current
Iout
Vout
order good performing system, with short response time output capacitor with required. regulator TPS76xxx/TPS770xx series, output capacitor least required. capacitor should between ensure stability.
Circuit Design
3-10
Chapter
Test Results
This chapter presents laboratory test results design.
Topic
Test Results
Page
Test Results
Test Results
Test Results
Figures through show results various tests test conditions circuit using TPS76933 device.
Figure 4-1. Rise Time Function Generator Gate MOSFET (high speed)
Figure 4-2. Rise Time Function Generator Gate MOSFET (low speed)
Test Results
Figure 4-3. Transient Input (Ch1); Input, Output (Ch2) Load, Cout
Spike
Output Voltage
Figure 4-4. Delay Time Output High
Enable Pulse
Output Voltage
Test Results
Test Results
Figure 4-5. Full Load (100 Load Transition, Vout Whole Period
Output Voltage (see Note
Load Transition (see Note
Figure 4-6. Full Load (100 Load Transition With Cout Electrolytic
Output Voltage (see Note
Load Transition (see Note
Test Results
Figure 4-7. Load Full Load (100 Transition With Cout Electrolytic
Output Voltage (see Note
Load Transition (see Note
Notes:
load transition measured voltage drop drain (see Figure 1-2). Therefore load displayed load displayed order display output voltage transient with high resolution, offset introduced. actual values seen with cursor lines Figure 4-5. output voltage without full load: 3.296 output voltage with full load: 3.278
Test Results

User's Guide Mixed Signal Products SLVU019 IMPORTANT NO

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