Programming Host Interface Mixed-Signal Product SLAA051

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Programming Host Interface Mixed-Signal Product SLAA051

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TVP5020 NTSC/P Video Decoder
Programming Host Interface
Mixed-Signal Product
SLAA051
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Contents
Introduction Hardware Platform Block Diagram Schematic Diagram Microcontroller Interface 2.2.1 Memory Mapped Interface Source File PAL1 Source File: VMI_PORT.C Make File: APP_VMI.LIN File: APP_VMI.M51 Schematic Diagram-TVP5020 NTSC/PAL Video Decoder Program Overview Microcontroller-Specific Macros Header File: REG652.H Source-Code Modules Program Description Source-Code Module: Main 4.1.1 Inclusion TVP5020 Microcode Files (Lines 11-14) 4.1.2 Function: Main() 4.1.3 Function: Power-up Initialization() 4.1.4 Function: Patch TVP5020 Registers() Header File: Main.H Source File: Main.C Source-Code Module: 4.4.1 Function: initia_i2c() (Lines 28-41) 4.4.2 Function: start_i2c() 4.4.3 Function: i2c_isr() (Lines 77-266) Header File: 12C.H Source File: I2C.C Source-Code Module: Timer 4.7.1 Function: timer0_isr() (Lines 26-59) 4.7.2 Function: timer0_initialize() (Lines 61-94) 4.7.3 Function: ResetTickCount() (Lines 96-112) 4.7.4 Function: current_tick() (Lines 114-131) 4.7.5 Function: timer0_elapsed_count() (Lines 133-150) 4.7.6 Function: timer0_wait() (Lines 152-167) Header File: Timer.H Source File: TIMER.C 4.10 Source-Code Module: VMI5020 4.10.1 Vertical Blanking Interval Data Processor (VDP) 4.10.2 Function: DecoderReset() (Lines 20-34) 4.10.3 Function: HandleDownload() (Lines 36-48) 4.10.4 Function: Write TVP5020() (Lines 50-56) 4.10.5 Function: Write TVP5020VMI() (lines 58-127) 4.10.6 Function: ReadSwitch() (Lines 129-154) 4.10.7 Function: ReadTVP5020() (Lines 156-168) 4.10.8 Function: ReadTVP5020VMI() (Lines 170-220) 4.11 Header File: VMI5020.H 4.12 Source File: VMI5020.C 4.13 Source-Code Module: I2C6000
TVP5020 NTSC/PAL Video Decoder
Figures
4.14 4.15 4.16 4.17 4.18 4.19
4.13.1 Function: read_tvp6000() (lines 23-40) 4.13.2 Function: write_tvp6000() (Lines 41-50) 4.13.3 Function: LoadTVP6000() (Lines 52-75) 4.13.4 Function: PatchTVP6000 (Lines 77-97) Header File: I2C6000.H Source File: I2C6000.C TVP6000 Initialization Data NTSC with CCIR601 Sampling TVP6000 Initialization Data NTSC with Square Pixel Sampling TVP6000 Initialization Data with CCIR601 Sampling TVP6000 Initialization Data with Square Pixel Sampling
List Figures
TVP56000EVM Block Diagram Microcontroller Interface Schematic TVP5020 NTSC/PAL Video Decoder Schematic TVP56000EVM Board Layout Help-About Dialog from uVision/51 Windows Help-About Dialog Signum Systems In-Circuit Emulator TVP5020 Microcode Hex-ASCII Format TVP5020 Microcode after Conversion Standard Format TVP5020 Microcode after Modification
List Tables
Microcontroller Port Utilization DIP-Switch Settings TVP56000EVM Jumper Settings TVP56000EVM Using Sampling Rate Dependent Jumper Settings Source Code Module Relationships TVP5020 Register Patches Controller: Master Transmitter States Controller: Master Receiver States
SLAA051
TVP5020 NTSC/PAL Video Decoder Programming Host Interface
Michael Tadyshak
ABSTRACT This application report provides complete working example C-language program initialize TVP5020 NTSC/PAL video decoder using interface. This Example Initialization Program executes TVP56000EVM evaluation module featuring TVP5020 video decoder TVP6000 video encoder. Topics covered include TVP56000EVM hardware platform, microcontroller-specific aspects, detailed description source code modules.
Introduction
TVP5020 NTSC/PAL Video Decoder enables wide range applications providing support each following host interfaces: (Inter-Integrated Circuit) 1995 Philips Semiconductors (Video Interface Port) 1994, 1996, 1997 Video Electronic Standards Association (Video Module Interface) 1997 Cirrus Logic
Software development time reduced utilizing this Example Initialization Program. user modify rebuild source code quick verification TVP56000EVM. Also, TVP5020 specific source code modules used reference software development user's hardware platform.
Hardware Platform
Hardware Platform
Block Diagram
This program tested TVP56000EVM (Evaluation Module TVP5020 Video Decoder TVP6000 Video Encoder). block diagram this shown Figure program executed Philips P80C652 Microcontroller. This device derivative Intel 80C51 microcontroller second-sourced Philips. P80C652 includes on-chip controller. program stored flash memory device. This device Atmel 29C512. Since this program scaled-down version complete microcode program, does support flash reprogramming serial port. order install this program EVM, must programmed into flash memory device with PROM programmer. also static available program use.
J3-Y J3-C Comp Comp S-Video In(Y) S-Video In(C) Y[7:0] TVP5020 TVP6000 Comp S-Video Out(Y) S-Video Out(C) XTAL Y[7:0] J5-Y J5-C
Y[7:0] SCLK XTAL Philips P80C652 Microcontroller D+3.3 PLL+3.3 XTAL Voltage Regulator D1CLK
Flash Memory
J7-4
J7-5
J7-3
RS-232
Figure TVP56000EVM Block Diagram
SLAA051
RBUS 2NBS08-TJ2-103-ND RPACK Bourns SOIC DIP-3 /SYSRST AD[7:0]
CONTROL SENSE /RESIN RESET /RESET
SW_PUSH
TLC7705 A[0:1] (socketed)
Polarized cap-stripe marked
RX2(in) (socketed) 80C652
HEADER T6RST T6RST 74F573
P1.4 P1.3 P1.2 P1.1 P1.0 P0.0/AD0 P0.0/AD1 P0.0/AD2 P0.0/AD3
Normal ('H')
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
Load ('L') INTREQ TX2(out) INTREQ P3.3
P3.6/WR P3.7/RD XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12
P1.5 P1.6/SCL P1.7/SDA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 PSEN P2.7/A15 P2.6/A14 P2.5/A13 /PSEN
/FRD /FWR
74ALS05
AT29C512 Byte Flash Memory
A[15:8]
74ALS05
11.059 PAL1 (socketed)
RI(in) DTR(out) CTS(in) TX(out) RTS(out) RX(in) DSR(in) DCD(in)
CONNECTOR
/TRD TVP5020 /TCE /RAMWR /RAMRD /FWR /FRD
TX2(out) RX2(in)
MCM6206DJ25 Byte /RAMWR
RI(in) DCD(in) CTS(in) DTR(out) TX1(out) RX1(in) RTS(out) DSR(in) TX(out) RX1(in) TX1(out) RX(in)
TVP5020NTSC/PAL Video Decoder
/PSEN IO18 IO17 IO16 IO15 IO14 IO13 IO12 TIBPAL16L8 HEADER
SN75185
Video Chip Evaluation System: Controller
Hardware Platform
Figure Microcontroller Interface Schematic
Hardware Platform
Schematic Diagram Microcontroller Interface
Figure shows schematic diagram microcontroller surrounding circuitry. Refer this diagram understand some hardware-specific aspects program. P80C652 four 8-bit ports. Since device configured external memory, port used multiplexed lower address data (AD[7-0]), port used output upper address bits A[15-8]. ports have some dedicated functions otherwise user-defined, described Table names signal name column shown exactly they would appear source code. Each macro representing special-function register special-function defined P80C652. user-defined bits FLASHJMP, LED1, LED2 used this program. used read corresponding DIP-switches select video mode shown Table DIP-switch used. T6RESET provides software means reset TVP6000 video encoder. INTREQ used read interrupt request signal from TVP5020. Notice that clock (SCL) data (SDA) signals must each pulled with resistor. Table Microcontroller Port Utilization
NAME P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 SIGNAL NAME T6RESET INTREQ FLASHJMP LED1 LED2 DIRECTION Output Input Input Input Output Output Output Input Output Input Input Output Output Output Output FUNCTION Flash memory state switch switch switch Flash memory state TVP6000 reset clock data RS-232 receive data RS-232 transmit data TVP5020 interrupt request Flash memory jumper External memory write strobe External memory read strobe DEFINITION User-defined User-defined User-defined User-defined User-defined User-defined Dedicated Dedicated Dedicated Dedicated User-defined User-defined User-defined User-defined Dedicated Dedicated
Table DIP-Switch Settings TVP56000EVM
VIDEO STANDARD NTSC NTSC SAMPLING RATE CCIR601 Square pixel CCIR601 Square pixel INDIVIDUAL SWITCHES S3-3 S3-2 S3-1
SLAA051
Hardware Platform
2.2.1 Memory Mapped Interface
TVP56000EVM uses memory-mapped scheme control TVP5020's host interface. external data memory space split half. lower chip (U9). chip enable active only when upper address (A15) logic equations PAL1 Section 2.3. signals state indicators flash memory reprogram process. other times TVP5020 chip enable (TCE) then active when This corresponds addresses 8000h FFFFh, only addresses 8000h 8003h actually used VMI. TVP5020 read-enable (TRD) goes active when read strobe (RD) from microcontroller goes active. TVP5020 write-enable (RWR) same equation write-enable goes active when write strobe (WR) from microcontroller goes active. signals activated when microcontroller accesses external data memory (`xdata') space. supports timing mode which: output connected. Jumper JP12 must removed. input must jumpered RAMWR connecting jumper across pins input connected directly from PAL1. input must jumpered connecting jumper across pins software side, array four bytes named g_pVMI declared xdata space. This must done separate source file shown listing VMI_PORT.C Section 2.4. make file shown Section 2.5, variables declared file VMI_PORT.C specified xdata space starting address 8000h. file (page shows that linker placed g_pVMI array xdata space from 8000h 8003h required.
TVP5020 NTSC/PAL Video Decoder
Hardware Platform
Source File PAL1
;PALASM Design Description Declaration Segment --------- TITLE FLASH/RAM CONTROL LOGIC PATTERN REVISION 1.02 AUTHOR MIKE TADYSHAK COMPANY DATE CHIP TEXAS INSTRUMENTS, INC. FUSE CHECKSUM 3EC4
8/18/98 PAL1 PAL16L8
Declarations ------------ PSEN_ FRD_ FWR_ RRD_ RWR_ TCE_ TRD_ COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL
Boolean Equation Segment ----- EQUATIONS ENABLE OUTPUTS FRD_.TRST FWR_.TRST RRD_.TRST RWR_.TRST TCE_.TRST TRD_.TRST VCC; VCC; VCC; VCC; VCC; VCC; (S1,
STATE DEFINITIONS
EXECUTE FROM FLASH, EXECUTE FROM EXECUTE FROM EXECUTE FROM
READ READ READ
WRITE WRITE
(NORMAL) (LOADER)
WRITE FLASH (PROGRAM) (POLL)
READ FLASH
SLAA051
Hardware Platform
Source File PAL1 (continued)
FLASH read-enable Normal state: Flash read PSEN_ (code space) Poll state: Flash read (XDATA space) when polling completion internal programming cycle /FRD_ /PSEN_
/RD_; ;FLASH WRITE STROBE Flash program state: Write strobe from routed flash memory /FWR_ /WR_;
;RAM read-enable Normal, Loader, Program states: Read control from routed Loader, Program, Poll states: Code executes from RAM. /RRD_ /RD_ /RD_ /PSEN_ /PSEN_;
;RAM WRITE STROBE Normal, Loader states: Write strobe from routed RAM. /RWR_ /WR_;
;VMI SLAVE CHIP ENABLE Normal state: Enabled addresses 8000h FFFFh range. /TCE_ A15;
;VMI SLAVE read-enable Normal state: Read control from routed slave /TRD_ /RD_;
Simulation Segment ------------ SIMULATION
TVP5020 NTSC/PAL Video Decoder
Hardware Platform
Source File: VMI_PORT.C
VMI_Port.C Declaration Memory-Mapped TVP5020 Ports These mapped 8000-8003h make file APP_VMI.LIN four locations TVP5020 mapped g_pVMI[ADDRESS] accesses address register g_pVMI[DATA g_pVMI[FIFO accesses data accesses FIFO register register register
g_pVMI[STATUS accesses status
unsigned char xdata g_pVMI[4];
Make File: APP_VMI.LIN
NOLI RS(128) PL(68) PW(78) XDATA( ?XD?VMI_PORT( 8000h
SLAA051
Hardware Platform
File: APP_VMI.M51
01/30/99 14:44:51 PAGE
BL51 BANKED LINKER/LOCATER V3.52 MEMORY MODEL: LARGE LINK MODULE: APP_VMI (MAIN)
TYPE
BASE
LENGTH
RELOCATION
SEGMENT NAME
0000H 0008H IDATA 0010H 0018H
0008H 0008H 0008H 0001H
ABSOLUTE
"REG BANK
ABSOLUTE UNIT
"REG BANK ?STACK
XDATA XDATA XDATA XDATA XDATA XDATA 0000H 0005H 0007H 0015H 0019H 001BH 0038H XDATA 8000H
0005H 0002H 000EH 0004H 0002H 001DH 7FC8H 0004H
UNIT UNIT UNIT UNIT UNIT UNIT
?XD?MAIN ?XD?TIMER ?XD?I2C ?XD?I2C6000 ?XD?VMI5020 _XDATA_GROUP_
UNIT ERROR(S)
?XD?VMI_PORT
LINK/LOCATE COMPLETE.
WARNING(S),
TVP5020 NTSC/PAL Video Decoder
Hardware Platform
Schematic Diagram-TVP5020 NTSC/PAL Video Decoder
schematic diagram showing TVP5020 surrounding circuitry shown Figure host interface includes eight data lines, address lines, five control lines. bidirectional multiplexed address/data lines P80C652 connected TVP5020 bidirectional data pins D7-D0 pulled through resistors. least significant address lines P80C652 (after demultiplexing) connected TVP5020 address pins A1-A0 pulled through resistors. TVP5020 VC0(RDY) output left unconnected. Jumper JP12 must removed. RAMWR output from PAL1 must connected TVP5020 VC1(WR) input. make this connection, jumper across pins output from PAL1 connected directly TVP5020 VC2(RD) input. output from PAL1 must connected TVP5020 VC3(CE) input. make this connection, jumper across pins TVP5020 INTREQ connected P80C652 user-defined P3.2, read using macro named INTREQ. Figure shows TVP56000EVM board layout. Refer this figure location orientation jumpers, switches, connectors. jumper settings summarized Table setting irrelevant, since program does make serial port. Jumper settings selection between CCIR601 square pixel sampling rates shown Table
SLAA051
DVDD_3.3 LT1585CT-3.3 Solid Tantalum mark polarization DVDD_3.3 RPACK 2NBS08-TJ2-103-ND RBUS GLCO
HEADER JP10 PALI EXT_DATA8 HEADER JP11 HEADER Y[7:0] RSTINB XTAL1 XTAL2 /RAMWR /TCE HSYN AVID VSYN SCLK INTREQ RBUS D[7:0] /TRD RSTINB XTAL1 XTAL2 /RAMWR /TCE HSYN AVID VSYN SCLK INTREQ
DGND DGND DVDD DGND DVDD 0.01 0.01 0.01
RPACK
Selects TVP5020 Mode: GLCO PALI Mode MODE
PCLK PREF SCLK XTAL2 XTAL1 PALI GLCO HSYN VSYN PLL_BYP AVID GPCL PLL_AVDD RSTINB
EXT_DATA8 INTREQ
VBIAS_CH1 CH1_AGND VI_1B VI_1A CH1_AVDD REFM REFP CH2_AVDD VI_2A VI_2B CH2_AGND VBIAS_CH2 AOUT_P AOUT_N AFE_GND NSUB AFE_VDD DTO_AVDD DTO_AGND
EXT_DATA_8 DVDD DGND DVDD INTREQ
TVP5020
PCLK PREF SCLK DGND XTAL2 XTAL1 DVDD PALI GLCO HSYN VSYN PLL_BYP AVID GPCL PLL_AVDD SCAN_CLK0 RSTINB GAN_EN TMODE
2NBS16-TG1-103-ND RPACK A[1:0] DGND DVDD_3.3 DGND DVDD_3.3 EXT_DATA8 DGND DVDD_3.3 DGND DVDD_3.3 INTREQ
LT1585CT-3.3
AVCC 0.01
QFP80SOC
PCLK PREF SCLK DGND XTAL2 XTAL1 DVDD_3.3 PALI GLCO HSYN VSYN PLL_BYP AVID GPCL PLL_AVDD DGND RSTINB DGND DGND
3VBIAS_CH1
5VI_1B 6VI_1A
VBIAS_CH2 AOUT_P AOUT_M
REFM REFP
VI_2A VI_2B
TVP5020NTSC/PAL Video Decoder
JP12 JUMPER
Install JP12 I2C. Remove JP12 VMI.
AVCC
/TCE HEADER /RAMWR HEADER
VI_1A VI_1B VI_2A VI_2B
VBIAS_CH1 AGND VI_1B VI_1A AVCC REFM AVCC AVCC VI_2A VI_2B AGND VBIAS_CH2 AOUTP AOUTN AGND AGND AVCC AVCC AGND
Hardware Platform
Sets I2CA Chip Enable Host
Selects /RAMWR Host
TVP5020
Figure TVP5020 NTSC/PAL Video Decoder Schematic
Hardware Platform
Composite Video S-Video Composite Video S-Video Composite Video
Analog Regulator Power Connector
TVP6000 Test Points
TVP5020 Test Points
TVP5020
-12V
TVP6000 JP12 80C652 Microcontroller
Regulator
LEDs
Digital Video
Reset Button Digital Video
PAL1 Flash Memory Switches
RS-232 Port
Figure TVP56000EVM Board Layout Table Jumper Settings TVP56000EVM Using
JUMPER(s) Position Description NORMAL 1-3, STRAIGHT CABLE TVP6000: RCVR SCLK JP9, JP10, JP11 mode JP12
Table Sampling Rate Dependent Jumper Settings
SAMPLING RATE CCIR601 Square Pixel
SLAA051
Program Overview
Program Overview
This program complete working example C-language program initialize TVP5020 NTSC/PAL video decoder using interface. program compiled linked using uVision/51 Windows, software package compiling code 80C51-type microcontrollers from Keil Software, Inc. Information about Keil Software found Internet www.keil.com. Help-About dialog this software package (Figure in-circuit emulator debugging P80C652 code USP-51 from Signum Systems. Information about Signum Systems found Internet www.signum.com. Help-About dialog USP-51 emulator software (Figure linker output standard Intel Intellec 8/MDS format. This format widely supported PROM programmers. program then installed TVP56000EVM programming flash memory device (Atmel 29C512) using PROM programmer. program contains TVP5020 microcode four video modes enable testing NTSC video standards using CCIR601 square pixel sampling rates. video mode selected setting switches shown Table
Figure Help-About Dialog from uVision/51 Windows
TVP5020 NTSC/PAL Video Decoder
Program Overview
Figure Help-About Dialog Signum Systems In-Circuit Emulator
Microcontroller-Specific Macros
Most source code standard C-language. main exception macros access special-function registers special-function bits defined P80C652. complete macros defined P80C652 contained file REG652.H, which shown section 3.2. Table shows, there several user-definable pins assigned special EVM. These named ports sections header file. these user-definable pins, this program uses only INTREQ, SW2, SW3, T6RESET. used read corresponding switches, T6RESET provides software reset TVP6000 video encoder. Many P80C652-specific special-function registers used control on-chip general-purpose timer interface. These localized TIMER source-code modules. P80C652 provides bytes on-chip RAM, direct support external data memory (xdata space), read-only memory (code space). keywords xdata code sometimes required variable declarations specify type memory storage. example, arrays unsigned char, which hold TVP5020 microcode modules, declared with code keyword that they stored flash memory.
SLAA051
Program Overview
Header File: REG652.H
REG652.H Header file Philips P80C652 Microcontroller. BYTE Registers 0x80; 0x90; 0xA0; 0xB0; PCON TCON TMOD S0CON S0BUF S1CON S1STA S1DAT S1ADR 0xD0; 0xE0; 0xF0; 0x81; 0x82; 0x83; 0x87; 0x88; 0x89; 0x8A; 0x8B; 0x8C; 0x8D; 0xA8; 0xB8; 0x98; UART control 0x99; UART data buffer 0xD8; 0xD9; 0xDA; 0xDB; control register status register data register address register
Register sbit 0xD7; sbit 0xD6; sbit 0xD5; sbit 0xD4; sbit 0xD3; sbit 0xD2; sbit 0xD0; TCON sbit sbit sbit sbit sbit sbit sbit sbit
0x8F; 0x8E; 0x8D; 0x8C; 0x8B; 0x8A; 0x89; 0x88;
TVP5020 NTSC/PAL Video Decoder
Program Overview
Header File: REG652.H (continued)
sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit sbit
0xAF; 0xAD; interrupt enable 0xAC; UART interrupt enable 0xAB; 0xAA; 0xA9; 0xA8; 0xBD; 0xBC; 0xBB; 0xBA; 0xB9; 0xB8; 0x97; 0x96; 0x95; 0x94; 0x93; 0x92; 0x91; 0x90; 0xB7; 0xB6; 0xB5; 0xB4; 0xB3; 0xB2; 0xB1; 0xB0;
sbit sbit sbit T6RESET sbit sbit sbit sbit sbit sbit sbit sbit LED2 sbit LED1 sbit FLASHJMP sbit INTREQ sbit sbit S0CON sbit sbit sbit sbit sbit sbit sbit S1CON sbit sbit sbit sbit sbit sbit sbit ENS1 sbit
0x9E; 0x9D; 0x9C; 0x9B; 0x9A; 0x99; 0x98; 0xD8; 0xD9; 0xDA; 0xDB; 0xDC; 0xDD; 0xDE; 0xDF;
SLAA051
Program Overview
Source-Code Modules
Table summarizes relationships between various source-code modules. Each source-code module contained source file associated header file. Timer modules described microcontroller-specific. order port these functions another hardware environment, equivalent functions, written specific processor, would need supplied created. Main I2C6000 modules could used virtually unchanged. environment, TVP6000 software reset (T6RESET), well reading INTREQ DIP-switch lines SW3, would have implemented. Table Source Code Module Relationships
SOURCE-CODE MODULE Main Timer VMI5020 I2C6000
DESCRIPTION Main program General-purpose timer routines routines TVP5020 routines TVP6000-specific routines
MICROCONTROLLERSPECIFIC?
TVP56000EVMSPECIFIC? (uses T6RESET) (uses INTREQ, SW3)
CALLS FUNCTIONS THESE MODULES I2C5020, I2C6000, Timer None Timer None I2C, Timer
TVP5020 NTSC/PAL Video Decoder
Program Description
Program Description
Source-Code Module: Main
4.1.1 Inclusion TVP5020 Microcode Files (Lines 11-14)
Header files containing TVP5020 microcode included. These provide support NTSC video standards with CCIR601 square pixel sampling. Each header file declares array type unsigned char. first byte each array subaddress writing TVP5020 program memory (0x7E). TVP5020 microcode supplied five-character Hex-ASCII format (Figure Conversion standard C-language header file done with utility called HexConv. output HexConv shown Figure necessary, #define constant code size (which includes subaddress byte 0x7E) well array name given unique name. target processor 80C51 derivative, keyword code must inserted. Also, adding comment identifying microcode type version very helpful. resulting microcode file shown Figure
4.1.2 Function: Main()
4.1.2.1 Declaration TVP5020 Register Patch Data (Lines 16-24) After microcode downloaded TVP5020 restarted, registers initialized with their default values defined TVP5020 data manual) internal CPU. Some registers must patched with different value TVP5020 function properly TVP56000EVM. array g_pTVP5020Patch[ contains address data three registers that must modified. Table describes these register changes. Table TVP5020 Register Patches
ADDRESS DEFAULT DATA PATCHED DATA COMMENT Enable HSYN, VSYN, AVID, SCLK, PCLK outputs Bypass luminance processing during vertical blank Select 8-bit ITU-R BT.656 interface
80000 00000 303FC C3F80
Figure TVP5020 Microcode Hex-ASCII Format
SLAA051
Program Description
#define TVP5020_CODE_SIZE 0x27b8 unsigned char TVP5020_CODE[] 0x7E, 0x08, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0xFC, 0x0C, 0x3F, 0x80
Figure TVP5020 Microcode after Conversion Standard Format
#define TVP5020_N601_CODE_SIZE 0x27b8 TVP5020 NTSC CCIR601 Version: unsigned char code T520_N601[] 0x7E, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0xFC, 0x0C, 0x3F, 0x80
Figure TVP5020 Microcode after Modification
TVP5020 NTSC/PAL Video Decoder
Program Description
4.1.2.2
Initialization (Lines 37-45) function call timer0_initialize() initializes P80C652 on-chip general-purpose timer generate timer-tick interrupt every Next, timer0_wait() called produce delay insure stabilization after reset. call DecoderReset() configures TVP5020 interrupt request output (INTREQ).
4.1.2.3
Video Mode Selection (Lines 47-72) current state switches read. lsbs used select video mode shown Table global variables g_nROMCodeSize g_pROMCode initialized with size selected microcode file bytes including subaddress byte) with starting address selected microcode data array.
4.1.2.4
Reset Timer-Tick (Line call ResetTickCount() resets internal count timer-tick interrupts (which occur every ms). timer-tick count about seconds before rolling over. program with multiple uses general-purpose timer, timer-tick count should reset only outermost loop.
4.1.2.5
Power-up Initialization (Line call PowerUpInitialization() performs tasks downloading TVP5020 microcode, restarting TVP5020 internal CPU, patching TVP5020 registers, initializing TVP6000 video encoder. parameter passed PowerUpInitialization() indicate selected video mode. Upon return from PowerUpInitialization(), program spins endless loop.
4.1.3 Function: Power-up Initialization()
4.1.3.1 Microcode Download (Line call HandleDownload() calls specific routine which will download microcode video decoder. code size code pointer variables passed parameters. HandleDownload() routines have been written I2C, VIP, interfaces. source-code module VMI5020.C contains version HandleDownload() Bus. 4.1.3.2 Restart Microprocessor (Lines 96-102) After microcode download completes, internal microprocessor restarted. This done writing byte (the data value) restart subaddress (7Fh). function WriteTVP5020() used whenever required write TVP5020 register. parameters passed WriteTVP5020() byte count (this always pointer storage location subaddress data byte. wait inserted after restart command enable internal microprocessor complete initialization code. 4.1.3.3 Patch TVP5020 Registers (Lines 104-105) call PatchTVP5020Registers() implements register modifications which were described Section 4.1.2.1 Table
SLAA051
Program Description
4.1.3.4
Reset TVP6000 Video Encoder (Lines 107-110) user-definable P1.5 used software-controlled reset TVP6000. T6RESET macro which allows control P1.5. TVP6000 reset input held active after TVP5020 initialized. This needed, since TVP6000 guaranteed have received clock from TVP5020 during power-up reset.
4.1.3.5
Initialize TVP6000 Video Encoder (Lines 112-113) call LoadTVP6000() initializes video encoder registers. parameter passed indicate selected video mode. register data located header file DATA6000.H.
4.1.4 Function: Patch TVP5020 Registers()
4.1.4.1 Loading Registers (Lines 120-123) loop used patch TVP5020 registers using data g_pTVP5020Patch array. This array global variable initialized lines 17-24. constant TVP5020_PATCH_SIZE holds number bytes array must changed number register writes changed.
Header File: Main.H
Main.H Header file main program initialize TVP5020 Video Decoder #define FALSE #define TRUE !FALSE #define TVP5020_RESTART_SUB_ADDR void void unsigned char void void unsigned void 0x7F
main (void); DecoderReset( void ReadSwitch( void PowerUpInitialization( nSwitch HandleDownload( unsigned nCount, unsigned char* pInBuf WriteTVP5020(int nLength, unsigned char *pBuf PatchTVP5020Registers(void);
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: Main.C
COMPILER V5.10, COMPILATION MODULE MAIN OBJECT MODULE PLACED MAIN.OBJ COMPILER INVOKED C:\C51\BIN\C51.EXE MAIN.C LARGE stmt level source Main.C Main program initialize TVP5020 Video Decoder #include "Main.h" #include "Timer.h" #include "Reg652.h" #include "I2C6000.H" //TVP5020 microcode files #include "5020NSQP.H" #include "5020N601.H" #include "5020PSQP.H" #include "5020P601.H" Registers modify after TVP5020 startup #define TVP5020_PATCH_SIZE unsigned char code g_pTVP5020Patch[] subaddress, data 0x03, 0x19, 0x07, 0x10, 0x0D, 0x0F Size TVP5020 microcode file (defined 5020xxxx.H) unsigned g_nROMCodeSize TVP5020_N601_CODE_SIZE; Pointer TVP5020 microcode unsigned char* g_pROMCode T520_N601;
SLAA051
Program Description
Source File: Main.C (Continued)
void main(void) Switch value unsigned char nSwitch Initialize general purpose timer timer0_initialize(); Wait 100ms stabilization after reset timer0_wait(ONE_HUNDRED_MS); Bus, this configures TVP5020 interrupt output //(INTREQ) Bus, this sends reset code emulation FPGA DecoderReset(); LSBs switch select video mode nSwitch ReadSwitch() Point microcode selected switch switch( nSwitch case g_pROMCode T520_N601; g_nROMCodeSize TVP5020_N601_CODE_SIZE; break; case g_pROMCode g_nROMCodeSize break; case g_pROMCode g_nROMCodeSize break; case g_pROMCode g_nROMCodeSize break; Reset timer-tick avoid rollover ResetTickCount(); Initialize video mode PowerUpInitialization( nSwitch After video initialized, nothing while(1) return;
T520_NSQP; TVP5020_NSQP_CODE_SIZE;
T520_P601; TVP5020_P601_CODE_SIZE;
T520_PSQP; TVP5020_PSQP_CODE_SIZE;
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: Main.C (Continued)
void PowerUpInitialization( nSwitch unsigned char buf[2]; Download video decoder microcode HandleDownload( g_nROMCodeSize, g_pROMCode //Restart microprocessor buf[0] TVP5020_RESTART_SUB_ADDR; buf[1] WriteTVP5020( Wait 10ms TVP5020 start-up timer0_wait(TEN_MS); Modify registers from default state required PatchTVP5020Registers(); Reset TVP6000 T6RESET timer0_wait(ONE_HUNDRED_MS); T6RESET Initialize TVP6000 LoadTVP6000( nSwitch void PatchTVP5020Registers (void) for( i=0; i<TVP5020_PATCH_SIZE; i+=2 WriteTVP5020( g_pTVP5020Patch+i return;
COMPILATION COMPLETE.
WARNING(S),
ERROR(S)
SLAA051
Program Description
Source-Code Module:
This source-code module included only communication with TVP6000 NTSC/PAL video encoder.
4.4.1 Function: initia_i2c() (Lines 28-41)
This function initializes signals (SCL SDA) high level. internal P80C652 interrupt enabled given (normal) priority. P80C652 on-chip controller initialized master with baud rate 92.16 kHz. This frequency P80C652 oscillator frequency (11.0592 MHz) divided 120.
4.4.2 Function: start_i2c()
This function called perform transaction bus. 4.4.2.1 Initialize Variables (Lines 54-64) current timer-tick count saved used later determine timeout condition occurred. macro used globally enable disable interrupts. global variables used interrupt service routine (ISR) are: b_counter-Byte counter. Initialized 00h, counts terminal count value. num_b-Number bytes. Holds terminal count value. slave_rw-Slave device read/write bit. i2cbuf-Pointer caller's data buffer. 4.4.2.2 Start Transaction (Lines 63-64) macro used start control register. Then, global interrupt control enables hardware interrupts. 4.4.2.3 Wait Transaction Complete (Lines 66-73) program remains loop waiting either bytes transferred occurrence error condition. Meanwhile, interrupts occurring controlling data transfer. timer-tick count checked timeout condition comparing elapsed time with g_nI2Ctimeout. value g_nI2Ctimeout units timer-ticks. timer-tick programmed occur once every
4.4.3 Function: i2c_isr() (Lines 77-266)
This interrupt service routine (ISR) interface. controller embedded P80C652. simple register interface provides access address, data, control status registers. Each time interrupt occurs, status register (S1STA) read obtain current state code from controller. state code used branch appropriate code segment handle interrupt. global variables updated data transferred to/from user's data buffer. states master transmitter master receiver described Tables last step interrupt handling writing following four codes back control register (S1CON) request specific action:
TVP5020 NTSC/PAL Video Decoder
Program Description
CONTROLLER STATE
I2C_RLS_STA -Release generate start condition I2C_RLS_ACK -Release acknowledge data transfer I2C_RLS_NACK -Release acknowledge data transfer I2C_STOP -Generate stop condition Table Controller: Master Transmitter States
DEFINITION MASTER TRANSMITTER STATES Start condition been transmitted Repeat start condition been transmitted Slave address been sent received Slave address been sent received Data been transmitted been received Send slave address Send slave address Transmit first data byte Transmit first data byte. Flag error. Transmit next data byte. data been transmitted, issue stop condition. NEXT ACTION TAKEN
Data been transmitted been received Transmit next data byte. data been transmitted, stop bus. Flag error. arbitration lost Flag arbitration lost error. Issue another start condition.
Table Controller: Master Receiver States
CONTROLLER STATE DEFINITION MASTER RECEIVER STATES Slave address been sent received transaction involves only data byte, signal controller next data byte received. Otherwise, signal controller acknowledge next data byte received. transaction involves only data byte, signal controller next data byte received. Otherwise, signal controller acknowledge next data byte received. Flag error. this previous NEXT-TO-LAST data byte, signal controller acknowledge next data byte received. this next-to-last data byte, signal controller next data byte received. NEXT ACTION TAKEN
Slave address been sent received
Data been received been transmitted
Data been received been transmitted this previous LAST data byte, signal controller acknowledge next data byte received flag error. this last data byte, then issue stop condition. relevant state information available action required error detection illegal start stop Flag error condition, controller detected entry into illegal state. controller reported state which supported Flag unsupported state error interrupt service routine
Other
SLAA051
Program Description
Header File: 12C.H
I2C.H Header file routines #define FALSE #define TRUE !FALSE #define #define #define #define #define #define ERR_I2C_NOTACK ERR_I2C_ARBILOST ERR_I2C_GERROR ERR_I2C_TIMEOUT ERR_I2C_BUSERROR ERR_I2C_DEVID 0x01 0x02 0x04 0x08 0x10 0x20
void initia_i2c(void); unsigned start_i2c(unsigned char i2c_addrs, buf_length, unsigned char bufaddrs);
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: I2C.C
COMPILER V5.10, COMPILATION MODULE OBJECT MODULE PLACED I2C.OBJ COMPILER INVOKED C:\C51\BIN\C51.EXE I2C.C LARGE stmt level source I2C.C Routines #include "I2C.h" #include "Timer.h" #include "reg652.h" #define FALSE #define TRUE #define I2C_STOP #define I2C_RLS_ACK #define I2C_RLS_NACK #define I2C_RLS_STA !FALSE 0xD5 0xC5 0xC1 0xE5
generated kBps Release Release Release
STOP condition I2C, generate generate generate START
Timeout unsigned g_nI2CTimeout
TEN_SECONDS;
unsigned unsigned unsigned unsigned
Errors length send buffer number bytes that will sent/read number bytes that will sent/read unsigned char xdata slave_rw slave address plus read/write direction static unsigned char *i2cbuf (unsigned char*)0; pointer send/receiving buffer This function will initialize interface void initia_i2c(void) data high level clock high level enable interrupt interrupt PRIORITY level S1CON I2C_RLS_ACK; 80C652 master only, rate 92.16k
xdata xdata xdata xdata
error_i2c b_counter num_b num_b_minus_1
SLAA051
Program Description
Source File: I2C.C (continued)
This function transfers block data unsigned start_i2c( unsigned char i2c_addrs, buf_length, unsigned char *bufaddrs unsigned xdata start_point; unsigned test reference time start_point current_tick Disable interrupt b_counter num_b (unsigned)buf_length; num_b_minus_1 num_b slave_rw i2c_addrs; i2cbuf bufaddrs; initialized buffer point S1CON, start wait until data buffer have been sent while (b_counter num_b) error_i2c g_nI2Ctimeout) error_i2c ERR_I2C_TIMEOUT; return( b_counter interrupt service routine interrupt number=5, address=0x002Bh, using register bank2 static void i2c_isr (void) interrupt using unsigned char i2cst; unsigned char nDummy i2cst S1STA;
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: I2C.C (continued)
switch (i2cst) following section will MASTER transmit mode START condition been sent will send slave address case 0x08: S1DAT slave_rw; S1CON I2C_RLS_ACK; break; repeat START been transmitted will load SLA+R/W, return case 0x10: S1DAT slave_rw; S1CON I2C_RLS_ACK; break; slave address been send received will send byte data case 0x18: S1DAT *i2cbuf; load byte data register S1CON I2C_RLS_ACK; break; received, will send byte data anyway case 0x20: S1DAT *i2cbuf; load byte data register S1CON I2C_RLS_ACK; error_i2c ERR_I2C_NOTACK; break; continue sending data byte data been sent received data were sent, then transmit STOP else continue transmit next byte case 0x28: b_counter++; Last state b_counter will num_b b_counter num_b S1DAT *(i2cbuf+b_counter); send byte data S1CON I2C_RLS_ACK; else S1CON I2C_STOP; data were sent,stop break;
SLAA051
Program Description
Source File: I2C.C (continued)
byte data been sent rcvd case 0x30: b_counter++; Last state b_counter will num_b b_counter num_b S1DAT *(i2cbuf+b_counter); send byte data S1CON I2C_RLS_ACK; else S1CON I2C_STOP; data were sent, stop error_i2c ERR_I2C_NOTACK; break; arbitration lost, release restart case 0x38: S1CON I2C_RLS_STA; error_i2c ERR_I2C_ARBILOST; break; following section will MASTER receive mode /*SLA+R been sent, received case 0x40: num_b Only byte will received, don't acknowledge This will signal slave transmitter stop S1CON I2C_RLS_NACK; else More than byte will received, acknowledge first S1CON I2C_RLS_ACK; break;
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: I2C.C (Continued)
received SLA+R, will ignore case 0x48: num_b Only byte will received, don't acknowledge This will signal slave transmitter stop S1CON I2C_RLS_NACK; else More than byte will received, acknowledge first S1CON I2C_RLS_ACK; error_i2c ERR_I2C_NOTACK; break;
byte been received, returned case 0x50: read byte from S1DAT *(i2cbuf b_counter) S1DAT; b_counter++; this prior next-to-last byte b_counter num_b_minus_1 Acknowledge next byte received S1CON I2C_RLS_ACK; this next-to-last byte else acknowledge next byte received (the last byte) This will signal slave transmitter stop S1CON I2C_RLS_NACK; break;
SLAA051
Program Description
Source File: I2C.C (continued)
byte received returned This should last byte received case 0x58: read byte from S1DAT *(i2cbuf b_counter) S1DAT; b_counter++; this last byte error condition b_counter num_b S1CON I2C_RLS_ACK; error_i2c ERR_I2C_NOTACK; this last byte, then STOP else S1CON I2C_STOP; break; Relevant state information available action required case 0xF8: nDummy break; error illegal start stop condition SIO1 entered illegal state case 0x00: S1CON I2C_RLS_ACK; error_i2c ERR_I2C_BUSERROR; break; other cases will error this system default: S1CON I2C_RLS_ACK; error_i2c ERR_I2C_GERROR; break; WARNING(S), ERROR(S)
COMPILATION COMPLETE.
TVP5020 NTSC/PAL Video Decoder
Program Description
Source-Code Module: Timer
general-purpose timer used insert time delays determine when timeout condition occurred. timer programmed that timer `tick' interrupt occurs every
4.7.1 Function: timer0_isr() (Lines 26-59)
This general-purpose timer. timer stopped. constant loaded into timer data registers (TL0 TH0). timer restarted. timer increments generates interrupt when reaches maximum count. Each time timer-tick interrupt occurs, global variable `timer0_tick' incremented constant calculated that time from timer restart until reaches maximum count equation calculating timer reload value (TH0, TL0) from desired timer-tick period shown below. calculated timer reload value with 11.0592 crystal timer-tick period F8CDh. TH0, 10000h fosc TH0, 10000h ((11059200 0.002) TH0, F8h,
4.7.2 Function: timer0_initialize() (Lines 61-94)
This function initializes general-purpose timer. called once program startup. timer-tick count initialized zero then timer stopped. timer mode 16-bit counter with prescaling, then timer reload value written. timer interrupt enabled given (normal) priority, then timer restarted. global interrupt control (EA) enabled. this point, timer-tick interrupts start occurring.
4.7.3 Function: ResetTickCount() (Lines 96-112)
call ResetTickCount() resets timer-tick count zero. timer-tick count about seconds before rolling over. program with multiple uses general-purpose timer, timer-tick count should reset only outermost loop.
4.7.4 Function: current_tick() (Lines 114-131)
This function returns current timer-tick count.
4.7.5 Function: timer0_elapsed_count() (Lines 133-150)
This function returns number elapsed timer-tick counts. parameter starting timer-tick count from which measure elapsed time.
4.7.6 Function: timer0_wait() (Lines 152-167)
This function generates time delay. parameter number timer-tick counts delay.
SLAA051
Program Description
Header File: Timer.H
Timer.H Header file P80C652 microcontroller general purpose timer routines #define TCLK 11059200 Clock speed TICK #define TEN_MS #define ONE_HUNDRED_MS #define ONE_SECOND #define TEN_SECONDS void unsigned unsigned void void
500u 5000u
timer0_initialize (void); current_tick (void); timer0_elapsed_count (unsigned start_tick); timer0_wait (unsigned num_tick); ResetTickCount( void
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: TIMER.C
COMPILER V5.10, COMPILATION MODULE TIMER OBJECT MODULE PLACED TIMER.OBJ COMPILER INVOKED C:\C51\BIN\C51.EXE TIMER.C LARGE stmt level source Timer.C P80C652 microcontroller general purpose timer routines #include "Timer.h" #include "reg652.h" Constant Declarations Every TIMER0 OVERFLOW interrupt will occur once tick: 10000h ((11,059,200 Hz/12) 0.002) 0xF8CD #define TIMER0_HI (unsigned char) 0xF8 #define TIMER0_LO (unsigned char) 0xCD Local Variable Declarations static unsigned xdata timer0_tick; static void timer0_isr (void); This function interrupt service routine TIMER should never called assembly function. will executed automatically when TIMER overflows.
SLAA051
Program Description
Source File: TIMER.C (Continued)
static void timer0_isr (void) interrupt using Adjust timer counter that another interrupt stop timer TIMER0_LO; TIMER0_HI; start timer
Increment timer-tick. This interrupt should occur approximately every 2ms. timer0_tick++; void timer0_initialize (void); TIMER0 mode 16bit timer This function enables TIMER TIMER will generate synchronous Interrupt once every void timer0_initialize (void) disable interrupts timer0_tick TMOD ~0x0F; TMOD 0x01; TIMER0_LO; TIMER0_HI; priority timer register enable timer interrupt, register start timer TCON register enable interrupts stop timer clear timer mode bits timer into 16-bit prescale
TVP5020 NTSC/PAL Video Decoder
Program Description
Source File: TIMER.C (Continued)
void ResetTickCount( void This function resets timer-tick variable zero. function should used before each time timer used time event prevent incorrect operation timer0_tick variable rolling over zero. This will work maximum 2ms, seconds. void ResetTickCount( void timer0_tick unsigned current_tick (void); This function returns current timer0 tick count. unsigned current_tick (void) unsigned xdata timer0_tick; return (t);
SLAA051
Program Description
Source File: TIMER.C (Continued)
unsigned timer0_elapsed_count (unsigned count); This function returns number timer-ticks that have elapsed since specified count. unsigned timer0_elapsed_count( unsigned start_tick return (current_tick( start_tick);
void timer0_wait unsigned count This function waits 'count' timer-ticks pass. void timer0_wait( unsigned num_tick unsigned xdata test1; unsigned xdata start_count; start_count current_tick while( test1 timer0_elapsed_count( start_count num_tick)
COMPILATION COMPLETE.
WARNING(S),
ERROR(S)
TVP5020 NTSC/PAL Video Decoder
Program Description
4.10
Source-Code Module: VMI5020
This module contains TVP5020 routines.
4.10.1 Vertical Blanking Interval Data Processor (VDP)
registers defined registers address range C2h. Non-VDP registers defined other registers. There different mechanisms accessing registers non-VDP registers. 4.10.1.1 Accessing Non-VDP Registers When writing non-VDP register writing data register, long latency will occur before TVP5020 ready write another data byte. This latency most horizontal sync period order µs). After this latency period, operation complete interrupt generated. This tested polling status register, using interrupt request signal (INTREQ) done this program. After receiving interrupt, TVP5020 initiate another write cycle writing data register again. Also, when loading address register with address readable non-VDP register, long latency will occur before data byte ready TVP5020 read. This latency most horizontal sync period. After this latency period, operation complete interrupt generated. This tested polling status register, using interrupt request signal (INTREQ) done this program. After receiving interrupt, data register read obtain read data. 4.10.1.2 Accessing Registers When writing register writing data register, long latency will occur before TVP5020 ready another data byte written operation complete interrupt will generated. After completion write cycle, another write cycle initiated immediately writing data register again. Also, when loading address register with address readable register, long latency will occur before data byte ready TVP5020 read, operation complete interrupt will generated. data register read immediately obtain read data.
4.10.2 Function: DecoderReset() (Lines 20-34)
This function configures TVP5020 interrupt output (INTREQ) required accessing non-VDP registers. First, register loaded with value 20h. This enables operation complete interrupt. Second, register loaded with value 05h. This sets INTREQ active high (bit enables outputs (bit enable must also miscellaneous controls register (address otherwise outputs will high-impedance state. This (address gets when TVP5020 registers patched after microcode download restart. Finally, written status register reset interrupt status bits initialize INTREQ inactive (0).
SLAA051
Program Description
4.10.3 Function: HandleDownload() (Lines 36-48)
This function called download microcode TVP5020 program memory. parameters passed this function. Parameter nCount number data bytes write (plus address byte). Parameter pInBuf pointer data written. first transaction, first byte data buffer must address microcode downloads (7Eh). WriteTVP5020VMI() called write address address register. global variable g_bVDPAddrRange FALSE because data will written non-VDP register. second transaction, WriteTVP5020VMI() called again write entire microcode data stream data register. third parameter FLAG_DATA_ONLY indicate that data buffer starts with data byte (not address) that address register does need loaded.
4.10.4 Function: Write TVP5020() (Lines 50-56)
This function called write TVP5020 register. parameters passed this function. Parameter nData number data bytes write (plus address byte). Parameter pBuf pointer data written. WriteTVP5020() function does nothing pass parameters WriteTVP5020VMI() function. This enables I2C5020, VMI5020 VIP5020 source-code modules used interchangeably without having change rest program.
4.10.5 Function: Write TVP5020VMI() (lines 58-127)
This function performs write cycle both non-VDP registers. Four parameters passed nLen number data bytes write (plus address byte-unless FLAG_DATA_ONLY flag set). pBuf pointer caller's data buffer. nFlags takes values FLAG_DATA_ONLY. -First byte data buffer address, load into address register. FLAG_DATA_ONLY -First byte data buffer data byte, load address register. nCtl indicates register where data bytes will written. 4.10.5.1 Address Phase (Lines 70-86) FLAG_DATA_ONLY flag set, number data bytes write same nLen count passed. address register loaded. Otherwise, subtract from nLen number data bytes. address from first byte data buffer point data pointer first data byte. Determine VDP/non-VDP status. Load address register. 4.10.5.2 Data Phase (Lines 88-125) Jump proper code segment based VDP/non-VDP status.
TVP5020 NTSC/PAL Video Decoder
Program Description
non-VDP Registers (Lines 90-117) perform following steps: Clear interrupt status register INTREQ inactive. Test wait INTREQ inactive. Write data byte from caller's data buffer data register. Test wait INTREQ active. Repeat steps thru data bytes. Clear interrupt status register INTREQ inactive. Registers (Lines 119-125), perform following steps: Write data byte from caller's data buffer data register. Repeat step data bytes.
4.10.6 Function: ReadSwitch() (Lines 129-154)
This function TVP56000EVM-specific. reads logic levels switches through defined pins P80C652. result packed into 8-bit return value.
4.10.7 Function: ReadTVP5020() (Lines 156-168)
This function called read from TVP5020 register. function used this program, included here reference. Three parameters passed this function. Parameter nLength number data bytes read. Parameter pBuf pointer caller's buffer where read data stored. Parameter nSubAddr address read from. ReadTVP5020() function does nothing pass parameters ReadTVP5020VMI() function. This enables I2C5020, VMI5020, VIP5020 source-code modules used interchangeably without having change rest program.
4.10.8 Function: ReadTVP5020VMI() (Lines 170-220)
This function performs read cycle both non-VDP registers. Three parameters passed this function: nLen number data bytes read. pBuf pointer caller's data buffer where read data stored. nSubAddr address read from. 4.10.8.1 Address Phase Determine VDP/non-VDP status. Jump proper code segment based VDP/ non-VDP status. non-VDP Registers (Lines 186-190) perform following steps: Clear interrupt status register INTREQ inactive. Load address register. Registers (Lines 212-213), load address register.
SLAA051
Program Description
4.10.8.2
Data Phase non-VDP Registers (Lines 192-208) perform following steps: Test wait INTREQ active. Clear interrupt status register INTREQ inactive Test wait INTREQ inactive. Read data byte from data register into caller's data buffer. Repeat steps thru data bytes. Registers (Lines 214-218) perform following steps: Read data byte from data register into caller's data buffer. Repeat step data bytes.
4.11
Header File: VMI5020.H
VMI5020.H Header file routines #define FALSE #define TRUE #define ADDRESS #define DATA #define FIFO #define STATUS #define ACTIVE #define INACTIVE !FALSE
#define FLAG_DATA_ONLY #define BOARD_TVP56000EVM void void unsigned
DecoderReset( void HandleDownload( unsigned nCount, unsigned char* pInBuf WriteTVP5020(int nData, unsigned char *pBuf WriteTVP5020VMI( nLen, unsigned char *pBuf, nFlags, nCtl
unsigned char ReadSwitch( void #if(0) unsigned #endif ReadTVP5020(int nLength, unsigned char *pBuf, unsigned char nSubAddr ReadTVP5020VMI( nLen, unsigned char *pBuf, nSubAddr
TVP5020 NTSC/PAL Video Decoder
Program Description
4.12
Source File: VMI5020.C
COMPILER V5.10, COMPILATION MODULE VMI5020 OBJECT MODULE PLACED VMI5020.OBJ COMPILER INVOKED C:\C51\BIN\C51.EXE VMI5020.C LARGE stmt level source VMI5020.C Routines TVP5020 using #include "VMI5020.h" #include "Reg652.h"
Identify board unsigned char g_nBoardID BOARD_TVP56000EVM; Memory-Mapped TVP5020 Ports extern unsigned char xdata g_pVMI[]; TRUE, INTREQ handshake required unsigned char g_bVDPAddrRange FALSE; void DecoderReset( void Initialize interrupts Enable operation complete interrupt g_pVMI[ADDRESS] 0xC1; g_pVMI[DATA] 0x20; INTREQ active high, enable outputs g_pVMI[ADDRESS] 0xC2; g_pVMI[DATA] 0x05; Reset interrupts g_pVMI[STATUS] 0xFF; return; void HandleDownload( unsigned nCount, unsigned char* pInBuf Write sub-address byte WriteTVP5020VMI( pInBuf++, DATA Write data block data bytes only g_bVDPAddrRange FALSE; FLAG_DATA_ONLY Buffer contains data bytes only WriteTVP5020VMI( nCount-1, pInBuf, FLAG_DATA_ONLY, DATA return;
SLAA051
Program Description
4.12 Source File: VMI5020.C (Continued)
unsigned WriteTVP5020(int nData, unsigned char *pBuf Write data 8-bit memory mapped port WriteTVP5020VMI( nData, pBuf, DATA return( nData WriteTVP5020VMI( nLen, unsigned char *pBuf, nFlags, nCtl nLen byte count including sub-address byte data bytes just data bytes pBuf pointer caller's buffer nFlags FLAG_DATA_ONLY nCtl register write data nAddr nDataLen unsigned char* pInData pBuf; Determine number data bytes nFlags FLAG_DATA_ONLY nDataLen nLen; else nDataLen nLen Point first data byte pInData++; address from buffer nAddr *pBuf; Save non-VDP status g_bVDPAddrRange nAddr 0x90 nAddr 0xC2 TRUE FALSE; Write address g_pVMI[ADDRESS] nAddr;
TVP5020 NTSC/PAL Video Decoder
Program Description
4.12 Source File: VMI5020.C (Continued)
Write 'nDataLen' bytes !g_bVDPAddrRange for(j=0; j<nDataLen; When there address write there know 'bVDPAddrRange'. Caller sets that variable before calling WriteTVP5020VMI() Reset interrupts g_pVMI[STATUS] (unsigned char)0xFF; while( INTREQ INACTIVE Write data g_pVMI[nCtl] *pInData++; register, wait interrupt that signals that write operation completed while( INTREQ ACTIVE Reset interrupts g_pVMI[STATUS] (unsigned char)0xFF; else for(j=0; j<nDataLen; Write data g_pVMI[nCtl] *pInData++; return(
SLAA051
Program Description
4.12 Source File: VMI5020.C (Continued)
unsigned char ReadSwitch( void unsigned char nVal REG652.H SW1.SW3 definitions //MSB //LSB nVal nVal nVal return( nVal
TVP5020 NTSC/PAL Video Decoder
Program Description
4.12 Source File: VMI5020.C (Continued)
#if(0) Note: This read TVP5020 register unsigned ReadTVP5020(int nLength, unsigned char *pBuf, unsigned char nSubAddr nLength data bytes read pBuf Pointer where first data word read should stored nSubAddr sub-address read ReadTVP5020VMI( nLength, pBuf, nSubAddr return( ReadTVP5020VMI( nLen, unsigned char *pBuf, nSubAddr nLen number bytes read pBuf pointer data buffer where read data stored nSubAddr sub-address read from Save non-VDP status g_bVDPAddrRange ((nSubAddr 0x90) (nSubAddr 0xC2)) TRUE FALSE; Write address !g_bVDPAddrRange Reset interrupts g_pVMI[STATUS] (unsigned char)0xFF; Write read address should INTREQ g_pVMI[ADDRESS] nSubAddr; for(j=0; j<nLen; while( INTREQ ACTIVE Reset interrupts g_pVMI[STATUS] (unsigned char)0xFF; while( INTREQ INACTIVE Read data should INTREQ *pBuf++ g_pVMI[nCtl];
SLAA051
Program Description
4.12 Source File: VMI5020.C (Continued)
else Write read address should INTREQ g_pVMI[ADDRESS] nSubAddr; for(j=0; j<nLen; Read data should INTREQ *pBuf++ g_pVMI[nCtl]; return( #endif
COMPILATION COMPLETE.
WARNING(S),
ERROR(S)
4.13
Source-Code Module: I2C6000
This module contains TVP6000-specific routines initialization data TVP6000.
4.13.1 Function: read_tvp6000() (lines 23-40)
This function called read from TVP6000 register. function used this program, included here reference. Three parameters passed this function. Parameter read_length number data bytes read. Parameter sub_addrs subaddress read from. Parameter output_buf pointer caller's buffer where read data stored. TVP6000, there restriction number bytes read transaction. function start_i2c() called first, with TVP6000 device writes, write subaddress value. Then, start_i2c() called again, with TVP6000 device reads, read requested number data bytes.
4.13.2 Function: write_tvp6000() (Lines 41-50)
This function called write TVP6000 register. parameters passed this function. Parameter write_length number data bytes write (plus subaddress byte). Parameter input_buf pointer data written. first byte data must subaddress. TVP6000, there restriction number bytes written transaction. function start_i2c() called perform data transfer. TVP6000 device writes passed parameter.
TVP5020 NTSC/PAL Video Decoder
Program Description
4.13.3 Function: LoadTVP6000() (Lines 52-75)
This function initializes TVP6000 registers. parameter nMode indicates video mode that will register data selected video mode written TVP6000 passing array name proper register data write_tvp6000(). Finally, function PatchTVP6000() called.
4.13.4 Function: PatchTVP6000 (Lines 77-97)
This function performs initialization step that necessary properly initialize interface. format momentarily changed 16-bit 4:2:2 mode then back 8-bit ITU-R BT.656 interface mode. global variable g_nBoard tested determine value write into subaddress 3Ah: video port video port This code inserted only make same code work prototype board that uses instead VP2. Normally, this statement should taken out.
4.14
Header File: I2C6000.H
I2C6000.H Header file TVP6000 routines #define ENCODER_WRITE #define ENCODER_READ #define NUM_OF_REGISTER 0x42 writing address encoder 0x43 reading address encoder 0x65 TVP6000 registers load
#define BOARD_TVP56000EVM #define BOARD_EVM3
#if(0) void read_tvp6000(int length_of_read, unsigned char first_subaddress, unsigned char* readout_buffer); #endif
void write_tvp6000(int length_of_write, unsigned char *write_buf); void LoadTVP6000( nMode void PatchTVP6000( void
SLAA051
Program Description
4.15
Source File: I2C6000.C
COMPILER V5.10, COMPILATION MODULE I2C6000 OBJECT MODULE PLACED I2C6000.OBJ COMPILER INVOKED C:\C51\BIN\C51.EXE I2C6000.C LARGE stmt level source I2C6000.C Routines TVP6000 using #include "I2C.h" #include "I2C6000.h" #include "timer.h" #include "DATA6000.h" extern unsigned char g_nBoardID;
static unsigned char patch1_6000[2] 0x3A, 0x0D //16-bit 4:2:2, color static unsigned char patch2_6000[2] 0x3A, 0x0F CCIR 656, #if(0) void read_tvp6000(int read_length, unsigned char sub_addrs, unsigned char *output_buf) unsigned char *sub_begin; sub_begin &sub_addrs; initia_i2c(); initialize
this will write first SUB-address TVP6000 after this, data will read start from this address start_i2c(ENCODER_WRITE, sub_begin); read registers TVP6000, them into temporary buffer start_i2c(ENCODER_READ, read_length, output_buf); return; #endif
TVP5020 NTSC/PAL Video Decoder
Program Description
4.15 Source File: I2C6000.C (Continued)
void write_tvp6000(int write_length, unsigned char *input_buf) initia_i2c(); initialize This will write first sub-address TVP6000 after this, data will read starting from this address subaddress will element input_buf start_i2c(ENCODER_WRITE, write_length, input_buf); return; void LoadTVP6000( nMode switch( nMode case write_tvp6000(NUM_OF_REGISTER, T600N601); break; case write_tvp6000(NUM_OF_REGISTER, T600NSQP); break; case write_tvp6000(NUM_OF_REGISTER, T600P601); break; case write_tvp6000(NUM_OF_REGISTER, T600PSQP); break; PatchTVP6000(); return; void PatchTVP6000( void unsigned nStartPoint write_tvp6000( patch1_6000 Delay 100ms nStartPoint current_tick while( timer0_elapsed_count( nStartPoint ONE_HUNDRED_MS g_nBoardID BOARD_TVP56000EVM video port TVP56000EVM patch2_6000[1] 0x1F; write_tvp6000( patch2_6000 return; WARNING(S), ERROR(S)
COMPILATION COMPLETE.
SLAA051
Program Description
4.16
TVP6000 Initialization Data NTSC with CCIR601 Sampling
DATA6000.H Header file containing TVP6000 register initialization data. unsigned char code T600N601[] Register Name Sub-Address 0x3A, SUB-ADDRESS 0x0F, F_CONTROL RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 3B-3F 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 40-47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 48-4F 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 50-57 0x00, 0x00, 58-59 0x00, C_PHASE 0x0E, GAIN_U 0x7D, GAIN_V 0xCE, BLACK_LEVEL 0xB8, BLANK_LEVEL 0x31, GAIN_Y 0x20, X_COLOR 0x0D, M_CONTROL 0x3A, BSTAMP 0x1F, S_CARR1 0x7C, S_CARR2 0xF0, S_CARR3 0x21, S_CARR4 0x00, LINE21_O0 0x00, LINE21_O1 0x00, LINE21_E0 0x00, LINE21_E1 0x12, LN_SEL 0x00, SYN_CTRL0 0x40, RCML21 0xF2, HTRIGGER0 0x00, HTRIGGER1 0xC0, VTRIGGER 0x89, BMRQ 0x39, EMRQ 0x61, BEMRQ 0x08, X2PH 0x90, X1PH 0x00, RESERVED 0xEA, BRCV 0x8A, ERCV 0x60, BERCV 0x0C, FLEN 0x06, 0x06, 0x22, FLAL 0x0E, SYN_CTRL1 RESERVED 0x00 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 80-87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 88-8F Scaling Processor Registers 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 90-97 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 98-9D
TVP5020 NTSC/PAL Video Decoder
Program Description
4.17
TVP6000 Initialization Data NTSC with Square Pixel Sampling
char code T600NSQP[] Register Name SUB-ADDRESS F_CONTROL RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, C_PHASE GAIN_U GAIN_V BLACK_LEVEL BLANK_LEVEL GAIN_Y X_COLOR M_CONTROL BSTAMP S_CARR1 S_CARR2 S_CARR3 S_CARR4 LINE21_O0 LINE21_O1 LINE21_E0 LINE21_E1 LN_SEL SYN_CTRL0 RCML21 HTRIGGER0 HTRIGGER1 VTRIGGER BMRQ EMRQ BEMRQ X2PH X1PH RESERVED BRCV ERCV BERCV FLEN FLAL SYN_CTRL1 RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, Scaling Processor Registers 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
unsigned 0x3A, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x7D, 0xCE, 0xB8, 0x31, 0x20, 0x0D, 0xBA, 0x55, 0x55, 0x55, 0x25, 0xA5, 0x50, 0xA5, 0x50, 0x14, 0x24, 0x40, 0xDE, 0x00, 0xDF, 0xBF, 0xBF, 0x50, 0x08, 0x90, 0x00, 0xD3, 0xD3, 0x50, 0x0C, 0x06, 0x06, 0x22, 0x0E, 0x00, 0x00, 0x00, 0x00,
Sub-Address 0x00, 3B-3F 0x00, 40-47 0x00, 48-4F 0x00, 50-57 58-59 0x00 0x00, 80-87 0x00, 88-8F 0x00, 90-97 98-9D
SLAA051
Program Description
4.18
TVP6000 Initialization Data with CCIR601 Sampling
char code T600P601[] Register Name SUB-ADDRESS F_CONTROL RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, C_PHASE GAIN_U GAIN_V BLACK_LEVEL BLANK_LEVEL GAIN_Y X_COLOR M_CONTROL BSTAMP S_CARR1 S_CARR2 S_CARR3 S_CARR4 LINE21_O0 LINE21_O1 LINE21_E0 LINE21_E1 LN_SEL SYN_CTRL0 RCML21 HTRIGGER0 HTRIGGER1 VTRIGGER BMRQ EMRQ BEMRQ X2PH X1PH RESERVED BRCV ERCV BERCV FLEN FLAL SYN_CTRL1 RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, Scaling Processor Registers 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Sub-Address 0x00, 3B-3F 0x00, 40-47 0x00, 48-4F 0x00, 50-57 58-59 0x00 0x00, 80-87 0x00, 88-8F 0x00, 90-97 98-9D
unsigned 0x3A, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x8C, 0xBC, 0xBC, 0x45, 0x20, 0x0E, 0x41, 0xCB, 0x8A, 0x09, 0x2A, 0xA2, 0x2A, 0xA2, 0x2A, 0x14, 0x00, 0x00, 0x16, 0x01, 0x80, 0x5F, 0x5F, 0x61, 0x08, 0x90, 0x00, 0x0E, 0xAE, 0x61, 0x70, 0x05, 0x35, 0x22, 0x0E, 0x00, 0x00, 0x00, 0x00,
TVP5020 NTSC/PAL Video Decoder
Program Description
4.19
TVP6000 Initialization Data with Square Pixel Sampling
char code T600PSQP[] Register Name SUB-ADDRESS F_CONTROL RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, C_PHASE GAIN_U GAIN_V BLACK_LEVEL BLANK_LEVEL GAIN_Y X_COLOR M_CONTROL BSTAMP S_CARR1 S_CARR2 S_CARR3 S_CARR4 LINE21_O0 LINE21_O1 LINE21_E0 LINE21_E1 LN_SEL SYN_CTRL0 RCML21 HTRIGGER0 HTRIGGER1 VTRIGGER BMRQ EMRQ BEMRQ X2PH X1PH RESERVED BRCV ERCV BERCV FLEN FLAL SYN_CTRL1 RESERVED 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, Scaling Processor Registers 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Sub-Address 0x00, 3B-3F 0x00, 40-47 0x00, 48-4F 0x00, 50-57 58-59 0x00 0x00, 80-87 0x00, 88-8F 0x00, 90-97 98-9D
unsigned 0x3A, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x8C, 0xBC, 0xBC, 0x45, 0x20, 0x0E, 0xC1, 0x0C, 0x8C, 0x79, 0x26, 0xA2, 0x2A, 0xA2, 0x2A, 0x14, 0x00, 0x00, 0x32, 0x01, 0x80, 0x5F, 0x5F, 0x61, 0x08, 0x90, 0x00, 0x28, 0x28, 0x71, 0x70, 0x05, 0x35, 0x22, 0x0E, 0x00, 0x00, 0x00, 0x00,
SLAA051

Programming Host Interface Mixed-Signal Product SLAA051

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