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Microcontroller Based Data Acquisition Using the TLC2543 12-Bit Serial-Out ADC

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Microcontroller Based Data Acquisition Using the TLC2543 12-Bit Serial-Out ADC
SLAA012 July 1995
Printed on Recycled Paper
Contents
Title Page
List of Illustrations
Figure Title Page
Introduction
Scope of this Application Report
This application report describes how to construct 12-bit data acquisition systems using the TLC2543 serial-out analog-to-digital converter (ADC) in conjunction with a range of four popular microcontrollers. The four microcontrollers used are the TMS370, H8 / 300, 68HC11 and 80C51.
The TLC2543
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 Input Address Register Control Logic Data Input I / O Clock
Analog Inputs
14-Channel Analog Input MUX
Sample and Hold
12-Bit ADC
Output Data Register
Parallel To Serial Converter
Serial Data Out
EOC 3 Self-Test Reference
12-Bit Resolution ADC 66-KSPS Sampling Rate 11 Analog Input Channels
Low Supply Current - 1 mA (Typ) Power-Down Mode - 4 µA (Typ) SPI Compatible Serial Interface
Figure 1. TLC2543 Block Diagram Interface Timing Four transfer methods are available for obtaining the full 12 bits of resolution from the TLC2543. Either 12 or 16 clock cycles can be used for each conversion and data transfer. A chip select (CS) pulse can be inserted at the start of each conversion or only once at the beginning of each sequence of conversions with CS remaining low until the sequence is completed.
Figure 2 shows the timing for the method which uses 16 clock cycles for each conversion and data transfer cycle and which inserts CS between each of these transfer cycles. Figure 3 shows the timing for the method which uses 16 clock cycles for each conversion and data transfer cycle but inserts CS only once at the start of each sequence of conversions. This application report describes various microcontroller interfaces, each of which uses 16 clock cycles for each conversion data transfer. CS is applied at the start of each conversion and data transfer. This method allows for the general case where one or more conversions may be required. It also simplifies the required software.
Previous Conversion Data
16-Clock Transfer Using CS (MSB First)
Figure 2. Timing for 16-Clock Transfer Using CS With MSB First
DATA OUT
Previous Conversion Data DATA INPUT
16-Clock Transfer Not Using CS (MSB First)
Figure 3. Timing for 16-Clock Transfer Not Using CS With MSB First Minimum Number of Data Transfers per Channel It should be noted that in any single data transfer cycle between the TLC2543 and the chosen microcontroller the data output from the ADC is the result of the previous conversion. The software listings included in this application report have been written for the general case where the conversion results may be required for any individual channel or sequence of channels. In this case the program included for each microcontroller interface must be run at least twice per channel so that valid data corresponding to the required analogue input channel and ADC mode is delivered. Software can be written to implement the consecutive channel scanning mode of operation of the TLC2543. In this case the result from the first analog-to-digital conversion should be ignored or overwritten.
DATA INPUT
Serial Peripheral Interface (SPI)
Simultaneous serial data input and output Synchronous operation Provision of frequency programmable serial clock Data transfer complete flag
Figure 4 shows the structure of the SPI. In this case the TMS370C010 is used to illustrate the main elements of the interface.
TLC2543
DATA OUT
SOMI Serial Input Buffer (SPIBUF)
DATA INPUT
Shift Register (SPIDAT) MSB LSB
SPICLK
Figure 4. Serial Peripheral Interface - Internal Structure and Data Flow The microcontroller can be configured by software to perform as the SPI master or slave. When operating as the master, data is input to the SPI shift register (SPIDAT) via the slave out master in (SOMI) terminal. At the same time data is output from the SPIDAT via the slave in master out (SIMO) terminal. The SPI functions as follows. The SPIDAT should be loaded with the first byte of data to be sent. This automatically initiates the transmission of this byte. During this transmission time data is received at the other end of the SPIDAT shift register. The SPI INT FLAG is regularly checked. As soon as the last bit of the input data byte is received the SPI INT FLAG is set to 1. This then signals that the received byte can be read from the serial input buffer (SPIBUF) and that the SPIDAT is ready to accept the next byte of data to be transmitted. Additional SPI features which apply to the specific microcontrollers are described in their respective sections which follow. TLC2543 to SPI Interface Timing The timing digram for the 16 clock transfer TLC2543 to SPI interface is shown in Figure 5. The channel select / mode data is read into the TLC2543 on the positive going edges of the I / O clock and analog-to-digital conversion results are read into the microcontroller on the negative going edges of the I / O clock.
I / O CLOCK DATA IN DATA OUT
A14 A13
tconv EOC
Figure 5. TLC2543 to SPI Interface Timing Software Flowcharts Figures 6, 7, and 8 show the flow charts for the main program and subroutines used in the TLC2543 to TMS370C010 interface software shown in this application report. The same program structure also applies to the other three interfaces included in this report.
1 START 2 CALL SUBROUTINE DATAIN
Reads channel / mode data for TLC2543 into microcontroller via parallel I / O port. (reformats channel / mode data if serial data is sent LSB first). Puts channel / mode data into accessible register. Derives destination address for STORE from channel data.
3 CALL SUBROUTINE ADC
Provides CS high to low transition prior to conversion. Provides serial I / O CLOCK to TLC2543. Sends channel / mode data to TLC2543. Receives MSbyte then LSbyte of previous A / D conversion.
4 CALL SUBROUTINE STORE
Stores MSbyte in even address of selected RAM space. Stores LSbyte in odd address of selected RAM space (all addresses mapped to corresponding channel number).
5 JUMP TO START Jump to start for next conversion
Figure 6. Flowchart for Main Program of TLC2543 to TMS370C010
Read Channel / Mode Data Into Chosen Register Store MSBYTE In Even Address Of RAM (Channel # Dependant) Map Channel Numbers To Registers Or RAM Store LSBYTE In Odd Address Of RAM (Channel # Dependant) Put Destination Address Into Chosen Register STORE
Return
DATAIN
Figure 7. Flowcharts of Subroutine DATAIN and STORE for TLC2543 to TMS370C010 Interface Software
Send CS Of TLC2543 Low
Figure 8. Flowcharts of Subroutine ADC for TLC2543 to TMS370C010 Interface Software
TLC2543 TO TMS370 Microcontroller Interface
Microcontroller Features
Within the family of TMS370 microcontrollers there are several versions which contain a serial peripheral interface (SPI) facility. One of these versions should be chosen to implement the interface method described below. One such version is the TMS370C010 which is used to illustrate the method.
Interface Circuit
Figure 9 shows the circuit interconnections for the TLC2543 to TMS370C010 microcontroller interface. Note that no extra logic is required to implement this interface.
Analog Inputs
VCC I / O CLOCK DATA INPUT DATA OUT CS AIN0 AIN1 AIN2 AIN3 TLC2543 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 GN D
VCC SPICLK SPISIMO SPISOMI D7
TMS370
Figure 9. TLC2543 to TMS370C010 Interface Circuit Depending upon the layout of the particular printed circuit board used it may be necessary to insert a small value capacitor of between 50 and 100 pF between the I / O CLOCK input of the TLC2543 and ground. This has the effect of ensuring that data applied to the DATA INPUT terminal of the TLC2543 is valid before the positive going transition of the I / O CLOCK. The positive reference, REF+, to the TLC2543 is provided directly from the VCC+ supply. The four digital interface terminals, I / O CLOCK, DATA INPUT, DATA OUT, and CS, of the TLC2543 connect directly to the SPICLK, SPISIMO, SPISOMI and D7 terminals respectively of the TMS370C010. The operation mode and channel number of the TLC2543 is determined by the serial data which is sent to its DATA INPUT terminal.
Software
List 1 contains the software listing for the program which controls the interface illustrated in Figure 5. The software consists of the main program and three subroutines called DATA IN, ADC and STORE. DATAIN reads in the channel select and mode control data into a holding register and maps the channel select number to a corresponding pair of registers between R64 and R91. The mapping vector is held in register R10. ADC provides the chip select pulse, controls the SPI operation, and puts the MSByte and LSByte of each conversion result into registers R20 and R21 respectively. STORE puts the MSByte into the even number register and the LSByte into the odd number register mapped by the contents of register R10.
The user can put channel select and ADC mode control data into the holding register within the microcontroller, via the 8-bit wide port A bidirectional I / O port, using a bank of eight toggle switches as shown in Figure 9. Alternatively, the mode and channel data can be sent to the microcontroller holding register via the asynchronous serial communications interface (SCI). This option is available only on those versions of the TMS370, such as the TMS370C020, which include both SPI and SCI interfaces. Additional software to control the SCI must be appended to the software shown in List 1 to provide this method of control.
List 1
LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 LOC OBJ SOURCE TLC2543 to TMS 370Cx10 Interface Program This program reads channel select and mode control data (provided by toggle switches) into the microcontroller, using subroutine DATAIN. It then provides the control signals to the TLC2543 to perform a 12 bit analog to conversion, using subroutine ADC. It finally stores the MSByte and LSByte of each conversion in consecutive even and odd number registers respectively starting at R64 corresponding to channel 0, using subroutine STORE. SPICCR .EQU P030 SPICTL .EQU P031 SPIBUF .EQU P037 SPIDAT .EQU P039 SPIPC1 .EQU P03D SPIPC2 .EQU P03E Name Peripheral SPIPRI .EQU P03F Registers APORT2 .EQU P021 ADATA .EQU P022 ADIR .EQU P023 DPORT1 .EQU P02C DPORT2 .EQU P02D DDATA .EQU P02E DDIR .EQU P02F RESET .EQU 7FFEH Reset vector named CSBIT .DBIT 7, DDATA TLC2543 Chip Select bit named CSBIT .TEXT 4000H Main Program START MOV #60H, B LDSP MOVW #4000H, A MOV A, RESET CLR A MOV A, APORT2 MOV A, ADIR MOV #080H, DDIR MOV #80H, A MOV A, SPICCR MOV #07, A MOV A, SPICCR MOV #03, A MOV A, SPIPC1 MOV #22H, A MOV A, SPIPC2 SPIF .DBIT 6, SPICTL MSLSB .DBIT 1, R11 CALL DATAIN CALL ADC CALL STORE Start program at 4000H Set SP to address 60H Set reset vector
0030 0031 0037 0039 003d 003e 003f 0021 0022 0023 002c 002d 002e 002f 7ffe 2e
Configure SPI for 8-bit character length. Configure SPICLK function and direction. Configure SPISOMI and SPISIMO pin functions. SPI INT FLAG named SPINTF Bit 1 of R11 named MSLSB
List 1 (Continued)
402d 402f 4031 4033 4034 4035 4036 4037 4039 403b 403d
9122 d10b 53f0 cc cc cc cc 5c02 5840 d10a f9
Read ADC mode / channel Put ADC mode / channel in R11 Retain channel number Map channel numbers to registers R64-R91 R10 contains storage address Even numbers - MS Byte Odd numbers - LS Byte
403e 4040 4043 4044 4046 4047 4049 404b 404d 4051 4053 4055 4059 405c 405f 4063 4066 406a 406c 406e 4072 4075 4077 4079 407d 4080 4082 4084 4086 4088 4089 408b 408e 4090 4092 4094 4096 4097 4099
List 1 (Continued)
LINE 129 130 131 132 133 134 135 136 137 138 139 LOC 409c OBJ f9 SOURCE RETURN RTS Subroutine :- STORE STORE MOV R20, A MOV A, @R10 INC R10 MOV R21, A MOV A, @R10 RTS .END
409d 409f 40a1 40a3 40a5 40a7
1214 9b0a d30a 1215 9b0a f9
Put MS Byte into even address contained in R10 (R10)+1 Put LS Byte into odd address contained in R10
Opto-Isolated 12-Bit Data Acquisition System
The serial nature of the data flow between the TLC2543 analog-to-digital converter and the accompanying microcontroller makes this ADC an ideal choice for isolated 12-bit data acquisition. Figure 10 shows an opto-isolated system which uses four optocouplers to provide a 3-kV isolation barrier. Note that the optocoupler which routes conversion result data from the TLC2543 to the microcontroller is a single device and does not share the same piece of silicon with any of the other optocouplers used. This ensures that the full 3 kV of isolation is maintained between the ADC and microcontroller. The choice of VP0610 P-channel enhancement MOSFETs avoids the use of an extra inverter stage for each optocoupler driver. In addition, the relatively low input capacitance of the VP0610 (typically 15 pF) allows data rates up to 100 kHz to be achieved without the need for external buffers to be added at the outputs of the TLC2543 and TMS370.
VCC1 VCC 470 R I / O CLOCK
VCC2 VCC VP0610 SPICLK
1 / 2 GCPL2631 470 R TLC2543 TMS370
470 R DATA INPUT
VP0610
1 / 2 GCPL2631 470 R
VP0610 DATA OUT AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 CS
470 R SPISOMI
A0 A1 A2 A3 D7 470 R VP0610 A4 A5 A6 A7
ADC Mode
ADC Channel Number
HCPL2601 470 R VSS 3 kV Isolation Barrier VSS
Figure 10. Opto-Isolated 12-Bit Data Acquisition System
TLC2543 to H8 / 325 Microcontroller Interface
Microcontroller Features
The individual members of the H8 family of microcontrollers can be differentiated by various criteria, for example the inclusion or otherwise of an on-board 8-bit resolution analog-to-digital converter (ADC). Those members which include an ADC generally cost between 10 and 20 percent more than their counterparts which do not. System requirements such as ADC resolution, remote location of ADC, flexibility, and total cost all influence the final choice of microcontroller architecture. The H8 / 325, used for this application report, does not include an on-board ADC but provides 1K of RAM, 32K of ROM, and two serial I / O ports. It is therefore well suited to interfacing with the TLC2543 serial output ADC.
Interface Circuit
5V TLC2543 VCC I / O CLOCK AIN0 AIN1 DATA INPUT AIN2 DATA OUT AIN3 CS AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 H8 / 325 SCK0 / P5.2 TxD0 / P5.0 RxD0 / P5.1 P6.0 VCC MD0 MD1 XTAL EXTAL P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 VSS 20 MHz (max)
Analog Inputs
ADC Mode
Channel Number
Figure 11. TLC2543 to H8 / 300 Microcontroller Interface Circuit
Software
List 2 shows the program which was written to coordinate the interface. It uses three subroutines to implement the overall interface to the TLC2543. The first of these is called DATAIN which reads ADC channel and mode information into the microcontroller. It also maps converter channel numbers to corresponding addresses in RAM where conversion results can be stored. In this case the addresses from 0040H to 0067H were chosen to store the results. The most significant byte of each result is placed in an even address and the least significant byte of each result is placed in the corresponding adjacent odd address. The conversion result of each channel is stored in left justified format and therefore occupies the upper 12 bits of the 16-bit words which occupy even addresses from 0040H up to 0066H. The second subroutine to be used is ADC. This begins by producing a chip-select high pulse. The trailing negative edge of this pulse is rapidly followed by the transmission of channel and mode information to the converter.
List 2
FFDD FFDB FFD8 FFDA FFDC FFD9 FFB8 FFBA FFB5 FFB7 FFB9 FFBB 1000
1000 79001000 1004 1008 100A 100C 100E 1010 1012 1014 1016 101A 101E 1022 1026 102A 7907FD00 F984 39D8 F931 39DA F901 39D9 F901 6A89FFB9 5E001082 5E00102C 5E0010B4 5E0010AC 40DC
102C 102E 1032 1034 1036 103A 103E 1040 1042 1046 1048 104A 104E
FA05 7FBB7000 1A0A 46FC 7FBB7200 6A0CFFB7 731C 461E 7EDC7370 47FA 34DB 7FDC7270 7EDC7360
List 2 (Continued)
1076 7FDC7260 107A 68DB 107C 731C 107E 46C2 1080 5470
1082 1086 108A 108E 1090 1092 1094 1096 1098 109C 109E 10A0 10A2 10A4 10A6 10A8 10AA
79040000 79050000 6A0CFFB7 0CCD 110D 110D 110D 110D 79060002 50E5 8D40 F008 110C 1204 1A00 46F8 5470
10AC 68D3 10AE 0A0D 10B0 68DB 10B2 5470
10B4 10B6 10B8 10BA 10BC 10BE 10C0 10C2
F008 1103 1207 1A00 46F8 0C73 F008 110B
List 2 (Continued)
LINE 136 137 138 139 140 141 10C4 10C6 10C8 10CA 10CC 10CE LOC 120F 1A00 46F8 0CFB 5470 OBJ SOURCE ROTXL R7L DEC R0H BNE LOOP2 MOV.B R7L, R3L RTS END Reformats LSBYTE Return from subroutine
TLC2543 to MC68HC11 Microcontroller Interface
Microcontroller Features
Interface Circuit
Figure 12 shows the circuit diagram of the interface between the 68HC11 and the TLC2543. The microcontroller device type used to illustrate this interface is the 48-pin dual-in-line version of the MC68HC811E2. The master in slave out (MISO), master out slave in (MOSI) and serial clock (SCK) terminals of the SPI are available as the alternative, user selectable, functions of port D pins PD2, PD3, and PD4 respectively. When the SPI is configured to operate as a master, the SS / PD5 terminal can be used as an output to drive the chip select (CS) terminal of the TLC2543. This leaves all other bidirectional I / O ports of the microcontroller uncommitted and available for other uses. Note that no extra glue logic is required to implement the interface.
TLC2543 VCC I / O CLOCK DATA INPUT DATA OUT CS
MC68HC811E2 VCC 22 pF SCK0 / PD4 MISO / PD2 MOSI / PD3 SS / PD5 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSS ADC Mode 10 M 22 pF
5V GND
MODB VSS
Channel Number
Figure 12. TLC2543 to MC68HC811E2 Microcontroller Interface
Software
List 3
BASEADD PORTA PORTC DDRC PORTD DDRD SPCR SPSR SPDR MSBYTE LSBYTE TEMP
F817 CE1000 F81A 8602 F81C 1C0820 F81F F820 F822 F825 4A 26FA 1D0820 1E030210
F829 A603 F82B A72A F82D 1F2980FC F831 A62A F833 97F0 F835 1E030210 F839 A603 F83B A72A F83D F841 F843 F845 1F2980FC A62A 97F1 1E0302E0
List 3 (Continued)
F849 39
F84A F84C F84F F851 F853 F855 F856 F857 F858 F859 F85A F85C F85D F85F F861 F863 F864 F866 F866 F868
A603 CE0030 97F2 86F0 94F2 46 46 46 46 16 8602 3D DDF2 96F0 A7F2 08 96F1 A7F2 A7F2 39
TLC2543 to 80C51 Microcontroller Interface
Microcontroller Features
Interface Circuit
Figure 13 shows the circuit for the interface of the TLC2543 to the 80C51 microcontroller. The I / O CLOCK, DATA INPUT and CS inputs to the TLC2543 are provided via the bidirectional parallel port 1 terminals P1.0, P1.1, and P1.3 respectively. Conversion result data from the TLC2543 is received by the 80C51 through the P1.2 terminal of port 1. The channel select / mode data is input to the microcontroller via port 3.
TLC2543 VCC I / O CLOCK DATA INPUT DATA OUT CS P1.0 P1.1 P1.2 P1.3
80C51 VCC
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
ADC Mode
Channel Number
Figure 13. TLC2543 to 80C51 Microcontroller Interface
Software
The listing for the program used to control the interface circuit mentioned above is shown in List 4. As for the other microcontroller interface programs, it consists of a main program and two subroutines - TLC2543 and STORE. The main program initializes the directions of the port 1 I / O terminals. P1.2 is configured as an input. P1.0, P1.1, and P1.3 are all programmed to perform as outputs. The chip select terminal of the TLC2543 is set high by setting P1.3. TLC2543 is then called. This subroutine contains the instructions which synthesize the SPI function and controls the exchange of data between the microcontroller and the TLC2543. The least significant bit first (LSBF) flag which is bit 1 of the channel select / mode data byte is checked to determine which byte (most significant - MSByte, least significant - LSByte) of the conversion result is to be expected first. The SPI function is synthesized by using the accumulator in conjunction with the rotate left through carry (RLC) instruction to act as the SPI shift register. The following sequence provides a slow motion version of the SPI function. The first bit of the first byte of the conversion result is read into the carry (C) bit. The contents of the accumulator are rotated left through carry and the first bit of the channel select / mode data is then output from P1.1. The first pulse of the serial clock is then provided by toggling the P1.0 bit of port 1 first high and then low. This sequence is repeated seven more times to complete the transfer of the first byte of data.
The second byte of data is tranferred between the TLC2543 and the 80C51 by repeating the entire sequence of eight sets of data transfer and clock pulse. The MSByte is placed in register 2 (R2) and the LSByte is placed in register 3 (R3). The subroutine STORE is used to map the MSByte and LSByte conversion results into even and odd number RAM addresses corresponding to the particular channel number which has been selected.
List 4
LINE LOC OBJ SOURCE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 TLC2543 12-bit Serial Out ADC to 80C51 Microcontroller Interface Program This program reads mode / channel select data into the 80C51 via Port 4 and transmits this data to the TLC2543 at the same time as reading the result from the previous conversion and storing the result in an adjacent pair of memory locations from 30H to 4CH. MSByte - Even Address LSByte - Odd Address MSByte Channel 0 in 30H, MSByte Channel 1 in 32H etc. ORG 100H START: MOV SP, #50H Initialise Stack Pointer MOV P1, #04H Initialize port 1 I / O Pins CLR P1.0 Set I / O clock low SETB P1.3 Set chip select high MOV A, #00FFH ACALL TLC2543 ACALL STORE JMP START TLC2543:MOV R4, P3 MOV A, R4 CLR P1.3 JB ACC.1, LSB Read mode / channel data into R4 and A Set chip select low If bit 1 of A is 1, do LSByte first MSB: MOV R5, #08 Load MS bit counter LOOP1: MOV C, P1.2 Read data bit into carry RLC A Rotate into accumulator MOV P1.1, C Output mode / channel bit SETB P1.0 Set I / O clock high CLR P1.0 Set I / O clock low DJNZ R5, LOOP1 Get / send another bit MOV R2, A Put MSByte in R2 MOV A, R4 Put mode / channel data in A JB ACC.1, RETURN LSB: MOV R5, #08 Load LS bit counter LOOP2: MOV C, P1.2 Read data bit into carry RLC A Rotate into accumulator MOV P1.1, C Output mode / channel bit SETB P1.0 Set I / O clock high CLR P1.0 Set I / O clock low DJNZ R5, LOOP2 Get / send another bit MOV R3, A Put LSByte in R3 MOV A, R4 Put mode / channel data in A JB ACC.1, MSB If bit 1 of R4 is 1, do MSbyte next RETURN: RET STORE: MOV A, R4 ANL A, #0F0H SWAP A MOV B, #02 Put mode / channel data in A Retain only channel number Swap high and low nibble of A
0100 0100 0103 0106 0108 010A 010C 010E 0110 0112 0114 0115 0117 011A 011C 011E 011F 0121 0123 0125 0127 0128 0129 012C 012E 0130 0131 0133 0135 0137 0139 013A 013B
758150 759004 C290 D293 74FF 3112 313F 80EE ACB0 EC C293 20E112 7D08 A292 33 9291 D290 C290 DDF5 FA EC 20E112 7D08 A292 33 9291 D290 C290 DDF5 FB EC 20E1DC
013E 22 013F 0140 0142 0143 EC 54F0 C4 75F002
List 4 (Continued)
LINE 0146 0147 0149 014A 014B A4 2430 F9 EA F7 LOC OBJ SOURCE 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 MUL ADD MOV MOV MOV AB A, #030H R1, A A, R2 @R1, A Add 30H to accumulator Put MSByte in corresponding even number address :- Channel 0 in address 30H, Channel 1 in address 32H etc. Put LSByte in corresponding odd number address :- Channel 0 in address 31H, Channel 1 in address 33H etc.
014C 09 014D EB 014E F7
INC R1 MOV A, R3 MOV @R1, A
014F 22
RET END
Analog Considerations
Power Supply Decoupling
Care should be taken with the design of the printed circuit board when using 12-bit devices such as the TLC2543. The power supply terminal of each analog integrated circuit should be separately decoupled to the analog ground using a 0.1 µF ceramic capacitor. The inclusion of a 10 µF tantalum capacitor in parallel with the ceramic capacitor at each device supply terminal is also recommended, particularly in noisy environments.
Grounding
Board Layout
Digital devices and power switching elements should be kept as far away physically from analog components, such as the TLC2543, as possible. Particular attention should be paid to the use of switching power supplies. The high frequency switching currents which flow in the ground return paths of these space saving power blocks can introduce several LSBs of noise into 12-bit analog circuits. Linear regulated power supplies should be used or, if essential, switching regulators should be as far as possible from the analog circuitry with their outputs decouple. Judicious use of ground planes can help to reduce analog ground impedances. Figure 14 illlustrates a typical bypassing scheme for the TLC2543-to-TMS370 microcontroller interface.
Direction Of Current Flow Connection To Output Of Power Supply +
10 µF 0.1 µF Tantalum Creamic VCC TMS370C010 SPICLK SPISIMO SPISOMI D7
0.1 µF Creamic
10 µF Tantalum Connection to Output of Power Supply -
AIN0 I / O CLOCK AIN1 AIN2 DATA INPUT AIN3 DATA OUT AIN4 AIN5 CS 0.1 µF AIN6 Creamic AIN7 AIN8 AIN9 AIN10 GND
External Data / Address Bus (If Used)
GND Ground Return To Power Supply
Direction Of Current Flow
Figure 14. TLC2543 to Microcontroller Interface: Grounding and Decoupling Scheme
Appendix A
References
Acknowledgement
I wish to express my thanks to Mike Williams (Microcontroller Field Applications Engineer - Northern European Industrial Segment) for his useful comments on the TMS370 interface.