SCEA006A August 1998 Copyright 1998, Texas Instruments Incorporat

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SCEA006A August 1998 Copyright 1998, Texas Instruments Incorporat

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Logic Family Technology Applications
SCEA006A August 1998
Copyright 1998, Texas Instruments Incorporated
Contents
Title Page Abstract Introduction Family Unparalleled Performance Novel Output Structure Mixed-Voltage Mode Power Design Issues Family Solutions Power (Optimized Unused Undriven Inputs (Bus Hold) Partial Power-Down Mixed-Voltage-Mode Data Communication
Device Characteristics Power Consumption Input Characteristics Switching Performance Signal Integrity Output Characteristics With Design Support Features Benefits Conclusion Acknowledgment Glossary Appendix Parameter Measurement Information
List Illustrations
Figure Title Page Low-Voltage Logic Family Performance Positioning Impedance Changes Through Switching Transitions Totem-Pole Input Structure Typical Bus-Hold Cell Hold Across Device 2.5-V With 3.3-V I/Os Side 2.5-V I/Os Other, Showing Switching Levels Device 1.8-V With 2.5-V Inputs 3.3-V Inputs, Showing Switching Levels Frequency With Outputs Switching tPHL tPLH tPHL Load Capacitance, Output Switching tPLH Load Capacitance, Output Switching tPHL Load Capacitance, Outputs Switching tPLH Load Capacitance, Outputs Switching Simultaneous-Switching Voltage (VOLP, VOLV) Time Simultaneous-Switching Voltage (VOHP, VOHV) Time Slow Input-Transition Time Pin-to-Pin Skew (tPHL, tPLH) (<100 nominal) Parameter Measurement Information (1.8 0.15 Parameter Measurement Information (VCC Parameter Measurement Information (VCC
List Tables
Table Title Page Various Conditions, Output Switching Selected Family Features Benefits
Abstract
Texas Instruments (TITM) announces industry's first logic family achieve maximum propagation delays less than TI's next-generation logic Advanced Very-low-voltage CMOS (AVC) family. Although optimized 2.5-V systems, logic supports mixed-voltage systems because compatible with 3.3-V 1.8-V devices. family features TI's Dynamic Output Control (DOCTM) circuit (patent pending). circuit provides enough current achieve high signaling speeds, automatically lowers output impedance circuit during signal transition subsequently increases impedance reduce overshoot undershoot noise that often found high-speed logic. This feature logic eliminates need series damping resistors. logic also power-off feature that disables outputs from device when power applied.
Introduction
Current trends advanced digital electronics design continue include lower power consumption, lower supply voltages, faster operating speeds, smaller timing budgets, heavier loads. Many designs making transition from speeds increasing beyond MHz. Encompassing these goals makes requirement signal integrity more difficult achieve. designs that require very-low-voltage logic bus-interface functions, produces logic family that designers next-generation high-performance workstations, PCs, networking, telecommunications equipment find particularly useful.
Family
TI's next-generation logic family (see Figure part TI's Widebusand Widebus+families, these devices give designers easy migration path higher performance lower voltages. Also offered family broad line logic gates octal bus-interface functions. devices TI's family available multiple JEDEC-standard advanced packages provide maximum flexibility board layout cost.
DOC, Widebus, Widebus+ trademarks Texas Instruments Incorporated.
ALVT
Drive Current
ALVC
Speed Maximum
Figure Low-Voltage Logic Family Performance Positioning Unparalleled Performance TI's family industry's first logic family achieve maximum propagation delays less than This premier performance achieved through combination advances. family designed high performance, incorporating several novel circuit structures changes conventional logic-circuit designs. TI's advanced 0.5-micron Enhanced-Performance Implanted CMOS (EPICTM) fabrication process used produce devices. Novel Output Structure family features TI's circuit, which changes output impedance during switching (see Figure circuit allows single device have desirable characteristics reduced noise, similar damping-resistor outputs during static conditions, high drive similar low-impedance output during dynamic conditions. circuit controls overshoots undershoots limits noise, which inherent high-speed, high-current devices.
EPIC trademark Texas Instruments Incorporated.
2.32 2.01 1.81 Output Voltage 1.55 1.29 1.03 0.77 Impedance 0.52 0.25 High Impedance
High Impedance
20.7
21.4
22.8
23.5
24.2
24.9
25.6
26.3
Switching Time
Figure Impedance Changes Through Switching Transitions Mixed-Voltage Mode Power family optimized low-power 2.5-V systems effectively supports mixed-voltage systems because compatible with 3.3-V 1.8-V devices. device inputs outputs 3.6-V tolerant 2.5-V 1.8-V VCC. This provides bidirectional data path between 3.3-V LVTTL 2.5-V CMOS, one-way data path from 3.3-V LVTTL 2.5-V CMOS 1.8-V CMOS. logic also power-off isolation feature that disables outputs from device during system partial power down.
Design Issues Family Solutions
Power (Optimized Perhaps most pervasive trends advanced digital-electronics design lower power consumption. Lower power consumption especially important extend battery life portable equipment. Reduced heat dissipation from lower power consumption simplifies measures necessary remove heat decrease necessary packaging area, leading production smaller less expensive products. most effective ways reduce power dissipation decrease integrated-circuit operating voltages. family, designed operate 2.5-V VCC, enables high-performance, low-power, advanced designs. simply scaled-down 3.3-V family, first logic family conceived designed optimized performance Unused Undriven Inputs (Bus Hold) circuit element that must addressed when designing with CMOS family, such AVC, circuit inputs. With totem-pole structure (see Figure that characterizes inputs CMOS devices, input node must held close rails possible.
Figure Totem-Pole Input Structure Precautions should taken prevent input voltage from floating near threshold voltage because this biases both input transistors creates undesirably high currents device. Under certain conditions, this damage device. address this concern place external pullup resistors input that might high-impedance, undriven state. This costly terms component count, reliability, board area. alternative solution employ devices family that utilize optional bus-hold circuit inputs (see Figure devices with bus-hold circuitry designated AVCH.
Input Inverter Stage
Bus-Hold Input Cell
Figure Typical Bus-Hold Cell bus-hold circuit consists series inverters with output back input through resistor. This provides weak positive feedback sinking sourcing current input node. bus-hold cell holds input last-known valid logic state until forcibly changed driving circuit. Figure shows input characteristics hold input voltage swept from These characteristics similar weak bistable latch. bus-hold cell sinks current when input low, sources current when input high. When input voltage near threshold, circuit sinks sources maximum current force input node toward either rail.
0.15 0.10 Input Current 0.05
40°C Process Nominal
-0.05 -0.10 -0.15
-0.20
Input Voltage
Figure Hold Across Generally, pullup pulldown resistors should used inputs devices with hold. applications that require pullup pulldown resistors hold inputs specific logic level, II(hold) maximum specification should considered. resistor value should chosen overcome hold under worst-case conditions. resistor must supply enough current that input pulled through threshold desired logic level. current supplied weak, input node could held near threshold, causing high that could damage part. Partial Power-Down Mixed-Voltage-Mode Data Communication inputs outputs family have been designed with reverse-current paths blocked. This IOFF current feature allows device remain electrically connected during partial power down without loading remaining live circuits. This feature also allows this family mixed-voltage environment. inputs outputs voltage greater than device, there current sourcing back through device from higher voltage node lower-voltage supply. With bidirectional transceiver powered with 2.5-V VCC, two-way data communication between 3.3-V LVTTL devices 2.5-V CMOS devices occur (see Figure inputs part 3.6-V tolerant accept LVTTL switching levels. outputs part, when powered 2.5-V under worst-case conditions, accepted valid switching levels input 3.3-V LVTTL device. With unidirectional driver powered with 1.8-V VCC, data communication from 2.5-V 3.3-V signal levels 1.8-V devices occur (see Figure inputs part tolerant higher voltages accept higher switching levels. outputs driver valid 1.8-V signal levels.
Figure Device 2.5-V With 3.3-V I/Os Side 2.5-V I/Os Other, Showing Switching Levels
1.35 1.17 0.63 0.45
Figure Device 1.8-V With 2.5-V Inputs 3.3-V Inputs, Showing Switching Levels
Device Characteristics
facilitate preliminary analysis characteristics family, SPICE analysis graphs from TI's initial AVC-family device, SN74AVC16245 16-bit transceiver with 3-state outputs shown Figures through These analyses outputs SPICE simulations using standard loads specified parameter measurement information illustrations Appendix unless otherwise noted. Power Consumption Figure presents SPICE information about device dynamic power consumption across operating frequencies. Table shows modeled values power dissipation capacitance (Cpd). data were obtained using input edge rate (0%-100%), open-circuit load output, output switching with 48-pin TSSOP (DGG) package.
Supply Current Output Switching Outputs Switching Process Nominal 40°C 48-pin TSSOP (DGG) Package Outputs Switching
Operating Frequency
Figure Frequency With Outputs Switching Table Various Conditions, Output Switching
PARAMETER TEST CONDITIONS Outputs enabled Outputs disabled 0.15 15.9 18.1 21.1
Input Characteristics Figures present SPICE information about device static behavior. Figure shows device supply-current requirements across input voltage Figure shows output-voltage versus input-voltage transfer curves.
40°C Process Nominal
Supply Current Input Voltage
Figure
40°C Process Nominal
Output Voltage
Input Voltage
Figure
Switching Performance Figures through present SPICE models device dynamic behavior. Propagation delay times across various conditions ambient temperature, load capacitance with output switching, load capacitance with outputs switching shown.
1.28 1.26 Propagation Delay Time 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 Output Switching Nominal Process 48-pin TSSOP (DGG) Package Junction Temperature
Figure tPHL
1.17
1.14 Propagation Delay Time
1.08 1.05
1.02 0.99
0.96
Output Switching Nominal Process 48-pin TSSOP (DGG) Package
Junction Temperature
Figure tPLH
Propagation Delay Time
Weak: Weak Process, 100°C Nominal: Nominal Process, 40°C Strong: Strong Process, -40°C 48-pin TSSOP (DGG) Package
Weak Nominal Strong
Load Capacitance
Figure tPHL Load Capacitance, Output Switching
Propagation Delay Time
Weak: Weak Process, 100°C Nominal: Nominal Process, 40°C Strong: Strong Process, -40°C 48-pin TSSOP (DGG) Package
Weak Nominal Strong
Load Capacitance
Figure tPLH Load Capacitance, Output Switching
Propagation Delay Time
Weak: Weak Process, 100°C Nominal: Nominal Process, 40°C Strong: Strong Process, -40°C 48-pin TSSOP (DGG) Package
Weak Nominal Strong
Load Capacitance
Figure tPHL Load Capacitance, Outputs Switching
Propagation Delay Time
Weak: Weak Process, 100°C Nominal: Nominal Process, 40°C Strong: Strong Process, -40°C 48-pin TSSOP (DGG) Package
Weak Strong Nominal
Load Capacitance
Figure tPLH Load Capacitance, Outputs Switching
Signal Integrity Perhaps most important measure device's performance dynamic domain effect varying conditions upon signal integrity. Figures through show SPICE simulations device dynamic behavior. effect multiple outputs switching simultaneously that held valid logic level shown (see Figures 18). effects slow input-transition time (see Figure 19), pin-to-pin skew (see Figure shown.
VOLP Time Outputs Switching Quiet Process Nominal 40°C
Output Voltage
VOLP VOLV Approximately Equal
Figure Simultaneous-Switching Voltage (VOLP VOLV) Time
Output Voltage Outputs Switching Quiet High Process Nominal 40°C Time
Figure Simultaneous-Switching Voltage (VOHP VOHV) Time
Process Nominal 40°C
Output Voltage
Outputs Switching
Time
Figure Slow Input-Transition Time
Process Nominal 40°C Outputs Switching
Output Voltage
<100 Nominal
Time
Figure Pin-to-Pin Skew (tPHL, tPLH) (<100 nominal)
Output Characteristics With Selecting component with improved output drive characteristics simplifies design engineer's ensuring signal integrity meeting timing requirements. signal integrity, output must have output impedance that minimizes overshoots undershoots. component with series damping resistors output ports sometimes necessary improve match impedance with transmission-line load output buffer. opposing characteristic that must considered having sufficient drive meet timing requirements. family features TI's circuit that automatically lowers output impedance circuit during signal transition subsequently raises impedance reduce overshoot undershoot. Figures contain typical voltage current curves that illustrate operation circuit transitions from state another.
40°C Process Nominal
Output Voltage
Output Current
Figure
40°C Process Nominal
Output Voltage
-144 -128 -112
-160
Output Current
Figure circuitry provides enough drive current achieve faster slew rates meet timing requirements, quickly switches impedance level reduce overshoot undershoot noise that often found high-speed logic. This feature logic eliminates need damping resistors output circuit, which often used series, sometimes integrated with logic devices, limit electrical noise. Damping resistors reduce noise, increase propagation delay decreased drive current. Because excellent signal integrity characteristics output, transmission-line termination typically unnecessary. high-impedance drive characteristics output static state, termination specifically discouraged. output current that required bias termination network could exceed static-state output-drive capabilities device. with circuitry ideally suited high-speed, point-to-point application unterminated distributed load, such high-speed memory interfacing. Design Support Examination characteristics device critical portion successful design. design engineer analysis device characteristics, latest versions IBIS models obtained from TI's website http://www.ti.com. SPICE models also available from Please contact your local field sales representative more information.
Features Benefits
Table provides selected family features benefits. Table Selected Family Features Benefits
FEATURES Optimized 2.5-V Broad product offerings Advanced EPIC fabrication process; turbo-circuit design BENEFITS Enables low-power designs Simplifies component choice Sub-2-ns (maximum) speeds Easier meet timing windows advanced high-speed designs Reduced ringing without series output resistors, increased performance cost savings Eliminates pullup pulldown resistors inputs Outputs disabled during power partial power down mixed-voltage designs
outputs require series damping resistors internally externally Bus-hold option IOFF reverse-current paths blocked inputs outputs
Conclusion
designs that require 1.8-V, 2.5-V, 3.3-V logic functions with highest performance, family provides fastest, quietest logic devices optimized 2.5-V unterminated load conditions. offers broad line Widebus Widebus+ functions, logic gates, octal bus-interface functions.
Acknowledgment
authors this application report Stephen Nolan Eyck.
Glossary
Advanced very-low-voltage CMOS
CMOS Complementary metal-oxide semiconductor
Dynamic output control (patent pending)
EPIC Enhanced-performance implanted CMOS
IBIS II(hold) buffer information specification Input current Input current (bus hold) High-level output current Low-level output current
LVTTL Low-voltage (3.3-V power supply interface levels)
Personal computer
SPICE Simulation program with integrated-circuit emphasis
tPHL tPLH TSSOP Propagation delay time Propagation delay time, high- low-level output Propagation delay time, low- high-level output Thin shrink small-outline package Transistor-transistor logic
VOHP VOHV VOLP VOLV High-level output voltage Low-level output voltage High-level output voltage peak High-level output voltage valley Low-level output voltage peak Low-level output voltage valley
Appendix Parameter Measurement Information
From Output Under Test (see Note Open TEST tPLZ/tPZL tPHZ/tPZH Open
LOAD CIRCUIT Timing Input Data Input VCC/2 VCC/2 VCC/2 VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control (low-level enabling) tPZL Input VCC/2 tPLH VCC/2 tPHL Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 Output Waveform (see Note Output Waveform (see Note tPZH Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2
VCC/2 VCC/2 tPLZ VCC/2 0.15 tPHZ 0.15 VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
VCC/2
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure A-1. Parameter Measurement Information (1.8 0.15
From Output Under Test (see Note Open TEST tPLZ/tPZL tPHZ/tPZH Open
LOAD CIRCUIT Timing Input Data Input VCC/2 VCC/2 VCC/2 VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control (low-level enabling) tPZL Input VCC/2 tPLH VCC/2 tPHL Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 Output Waveform (see Note Output Waveform (see Note tPZH Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2
VCC/2 VCC/2 tPLZ VCC/2 0.15 tPHZ 0.15 VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
VCC/2
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure A-2. Parameter Measurement Information (VCC
From Output Under Test (see Note Open
TEST tPLZ/tPZL tPHZ/tPZH
Open
LOAD CIRCUIT
Input VCC/2 VCC/2 VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VCC/2
VCC/2
VCC/2 Output Control (low-level enabling)
VCC/2 VCC/2 tPZL tPLZ VCC/2 tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
VOLTAGE WAVEFORMS SETUP HOLD TIMES
Input VCC/2 VCC/2 tPLH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VCC/2
Output Waveform (see Note tPZH Output Waveform (see Note
VCC/2
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure A-3. Parameter Measurement Information (VCC

SCEA006A August 1998 Copyright 1998, Texas Instruments Incorporat

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