Target Applications: Interfaces Processor Peripherals Family: FLE

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Target Applications: Interfaces Processor Peripherals Family: FLE

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Master Interface Megafunction
Target Applications:
Interfaces Processor Peripherals Family: FLEX® FLEX 6000 Vendor:
Features
Supports system clocks Supports inter integrated circuit (I2C) fast mode Reads writes data bursts Supports special mode read write access dedicated register address Generates wait states Filters spikes Fully synchronous design
General Description
SICAN Microelectronics Corp. Oyster Point Blvd. Suite Francisco, 94080 http://www.sican.com Tel. (650) 871-1494 (650) 871-1504 master interface megafunction interfaces host with bus. This megafunction essentially converter, converting host CPU's parallel data into serial format transfer over bus, vice versa. Thus, host control other devices same bus. master interface megafunction also takes care interface timing, data structure, error handling. Figure shows symbol master interface megafunction.
Figure Master Interface Megafunction Symbol
reset_n HIF_data[15.0] HIF_adr[1.0] HIF_IIC_rw HIF_IIC_req IIC_HIF_ack IIC_HIF_irq IIC_HIF_data_valid IIC_HIF_data[15.0] IICCLK_in IICCLK_out Master Interface Megafunction
IICCLK
IICDATA_in IICDATA_out IICDATA
Host Interface
Interface
Functional Description
master interface megafunction includes three registers communication between host bus. Table
Table Master Interface Registers
Register Name
data_reg cfg_reg read_reg
Width (Bits)
Address
Mode
Write Write Read
data_reg register 32-bit writeable data register consisting 16-bit registers, data_reg_high[31.16] data_reg_low[15.0]. These registers handle 16-bit data host CPU. Figure shows information stored megafunction registers.
Altera Corporation
A-SB-039-01
ALTERA MEGAFUNCTION PARTNERS PROGRAM
ALTERA MEGAFUNCTION PARTNERS PROGRAM
Master Interface Megafunction
Figure Master Interface Registers
data_reg_low data_reg_high
rw_mode cfg_reg
Device
Address
Data
spike_filter read_reg
Clock Reference
write_allowed interrupt error
Data
writeable registers (i.e., data_reg_high[31.16], data_reg_low[15.0], cfg_reg) must loaded initialize master interface megafunction. When data_reg_low[15.0] loaded, data begins transferring bus. During direct read direct write modes, data packet begins transfer when both read_reg data_reg_low[15.0] registers accessed. direct read direct write mode stops when data_reg_high[31.16] cfg_reg register accessed. megafunction monitors status IICCLK_in IICCLK_out signals; component holds IICCLK low, megafunction stays wait state. noisy environments, apply spike filter, stored cfg_reg register, incoming data clock signals. spike filter evaluates signals programmed number clock cycles maximum eight clock cycles). During this time, spike filter removes spikes signals. master interface megafunction supports four operating modes. Table
Table Master Interface Operating Modes
Mode
Direct write Direct read Random access write Random access read
Description
Writes burst data. Reads burst data. Writes data byte specified address. Reads data byte from specified address.
Altera Corporation
Master Interface Megafunction
Tables describe megafunction's global signals, interface signals host CPU, interface signals bus, respectively.
Table Master Interface Megafunction Global Signals
Name
reset_n
Type
Input Input Device clock signals.
Description
active asynchronous reset signal.
Table Interface Signals Host
Name
HIF_data[15.0] HIF_adr[1.0] HIF_IIC_rw HOST_IIC_req IIC_HIF_ack IIC_HIF_irq IIC_HIF_data_valid IIC_HIF_data[15.0]
Type
Input Input Input Input Output Output Output Output
Description
16-bit data from host CPU. 2-bit address addressing internal registers. Read/write select. indicates write, indicates read. Request. Host requests next read/write data. Acknowledge. megafunction acknowledges read/write request. Interrupt. Data must read from megafunction's data register. Data valid bus. 16-bit data host CPU.
Table Interface Signals
Name
IICCLK_in IICDATA_in IICCLK_out IICDATA_out
Type
Input Input Output Output
Description
Clock input megafunction. Data input megafunction. Clock output megafunction. Data output megafunction.
Performance
Table describes megafunction's logic element (LE) requirements FLEX FLEX 6000 devices.
Altera Corporation
Master Interface Megafunction
Table Master Interface Megafunction Requirements
Device Speed Grade
EPF10K10 EPF10K10A EPF10K30E EPF10K50E EPF10K100B EPF10K200E EPF10K250A EPF6010A EPF6016 EPF6016A EPF6024A Note:
EABs embedded array blocks.
Utilization EABs
Performance (MHz)
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 1999 Altera Corporation. Altera, EPF10K10, EPF10K10A, EPF10K30E, EPF10K50E, EPF10K100B, EPF10K200E, EPF10K250A, EPF6010A, EPF6016A, EPF6024A, FLEX, FLEX 10K, FLEX 6000, AMPP trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

Target Applications: Interfaces Processor Peripherals Family: FLE

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