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Single-Chip North Bridge Pentium CPUs with plus Advanced Memory Controller supporting PC2700 2100 PC1600 DRAM Desktop Systems
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Copyright 2001, 2002 Technologies Incorporated. Rights Reserved. part this document reproduced, transmitted, transcribed, stored retrieval system, translated into language, form means, electronic, mechanical, magnetic, optical, chemical, manual otherwise without prior written permission Technologies Incorporated. material this document information only subject change without notice. Technologies Incorporated reserves right make changes product design without reservation without notice users.
Trademark Notices:
VT8233, VT8233A, VT8233C, VT8235, VT8703, VT8751, VT8753, VT8754, P4M266, P4N266, P4X266, P4X266A, P4X333 only used identify products Technologies. IntelTM, Pentiumand MMXare registered trademarks Intel Corp. CyrixTM, Cyrix6X86TM, WinChipand C3are registered trademarks Technologies Athlonand AMD-K7are registered trademarks Advanced Micro Devices Corp. Windows XPTM. Windows 2000TM. Windows METM, Windows 98TM, Plug Playare registered trademarks Microsoft Corp. PCIis registered trademark Special Interest Group. PS/2is registered trademark International Business Machines Corp. trademarks properties their respective owners.
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REVISION HISTORY
Document Release Date 12/18/01 Revision Initial internal release based P4X266A data sheet published 12/5/01 Updated cover, block diagram feature bullets Updated diagram project #3168 engg ballout dated 12/7/01 Updated lists, updated descriptions mode Added pins HA34-35, AP[1-0], HDP[3-0], RSP, VCC/GNDHCK2 Added pins AGP8XDT#, GCKE, GSERR# Added pins MAA15, MAB15, QDRRD#, QDRWR# Added V-Link VPAR Miscellaneous Replaced mechanical spec with HSBGA-859 Fixed SDRAM feature bullets; Changed mechanical spec HSBGA-858 Updated pinouts match engineering ballout (removed VCC25 ball AA10) Fixed PC2700 notation; fixed various formatting typographical errors Fixed/updated ball count, V-Link DRAM feature bullets overview Updated block diagram, feature bullets overview VT8235 south bridge Updated strap definitions; Removed support Updated Device Rx13-10, 43-44, 47-49, 4B-4C, 4F-52, 54-55, 66-67, 6A-6E, 80-83, A4-B0, B4-B6, B8-BA, BC-BE, D0-D6, DA-DB, E0-E3, E8-EF, Device Rx3-2, Replaced mech spec with correct 858-ball diagram Regenerated file non-printing mechnical spec diagram Added P4X333 "product logo" cover page page headers Fixed first main feature bullet target high performance desktop systems Fixed Figure block diagram (bad diagram printout MS-Word bug) Changed V-Link MB/sec feature bullets overview Fixed errors typos (package count, slots, etc) Overview text Fixed mistakes power/ground lists bottom list tables Fixed part number product name typos descriptions Fixed register references memory descriptions electrical specs Fixed voltages AGPVREF, VCCMEM, VCCAGP descriptions Fixed AGPVREF AGPVCC descriptions Device Fixed Rx3-2 default, 52[5], 53-54, A7-A4 default, 64[6-4], 69[6], B2[7] Device Removed Rx52[4], 67[7-6], (8233 configuration only) Fixed P4X333 logo print color; changed memory 16GB Added feature bullet include support both registered unbuffered DIMMs Changed pins AJ16 Updated AGPVREF description Added type name GCKE, HDP[3-0], AP[1-0], RSP#, NMI, GSERR# Updated Table Mapping 512Mb DRAMs; Updated Rx69[6] Initials
1/3/02 2/8/02
0.31
2/11/02 2/27/02
2/28/02
3/11/02
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TABLE CONTENTS
REVISION HISTORY TABLE CONTENTS. LIST FIGURES LIST TABLES PRODUCT FEATURES. OVERVIEW. PINOUTS. DESCRIPTIONS. REGISTERS. REGISTER OVERVIEW MISCELLANEOUS CONFIGURATION SPACE DEVICE REGISTER DESCRIPTIONS Device Host Bridge Header Registers Device Host Bridge Device-Specific Registers.
V-Link Control. Host Control DRAM Control Control. GART Graphics Aperture Control CPU-to-Memory Access Control Control Control (continued) V-Link Compensation Drive Control. Power Management Control Extended Power Management Control. Error Control. Host AGTL+ Control DRAM Above Control Host Interface DRDY Timing Control BIOS Scratch
DEVICE REGISTER DESCRIPTIONS Device PCI-to-PCI Bridge Header Registers Device PCI-to-PCI Bridge Device-Specific Registers
Control Control (continued) Power Management.
FUNCTIONAL DESCRIPTION CONFIGURATION STRAPPING ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS
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POWER CHARACTERISTICS TIMING SPECIFICATIONS MECHANICAL SPECIFICATIONS.
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LIST FIGURES
FIGURE P4X333 CHIPSET SYSTEM BLOCK DIAGRAM. FIGURE VT8754 P4X333 BALL DIAGRAM (TOP VIEW). FIGURE GRAPHICS APERTURE ADDRESS TRANSLATION. FIGURE MECHANICAL SPECIFICATIONS HSBGA-858 BALL GRID ARRAY PACKAGE WITH HEAT SPREADER
LIST TABLES
TABLE VT8754 LIST (NUMERICAL ORDER). TABLE VT8754 LIST (ALPHABETICAL ORDER). TABLE VT8754 P4X333 DESCRIPTIONS. TABLE VT8754 P4X333 REGISTERS TABLE SYSTEM MEMORY MAP. TABLE DEVICE RX58 TYPE ENCODING. TABLE DRAM MEMORY ADDRESS MAPPING TABLE TABLE DIMM MODULE CONFIGURATION. TABLE VGA/MDA MEMORY/IO REDIRECTION TABLE ABSOLUTE MAXIMUM RATINGS. TABLE CHARACTERISTICS. TABLE POWER CHARACTERISTICS INTERNAL INTERFACE DIGITAL LOGIC TABLE POWER CHARACTERISTICS ANALOG REFERENCE VOLTAGES. TABLE TIMING CONDITIONS
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CHIPSET
VT8754
Single-Chip North Bridge Pentium CPUs with /400 Front Side plus Advanced Memory Controller supporting PC2700 2100 PC1600 SDRAM Desktop Systems
PRODUCT FEATURES
Defines Highly Integrated Solutions Performance Desktop Designs
High performance North Bridge with Front Side Pentium4 plus external 64-bit Advanced Memory controller supporting PC2700 PC2100 PC1600 Synchronous DRAM Combines with VT8235 V-Link South Bridge integrated LAN, Audio, ATA133 IDE, ports 2.5V Core AGTL+ 35mm HSBGA package (Ball Grid Array with Heat Spreader) with balls ball pitch
High Performance Interface
Support IntelPentium processors with MHz) Front Side (FSB) Built-in Phase Lock Loop circuitry optimal skew control within between clocking regions Thirteen outstanding transactions (twelve In-Order Queue (IOQ) plus output latch) Dynamic deferred transaction support
Full Featured Accelerated Graphics Port (AGP) Controller
Supports transfer modes signaling v3.0 compliant with transfer mode Pseudo-synchronous with host with optimal skew control Supports SideBand Addressing (SBA) mode (non-multiplexed address data) pipelined split-transaction long-burst transfers 1GB/sec Eight level read request queue Four level posted-write request queue Thirty-two level (quadwords) read data FIFO (256 bytes) Sixteen level (quadwords) write data FIFO (128 bytes) Intelligent request reordering maximum utilization Supports Flush/Fence commands Graphics Address Relocation Table (GART) level structure Sixteen entry fully associative page table replacement scheme Independent GART lookup control host master accesses
Windows OSR-2 integrated Windows Windows 2000 miniport driver support
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Advanced High-Performance DRAM Controller
DRAM interface pseudo-synchronous with host (166/133/100 MHz) most flexible configuration DRAM interface faster than allow memory with clock memory with clock Concurrent CPU, AGP, V-Link access Clock Enable (CKE) control DRAM power reduction high speed systems Mixed 128M 8/16/32 DRAMs Supports banks DRAMs Allows either unbuffered registered memory modules Flexible column addresses. 64-bit data width only 2.5V SSTL-2 DRAM interface Programmable drive capability command signals Dual copies control signals improved drive (single-bit error correction multi-bit error detection) (error checking only) DRAM integrity Two-bank interleaving 16Mbit DRAM support Four bank interleaving 64Mb, 128Mb, 256Mb, 512Mb, DRAM support Supports maximum 16-bank interleave (i.e., pages open simultaneously); banks allocated based Seamless DRAM command scheduling maximum DRAM utilization (e.g., precharge other banks while accessing current bank) Four cache lines quadwords) DRAM write buffers Four cache lines DRAM read prefetch buffers Read around write capability non-stalled read Speculative DRAM read before snoop result Burst read write operation Burst length Supports 2/2.5 command command rate which specified bank bank Decoupled burst DRAM refresh with staggered timing (CAS before self refresh)
High Bandwidth 8-bit V-Link Host Controller
Supports V-Link Host interface with peak bandwidth MB/sec Operates modes Full duplex commands with separate command strobe Request Data split transaction Configurable outstanding transaction queue Host V-Link Client accesses Supports Defer Defer-Reply transactions Transaction assurance V-Link Host Client access eliminates V-Link Host-Client Retry cycles Intelligent V-Link transaction protocol eliminate data wait-state throttle transfer latency V-Link transactions both Host Client have consistent view transaction data depth buffer size avoid data overflow Highly efficient V-Link arbitration with minimum overhead V-Link transactions have predictable cycle length with known command data duration
Advanced System Power Management Support
Dynamic power down DRAM (CKE) suspend power plane preserves memory data Suspend-to-DRAM self-refresh power down Low-leakage pads ACPI 1.0B Power Management compliant
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OVERVIEW
P4X333 (VT8754 North Bridge plus VT8235 South Bridge) high performance, cost-effective energy efficient chip implementation desktop personal computer systems with (4x133 MHz) (4x100 MHz) host ("Front Side Bus") based 64-bit Intel Pentium-4 super-scalar processors.
System Management
64-bit with 66MHz 8-bit V-Link
Network Interface 10/100 Ethernet VT6103
UDMA
Pentium
(4x133 MHz) Front Side
P4X333 Chipset VT8754 Pentium North Bridge 858-pin HSBGA
Slots
33MHz, 32-bit
P4X333 Chipset VT8235 V-Link South Bridge
487-pin PBGA
Direct EPROM AC-Link VT1616 AC'97 Audio Codec VT1211 Super Serial Parallel Floppy Disk
Slot
MC-97 Modem Codec Integrated AC'97 Audio
Keyboard Mouse
Figure P4X333 Chipset System Block Diagram
P4X333 chip consists VT8754 North Bridge (858-pin BGA) VT8235 V-Link South Bridge (487 BGA). VT8754 (sometimes also called "Host System Controller") update VIA's VT8753A (P4X266A) with faster memory interface pinout enhanced functionality. VT8754 provides superior performance between CPU, DRAM, V-Link graphics controller with pipelined, burst, concurrent operation. VT8235 (which also referred "V-Link Client Controller") highly integrated controller. internal structure based that provides bandwidth compared previous generation bridge chips. VT8235 also provides MB/sec bandwidth Host Client V-Link interface with V-Link-PCI V-Link-LPC controllers. supports slots arbitration decoding integrated functions bus. VT8754 supports eight banks Synchronous DRAMs (SDRAMs) DRAM controller supports PC2700 PC2100 PC1600 Double-Data-Rate (DDR) SDRAM. DRAM interface allows zero wait state bursting between DRAM data buffers MHz. different banks DRAM composed arbitrary mixture 128M 8/16/32 DRAMs. Both unbuffered registered memory modules supported. DRAM controller also supports optional (single-bit error correction multi-bit detection) (error checking) capability. DRAM controller either synchronous pseudo-synchronous with host bus. VT8754 supports high speed 8-bit Quad Data Transfer interconnect (V-Link) VT8235 South Bridge. chip also contains built-in bus-to-bus bridge allow simultaneous concurrent operations each bus. Five levels (doublewords) post write buffers included allow concurrent V-Link operation. V-Link Host operation, forty-eight levels (doublewords) post write buffers sixteen levels (doublewords) prefetch buffers included concurrent V-Link
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DRAM/cache accesses. When combined V-Link Host Client controllers, realizes complete sub-system supports enhanced commands such "Memory-Read-Line", "Memory-Read-Multiple" "Memory-Write-Invalid" commands minimize snoop overhead. addition, advanced features supported such snoop ahead, snoop filtering, write-back forward master, write-back merged with post write buffers minimize master read latency DRAM utilization. Delay transaction read caching mechanisms also implemented further improvement overall system performance. 487-pin Ball Grid Array VT8235 Client V-Link controller supports four levels (doublewords) line buffers, type transfers delay transaction allow efficient utilization (PCI-2.1 compliant). VT8235 integrated controller arbitration five slots. pairs configured high-priority better support latency master device. VT8235 integrated networking controller with standard interface external 10/100Mb base-T Ethernet 1/10Mb home networking. VT8235 also includes integrated keyboard controller with mouse support, integrated DS12885 style real time clock with extended byte CMOS RAM, integrated master mode enhanced controller with full scatter gather capability extension UltraDMA-133/100/66/33 133/100/66/33 MB/sec transfer rate, integrated interface with three root hubs functional ports with built-in physical layer transceivers, Distributed support, OnNow ACPI compliant advanced configuration power management interface. sophisticated power management, P4X333 chipset provides independent clock stop controls SDRAM plus Dynamic control powerdown SDRAM. separate suspend-well plane implemented SDRAM control signals Suspend-to-DRAM operation. Coupled with VT8235 south bridge chip, complete power conscious main board implemented with external TTLs.
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Figure VT8754 P4X333 Ball Diagram (Top View)
GD18 BE2# IRDY# GDS0# GDS0S GD11 SCAS MD51 SRAS MD49 CS5#
PINOUTS
STOP# SERR# GD14 GD12 BE0# STB# SET# MD63 MD62 MD57 MD56 MD55 MD53 MD48 MD43 CS7#
DSEL# BE1# GD10 MD58 MD61 MD50 MD47 CS6#
TRDY# GDS0 GDS0F STB# VREF MD59 MD60 MD54 MD52 MD46 CS4# CS3#
GD17 GD16 FRM# GD15 GD13 COMP VSUS SCAS SRAS MD42 CS1#
GD19 GD25 GD20 VREF COMP VREF CS2# CS0# MD41
BE3# GD21 GD22 GD27 GD24
GD23 GD26 GDS1 GDS1F GDS1# GDS1S GD31
GD28 GD29 GD30
GDBIL GDBIH GPIPE# VREF
SBS# SBSS SBSF
RBF#
GNT# PIPE# WBF#
8XDT# REQ#
RST#
HD62# HD60# HD61# HD58# VREF
HD63# HD56# HD57# HD59#
HD55#
HD51# HD54# HD53# HD52# HDBI
HD48# HD49# HD50# HD47# HD46#
HD43# HD44# HD45# VREF
HDBI HD42# HD41# HD34# HD40#
HD38# HD33# HD36#
HD37# HD39# HD32#
HD35# VREF
HD26# HD31# HD29# HD25# HD27# VREF CLK# VREF VREF VREF
HD28# HDBI HD24# HD11# HDBI HCMP VREF HCK1 HCK2 RS1# HA16 HA24 HA28 HA26
HD30# HD7# HD10# HD3# COMP HCK1 HCK2 BNR# RDY# HREQ HREQ HA20 HA19 HA30 RSP#
HD22# HD16# HD23# HD14# HD8# HD5# FER# BSY# REQ# HREQ HA14 HA18 HA21 HA25 HA33 HA35
HD19# HD17# HD13# HD2# HD4# LOCK# HREQ HA13 HA15 HA23 HA27 HA31
HD20# HD21# HD18# HD15# HD12# HD9# HD6# HD1# HD0# BPRI# HITM# HIT# ADS# RDY# HREQ HA11 HA10 HA12 HA17 HA22 HA32 HA29 HA34 MCLK MCLK TEST
MD45 MD40 MD35 MD44
Pins VLink Pins
Pins
AB13
AB22
AB26
AA10
AC10
AC25
AD11 AE11
AD24
AE22 AE23
AF12
AF21
Pins
MD39
MD38
MD34 MD37 MD33
VREF MD36
MDLL MECC MD32 MECC MECC
MDLL MECC MECC
MECC
MD27 MD31 MECC MECC
MD26 MD30
VREF
MD24 MD28 MD29 MD25
MD22 MD19 MD23
MD18
MD21 MD17 MD16
VREF MD20 MD11 MD10
MD15 MD14
GCKE MD12 MD13
AH28
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Table VT8754 List (Numerical Order)
Name
GSTOP# GDEVSEL# GTRDY# GD18 GD17 GD19 GBE3# GD23 GD28 SBA5 SBA3 GRBF# GGNT# AGP8XDT# CPURST# HD62# HD63# HD55# HD51# HD48# HD43# HDBI2# HDS2# HD37# HDP0 HD26# HD28# HD30# HD22# HD19# HD20# GBE2# GD16 GD21 GD26 SBA7 SBA1 HD60# HD56# HD54# HD49# HD42# HDS2 HDP2 HD31# HDS1# HD16# HD21# GIRDY# GFRM# GD25 GD22 GDS1 GDS1F GD29 SBA6 SBS# SBSS SBA2 GPIPE# GREQ# HD61# HD57# HDS3 HD53# HD50# HD44# HD41#
Name
HD38# HD39# HD35# HD29# HDBI1# HDS1 HD23# HD17# HD18# GD20 GD27 GDS1# GDS1S GD30 GDBIL SBSF SBA0 GWBF# HD58# HD59# HDS3# HD52# HD47# HD45# HD34# HD33# HD32# HDP3 HD25# HD24# HD07# HD14# HD15# GD24 GD31 GDBIH GPIPE# SBA4 HDBI3# HD46# HD40# HD36# HDP1 HD27# HD10# HDS0# HD13# HD12# GSERR# AGPVREF HDVREF HDVREF GNDTT HDVREF HD11# HDS0 HD09# GD14 GBE1# HDBI0# HD03# HD08# HD02# HD06# GD12 HCMPVREF HRCOMP
Name
HD05# HD04# HD01# GD10 GPAR HDVREF HD00# GBE0# GDS0 GDS0F GDS0# GDS0S GD11 GD15 GD13 AGPVREF VAD4 strap GCLK VCCQQ VAD5 strap VPAR GNDQQ AGPCOMP VBE# VAD1 strap VAD0 strap BPRI# UPSTB# UPSTB DNSTB# DNSTB DNCMD HCLK# VCCHCK1 GNDHCK1 DEFER# HITM# VAD6 strap VAD7 strap VAD3 strap VAD2 strap VLCOMP HCLK VCCHCK2 GNDHCK2 RS2# RS0# HIT# SUSST# UPCMD VLVREF VSUS25 GTLVREF RS1# BNR# DBSY# HLOCK# ADS#
AA29 AA30 AA31 AA32 AA33 AA34 AB29 AB31 AB32 AB34 AC30 AC31 AC32 AC33 AC34 AD29 AD30 AD31 AD32 AD33 AD34 AE01 AE03 AE31 AE32 AE34 AF01 AF02 AF03 AF04 AF05 AF06 AF30 AF31 AF32 AF33 AF34 AG01 AG02 AG03 AG04 AG05 AG30 AG31 AG32 AG33 AG34 AH01 AH03 AH04 AH31 AH32 AH34 AJ01 AJ02 AJ03 AJ05
Name
RESET# PWROK HTRDY# BREQ# DRDY# HA04 HREQ2# HA03 HREQ0# HREQ4# HAVREF HAS0# HREQ3# HA09 HA07 HA06 GNDTT HA05 HREQ1# HA11 HA16 HA08 HA14 HA13 HA10 HAVREF HA24 HA20 HA18 HA15 HA12 MD63 MD59 HA19 HA21 HA17 MD62 MD58 DQS7# CKE7 SCASB# SCASA# MEMVREF HA28 HAS1# HA25 HA23 HA22 MD57 MD61 DQM7 CKE7 SWEA# SWEB# HA26 HA30 HA33 HA27 HA32 MD56 MD60 MD51 RSP# HAP1 HA29 MD55 MD50 MD54 SRASA#
AJ06 AJ07 AJ11 AJ12 AJ13 AJ16 AJ17 AJ23 AJ31 AJ32 AJ33 AJ34 AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK09 AK12 AK15 AK16 AK18 AK19 AK21 AK22 AK24 AK25 AK32 AK33 AK34 AL01 AL03 AL04 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL34 AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12
Names
MAA10 MAB10 MEMVREF VCCMDLL GNDMDLL MEMVREF MEMVREF HAP0 HA35 HA31 HA34 DQS6# CKE6 DQM6 CKE6 MAB11 SRASB# MAA11 MAA12 MAB01 MAA03 MAB06 MAA05 MAB08 MAA07 MAA14 MAA15 MAB15 GCKE VCCMCK GNDMCK MCLK MD53 MD52 MD49 MAB12 MD45 MAB00 MAA01 MAA02 MAB02 MECC6 CKE6 MECC2 CKE2 MAA04 MD27 MAA06 MAA08 MD24 MAB07 MAA13 MAB13 MAB14 MD20 DQS1# CKE1 MCLKF MD48 MD47 MD46 CS5# MD42 CS2# MD40 MAA00 MD38 MD34 MAB03 MD32
AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM30 AM34 AN01 AN03 AN04 AN06 AN07 AN09 AN10 AN12 AN13 AN15 AN16 AN18 AN19 AN21 AN22 AN24 AN25 AN27 AN28 AN30 AP01 AP02 AP03 AP04 AP05 AP06 AP07 AP08 AP09 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30
Name
MECC1 CKE1 MAB04 MD31 MAB05 DQS3# CKE3 MD28 MD22 MAB09 MD21 MD11 DQM1 CKE1 MD08 MD03 MD02 MD01 MAA09 TESTIN# MD43 CS4# DQS5# CKE5 CS0# MD35 DQS4# CKE4 MD37 MECC7 CKE7 DQS8# MECC5 CKE5 MD26 MD29 MD19 DQM2 CKE2 MD17 MD15 MD12 MD06 DQS0# CKE0 MD04 CS7# CS6# CS3# DQM5 CKE5 CS1# MD41 MD44 MD39 DQM4 CKE4 MD33 MD36 MECC3 CKE3 DQM8 MECC0 CKE0 MECC4 CKE4 MD30 DQM3 CKE3 MD25 MD23 MD18 DQS2# CKE2 MD16 MD10 MD14 MD13 MD09 MD07 DQM0 CKE0 MD05 MD00
VCC25 pins): VCCMEM pins): VCCAGP pins): VCCVL pins): pins): (199 pins):
A15-17, B15-17, C15-17, D15-17, E14-17, F14-17, K12-14,18-22, P10, R10, T10,25, U25, V25, W10,25, Y25, AA25, AB10,25, AE12-21 V12, W11-12, Y11-12, AA11-12, AB1-6,11-12,24, AC1-6,11-24, AD1-6,12-23, AJ26-30, AK26-31, AL26-33, AM29-33, AN31-34, AP31-34 C1-2, D1-3, E1-4, F2-5, G3-6, H4-6, J5-6, L12-17, M11-17, N11-12, P11-12, R11-12 T11-12, U11-12, V11, Y1-6, AA1-6 K29-34, L18-23,29-34, M18-24,29-34, N23-24,29-34, P23-24,29-33, R23-24, T23-24, U23-24, V23-24, W23-24, Y23-24, AA23-24 C3,18, D4-5,18,33, E5-6,9,12,18-21,24,27,30, G29, H2-3,29, J4,30-33, L2,6, P2,6,14-21, R4-6,14-21,29-33, T6,14-21,33, U2,14-21, V4,6,14-21, W2,4-5,14-21,29-30,33, Y14-21,29, AA14-21, AB23,30,33, AC29, AE2,4-6,29-30,33, AF29, AG6,29, AH2,5-6,29-30,33, AJ4,8-10,14-15,18-22,24-25, AK8,10-11,13-14,17,20,23, AL2,5,25, AN2,5,8,11,14,17,20,23,26,29
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Table VT8754 List (Alphabetical Order)
AN06 AP05 AM06 AP03 AN03 AM04 AP02 AP01 AP28 AM24 AN21 AP17 AP09 AP04 AK02 AG03 AP13 AN28 AL24 AP21 AM17 AN09 AN04 AK01 AF03 AN13 AK25
Name
ADS# AGP8XDT# AGPCOMP AGPVREF AGPVREF BNR# BPRI# BREQ# CPURST# CS0# CS1# CS2# CS3# CS4# CS5# CS6# CS7# DBSY# DEFER# DNCMD DNSTB DNSTB# DQM0 CKE0 DQM1 CKE1 DQM2 CKE2 DQM3 CKE3 DQM4 CKE4 DQM5 CKE5 DQM6 CKE6 DQM7 CKE7 DQM8 DQS0# CKE0 DQS1# CKE1 DQS2# CKE2 DQS3# CKE3 DQS4# CKE4 DQS5# CKE5 DQS6# CKE6 DQS7# CKE7 DQS8# DRDY# GBE0# GBE1# GBE2# GBE3# GCKE GCLK GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19
AK33 AJ13 AB29 AB31 AA34 AA33 AC31 AA32 AC34 AB34 AD34 AC33 AC32 AD33 AC30 AE34 AD32 AE31 AD31 AE32 AF34 AF33 AD30 AF32 AG30 AG33 AF30 AH34 AG31 AJ33
Name
GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 GDBIH GPIPE# GDBIL GDS0 GDS0F GDS0# GDS0S GDS1 GDS1F GDS1# GDS1S GDEVSEL# GFRM# GGNT# GIRDY# GNDHCK1 GNDHCK2 GNDMCK GNDMDLL GNDQQ GNDTT GNDTT GPAR GPIPE# GRBF# GREQ# GSERR# GSTOP# GTLVREF GTRDY# GWBF# HA03 HA04 HA05 HA06 HA07 HA08 HA09 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31
AG34 AG32 AJ34 AJ32 AJ31 AH32 AA30 AF31 AA29 AD29
Name
HA32 HA33 HA34 HA35 HAP0 HAP1 HAS0# HAS1# HAVREF HAVREF HCLK HCLK# HCMPVREF HD00# HD01# HD02# HD03# HD04# HD05# HD06# HD07# HD08# HD09# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53#
AB32 AA31 AM08 AL09 AL10 AK12 AL14 AK16 AL16 AK19 AL17 AM30 AJ06 AK05 AK06 AL20 AK21 AK22 AL08 AK09 AL11 AM11 AM14 AM16 AK15 AL19 AK18 AM21 AJ07
Name
HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HDBI0# HDBI1# HDBI2# HDBI3# HDP0 HDP1 HDP2 HDP3 HDS0 HDS0# HDS1 HDS1# HDS2 HDS2# HDS3 HDS3# HDVREF HDVREF HDVREF HDVREF HIT# HITM# HLOCK# HRCOMP HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HTRDY# MAA00 MAA01 MAA02 MAA03 MAA04 MAA05 MAA06 MAA07 MAA08 MAA09 MAA10 MAA11 MAA12 MAA13 MAA14 MAA15 MAB00 MAB01 MAB02 MAB03 MAB04 MAB05 MAB06 MAB07 MAB08 MAB09 MAB10
AK03 AL06 AL21 AL22 AK24 AK34 AL34 AP30 AM28 AM27 AM26 AN30 AP29 AN27 AP27 AM25 AP26 AP23 AM23 AN25 AP25 AP24 AN24 AP22 AN22 AP20 AN19 AL23 AM22 AM19 AP19 AL18 AP18 AN16 AL15 AM18 AN18 AP16 AM15 AM12 AP10 AM10 AN07 AP11 AN10 AM09 AP08 AM07 AP06 AM05 AN01 AP07 AL07 AM03 AM02 AM01 AL04 AJ02 AH04 AL03 AL01 AJ03 AJ01 AH01 AG01 AF02 AE03
Names
MAB11 MAB12 MAB13 MAB14 MAB15 MCLK MCLKF MD00 MD01 MD02 MD03 MD04 MD05 MD06 MD07 MD08 MD09 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59
AH03 AG02 AF01 AE01 AP14 AM13 AL13 AP12 AP15 AN15 AL12 AN12 AF06 AJ11 AJ17 AJ23 AK07 AJ16 AH31 AF05 AF04 AJ05 AK04 AG04 AG05 AM34 AK32 AJ12
Name
MD60 MD61 MD62 MD63 MECC0 CKE0 MECC1 CKE1 MECC2 CKE2 MECC3 CKE3 MECC4 CKE4 MECC5 CKE5 MECC6 CKE6 MECC7 CKE7 MEMVREF MEMVREF MEMVREF MEMVREF PWROK RESET# RS0# RS1# RS2# RSP# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 SBSF SBS# SBSS SCASA# SCASB# SRASA# SRASB# SUSST# SWEA# SWEB# TESTIN# UPCMD UPSTB UPSTB# VAD0 strap VAD1 strap VAD2 strap VAD3 strap VAD4 strap VAD5 strap VAD6 strap VAD7 strap VBE# VCCHCK1 VCCHCK2 VCCMCK VCCMDLL VCCQQ VLCOMP VLVREF VPAR VSUS25
VCC25 pins): VCCMEM pins): VCCAGP pins): VCCVL pins): pins): (199 pins):
A15-17, B15-17, C15-17, D15-17, E14-17, F14-17, K12-14,18-22, P10, R10, T10,25, U25, V25, W10,25, Y25, AA25, AB10,25, AE12-21 V12, W11-12, Y11-12, AA11-12, AB1-6,11-12,24, AC1-6,11-24, AD1-6,12-23, AJ26-30, AK26-31, AL26-33, AM29-33, AN31-34, AP31-34 C1-2, D1-3, E1-4, F2-5, G3-6, H4-6, J5-6, L12-17, M11-17, N11-12, P11-12, R11-12 T11-12, U11-12, V11, Y1-6, AA1-6 K29-34, L18-23,29-34, M18-24,29-34, N23-24,29-34, P23-24,29-33, R23-24, T23-24, U23-24, V23-24, W23-24, Y23-24, AA23-24 C3,18, D4-5,18,33, E5-6,9,12,18-21,24,27,30, G29, H2-3,29, J4,30-33, L2,6, P2,6,14-21, R4-6,14-21,29-33, T6,14-21,33, U2,14-21, V4,6,14-21, W2,4-5,14-21,29-30,33, Y14-21,29, AA14-21, AB23,30,33, AC29, AE2,4-6,29-30,33, AF29, AG6,29, AH2,5-6,29-30,33, AJ4,8-10,14-15,18-22,24-25, AK8,10-11,13-14,17,20,23, AL2,5,25, AN2,5,8,11,14,17,20,23,26,29
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DESCRIPTIONS
Table VT8754 P4X333 Descriptions
Interface
Signal Name HA[35:3]# (see pinout tables) AH32, AJ31 AF31, AA30 Signal Description Host Address Bus. Connect address host CPU. Inputs during cycles driven VT8754 during cache snooping operations. Address signals through HA[35] allow support Gbyte memory space. Host Addres Parity. Host Address Strobe. Source synchronous strobes used transfer HA[31:3]# HREQ[4:0]# transfer rate. HAS1# strobe HA[31:17]# HAS0# strobe HA[16:3] HREQ[4:0]#. Host Data. These signals connected data bus. Host Data Parity.
HAP[1:0] HAS[1:0]#
HD[63:0]# HDP[3:0] HDBI[3:0]#
Host Dynamic Inversion. Driven along with HD[63:0]# indicate associated signals inverted not. Used limit number simultaneously switching signals associated 16-bit data group (HDBI3# HD[63:48]#, HDBI2# HD[47:32]#, HDBI1# HD[31:16]#, HDBI0# HD[15:0]#). HDBIn# asserted such that number data bits driven corresponding group does exceed C21, B26, Host Differential Data Strobes. Source synchronous strobes used transfer HDS[3:0] C31, HD[63:0]# HDBI[3:0]# transfer rate. HDS3 HDS3# strobes HD[63:48]# HDBI3#; HDS2 HDS2# strobes HD[47:32]# D21, A26, HDBI2#; HDS1 HDS1# strobes HD[31:16]# HDBI1#; HDS0 HDS[3:0]# B31, HDS0# strobes HD[15:0]# HDBI0#. Address Strobe. asserts ADS# cycle. ADS# Data Busy. Used data owner hold data transfers requiring DBSY# more than cycle. Data Ready. Asserted each cycle that data transferred. DRDY# Hit. Indicates that caching agent holds unmodified version requested line. HIT# Also driven conjunction with HITM# target extend snoop window. Modified. Asserted indicate that address modified HITM# cache needs written back. Host Lock. cycles sampled with assertion HLOCK# ADS# until HLOCK# negation HLOCK# must atomic. Y34, AA31, Request Command. Asserted during both clocks request phase. first HREQ[4:0]# Y31, AB32, clock, signals define transaction type level detail that sufficient begin snoop request. second clock, signals carry additional information define complete transaction type. Host Target Ready. Indicates that target processor transaction able HTRDY# enter data transfer phase. Note: Clocking interface performed with HCLK HCLK# (see clock description group). Note: Internal pullup resistors provided AGTL+ interface pins. does have internal pullups, these north bridge internal pullups enabled allow interface meet AGTL+ interface specifications (see VAD3 strap).
(see pinout tables) D28, B28, E28, E22, A25, C30,
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Interface (continued)
Signal Name RS[2:0]# U32, V30, Signal Description Response Signals. Indicates type response table below: RS[2:0]# Response type RS[2:0]# Response type Idle State Hard Failure Retry Response Normal Without Data Defer Response Implicit Writeback Reserved Normal With Data Response Parity. Request. request output CPU. Priority Agent Request. owner this signal will always next owner. This signal priority over symmetric requests causes current symmetric owner stop issuing transactions unless HLOCK# signal asserted. VT8754 drives this signal gain control processor bus. Block Next Request. Used block current request owner from issuing requests. This signal used dynamically control processor pipeline depth. Defer. VT8754 uses dynamic deferring policy optimize system performance. VT8754 also uses DEFER# signal indicate processor retry response. Reset. Reset output CPU. External pullup filter capacitor ground should provided manufacturer's recommendations.
RSP# BREQ# BPRI#
AH31
BNR# DEFER# CPURST#
pinouts were defined assuming layout model shown below (and general layout shown) guide component placement. Other layouts (AT, LPX, NLX) were also considered typically follow same general component placement.
Pentium Slots Slot
Power Supply
VT8235 V-Link South Bridge
8754 DRAM
Connectors
DRAM Modules
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DRAM Interface
Signal Name MD[63:0] (see lists) Signal Description Memory Data. These signals connected DRAM data bus. Output drive strength Device RxE8. DRAM Data: when enabled. Clock Enables: each DRAM bank powering down SDRAMs notebook applications. Also used desktop systems clock control reduce power usage reducing heat/temperature high-speed memory systems. Memory Address DRAM address lines (two sets better drive). Output drive strength Device RxEA. Memory Address DRAM address lines (two sets better drive). Output drive strength Device RxEB. Address, Column Address Write Enable Command Indicator (two sets better drive). Output drive strength Device RxEA. Address, Column Address Write Enable Command Indicator (two sets better drive). Output drive strength Device RxEB. Chip Select. Chip select each bank. Output drive strength Device RxE9. Data Mask. Data mask each byte lane plus DQM8 byte. Output drive strength Device RxE8. Data Strobe. Data strobe each byte lane plus DQS8# byte. Output drive strength Device RxE8. Clock Enables. Clock enables each DRAM bank powering down SDRAM clock control reducing power usage reducing heat temperature highspeed memory systems. Device RxBD[6] function enable. Global Clock Enable. Connect. Reserved future use.
MECC[7:0] CKE[7:0]
AN12, AL12, AN15, AP15, AP12, AL13, AM13, AP14
MAA[15:0]
(see lists)
MAB[15:0]
(see lists)
SRASA#, SCASA#, SWEA# SRASB#, SCASB#, SWEB# CS[7:0]# DQM[8], DQM[7:0] CKE[7:0] DQS[8], DQS[7:0]# CKE[7:0] CKE[7:0] MECC[7:0] -orCKE[7:0] DQM[7:0] -orCKE[7:0] DQS[7:0]# GCKE
AJ5, AF5,
AK4, AF4,
AP1, AP2, AM4, AN3, AP3, AM6, AP5, AP13, AG3, AK2, AP4, AP9, AP17, AN21, AM24, AP28 AN13, AF3, AK1, AN4, AN9, AM17, AP21, AL24, AN28 (see above)
AK25 AJ16,
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Interface
Signal Name GD[31:0] GBE[3:0]# (GBE[3:0] mode) (see pinlist) Signal Description Address Data Bus. Address driven with assertion AGP-style transfers with GFRM# assertion PCI-style transfers. Command Byte Enable. (Interpreted C/BE# 2x/4x C#/BE AGP: These pins provide command information (different commands than PCI) driven master (graphics controller) when requests being enqueued using GPIPE# (2x/4x only GPIPE# isn't used mode). These pins provide valid byte information during write transactions driven master. target (this chip) drives these lines "0000" during return read data. PCI: Commands driven with GFRM# assertion. Byte enables corresponding supplied requested data driven following clocks. Parity. single parity provided over GD[31:0] GBE[3:0]. Dynamic Inversion High Low. transfer mode only. Driven source indicate whether corresponding data group (GDBIH GD[31:16] GDBIL GD[15:0]) needs inverted receiving GDBIx indicates that corresponding data group should inverted). Used limit number simultaneously switching outputs each 16-pin group. Strobe Source synchronous strobes GD[15:0] (the agent that providing data drives these signals). .GDS0 provides timing data transfer mode; GDS0 GDS0# provide timing transfer mode. transfer mode, GDS0 interpreted GDSF0 ("First" strobe) GDS0# GDSS0 ("Second" strobe). Strobe Source synchronous strobes GD[31:16] (i.e., agent that providing data drives these signals). .GDS1 provides timing data transfer mode; GDS1 GDS1# provide timing transfer mode. transfer mode, GDS1 interpreted GDSF1 ("First" strobe) GDS1# GDSS1 ("Second" strobe). Frame. Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. Interpreted active high Initiator Ready. (Interpreted active PCI/AGP2x/4x high AGP: write operations, assertion this indicates that master ready provide write data current transaction. Once this asserted, master allowed insert wait states. read operations, assertion this indicates that master ready transfer subsequent block read data. master never allowed insert wait state during initial block read transaction. However, insert wait states after each block transfers. PCI: Asserted when initiator ready data transfer. Target Ready. (Interpreted active PCI/AGP2x/4x high AGP: Indicates that target ready provide read data entire transaction (when transaction complete within four clocks) ready transfer (initial subsequent) block data when transfer requires more than four clocks complete. target allowed insert wait states after each block transfer both read write transactions. PCI: Asserted when target ready data transfer. Stop (PCI transactions only). Asserted target request master stop current transaction. Interpreted active high Device Select (PCI transactions only). This signal driven VT8754 when initiator attempting access main memory. input when VT8754 acting initiator. used cycles. Interpreted active high Pipelined Request. Asserted master (the external graphics controller) indicate that full-width request enqueued target VT8754. master enqueues request each rising edge GCLK while GPIPE# asserted. When GPIPE# deasserted requests enqueued across bus. used -11Pin Descriptions
GPAR GDBIH GPIPE#, GDBIL
GDS0 (GDSF0 8x), GDS0# (GDSS0 GDS1 (GDSF1 8x), GDS1# (GDSS1 GFRM# (GFRM GIRDY# (GIRDY
GTRDY# (GTRDY
GSTOP# (GSTOP GDEVSEL# (GDEVSEL mode) GPIPE# (GPIPE
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Interface (continued)
Signal Name AGP8DT# GRBF# (GRBF GWBF# (GWBF SBA[7:0] (SBA[7:0]# Signal Description Transfer Mode Detect. indicates that external graphics card support transfer mode Read Buffer Full. Indicates master (graphics controller) ready accept previously requested priority read data. When GRBF# asserted, VT8754 will return priority read data graphics controller. Write Buffer Full. SideBand Address. Provides additional pass address command information from master (graphics controller) target (VT8754 north bridge logic). These pins ignored until enabled. Sideband Strobe. Driven master provide timing SBA[7:0]. used while SBS# used together mode, strobe mechanism works differently with interpreted SBSF ("First" strobe) SBS# SBSS ("Second" strobe). Status (AGP only). Provides information from arbiter master indicate what Only valid while GGNT# asserted. Indicates that previously requested priority read flush data being returned master (graphics controller). Indicates that previously requested high priority read data being returned master. Indicates that master provide priority write data previously enqueued write command. Indicates that master provide high priority write data previously enqueued write command. Reserved. (arbiter must issue, defined future). Reserved. (arbiter must issue, defined future). Reserved. (arbiter must issue, defined future). Indicates that master (graphics controller) been given permission start transaction. master enqueue requests asserting PIPE# start transaction asserting GFRM#. ST[2:0] always outputs from target (north bridge logic) inputs master (graphics controller). Request. Master (graphics controller) request bus. Grant. Permission given master (graphics controller) bus. System Error.
B10, C10, A10, E11, A11, C12, B11,
(SBSF 8x), SBS# (SBSS
ST[2:0]
E13, B13,
GREQ# (GREQ GGNT# (GGNT GSERR#
Note:
Note: Note: Note: Note:
Note:
operation bus, following pins required: PERR# (parity error reporting required transient data devices such graphics controllers) LOCK# lock requirement AGP) IDSEL (internally connected AD16 AGP-compliant masters) Separate system interrupts provided AGP. connector provides interrupts INTA-B#. supports only master directly (REQ[3:0]# GNT[3:0]# provided). External logic required implement additional master capability. Note that arbitration mechanism different from bus. separate reset required (RESET# resets both buses) mechanisms provided enqueue master requests: GPIPE# send addresses multiplexed lines) port send addresses unmultiplexed). masters implement other select initialization time (they allowed change during runtime). Only will used; signals associated with other will used. GRBF# internal pullup maintain deasserted state case implemented master device. mode allows only (GPIPE# isn't used mode). signal levels 0.8V. mode maintains most signals level when inactive resulting current flow.
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V-Link Interface
Signal Name VAD7 strap, VAD6 strap, VAD5 strap, VAD4 strap, VAD3 strap, VAD2 strap, VAD1 strap, VAD0 strap VPAR VBE# UPCMD UPSTB UPSTB# DNCMD DNSTB DNSTB# Signal Description Address Data Bus. Connection VAD7 strap Dual L=Single, H=Dual VAD6 strap Auto-Configure L=Disable, H=Enable VAD5 strap AGTL+ Drive Strength L=1x, H=4x VAD4 strap AGTL+ Drive Strength L=1x, H=2x VAD3 strap Internal AGTL+ Pullups L=Enable, H=Disable VAD2 strap Depth L=1-level, H=12-level VAD1 strap -reservedVAD0 strap Frequency L=100 MHz, H=133 Parity. Byte Enable. Command from Client (South Bridge) Host (North Bridge). Strobe from Client Host. Complement Strobe from Client Host. Command from Host (North Bridge) Client (South Bridge). Strobe from Host Client. Complement Strobe from Host Client. Register Rx50[6] Rx54[5] SDCS3# SDA2 SDA1 SDA0 SA19 SA18 SA17 SA16
Rx52[5] Rx50[7] Rx54[6]
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Clocks, Resets, Power Control, General Purpose I/O, Interrupts Test
Signal Name HCLK HCLK# MCLK MCLKF GCLK RESET# AK34 AL34 Signal Description Host Clock. This receives host clock (100 MHz). This clock used P4X333 logic that host domain. Host Clock Complement. Used Quad Data Transfer host bus. Memory (SDRAM) Clock. Output from internal clock generator external clock buffer. Memory (SDRAM) Clock Feedback. Input from external clock buffer. Clock. Clock logic. Reset. Input from South Bridge chip. When asserted, this signal resets P4X333 sets register bits default value. rising edge this signal used sample power-up strap options Power Connect South Bridge Power Good circuitry. Suspend Status. implementation Suspend-to-DRAM feature. Connect external pull-up disable. Maskable Interrupt. Connect South Bridge input. Test This used testing must left unconnected tied high board designs.
PWROK SUSST# TESTIN#
AM34
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Reference Voltages
Signal Name GTLVREF HDVREF HAVREF HCMPVREF MEMVREF VLVREF AGPVREF F19, F24, F28, AA29, AD29 AF6, AJ11, AJ17, AJ23 F10, Signal Description Host Interface AGTL+ Voltage Reference. typically derived using resistive voltage divider. P4X333 Design Guide. Host Data Voltage Reference. typically derived using resistive voltage divider. P4X333 Design Guide. Host Address Voltage Reference. typically derived using resistive voltage divider. P4X333 Design Guide. Host Compensation Voltage Reference. typically derived using resistive voltage divider. P4X333 Design Guide. Memory Voltage Reference. VCC25 typically derived using resistive voltage divider. P4X333 Design Guide. V-Link Voltage Reference. 0.9V derived using resistive voltage divider consisting VCC25 1.13K ground. Voltage Reference. VCCQQ (0.75V) transfer mode) 0.23 VCCQQ (0.35V) transfer mode). P4X333 Design Guide additional information circuit implementation details.
Compensation
Signal Name HRCOMP VLCOMP AGPCOMP Signal Description Host Compensation. Connect 20.5 resistor ground. Used Host interface buffer calibration. Vlink Compensation. Connect resistor ground. Compensation.
Analog Power Ground
Signal Name VCCHCK1 GNDHCK1 VCCHCK2 GNDHCK2 VCCMCK GNDMCK VCCMDLL GNDMDLL AK32 AK33 AJ12 AJ13 Signal Description Power Host Clock (2.5V ±5%) Ground Host Clock Circuitry. Connect main ground plane through ferrite bead. Power Host Clock (2.5V ±5%) Ground Host Clock Circuitry. Connect main ground plane through ferrite bead. Power Memory Clock (2.5V ±5%) Ground Memory Clock Circuitry. Connect main ground plane through ferrite bead. Power Memory Strobe (2.5V ±5%) Ground Memory Strobe Circuitry. Connect main ground plane through ferrite bead.
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Digital Power Ground
Signal Name GNDTT VCCMEM VCCVL VCCAGP VCCQQ GNDQQ VCC25 VSUS25 (see lists) F25, AB29 (see lists) (see lists) (see lists) (see lists) (see lists) Signal Description Power Interface Logic Pins). Voltage dependent. Ground Interface Logic Pins). Power Memory Interface Logic Pins). 2.5V ±5%. Power V-Link Interface Logic Pins). 2.5V Power Interface Logic Pins). 1.5V Quiet Power. Connect main power (VCCAGP) through ferrite bead. Ground Quiet Power. Connect main ground plane. Power Internal Logic Pins). 2.5V Suspend Power. 2.5V Digital Ground (199 Pins). Connect main ground plane.
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REGISTERS
Register Overview
following tables summarize configuration registers P4X333. These tables also document power-on default value ("Default") access type ("Acc") each register. Access type definitions used (Read/Write), (Read/Only), reserved used (essentially same RO), just (Read Write Clear individual bits), (Write Once then Read Only after that). Registers indicated have some read/only bits that always read back fixed value (usually unused); registers designated have some read-only read write bits (see individual register descriptions following these tables details). offset default values shown hexadecimal unless otherwise indicated. graphics registers described separate document.
Table VT8754 P4X333 Registers
P4X333 Ports Port CFB-8 CFF-C Port Arbiter Disable Configuration Address Configuration Data Default 0000 0000 0000 0000
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P4X333 Device Registers Host Bridge Header Registers Offset 13-10 14-2B 2D-2C 2F-2E 30-33 37-34 38-3F Configuration Space Header Vendor Device Command Status Revision Program Interface Class Code Base Class Code -reservedLatency Timer Header Type Built Self Test (BIST) Graphics Aperture Base -reservedSubsystem Vendor Subsystem -reservedCapability Pointer -reservedDefault 1106 3168 0006 0210 0000 0008 0000 0000 0000 00A0 Device-Specific Registers (continued) Offset 56-57 59-58 5F-5A Offset 77-7F DRAM Control Default DRAM Control (see below) Type 2222 DRAM Ending Address: Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) Bank Ending (HA[31:24]) DRAM Type Shadow Control C0000-CFFFF Shadow Control D0000-DFFFF Shadow Control E0000-FFFFF DRAM Timing Banks DRAM Arbitration Timer DRAM Arbitration Control DRAM Strobe Input Delay DRAM Strobe Output Delay DRAM Clock Select DRAM Refresh Counter DRAM Arbitration Control DRAM Clock Control -reserved00 Control Status Control Buffer Control Flow Control -reservedPCI Master Control -reservedPCI Arbitration Arbitration -reservedDefault
Device-Specific Registers Offset Offset V-Link Control V-Link Revision V-Link Capability V-Link Downlink Command V-Link Uplink Depth V-Link Uplink Buffer Size V-Link Timer V-Link Misc Control V-Link Control V-Link NB/SB Configuration V-Link Capability V-Link Downlink Status V-Link Uplink Depth V-Link Uplink Buffer Size V-Link Timer Master High Priority V-Link Miscellaneous Control Host Protocol Control Interface Request Phase Control Interface Basic Control Interface Advanced Control Interface Arbitration Control Frequency Default Default
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Register Summary Tables
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Device Device-Specific Registers (continued) Offset D3-D0 Offset Error Control DRAM Error Address DRAM Error Syndrome Host Parity Status Host Parity Enable -reservedHost AGTL+ Control Host Address (2x) Pullup Drive Host Address (2x) Pulldown Drive Host Data (4x) Pullup Drive Host Data (4x) Pulldown Drive AGTL+ Output Delay Stagger Ctrl AGTL+ Control AGTL+ Compensation Status AGTL+ AutoCompensation Offset Default Default Default Default
Device Device-Specific Registers (continued) Offset 81-83 8B-88 8C-9F Offset A7-A4 AB-A8 Offset
GART/TLB Control Default GART Control -reserved00 Graphics Aperture Size CPU-to-Memory Write Policy CPU-to-Memory Bandwidth Timer CPU-to-Memory Bandwidth Limit Aperture Base Register Base 0000 0000 -reserved00 Control Next Item Pointer Specification Revision -reservedAGP Status Command Control Miscelleneous Control Miscellaneous Control Control Compensation Control Status Output Drive Strength Drive Delay Control Strobe Drive Strength V-Link Compenation Drive Ctrl V-Link Compensation Control V-Link Strobe Drive Control V-Link Data Drive Control -reservedV-Link Compensation Control V-Link Strobe Drive Control V-Link Data Drive Control -reservedPower Management Control Power Management Mode DRAM Power Management Dynamic Clock Stop SCMD Toggle Reduction Extended Power Management Ctrl Power Management Capability Power Management Next Pointer Power Management Capabilities Power Management Capabilities Power Management Control/Status Power Management Status PCI-to-PCI Bridge Support Extension Power Management Data -reservedDefault 1F00 0237 0000 0000 Default Default Default
Offset Control (reserved) E0-E3 -reservedOffset EC-ED DRAM Above Control Address Address High APIC Decoding -reservedDRAM Drive DRAM Drive DRAM Drive DRAM Drive -reserved-
Offset Interface DRDY Timing Control Default DRDY Timing DRDY Timing Offset F0-F2 F3-F4 F5-FF Test, BIOS Scratch, Miscellaneous Reserved Program) BIOS Scratch Registers Reserved Program) Default
Offset Offset C8-CF
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P4X333 Device Registers PCI-to-PCI Bridge Header Registers Offset 10-17 1F-1E 21-20 23-22 25-24 27-26 28-33 35-3D 3F-3E Configuration Space Header Vendor Device Command Status Revision Program Interface Class Code Base Class Code -reservedLatency Timer Header Type -reserved- (Built Self Test) -reservedPrimary Number Secondary Number Subordinate Number Secondary Latency Timer Base Limit Secondary Status Memory Base Memory Limit (Inclusive) Prefetchable Memory Base Prefetchable Memory Limit -reservedCapability Pointer -reservedPCI-to-PCI Bridge Control Default 1106 B168 0007 0230 0000 FFF0 0000 FFF0 0000 Device-Specific Registers Offset 47-46 49-7F Offset 88-FF Control CPU-to-AGP Flow Control CPU-to-AGP Flow Control Master Control Master Latency Timer Reserved Program) Fast Write Control PCI-to-PCI Bridge Device PCI2 Error Reporting -reservedPower Management Capability Next Pointer Power Management Capabilities Power Management Capabilities Power Management Control Status Power Management Status PCI-PCI Bridge Support Extensions Power Management Data -reservedDefault 0000 Default
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Register Summary Tables
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Chipset VT8754 Pentium V-Link North Bridge Configuration Space
registers P4X333 (listed above) addressed following configuration mechanism: Mechanism These ports respond only double-word accesses. Byte word accesses will passed unchanged. Port CFB-CF8 Configuration Address. Configuration Space Enable Disabled. default Convert configuration data port writes configuration cycles 30-24 Reserved .always reads 23-16 Number Used choose specific system 15-11 Device Number Used choose specific device system (devices defined P4X333) 10-8 Function Number Used choose specific function selected device supports multiple functions (only function defined P4X333). Register Number (also called "Offset") Used select specific DWORD P4X333 configuration space Fixed .always reads Port CFF-CFC Configuration Data.
Miscellaneous
port defined P4X333: Port Port Arbiter Disable Reserved always reads Arbiter Disable Respond GREQ# signal .default respond GREQ# signal Arbiter Disable Respond REQ# signals .default respond REQ# signals, including PREQ# This port enabled read/write access setting bit-7 Device Configuration Register
Refer Specification Version further details operation above configuration registers.
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Miscellaneous Configuration Space
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Device Offset Status (0210h).RWC Detected Parity Error parity error detected. default Error detected either address data phase. This even error response disabled (command register bit-6). .write clear Signaled System Error (SERR# Asserted) .always reads Signaled Master Abort abort received default Transaction aborted master .write clear Received Target Abort abort received default Transaction aborted target .write clear Signaled Target Abort .always reads Target Abort never signaled 10-9 DEVSEL# Timing Fast Medium .always reads Slow Reserved Data Parity Error Detected data parity error detected default Error detected data phase. only error response enabled command bit-6 P4X333 initiator operation which error occurred. .write clear Fast Back-to-Back Capable .always reads User Definable Features .always reads 66MHz Capable.always reads Supports Capability list.always reads Reserved .always reads Device Offset Revision (0nh). Chip Revision Code.always reads Device Offset Programming Interface (00h). Interface Identifier .always reads Device Offset Class Code (00h). Class Code .reads indicate Host Bridge Device Offset Base Class Code (06h). Base Class Code. reads indicate Bridge Device Device Offset Latency Timer (00h) Specifies latency timer value clocks. Guaranteed Time Slice default=0 Reserved (fixed granularity clks) always read These bits writeable read specification compatibility. programmed value read back Rx75[6-4] (PCI Arbitration
Device Register Descriptions
Device Host Bridge Header Registers registers located configuration space. They should programmed using configuration mechanism through with number, function number, device number equal zero. Device Offset Vendor (1106h) 15-0 Code (reads 1106h identify Technologies) Device Offset Device (3168h).RO 15-0 Code (reads 3168h identify P4X333) Device Offset -Command (0006h).RW 15-10 Reserved always reads Fast Back-to-Back Cycle Enable Fast back-to-back transactions only allowed same agent.default Fast back-to-back transactions allowed different agents SERR# Enable. SERR# driver disabled.default SERR# driver enabled (SERR# used report errors). Address Data Stepping Device never does stepping.default Device always does stepping Parity Error Response.RW Ignore parity errors continue.default Take normal action detected parity errors Palette Snoop Treat palette accesses normally.default Don't respond palette accesses Memory Write Invalidate Command masters must Write.default masters generate Write Inval Special Cycle Monitoring Does monitor special cycles.default Monitors special cycles Master. Never behaves master behave master.default Memory Space. Does respond memory space Responds memory space.default Space Does respond space .default Responds space
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Device Host Bridge Header Registers (continued) Device Offset Header Type (00h).RO Header Type Code reads single function Device Offset Built Self Test (BIST) (00h).RO BIST Supported .reads supported functions Reserved always reads Device Offset 13-10 Graphics Aperture Base (00000008h) 31-30 Upper Programmable Base Address Bits def=0 29-22 Lower Programmable Base Address Bits def=0 These bits behave hardwired corresponding Graphics Aperture Size register (Device Offset 84h) (This Register) Aper Size) 128M 256M Device Offset 2D-2C Subsystem Vendor (0000h)R/W1 15-0 Subsystem Vendor default This register written once then read only. Device Offset 2F-2E Subsystem (0000h). R/W1 15-0 Subsystem default This register written once then read only. Device Offset 37-34 Capability Pointer (000000A0h) Contains offset from start configuration space. 31-0 Capability List Pointer always reads
21-4 Reserved always reads Prefetchable. always reads indicate prefetchable Type always reads indicate address range 32-bit adddress space Memory Space always reads indicate space
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Device Host Bridge Device-Specific Registers These registers normally programmed once system initialization time. V-Link Control Device Offset V-Link Specification (00h) Specification Revision. always reads Device Offset V-Link Capability (19h) V-Link Parity Error Detected NB.WC V-Link Parity Error Detected.default V-Link Parity Error Detected (write clear) Reserved always reads 16-bit Width Supported Supported .default Supported 8-Bit Width Supported NB.RO Supported Supported .default Rate Supported NB.RO Supported Supported .default Rate Supported NB.RO Supported .default Supported Reserved always reads Rate Supported NB.RO Supported Supported .default Device Offset Downlink Command (88h) DnCmd Request Depth (0=1 DnCmd) DnCmd Write Buffer Size (doublewords). Device Offset Uplink Depth (80h) UpCmd Request Depth (0=1 UpCmd) Indicates maximum allowable number outstanding UPCMD requests Reserved always reads Device Offset Uplink Buffer Size (82h) UpCmd Write Buffer Size (max lines). UpCmd Write Buffer Size (max lines) Device Offset V-Link Timer (44h). Timer Normal Priority Requests from 0000 Immediate 0001 VCLKs 0010 VCLKs 0011 VCLKs 0100 VCLKs default 0101 VCLKs 0110 VCLKs 0111 VCLKs 1000 VCLKs 1001 16*4 VCLKs 1010 32*4 VCLKs 1011 64*4 VCLKs 11xx long there request Timer High Priority Requests from 0000 Immediate 0001 VCLKs 0010 VCLKs 0011 VCLKs 0100 VCLKs default 0101 VCLKs 0110 VCLKs 0111 VCLKs 1000 VCLKs 1001 16*2 VCLKs 1010 32*2 VCLKs 1011 64*2 VCLKs 11xx long there request
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Device Offset NB/SB V-Link Configuration (18h)RW V-Link Parity Check Disable. default Enable Rest Width Supported Supported default Supported 16-bit Width Supported Supported default Supported 8-Bit Width Supported Supported Supported default Rate Supported Supported Supported default Rate Supported Supported default Supported Reserved .always reads Rate Supported Supported default Supported Device Offset V-Link Capability (19h) V-Link Parity Error Detected parity error detected. default Parity error detected Reserved .always reads 16-bit Width Supported Supported default Supported 8-Bit Width Supported Supported Supported default Rate Supported Supported Supported default Rate Supported Supported default Supported Reserved .always reads Rate Supported Supported Supported default
Device Offset V-Link Misc Control (00h).RW Downstream High Priority Disable High Priority Down Commands .def Enable High Priority Down Commands Downlink Priority Treat Downlink Cycles Normal Priority.def Treat Downlink Cycles High Priority Combine Multiple STPGNT Cycles Into VLink Command Compatible, command V-Link cmd.def commands V-Link command commands V-Link command commands V-Link command V-Link Master Access Ordering Rules High priority read, pass normal read (not pass write) .default Read (high/normal) pass write (HR>LR>W) Read write order Reserved always reads Device Offset V-Link Control (00h) Parity Error SERR# Reported Disable .default Enable Parity Error SERR# Reported Vlink Disable .default Enable Read Ready Return Timing V-Link decodes Read .def Wait till previous write cycles flushed Reserved always reads Down Strobe Dynamic Stop Disable .default Enable Auto-Disconnect Disable .default Enable V-Link Disconnect Cycle HALT cycle Disable .default Enable V-Link Disconnect Cycle STPGNT Cycle Disable .default Enable
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Device Offset Master Priority (00h). 1394 High Priority priority. default High priority High Priority priority. default High priority Reserved .always reads High Priority priority. default High priority Reserved .always reads High Priority priority. default High priority AC97-ISA High Priority priority. default High priority High Priority priority. default High priority Device Offset V-Link Misc Control (00h) Upstream Command High Priority Disable high priority commands. default Enable high priority commands Reserved .always reads Strobe Dynamic Stop Disable. default Enable Reserved .always reads Down Cycle Wait Cycle Write Flush (Except Down Cycle Post Write) Disable. default Enable
Device Offset Downlink Status (88h) DnCmd Request Depth (0=1 DnCmd) DnCmd Write Buffer Size (doublewords). Device Offset Uplink Command (80h) UpCmd Request Depth (0=1 UpCmd) Indicates maximum allowable number outstanding UPCMD requests Reserved always reads Device Offset Uplink Command (82h).RW UpCmd Write Buffer Size (max lines). UpCmd Write Buffer Size (max lines) Device Offset V-Link Timer (44h) Timer Normal Priority Requests from 0000 Immediate 0001 VCLKs 0010 VCLKs 0011 VCLKs 0100 VCLKs .default 0101 VCLKs 0110 VCLKs 0111 VCLKs 1000 VCLKs 1001 16*4 VCLKs 1010 32*4 VCLKs 1011 64*4 VCLKs 11xx long there request Timer High Priority Requests from 0000 Immediate 0001 VCLKs 0010 VCLKs 0011 VCLKs 0100 VCLKs .default 0101 VCLKs 0110 VCLKs 0111 VCLKs 1000 VCLKs 1001 16*2 VCLKs 1010 32*2 VCLKs 1011 64*2 VCLKs 11xx long there request
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Host Control Device Offset Request Phase Control (00h) Hardwired Order Queue) Size Default from inverse VAD2 strap. This register written restrict chip level IOQ. 1-Level (strap pulled high) 12-Level (strap pulled low) Dual Default from VAD7 strap (South Bridge SDCS3# pin) ROMSIP. Single (strap pulled low) .default Dual (strap pulled high) Fast DRAM Access Disable .default Enable Dynamic Defer Snoop Stall Count (granularity normally 01000b) Device Offset Interface Basic Control (00h)RW Read DRAM Fast Ready Wait until received before DRDY returned. default RxEE/EF DRDY timing Read Around Write Disable. default Enable Control pipelined similar VT8633. default Pipelined Read Defer Disable. default Enable Defer Retry Entries Disable. default Enable Defer Retry Entries Shared Each entry dedicated default Each entry shared CPUs Master Pipelined Access Disable. default Enable Reserved .always reads
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Device Offset Frequency (00h) Frequency .Set from VAD1-0 Straps (both straps pulled low) (VAD1 pulled low, VAD0 pulled (VAD1 pulled high, VAD0 ignored) (166 capability VT8754; VT8753 fixed VT8753A allowed MHz) Auto Configure. from VAD6 Strap Disable (strap pulled low) Enable (strap pulled high). AGTL+ Drive settings other chip configuration settings stored ROM, transferred from south bridge (via V-Link bus), loaded into VT8754 automatically after system reset. Refer VT8754 BIOS Porting Guide layout AutoConfigure settings recommended settings. SDRAM Burst Length Disable. default Enable Rx85, Writeable Disable. default Enable Master Operation Disable. default Enable Reserved .always reads Mode Disable (AGP Mode). default Enable (VPX Mode)
Device Offset Interface Advanced Ctrl (00h)RW DRAM Back-to-Back Pipeline Access Disable .default Enable HREQ High Priority Disable .default Enable AGTL+ Pullups Default from inverse VAD3 strap. Disable (strap pulled high) Enable (strap pulled low) Reserved always reads Write Retire Policy After Writes Disable .default Enable 2-Level Defer Queue with Lock Normal Operation .default Enhanced Operation (this should always Consecutive Speculative Read Disable .default Enable Speculative Read Disable .default Enable Device Offset Arbitration Control (00h) Host Timer default BPRI Timer (units HCLKs) default
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DRAM Control These registers normally system initialization time accessed after that during normal system operation. Some these registers, however, need programmed using specific sequences during power-up initialization properly detect type size installed memory (refer Technologies VT8754 BIOS porting guide details). Device Offset DRAM Control (00h). Back-to-Back Write Different Bank Disable. default Enable Fast Read Read Turnaround Disable. default Enable (DQS postamble overlap with preamble) Input Adjust Disable. default Enable Output Adjust Disable. default Enable Removal (Always Perform 4-Burst Disable. default Enable Output Disable. default Enable Auto Precharge Read WriteBack Disable. default Enable Write Recovery Time (for 266). default (for 333)
Table System Memory
Space Start Size Address Range 640K 00000000-0009FFFF BIOS BIOS BIOS BIOS BIOS BIOS BIOS BIOS BIOS BIOS 768K 784K 800K 816K 832K 848K 864K 880K 896K 960K 000C0000-000C3FFF 000C4000-000C7FFF 000C8000-000CBFFF 000CC000-000CFFFF 000D0000-000D3FFF 000D4000-000D7FFF 000D8000-000DBFFF 000DC000-000DFFFF 000E0000-000EFFFF 000F0000-000FFFFF Comment Cacheable Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl Shadow Ctrl
640K 128K 000A0000-000BFFFF Used
00100000-DRAM have hole DRAM Top-FFFEFFFF Init 4G-64K FFFEFFFF-FFFFFFFF 000Fxxxx alias
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Device Offset 5F-5A DRAM Ending Address: Offset Bank Ending (HA[31:24]) (01h) Offset Bank Ending (HA[31:24]) (01h) Offset Bank Ending (HA[31:24]) (01h) Offset Bank Ending (HA[31:24]) (01h) Offset Bank Ending (HA[31:24]) (01h) Offset Bank Ending (HA[31:24]) (01h) Offset Bank Ending (HA[31:24]) (01h). Offset Bank Ending (HA[31:24]) (01h). Note BIOS required fill ending address registers banks even memory populated. endings have incremental order. Device Offset DRAM Type (00h). DRAM Type Banks -reserved- program). default -reserved- program) SDRAM -reservedDifferent DRAM types cannot mixed. Reserved .always reads
Device Offset 59-58 DRAM Type (2222h) 15-13 Bank Type (see table below) Bank Command Rate Command .default Command 11-9 Bank Type (see table below) Bank Command Rate Command .default Command Bank Type (see table below) Bank Command Rate Command .default Command Bank Type (see table below) Bank Command Rate Command .default Command
Table Device Rx58 Type Encoding
16Mb 64/128Mb 64/128Mb 64/128Mb 256Mb 256Mb 256Mb 8-bit, 9-bit, 10-bit Column Address 8-bit Column Address .default 9-bit Column Address 10/11-bit Column Address -reserved8-bit Column Address 9-bit Column Address 10/11-bit Column Address
Table DRAM Memory Address Mapping Table
16Mb (000) 64/128Mb page page page 256/512Mb page page page 10,9,8 (14,8) (14,8) (14,9) (14,9) (14,10) (14,10) (14,11) (15,8) (15,9) (15,9) (15,10) (15,10) (15,11) (15,11) (15,12)
page
(16,10) (16,11) (16,12)
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Device Offset Shadow Control (00h) E0000h-EFFFFh Read/write disable default Write enable Read enable Read/write enable F0000h-FFFFFh Read/write disable default Write enable Read enable Read/write enable Memory Hole None default 512K-640K 15M-16M (1M) 14M-16M (2M) Disable A,BK SMRAM Direct Access Enable A,BK DRAM Access Mapping Control: Bits Code Data DRAM DRAM DRAM DRAM DRAM DRAM DRAM Non-SMM Code Data DRAM DRAM DRAM DRAM
Device Offset Shadow Control (00h).RW CC000h-CFFFFh Read/write disable.default Write enable Read enable Read/write enable C8000h-CBFFFh Read/write disable.default Write enable Read enable Read/write enable C4000h-C7FFFh Read/write disable.default Write enable Read enable Read/write enable C0000h-C3FFFh Read/write disable.default Write enable Read enable Read/write enable Device Offset Shadow Control (00h).RW DC000h-DFFFFh Read/write disable.default Write enable Read enable Read/write enable D8000h-DBFFFh Read/write disable.default Write enable Read enable Read/write enable D4000h-D7FFFh Read/write disable.default Write enable Read enable Read/write enable D0000h-D3FFFh Read/write disable.default Write enable Read enable Read/write enable
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Device Offset DRAM Clock Select (00h) Host MHz, DRAM Disable. default Enable DRAM Operating Frequency Faster Than DRAM Same Equal default DRAM Faster Than DRAM Rx54[7-6] Rx69[7] (DDR-200) (DDR-266) (DDR-333) (DDR-266) (DDR-333) (DDR-333)
Device Offset DRAM Timing Banks (E4h)RW Precharge Command Active Command Period 3T.default Active Command Precharge Command Period TRAS TRAS 7T.default Latency 1.5T 2.5T .default Reserved always reads ACTIVE .default Bank Interleave Interleave.default 2-way 4-way Reserved 16Mb DRAMs bank interleave always 2-way
(DDR-400) (DDR-400) other combinations reserved.
Device Offset DRAM Arbitration Timer (00h) Timer (units DRAM clocks) default Timer (units DRAM clocks). default Device Offset DRAM Arbitration Control (00h).RW Input Delay Setting Auto (Rx67 reads calibration result) .def Manual (Rx67 reads input delay) DRAM Access Timing .default (set this DRAM clock) Arbitration Parking Policy Park last owner .default Park Park -reserved3-0 Priority (units DRAM clocks)
DRAM Ctrlr Queue Greater Than Disable. default Enable DRAM Ctrlr Queue Equal Disable. default Enable DRAM Page Enable Disable. default Enable DRAM Page Enable Disable. default Enable DIMM Type Unbuffered default Registered Multiple Page Mode Disable. default Enable
Device Offset Strobe Input Delay (00h).RW Reserved always reads Input Delay. default Rx66[7]=0, read calibration result) Device Offset Strobe Output Delay (00h).RW Output Delay default
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Device Offset DRAM Clock Control (00h) Early Clock Select Latest default Earliest Early Clock Select SCMD, Latest default Earliest Reserved .always reads Note: Refer VT8754 BIOS Porting Guide SDRAM configuration algorithms recommended settings these bits typical memory system configurations.
Device Offset Refresh Counter (00h) Refresh Counter units DRAM clocks) DRAM Refresh Disabled .default DRAM clocks DRAM clocks DRAM clocks DRAM clocks DRAM clocks programmed value desired number 16DRAM clock units minus one. Device Offset DRAM Arbitration Control (10h).RW Fast Read Write Turn-around Disable .default Enable Page Kept Active When Cross Bank Disable .default Enable Burst Refresh Disable .default Enable Reserved Program). default HA14 HA22 Swap Normal .default Swap improve performance SDRAM Operation Mode Select Normal SDRAM Mode.default Command Enable All-Banks-Precharge Command Enable (CPU-to-DRAM cycles converted All-Banks-Precharge commands). Enable CPU-to-DRAM cycles converted commands commands driven MA[14:0]. BIOS selects appropriate host address each memory such that right commands generated MA[14:0]. Cycle Enable this code selected, CAS-before-RAS refresh used; selected, RAS-Only refresh used) Reserved Reserved
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error checking reporting only (EC) selected, read write cycles will normal timing. Partial writes (with enabled) will read-modify-write cycles maintain correct error correction codes additional data bits. disabled particular bank pair, partial writes that bank pair will byte enables write only selected bytes (using normal write cycles cycle timing). error correction (ECC) selected, first read transaction will always have additional cycle latency. Bit-7 Bits Error Checking Error Correction Device Offset Status (00h).RWC Multi-bit Error Detected write resets Multi-bit Error DRAM Bank. default=0 Encoded value bank with multi-bit error. Single-bit Error Detected write resets Single-bit Error DRAM Bank default=0 Encoded value bank with single-bit error.
Device Offset Control (00h) Mode Select Checking Reporting.default Checking, Reporting, Correcting Reserved always reads Enable SERR# Multi-Bit Error Don't assert SERR# multi-bit errors .def Assert SERR# multi-bit errors Enable SERR# Single-Bit Error Don't assert SERR# single-bit errors .def Assert SERR# single-bit errors Enable Bank (DIMM Disable banks 7/6).default Enable (ECC bit-7) Enable Bank (DIMM Disable banks 5/4).default Enable (ECC bit-7) Enable Bank (DIMM Disable banks 3/2).default Enable (ECC bit-7) Enable Bank (DIMM Disable banks 1/0).default Enable (ECC bit-7) Error checking correction enabled bank-pair bankpair (DIMM DIMM) using bits above. Bank pairs must populated with 72-bit memory enable since additional data bits must present either case. this reason, 64-bit memory populated particular bank pair, corresponding should disable both that bank pair. those bank pairs that have 72-bit memory available (and have corresponding set), either selected bit-7 above (i.e., enabled bank pairs will will ECC).
(see RxD0-4 Error Address Error Syndrome)
Table DIMM Module Configuration
Rx6E Rx55
[3-0] DIMM Module Configuration MECC [7-0] Pins [8-0] Pins DQS# [8-0] Pins
with
MECC[7-0] CKE[7-0]
CKE[7-0] DQM[7-0]
DQS[8-0]# DQS[7-0]#
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Control These registers normally programmed once system initialization time. Device Offset Buffer Control (00h).RW Post-Write Disable .default Enable Reserved always reads Master DRAM Prefetch Always prefetch .default Never prefetch Prefetch only Enhance command Reserved always reads Master Read Buffering Disable .default Enable Delay Transaction Disable .default Enable Reserved always reads Device Offset Flow Control (48h). Retry Status. retry occurred .default Retry occurred Retry Timeout Action Retry forever (record status only) Flush buffer return FFFFFFFFh reads .default Retry Count Retry Backoff Retry times, backoff .default Retry times Retry times Retry times Burst Disable Enable .default Reserved always reads Compatible Type#1 Configuration Cycles Disable (fixed AD31).default Enable IDSEL Control AD11, AD12 .default AD30, AD31 Device Offset Master Control (00h) Reserved .always reads Master 1-Wait-State Write Zero wait state TRDY# response. default wait state TRDY# response Master 1-Wait-State Read Zero wait state TRDY# response. default wait state TRDY# response WSC# Disable. default Enable Reserved .always reads Master Broken Timer Enable Disable. default Enable. Force into arbitration when there FRAME# PCICLK's after grant.
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Device Offset Arbitration (00h). Port Access access address passed default access address processed internally Reserved .always reads Master Priority Rotation Control Disable. default Grant after every master grant Grant after every master grants Grant after every master grants Setting will always granted access after current master completes, matter many masters requesting. Setting other masters requesting during current master grant, highest priority master will after current master completes, will guaranteed after that master completes. Setting other masters requesting, highest priority will next, then next highest priority will bus, then will bus. other words, with above settings, even multiple masters continuously requesting bus, guaranteed access after every master grant (01), after every other master grant (10) after every third master grant (11). Select REQn# REQ4# mapping REQ4#. default REQ0# REQ1# REQ2# Reserved .always reads REQ4# High Priority Master Disable. default Enable
Device Offset Arbitration (00h) Arbitration Mode REQ-based (arbitrate REQ#) .default Frame-based (arbitrate FRAME# assertion) Latency Timer. read only, reads Rx0D bits Reserved always reads Master Time-Out (force into arbitration after period time) Disable .default 1x16 PCICLKs 2x16 PCICLKs 3x16 PCICLKs 4x16 PCICLKs 7x16 PCICLKs
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GART Graphics Aperture Control function Graphics Address Relocation Table (GART) translate virtual 32-bit addresses issued device into 4K-page based physical addresses system memory access. this translation, upper bits (A31A12) remapped, while lower address bits (A11-A0) used unchanged. one-level fully associative lookup scheme used implement address translation. this scheme, upper bits virtual address used point entry page table located system memory. Each page table entry contains upper bits physical address "physical page" address). simplicity, each page table entry bytes. total size page table depends GART range (called "aperture size") which programmable P4X333. This scheme shown figure below. Device Offset GART/TLB Control (00h) Flush Page Disable. default Enable Reserved .always reads Note: master access Graphics Aperture range, snoop will performed. Device Offset Graphics Aperture Size (00h) Graphics Aperture Size 11111111 1111000 11111110 1110000 11111100 11000000 11111000 10000000 128M 00000000 256M (See Next Page Rx85-87)
Virtual Page Address index Base Page Table
Page Offset
Physical Page Address
Page Offset
Figure Graphics Aperture Address Translation
Since address translation using above scheme requires access system memory, on-chip cache (called "Translation Lookaside Buffer" TLB) utilized enhance performance. P4X333 contains entries. Address "misses" require access system memory retrieve translation data. Entries replaced using (Least Recently Used) algorithm. Addresses translated only accesses within "Graphics Aperture" (GA). Graphics Aperture power size from 256MB (i.e., 1MB, 2MB, 4MB, 8MB, etc). base Graphics Aperture anywhere system virtual address space address boundary determined aperture size (e.g., aperture size 4MB, base must address boundary). Graphics Aperture Base defined register offset device Graphics Aperture Size Table Base defined following register group (offsets respectively) along with various control bits.
Offset 8B-88 Translation Table Base (00000000h) 31-12 Graphics Aperture Translation Table Base. Pointer base translation table system memory used addresses aperture range (the pointer base "Directory" table). 11-2 Reserved .always reads Graphics Aperture Enable Disable. default Enable Note: disable Graphics Aperture, this bits Graphics Aperture Size enable Graphics Aperture, this program Graphics Aperture Size desired aperture size. Reserved .always reads
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CPU-to-Memory Access Control Offset CPU-to-Memory Write Policy Write Request Limit default Write Request Base. default When number outstanding write requests eqaul "limit", P4X333 will priority decreasing write requests until number pending equal "base". Offset CPU-to-Memory Bandwidth Timer Host Bandwidth Timer. default DRAM Bandwidth Timer default Offset CPU-to-Memory Bandwidth Limit Reserved always reads Bandwidth Limit Disable .default Fixed DRAM bandwidth limit Fixed bandwidth limit Dynamically toggle between DRAM bandwidth limits (two timers Rx86[74] Rx86[3-0] used) Access DRAM Read After Write Normal .default Improved
Rx85, should programmed optimum values recommended increase system performance. Rx85, Write Enabled Rx54[3]
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Control Device Offset A3-A0 Capability Identifier (0020C002h) 31-24 Reserved always reads 23-20 Major Specification Revision always reads 0010 Major spec which device conforms 19-16 Minor Specification Revision always reads 0000 Minor spec which device conforms 15-8 Pointer Next Item always reads (last item) (always reads indicate AGP) Device Offset A7-A4 Status (1F000237h) 31-24 Maximum Requests. always reads requests device manage (32) 23-10 Reserved always reads Supports SideBand Addressing always reads Reserved always reads Supported always reads Fast Write Supported always reads Reserved always reads Rate Supported always reads Rate Supported always reads Rate Supported always reads Device Offset AB-A8 Command (00000000h).RW 31-24 Request Depth (reserved target) .always reads 23-10 Reserved .always reads SideBand Addressing Enable Disable .default Enable Enable Disable .default Enable Reserved .always reads Enable Disable .default Enable Fast Write Enable Disable .default Enable Reserved .always reads Mode Enable Disable .default Enable Mode Enable Disable .default Enable Mode Enable Disable .default Enable Device Offset Control (00h). Disable Disable. default Enable Read Synchronization Disable. default Enable Read Snoop DRAM Post-Write Buffer Disable. default Enable GREQ# Priority Becomes Higher When Arbiter Parked Master Disable. default Enable Reserved .always reads Grant Parking Policy Non-Parking Grant GFRM# GPIPE# asserted, GGNT# deasserted. default Parking Grant GFRM# GPIPE# asserted, GGNT# de-asserted until GREQ# deasserted timeout Master Turnaround Cycle Timing default Timing Device Offset Miscellaneous Control (02h)RW Performance Improvement Disable. default Enable (GGNT granted earlier deasserted after PIPE asserted RxAC[1]=0). Pipe Mode Performance Improvement Disable. default Enable Input Pads Disable. default Enable Performance Improvement Disable. default Enable (connect AGPREQ qualified HBHIT) Data Phase Latency Timer. default Device Offset Miscellaneous Control (00h)RW Reserved .always reads GART Read, GART Write Coherency Disable. default Enable
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Control (continued) Device Offset Control (00h) Master GART Access Disable .default Enable Calibration Disable .default Enable Coherent Non-coherent Access Disable .default Enable Pipe Function Disable .default Enable Function (Global Enable) Disable (DBI input masked, outputs assume DBI=0) .default Enable Output Transactions Disable .default Enable Output Frame Transactions Including Fast Write Disable .default Enable Output from Frame Transactions Disable .default Enable Device Offset Control Status (8xh) Strobe VREF Control This valid only when RxA8[2] transfer mode enabled) RxA8[3] transfer mode enabled), otherwise, VREF AGPVREF. VREF STB# vice versa VREF AGPVREF (0.5 1.5V).default Strobe Drive Strength Drive strength compensation circuit default .default Drive strength controlled RxB1[7-0] Compensation Circuit Control Output.RO Compensation Circuit Control Output Device Offset Drive Strength (63h) Output Buffer Drive Strength Ctrl.def=6 Output Buffer Drive Strength Ctrl .def=3 Device Offset Drive Delay Ctrl (08h)RW GD/GDS/GDS#/GBE Control. default VDDQ=1.5V: Normal Normal VDDQ=1.5V: Normal Delayed Receive Strobe Delay delay default Delay Delay Delay GD[31:16] Output Stagger Delay delay default Delay GD[31:16] GDS, GDS# Slew Rate Control Disable Enable. default Receive Strobe Delay delay default Delay Output Delay delay default Delay Delay Delay (GDS GDS# will delayed more bit-4
Device Offset Strobe Drive Strength (63h) Strobe Output Drive Strength Ctrl .def=6 Strobe Output Drive Strength Ctrl.def=3
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V-Link Compensation Drive Control VT8235 South Bridge: Device Offset V-Link Compensation Ctrl (00h)RW V-Link Autocomp Output Value High Drive Reserved always reads V-Link Autocomp Output Value Drive. Compensation Select Auto Comp (use values bits 7-5, 3-1) default Manual Comp (use values RxB5, Device Offset V-Link Strobe Drive Ctrl (00h)RW V-Link Strobe Pullup Manual Setting (High) Reserved always reads V-Link Strobe Pulldown Manual Setting (Low) Reserved always reads Device Offset V-Link Data Drive Ctrl (00h).RW V-Link Data Pullup Manual Setting (High) Reserved always reads V-Link Data Pulldown Manual Setting (Low) Reserved always reads VT8235 South Bridge: Device Offset V-Link Compensation Ctrl (00h)RW V-Link Autocomp Output Value High Drive Reserved .always reads V-Link Autocomp Output Value Drive Compensation Select Auto Comp (use values bits 7-5, 3-1) default Manual Comp (use values RxB9, Device Offset V-Link Strobe Drive Ctrl (00h)RW V-Link Strobe Pullup Manual Setting (High) Reserved .always reads V-Link Strobe Pulldown Manual Setting (Low) Reserved .always reads Device Offset V-Link Data Drive Ctrl (00h) V-Link Data Pullup Manual Setting (High) Reserved .always reads V-Link Data Pulldown Manual Setting (Low) Reserved .always reads
VT8233 South Bridge (VT8233, 8233C, 8233A):
VT8233 South Bridge (VT8233, 8233C, 8233A): Device Offset V-Link Compensation Ctrl (00h)RW V-Link Autocomp Output Value .always reads Pullup Compensation Selection Auto Comp (use values bits 7-6) default Manual Comp (use values bits 3-2) Pulldown Compensation Selection Auto Comp (use values bits 7-6) default Manual Comp (use values bits 1-0) Pullup Compensation Manual Setting. Pulldown Compensation Manual Setting.
Device Offset V-Link Drive Control (00h).RW V-Link Strobe Pullup Manual Setting V-Link Strobe Pulldown Manual Setting Reserved always reads V-Link Slew Rate Control Disable .default Enable
Device Offset V-Link Drive Control (00h). V-Link Strobe Pullup Manual Setting V-Link Strobe Pulldown Manual Setting Reserved .always reads V-Link Slew Rate Control Disable. default Enable
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Power Management Control Device Offset Power Management Mode (00h).RW Dynamic Power Management Disable .default Enable Halt Shutdown Power Management Disable .default Enable Stop Clock Power Management Disable .default Enable Suspend Status Power Management Disable .default Enable Reserved always reads Device Offset DRAM Power Management (00h)RW DRAM Self-Refresh Mode Disable .default Enable Dynamic when DRAM Idle Disable .default Enable Dynamic DRAM Power Down (Float) Disable .default Enable Reserved always reads Device Offset Dynamic Clock Stop Control (00h)RW Host Interface Power Management Disable. default Enable DRAM Interface Power Management Disable. default Enable V-Link Interface Power Management Disable. default Enable Interface Power Management Disable. default Enable Interface Power Management Disable. default Enable Graphics Interface Power Management Disable. default Enable Reserved .always reads Host Fast Power Management (DADS Fast Timing) Disable. default Enable Device Offset DRAM Toggle Reduction (00h)RW SCMD Toggle Reduction Disable. default Enable command pins won't toggle accessed) Reserved .always reads DIMM Select default DIMM Select default DIMM Select default DIMM Select default
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Error Control Device Offset D3-D0 DRAM Error Address. Device Offset DRAM Error Syndrome
Extended Power Management Control Device Offset Power Management Capability IDRO Capability always reads Device Offset Power Management Next Pointer Next Pointer.always reads ("Null" Pointer) Device Offset Power Mgmt Capabilities Power Management Capabilities. always reads Device Offset Power Mgmt Capabilities Power Management Capabilities. always reads Device Offset Power Mgmt Control Status.RW Reserved always reads Power State .default -reserved10 -reserved11 Device Offset Power Management Status Power Management Status always reads Device Offset PCI-to-PCI Bridge Support Ext. Bridge Support Extensions. always reads Device Offset Power Management Data.RO Power Management Data. always reads
Device Offset Host Parity Status Host Address Parity Error Detected Address Parity Error Detected default Addr Parity Error Detected (write clear) Host Data Parity Error Detected Data Parity Error Detected default Data Parity Error Detected (write clear) Access Above Detected Access Detected. default Access Detected (write clear) Host Lock Cycle Detected Lock Cycle Detected default Lock Cycle Detected (write clear) Reserved .always reads Device Offset Host Parity Enable. Host Address Parity Generation Checking (AP[1:0]#) Disable. default Enable Host Data Parity Generation Checking (DP[3:0]#) Disable. default Enable Host Response Parity Generation (RSP#) Disable. default Enable Parity Error Generates SERR# Disable. default Enable (either SERR# generated depending Rx47[7-6]) Parity Test Mode Normal Parity default Invert Parity Generation Checking Reserved .always reads
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Host AGTL+ Control Device Offset Host Address (2x) Pullup Drive.RW Reserved always reads Strobe Pullup Drive (HAS#) default Reserved always reads Address Pullup Drive (HA,HREQ#) default Device Offset Host Address (2x) Pulldown DriveRW Reserved always reads Strobe Pulldown Drive (HAS#) default Reserved always reads Address Pulldown Drive (HA,HREQ#) default Device Offset Host Data (4x) Pullup Drive.RW Reserved always reads Strobe Pullup Drive (HDS,HDS#) default Reserved always reads Data Pullup Drive (HD,HDBI#) default Device Offset Host Data (4x) Pulldown Drive Reserved always reads Strobe Pulldown Drive (HDS,HDS#) default Reserved always reads Data Pulldown Drive (HD,HDBI#). default Note: Refer VT8754 BIOS Porting Guide recommended settings these bits typical system configurations. Device Offset Output Delay Stagger Control.RW Data Strobe Relative Delay Data delay strobe delay psec.default Data delay strobe delay Data delay strobe delay psec Data delay strobe delay psec HD[63:48, 31:16], HDBI[3,1]# Output Stagger delay.default nsec delay HA[31:17] Output Stagger delay.default nsec delay HDS# Output Extra Delay delay.default psec delay psec delay psec delay Output Extra Delay delay.default psec delay psec delay psec delay Device Offset AGTL+ Control (00h) AGTL+ Input Increase Delay Filter Noise Disable. default Enable AGTL+ Input Increase Delay Filter Noise Disable. default Enable AGTL+ Slew Rate Control Disable. default Enable Reserved .always reads Input Pullup Disable. default Enable AGTL+ Strobe Internal Termination Pullups Disable. default Enable AGTL+ Data Internal Termination Pullups Disable. default Enable AGTL+ Dynamic Compensation Disable. default Enable Device Offset AGTL+ Comp Status (00h) Select AutoCompensation Drive Disable. default Enable (RxD8-DB automatically on-chip based auto compensation results) AGTL+ Compensation Result default AGTL+ Function Inputs always powered default Inputs powered down when input mode Double Check Disable. default Enable (bit-1 must also (Dynamic Inversion) Function Enable. default Disable (DBI always high) Reserved .always reads Device Offset AGTL+ Auto Comp Offset (00h). AGTL+ Drive Offset Comp Result default AGTL+ Drive Offset Comp Result default
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
DRAM Above Control Device Offset Address (00h).RW Address default DRAM Granularity Total DRAM less than .default Total DRAM less than Total DRAM less than 128M Total DRAM less than 256M Total DRAM less than -reservedDevice Offset Address High (FFh).RW Address High default Device Offset APIC Decoding (01h) Reserved always reads APIC Lowest Interrupt Arbitration Disable .default Enable APIC Decoding FECxxxxx accesses .default FEC00000 FEC7FFFF accesses FEC80000 FECFFFFF accesses (Processor Message) Support Disable (master access FEExxxxx will PCI) .default Enable (master access FEExxxxx will passed host side snoop) Disable .default Enable Reserved always reads Compatible Disable Enable .default Device Offset Drive (MD,MECC,DQS,DQM)RW High Drive 0000 Lowest default 1111 Highest Drive 0000 Lowest default 1111 Highest Device Offset Drive (CS, CKE). High Drive 0000 Lowest default 1111 Highest Drive 0000 Lowest default 1111 Highest Device Offset Drive (MAA, ScmdA) High Drive 0000 Lowest default 1111 Highest Drive 0000 Lowest default 1111 Highest Device Offset Drive (MAB, ScmdB) High Drive 0000 Lowest default 1111 Highest Drive 0000 Lowest default 1111 Highest
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Device Register Descriptions
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BIOS Scratch Device Offset F3-F4 BIOS Scratch Registers hardware function default
Host Interface DRDY Timing Control Device Offset DRDY Timing Control (00h).RW Wait State default Wait State default Wait State default Wait State default Device Offset DRDY Timing Control (00h).RW Burst DRDY Wait States DRDY Burst .default DRDY Burst Reserved always reads Wait State default
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Device Register Descriptions
Device PCI-to-PCI Bridge Header Registers registers located configuration space. They should programmed using configuration mechanism through with number function number equal device number equal one. Device Offset Vendor (1106h) 15-0 Code (reads 1106h identify Technologies) Device Offset Device (B168h) 15-0 Code (reads B168h identify P4X333 PCIto-PCI Bridge device) Device Offset Command (0007h).RW 15-10 Reserved always reads Fast Back-to-Back Cycle Enable Fast back-to-back transactions only allowed same agent.default Fast back-to-back transactions allowed different agents SERR# Enable. SERR# driver disabled.default SERR# driver enabled (SERR# used report errors). Address Data Stepping Device never does stepping.default Device always does stepping Parity Error Response.RW Ignore parity errors continue.default Take normal action detected parity errors Reserved always reads Memory Write Invalidate Command masters must Write.default masters generate Write Inval Special Cycle Monitoring Does monitor special cycles.default Monitors special cycles Master Never behaves master Enable operate master primary interface behalf master secondary interface .default Memory Space.RW Does respond memory space Enable memory space access .default Space Does respond space Enable space access .default Device Offset Status (Primary Bus) (0230h).RWC Detected Parity Error .always reads Signaled System Error (SERR#).always reads Signaled Master Abort abort received default Transaction aborted master with Master-Abort (except Special Cycles). write clear Received Target Abort abort received default Transaction aborted target with TargetAbort write clear Signaled Target Abort .always reads 10-9 DEVSEL# Timing Fast Medium .always reads Slow Reserved Data Parity Error Detected .always reads Fast Back-to-Back Capable .always reads User Definable Features .always reads 66MHz Capable.always reads Supports Capability list.always reads Reserved .always reads Device Offset Revision (00h) P4X333 Chip Revision Code (00=First Silicon) Device Offset Programming Interface (00h). This register defined different ways each Base/SubClass Code value undefined this type device. Interface Identifier .always reads
Device Offset Class Code (04h). Class Code .reads indicate PCI-PCI Bridge Device Offset Base Class Code (06h). Base Class Code. reads indicate Bridge Device Device Offset Latency Timer (00h) Reserved .always reads Device Offset Header Type (01h) Header Type Code. reads PCI-PCI Bridge
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Device Offset 3F-3E PCI-to-PCI Bridge Control (0000h) 15-4 Reserved .always reads VGA-Present Forward accesses Bus. default Forward accesses Note: addresses memory A0000-BFFFFh addresses 3B0-3BBh, 3C0-3CFh 3D03DFh (10-bit decode). "Mono" text mode uses B0000-B7FFFh "Color" Text Mode uses B8000BFFFFh. Graphics modes Axxxxh. Mono uses addresses 3Bx-3Cxh Color uses 3Cx-3Dxh. present, will 3Bxh addresses B0000-B7FFFh memory space; not, will those addresses emulate modes. Block Forward Addresses Forward accesses they range defined Base Limit registers (device offset 1C1D) default forward accesses that 100-3FFh address range even they range defined Base Limit registers. Reserved .always reads
Device Offset Primary Number (00h).RW Primary Number default This register read write, internally chip always uses primary. Device Offset Secondary Number (00h) Secondary Number. default Note: must these bits convert Type Type Device Offset Subordinate Number (00h) Primary Number default Note: must these bits decide Type Type command passing allowed. Device Offset Secondary Latency Timer (00h) Reserved always reads Device Offset Base (F0h).RW Base AD[15:12]. default 1111b Addressing Capability default Device Offset Limit (00h).RW Limit AD[15:12] default Addressing Capability default Device Offset 1F-1E Secondary Status.RO 15-0 Secondary Status Rx44[4] these bits read back 0000h Rx44[4] these bits read back same Rx7-6 Device Offset 21-20 Memory Base (FFF0h).RW 15-4 Memory Base AD[31:20] .default FFFh Reserved always reads Device Offset 23-22 Memory Limit (Inclusive) (0000h) 15-4 Memory Limit AD[31:20] default Reserved always reads Device Offset 25-24 Prefetchable Base (FFF0h) 15-4 Prefetchable Memory Base AD[31:20]default FFFh Reserved always reads Device Offset 27-26 Prefetchable Memory Limit (0000h) 15-4 Prefetchable Memory Limit AD[31:20] default Reserved always reads Device Offset Capability Pointer (80h) Contains offset from start configuration space. Capability List Pointer. always reads
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Device PCI-to-PCI Bridge Device-Specific Registers Control Device Offset CPU-to-AGP Flow Control (00h) CPU-AGP Post Write Disable .default Enable Reserved always reads CPU-AGP Wait State Burst Write Disable .default Enable Read Prefetch Control Always prefetch .default Never prefetch Prefetch only Enhance command Present Forward accesses .default Forward accesses Note: Forward despite Memory Base Limit Note: (Monochrome Display Adapter) addresses memory addresses B0000h-B7FFFh addresses 3B4-3B5h, 3B8-3BAh, 3BFh (10-bit decode). 3BC-3BE reserved printers. Note: Rx3E bit-3 this don't care (MDA accesses forwarded bus). Master Read Caching Disable .default Enable Delay Transaction Disable .default Enable Device Offset CPU-to-AGP Flow Control (08h) Retry Status retry occurred. default Retry Occurred .write clear Retry Timeout Action action taken except record status Flush buffer write return read Retry Count Retry backoff default Retry backoff Retry backoff Retry backoff CPU-to-AGP Bursting Timeout Disable Enable. default Reserved .always reads CPU-to-PCI/AGP Cycles Invalidate PCI/AGP Buffered Read Data Disable. default Enable Reserved .always reads Device Offset Master Control (00h) Reserved (Must Programmed When this set, P4X333 will automatically resolve problem master cycles being blocked Master Cycles. Master Wait State Write Disable. default Enable Master Wait State Read Disable. default Enable Break Consecutive Master Accesses Disable. default Enable Reserved .always reads Claim Memory Read Cycles Disable. default Enable Claim Local APIC FEEx xxxx Cycles Disable. default Enable Snoop Write Enable Rate, Support Host Side Snoop Cycles Rate Disable. default Enable
Table VGA/MDA Memory/IO Redirection
3E[3] 40[2] Pres. Pres. Axxxx, B8xxx Access B0000 -B7FFF Access 3Cx,
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Device Offset Fast Write Control (72h) Force Fast Write Cycle Aligned Rx45[6] Disable. default Enable Merge Multiple Transactions Into Fast Write Burst Transaction Disable Enable. default Merge Multiple Write Cycles Memory Offset 23-20 Into Fast Write Burst Cycles Rx45[6] Disable Enable. default Merge Multiple Write Cycles Prefetchable Memory Offset 27-24 Into Fast Write Burst Cycles Rx45[6] Disable Enable. default Reserved .always reads Fast Write Burst Slave Flow Control) Disable. default Enable Fast Write Fast Back Back Disable Enable. default Fast Write Initial Block Wait State Disable. default Enable Rx45 Write Write Bits Address Address Mem1 Mem2 x1xx 0000 x010 0010 x010 x001 x001 0001 x011 x011 x011 1000 1010 1001
Device Offset Master Latency Timer (22h) Host Time slot Disable timer) GCLKs GCLKs .default GCLKs Master Time Slot Disable timer) GCLKs GCLKs .default GCLKs
Fast Write Cycle Alignment aligned, burstable aligned, nonburstable aligned, non-burstable aligned, burstable aligned, burstable aligned, non-burstable aligned, burstable aligned, burstable aligned, non-burstable aligned, non-burstable aligned, non-burstable
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
Power Management Device Offset Capability (01h) Capability .always reads Device Offset Next Pointer (00h) Next Pointer: Null .always reads
Control (continued) Device Offset 47-46 PCI-to-PCI Bridge Device ID.RW 15-0 PCI-to-PCI Bridge Device default 0000
Device Offset PCI2 Error Reporting Cycle Data Parity Error.WC Parity Error occur.default Parity error occurred .write clear GSERR Error.WC Parity Error occur.default Parity error occurred .write clear Reserved always reads Generate Parity Error Data Parity Error Disable .default Enable Reserved always reads Generate Parity Error Data Parity Error Disable .default Enable Generate Parity Error Address Parity Error
Device Offset Power Mgmt Capabilities (02h) Power Mgmt Capabilities .always reads Device Offset Power Mgmt Capabilities (00h) Power Mgmt Capabilities .always reads Device Offset Power Mgmt Ctrl/Status (00h). Reserved .always reads Power State default -reserved10 -reserved11 Device Offset Power Mgmt Status (00h). Power Mgmt Status default Device Offset Support Extensions (00h) Bridge Support Extensions default Device Offset Power Management Data (00h) Power Management Data default
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Device Register Descriptions
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Chipset VT8754 Pentium V-Link North Bridge
FUNCTIONAL DESCRIPTION
Configuration Strapping
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Functional Description
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Chipset VT8754 Pentium V-Link North Bridge
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Table Absolute Maximum Ratings
Symbol
VOUT
Parameter
Case Operating Temperature Storage Temperature Input Voltage Output Voltage
-0.5 -0.5
VRAIL VRAIL
Unit
Volts Volts
Notes
Note Stress above conditions listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions. Note VRAIL defined level respective rail. interface 2.5V. Memory 2.5V. 1.5V transfer mode) 0.8V transfer mode).
Characteristics
0-85oC, VRAIL ±5%, VCORE 2.5V ±5%,
Table Characteristics
Symbol
Parameter
Input Voltage Input High Voltage Output Voltage Output High Voltage Input Leakage Current Tristate Leakage Current
-0.50
0.55
Unit
Condition
-1.0 0.55 <VOUT
Drive strength selected output pins programmable. Device RxB0[6], D8-DB, E8-EB straps VAD4-5 details.
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Electrical Specifications
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Power Characteristics
0-85oC, VRAIL VCORE 2.5V GND=0V
Table Power Characteristics Internal Interface Digital Logic
Symbol
ITTPOS ITTSTR ITTSOF ICCG ICCGPOS ICCGSTR ICCGSOF ICCV ICCVPOS ICCVSTR ICCVSOF ICCM ICCMPOS ICCMSTR ICCMSOF ICC25 ICC25POS ICC25STR ICC25SOF ISUS25 ISUS25POS ISUS25STR ISUS25SOF ICCQQ
Parameter
Power Supply Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current VCCAGP Power Supply Current VCCAGP Power Supply Current VCCAGP Power Supply Current VCCAGP Power Supply Current VCCVL Power Supply Current VCCVL Power Supply Current VCCVL Power Supply Current VCCVL Power Supply Current VCCMEM Power Supply Current VCCMEM Power Supply Current VCCMEM Power Supply Current VCCMEM Power Supply Current VCC25 Power Supply Current VCC25 Power Supply Current VCC25 Power Supply Current VCC25 Power Supply Current VSUS25 Power Supply Current VSUS25 Power Supply Current VSUS25 Power Supply Current VSUS25 Power Supply Current VCCQQ Power Dissipation
Unit
Condition
Full-On Operation Soft-Off Full-On Operation Soft-Off Full-On Operation Soft-Off Full-On Operation Soft-Off Full-On Operation Soft-Off Full-On Operation Soft-Off operating frequency operating frequency
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Electrical Specifications
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Chipset VT8754 Pentium V-Link North Bridge
Table Power Characteristics Analog Reference Voltages
Symbol
ICCGTL ICCHAREF ICCHDREF ICCHCREF ICCMREF ICCGREF ICCVLREF ICCHCK ICCMCK ICCMDLL
Parameter
Power Supply Current GTLVREF Power Supply Current HAVREF Power Supply Current HDVREF Power Supply Current HCMPVREF Power Supply Current MEMVREF Power Supply Current AGPVREF Power Supply Current VLVREF Power Supply Current VCCHCK Power Supply Current VCCMCK Power Supply Current VCCMDLL
Unit
Condition
operating frequency operating frequency operating frequency operating frequency operating frequency operating frequency operating frequency operating frequency operating frequency operating frequency
Timing Specifications
timing specifications provided based external zero-pf capacitance load. Min/max cases based following table:
Table Timing Conditions
Parameter
2.5V Power (Internal Logic) 1.5V Power (VCCQQ transfer mode) 0.8V Power (VCCQQ transfer mode) Case Temperature
2.375 1.425 0.76
2.625 1.575 0.84
Unit
Volts Volts Volts
Drive strength selected output pins programmable effect timing specifications. Device RxB0[6], D8-DB, E8-EB straps VAD4-5 details.
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Electrical Specifications
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Chipset VT8754 Pentium V-Link North Bridge
MECHANICAL SPECIFICATIONS
30.00 REF. 4.00 (4X)
1.00 (3X) REF.
HEAT SLUG 22.0 24.5 0.30
Chipset Name
30.00 REF.
P4X333
VT8754 NJC0AA YYWW LLLLLLL.XX TAIWAN
Trace Code Date Code, Code.Wafer Country Assembly
Chip Part Number (optional this marked chip, chipset name should used unique part identification)
0.10 0.30 0.50 0.70 (858X)
CORNER
1.00
JEDEC Spec MO-151
35.00 ±0.20
33.00
1.00 33.00
0.20 (4X)
35.00 ±0.20
1.17 REF.
0.15
0.15
0.56 REF.
SEATING PLANE
0.40 0.60
2.23 ±0.13
Figure Mechanical Specifications HSBGA-858 Ball Grid Array Package with Heat Spreader
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0.15
HSBGA-858 Ball Grid Array with Heat Spreader 2.23 with 1.00 Ball Pitch
Mechanical Specifications
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