Dual UART with 1284 Parallel Port Plug-and-Play Controller June 1
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XR16C872
Dual UART with 1284 Parallel Port Plug-and-Play Controller
June 1999-1
FEATURES Plug Play Specification Compliant Auto Configuration Direct Connection, Needing External Buffers Resource Data External EEPROM 10-Interrupts IRQ3-7, IRQ9-12, IRQ15 Manual Configuration Standard COM1-COM-4 LPT1-LPT2 IEEE 1284 Compliant Bidirectional Host Port Level-II Electrical Interface, Needing External Transceivers Standard Centronics/ECP/EPP Mode 16-byte FIFO mode Dual UART Software Compatible with 16C550 128-Byte Transmit Receiver FIFOs Reduce Interrupt FIFO Counters Transmitter Receiver Automatic RTS/CTS Flow Control with Hysteresis Increase Data Throughput DESCRIPTION XR16C8721 (872) dual universal asynchronous receiver transmitter (UART) with 1284 bi-directional parallel port Plug-and-Play (PnP) interface. interface supports auto configuration desktop embedded computers. host interface also configured manually support standard addresses COM1-4 LPT1-2. parallel port compatible IEEE 1284 specification supports Compatible Centronics, Extended Capability (ECP) Enhanced Parallel Port (EPP) protocols. UARTs software compatible industry standard 16C550 include enhanced features bytes transmit receive FIFOs, programmable transmit receive FIFO trigger levels, transmit receive FIFO counters, IrDA (Infrared ORDERING INFORMATION
Part Number XR16C872CQ XR16C872IQ Package Operating Temperature 100-Lead 100-Lead -40°
IrDA Infrared Pulse Shaping Encoder/Decoder 115.2Kbps Data Rate 460.8 Kbps Standard Serial Data Rate +3.3V Operation 100-pin Quad Flat Package (14x20mm) Reference Card Design Available Windows2 NT4.0 Device Drivers Available
APPLICATIONS Multi-function PC/ISA Card with RS-232/ RS-422/RS-485 Interface Printer/parallel Port Embedded Systems Portable Infrared Wireless Systems High-speed Bidirectional Parallel Port High-speed Serial Ports
Data Association) encoder/decoder, automatic RTS/ hardware flow control with selectable hysteresis, automatic software (Xon/Xoff) flow control. board status registers provide interrupt priorities, receive data errors modem status. Each channel programmable baud rate generator provide data rates 460.8Kbps. bi-directional parallel port configured general purpose input/output interface connected printer portable storage devices. operates single +3.3 power supply. available small 100-pin package offers commercial industrial temperature ranges. chip fabricated advanced CMOS process reduce power consumption.
Notes: Covered U.S. patent number 5,649,122 patent pending. Windows trademark Microsoft Corp.
Rev. P1.00
EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017 www@exar.com
XR16C872
UART Channel Internal Transmit FIFO (128 bytes) Transmit Shift Register IrDA v1.0 Encoder Receive Shift Register IrDA v1.0 Decoder DTRA# RTSA# MAN# Baud Rate Gen. Modem Interface DSRA# CTSA# CDA# RIA# TXB, RXB, DTR#, RTS#, etc. PD0-PD7 RESET 7.3728 XTAL1 (22.1184 MHz) XTAL2 Divide 1284 Bi-directional Parallel Port Controller with Level Electrical Interface INIT# STROBE# SELCTIN# AUTOFD# PDIR SELECT BUSY ACK# ERR#
D0-D7 A0-A15 IOR# IOW# IOCHRDY IRQ3-7,9-12,15 DREQ0,1,3,5 DACK0,1,3,5# Plug-and-Play Controller
UART Control Registers
Receive FIFO (128 bytes)
Serial Port Transceivers
External EEPROM
EECLK EECS
EEPROM Controller
UART Channel (same channel block)
Serial Port Transceivers
Parallel Port Printer
Osc./ Buffer
Figure Functional Block Diagram with Plug-and-Play Interface
Rev. P1.00
XR16C872
UART Channel Internal Transmit FIFO (128 bytes) Transmit Shift Register IrDA v1.0 Encoder Receive Shift Register IrDA v1.0 Decoder DTRA# RTSA# DSRA# CTSA# CDA# RIA# TXB, RXB, DTR#, RTS#, etc. Serial Port Transceivers
D0-D7 A0-A10 IOR# IOW# IOCHRDY IRQ3 IRQ4 IRQ5 IRQ7 DREQ3 DACK3# MAN#
Interface Controller
UART Control Registers
Receive FIFO (128 bytes)
Serial Port Transceivers
Modem Interface Baud Rate Gen.
Hardwired Jumpers Address Decoder COM1-4 LP1-2
UART Channel (same channel block)
PD0-PD7 RESET 7.3728 XTAL1 (22.1184 MHz) XTAL2 Divide 1284 Bi-directional Parallel Port Controller with Level Electrical Interface INIT# STROBE# SELCTIN# AUTOFD# PDIR SELECT BUSY ACK# ERR#
Osc./ Buffer
Parallel Printer Port
Figure Functional Block Diagram with Manual Configuration Interface.
Rev. P1.00
XR16C872
DREQ1 DREQ3 DREQ5 EECLK XTAL1 XTAL2 MAN# EECS RIA#
DSRA#
DSRB#
DTRA#
DTRB#
CTSA#
RTSA#
CTSB#
RTSB#
CDA#
CDB#
ERR#
DREQ0 DACK5# DACK3# DACK1# DACK0# IRQ15 IRQ12 IRQ11 IRQ10 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IOR#
ACK#
RIB#
BUSY SELECT STROBE# AUTOFD# INIT# SELCTIN# PDIR
XR16C872
IOW#
IOCHRDY
RESET
A12/S4
A13/S3
A14/S2
100-Pin (14X20x3 1.95 form) Package Description (Top View)
Rev. P1.00
A11/LPT
A15/S1
DESCRIPTION
XR16C872
Signal Type Definition. following signal type definitions from device point view. Standard input Standard active output OT24 Tri-state output IOP14 Tri-state bi-directional input/output IO24 Tri-state bi-directional input/output
Symbol
Type
Description
HOST INTERFACE A0-A15 2-15 Address. 16-bits used during auto configuration sequence with external EEPROM providing resource data. manual configuration mode A0-A10 used decoding COM1-4 LPT1-2 addresses. After auto manual configuration, bits A0-A2 select UART internal registers A3-A10 used select UART 1284 printer port. Data Bus. These eight three state data lines transferring data from controlling CPU. least significant first data transmit receive serial data stream. Address Enable. Active high validate A0-A15 address lines during Direct Memory Access operation bus. Connect logic when used. Read Strobe. logic transition this will request contents Internal register defined address bits A0-A2 either UART channels A0-A1 printer port, place onto D0-D7 data read cycle CPU. Write Strobe. logic transition this will transfer data data (D0-D7), defined either address bits A0-A2 UART channels A0-A1 printer port, into internal register during write cycle from CPU. Interrupt Request Lines. These three state active high interrupt lines controlling when interrupt request generated UART channel 1284 printer port.
D0-D7
30-21
IO24
IOR#
IOW#
IRQ15 IRQ12-10 IRQ9 IRQ3-7 DREQ5 DREQ3 DREQ1 DREQ0 DACK5# DACK3# DACK1# DACK0#
87-89 92-96
OT24
OT24
Request Channel 0,1,3 These three state active high outputs with internal weak pull down resistor. request used 1284 parallel port during FIFO mode.
Acknowledge Channel 0,1,3 These active inputs used 1284 parallel port during FIFO mode.
Rev. P1.00
XR16C872
DESCRIPTION (CONT'D)
Symbol IOCHRDY Type OT24
Description Input/Output Channel Ready. IOCHRDY three-state active high output with internal weak pull-up resistor. This goes when 1284 parallel port requires additional clock during read write cycle. Terminal Count. active high input during cycle when DACK# indicate data transfer complete. System Reset. Reset active high input. 40ns minimum pulse will reset internal registers outputs default state. output logic input internally held logic during reset. XR16C872 Reset Conditions details. Crystal Oscillator Input. 22.1184 crystal must connected this input XTAL2 form internal oscillator circuit which provides main clock baud rate generators. external clock same frequency used instead. Crystal Oscillator Output. other side crystal connected this form internal crystal oscillator. bi-directional serial data external 93C46 EEPROM. EECLK 500KHz clock output external EEPROM serial data timing reference. EEPROM Chip Select. EECS active high output external EEPROM. During Manual configuration mode, logic input will bypass internal divide-by-3 clock circuit UARTs. Manual Configuration Select. MAN# active input that enables S1-S5 selection COM1-4 LPT1-2 embedded applications. Parallel Data Bus. PD0-PD7 three-state bi-directional data lines parallel port. least significant with being most significant bit. PD0-PD7 high current drive outputs connect printer/parallel connector without external buffers. Acknowledge. ACK# active input with with internal weak pull-up. general purpose input line printer acknowledge signal. logic from parallel/printer indicates successful data transfer print buffer. AutoLineFeed. AUTOFD# active tri-state with internal weak pullup. general purpose automatic line feed. When this signal printer should automatically line feed after each printed line.
RESET
XTAL1
XTAL2
EECLK
Bidir
EECS
Bidir
MAN#
1284 CONTROLLER INTERFACE PD7-PD0 32-34 IOP14 37-41
ACK#
IP24
AUTOFD#
IOP14
Rev. P1.00
DESCRIPTION (CONT'D)
Symbol PDIR Type Description
XR16C872
Parallel Port Direction Indicator. PDIR indicates operating direction parallel port. output logic indicates parallel port operating output port logic indicates input port. BUSY active high printer busy indicator general purpose input. Generally, used input from printer logic indicates ready. input internal weak pull-up resistor. ERR# printer error indicator general purpose input. Generally, used input from printer logic indicates error condition. input weak internal pull-up resistor. INIT# printer initialization signal general purpose output. Generally, used with printer (active low) system initialization reset. tri-state output internal weak pull-up resistor. signal from printer indicating paper empty condition general purpose input. Generally, used with printer logic indicates printer paper. This input internal weak pull-up resistor. SELECT printer select status indicator host general purpose input. Normally this connected printer output logic indicates ready status printer, i.e., on-line and/or on-line ready condiftion. This internal weak pull-up resistor. SELCTIN# select signal printer general purpose pin. This read bit-3 printer command register, written bit-3 printer control register. Normally this signal connected printer select printer with active signal. tri-state output internal weak pull-up resistor. STROBE# data strobe output general purpose pin. Normally this output connected printer indicates that valid data available data (PD0-PD7). tri-state output with intenal weak pull-up resistor.
BUSY
IP24
ERR#
IP24
INIT#
IOP14
IP24
SELECT
IP24
SELCTIN#
IOP14
STROBE#
IOP14
MODEM SERIAL PORT INTERFACE RXA, 63,53 Receive Data A/B. Serial receive data pulses input UART channel signal UART should logic state during reset, idle data) sleep mode. During local loop-back mode, input pins disabled data internally connected UART Inputs. mode, this input normally logic Transmit Data A/B. Serial transmit data pulses output from channel normal output logic serial data during reset, idle data), sleep mode, when transmitter disabled. During local loopback mode, output held logic 1and internally connects input. mode, output changes logic after enabled (MCR 5=1).
TXA,
64,54
Rev. P1.00
XR16C872
DESCRIPTION (CONT'D)
Symbol DTRA#, DTRB# Type
Description Data Terminal Ready general purpose output. DTRA/B# active associated with UARTchannel logic indicates that UART ready. This controlled register channel A/B. Setting bit-0 logic puts output logic This will logic after writing logic bit-0. This effect UART transmitter receiver. Request Send general purpose output. RTSA/B# active outputs associated with UART channels A/B. Writing logic bit-1sets logic requests remote unit send data. After reset this logic When auto flow control enabled (EFR bit-6=1), logic asks remote modem send data logic requests suspend. user must assert RTS# after enabling auto flow control. Clear Send general purpose input. CTSA/B# active inputs associated with UART channels logic indicates remote modem ready data. level change this input will generate status change interrupt (MSR bit-0). When auto flow control enabled, logic suspends local data transmission logic restarts local transmitter. Data Read general purpose input. DSRA/B# active inputs associated with UARTchannel logic indicates modem ready data exchange with UART. logic level change this input will generate status change interrupt (MSR bit-1).This effect UART's transmit receive operation. Carrier Detect general purpose input. CDA/B# active inputs associated with UART channels logic this indicates carrier signal been detected modem. logic level change this input will generate status change interrupt (MSR bit-3). This effect UART's transmit receive operation. Ring Indicator general purpose input. RIA/B# active inputs associated with UART channels logic indicates modem received ringing signal from telephone line. logic transition this input will generate status change interrupt (MSR bit-2). This effect UART's transmit receive operation. Volts power supply.
RTSA#, RTSB#
CTSA#, CTSB#
DSRA#, DSRB#
CDA#, CDB#
RIA#, RIB#
25,35,42 62,90 16,26,36,43
Signal ground.
61,77,98
Rev. P1.00
XR16C872
ELECTRICAL CHARACTERISTICS TA=0° (-40° +85°C package), Vcc=3.3 unless otherwise specified.
Symbol Parameter Limits -0.5 -0.5 Limits Units Conditions
VILCK VIHCK ICAP
Clock input level Clock input high level Input level Input high level Output level type outputs Output level type OT24 outputs Output level type IO14 outputs Output level type I024 outputs Output level type outputs Output level type OT24 outputs Output level type IO14 outputs Output level type I024 outputs Output high level type outputs Output high level type OT24 outputs Output high level type IO14 outputs Output high level type I024 outputs Output high level type outputs Output high level type OT24 outputs Output high level type IO14 outputs Output high level type I024 outputs Input leakage Clock leakage Input capacitance Internal pull up/down resistance Supply current
ohms
IOL= 24mA IOL= IOL= IOL= IOH= IOH= IOH= IOH= IOH= IOH=
typ.
Rev. P1.00
XR16C872
HOST INTERFACE UART ELECTRICAL CHARACTERISTICS 70°C (-40° +85°C Industrial grade packages), Vcc=3.3 unless otherwise specified.
Symbol Parameter Limits 16-1 16-1 Limits Units Conditions
T1CW T2FQ T3AS T4AH T5RD T6DY T7DA T8DH T9WR T10DS T11DH T12D T13D T14D T15D T16D T17D T18D T19D TRST
Clock pulse duration Oscillator/Clock frequency Address setup time Address hold time IOR# strobe width Read/Write cycle delay Delay from IOR# data Data disable time IOW# strobe width Data setup time Data hold time Delay from IOW# modem output Delay from modem input interrupt Delay from IOR# reset interrupt Delay from stop interrupt Delay from IOR# reset interrupt Delay from stop interrupt Delay from reset transmit start Delay from IOW# reset interrupt Reset pulse width Baud rate divisor
Rclk Rclk Rclk
load load load load
Rev. P1.00
XR16C872
1284 CONTROLLER ELECTRICAL CHARACTERISTICS TA=0° 70°C (-40° +85°C Industrial grade packages), Vcc=3.3 unless otherwise specified.
Symbol
Parameter
Limits
Limits
Units
Conditions
PD7-PD0, STROBE#, AUTOFD#, INIT, SLCTIN# delay from IOW# inactive Interrupt delay from ACK# Interrupt pre-charge pulse release pulse width active DRQx inactive DRQx active DACKx# active DRQx inactive delay from DACKx# active PD7-PD0 setup STROBE# active STROBE# width PD7-PD0 hold from STROBE# inactive PD7-PD0 hold from BUSY inactive STROBE# active BUSY active (handshake) BUSY inactive STROBE# active (cycle delay) PD7-PD0, AUTOFD# setup STROBE# active PD7-PD0, AUTOFD# hold from BUSY active STROBE# inactive BUSY inactive BUSY inactive #STROBE active #STROBE active BUSY active BUSY active #STROBE inactive PD7-PD0, BUSY setup ACK# active PD7-PD0 data hold from AUTOFD# active ACK# inactive AUTOFD# active AUTOFD# active ACK# active ACK# active AUTOFD# inactive AUTOFD# inactive ACK# inactive Host address setup IOW# active Host address hold from IOW# active Host data setup IOW# active Host data hold from IOW# active IOW# active IOCHRDY IOCHRDY high Host terminate (IOW# inactive)
Rev. P1.00
XR16C872
1284 CONTROLLER ELECTRICAL CHARACTERISTICS (CONT'D)
Symbol Parameter Limits Limits Units Conditions
IOW# inactive Host command active (IOW# IOR#) IOCHRDY pre-charge width release Host address setup IOR# active Host address hold from IOR# active Host data setup IOR# inactive Host data hold from IOR# inactive IOR# active IOCHRDY IOCHRDY high Host terminate (IOR# inactive) IOR# inactive Host command active (IOW# IOR#)
ABSOLUTE MAXIMUM RATINGS
Supply range Voltage
-0.5 -0.5 VCC+0.5V -40°C +85°C -65°C +150°
Operating temperature Storage temperature
Rev. P1.00
theta-jc
Package dissipation (100-PQFP) thermal resistance: theta-ja
°C/Watt °C/Watt
FUNCTION DESCRIPTION XR16C872 (872) highly integrated chip combining functionality XR16C850 enhanced UART, IEEE 1284 bi-directional printer interface, PC/ISA Plug-and-Play (PnP) interface. interface meets Plug-and-Play Specification Version 1.0a 5,1994. interface 1284 printer port both clocked maximum performance external crystal oscillator 22.1184 MHz. This clock then internally divided three obtain 7.3728 clock UARTs. Interface Options data interface modes, manual. mode, chip will interface directly automatically configure each UART the1284 parallel port address interrupt. Figure depicts block diagram interface. Plug-and-Play Mode interface supports industry standard jumperless auto configuration procedure PC/ISA system. With external EEPROM chip providing resource data each logical devices, automatically negotiates with Windows© operating system configures operating setting each device. host system identifies configures each device using defined registers accessed through three 8-bit ports. interfaces host system respond these same ports, after first sending initiation order enable interfaces, each interface then isolated through Isolation Protocol. Even though interfaces initially respond Isolation Protocol, protocol accomplished such that contention will occur. After given interface been isolated then assigned unique Card Select Number (CSN) that there after interface uniquely addressed.
XR16C872
interfaces support defined readable resource data structure that completely describes total resources required options supported interface. Resource requirements each interface broken down into groupings called Logical Devices, each which thought separate device. UART 1284 parallel data port referred logical device, total three logical devices. When resource requirements entire system known, process resource arbitration invoked host system under Windows operating system determine resources allocate each device. Finally, each device's resource usage programmed through configuration registers. Some these configuration registers common logical devices bulk registers accessed separately each logical device interface, with each particular logical device's configuration registers being mapped into register time. After configuration complete, each interface removed from configuration mode order prevent accidental erasure modification interface's configuration. re-enable configuration mode, initiation must re-issued. uses 16bit address lines (A0-A15) address decoding supports IRQ's (IRQ3-7, 9-12 15). Application note #xxxx describes operation interface more detail.
Rev. P1.00
XR16C872
Manual Configuration Mode Interface
provides input (MAN#) bypass auto configuration procedure. changes address lines A12-A15 manual configuration inputs S1-S4 LPT. These inputs designed with external jumpers select COM1-COM4 serial ports, LPT1 LPT2 1284 printer port. Manual configuration mode supports standard port addresses associated IRQ. However, address lines mapped other memory space areas embedded applications, more this later. eliminates external address decoding logic circuitry that typically required. manual configuration selected making MAN# logic (GND). This changes five address lines become configuration inputs. manual configuration accomplished decoding address bits, through inside chip select. These addresses select UART standard ports: COM-1, COM-2, COM-3, COM-4 LPT-1 LPT-2. Five inputs (S1-S5)
generally externally jumper wired logic logic operating port. configuration inputs also associated with given interrupt. mapping port their associated interrupt selections listed Table Besides port addresses, also decodes parallel printer addresses. chip mapped into embedded system memory space. Figure shows example wiring S1-S5 default port configuration with IRQA IRQB UARTs, IRQC with DREQ, DACK parallel port. Address lines A3-A10 connected embedded system address lines A8A15 instead, mapping address location 0x7F087F0F, 0x5F00-5F08, 0x6F00-6F08 respectively. Application note #xxxx describes design with manual configuration mode more detail.
MAN#
A3-A9 3F8-3FF 2F8-2FF 3E8-3EF 2E8-2EF 3F8-3FF 2F8-2FF 3E8-3EF 2E8-2EF 378-37F 278-27F
Port COM-1 COM-2 COM-3 COM-4 COM-1 COM-2 COM-3 COM-4 LPT-1 LPT-2
IRQ4 IRQ3 IRQ4 IRQ3 IRQ4 IRQ3 IRQ4 IRQ3 IRQ7 IRQ5
Device Selected UART Channel UART Channel UART Channel UART Channel UART Channel UART Channel UART Channel UART Channel 1284 Parallel Port 1284 Parallel Port
don't care
Table Manual Configuration Mode Internal Addess Decode
Rev. P1.00
XR16C872
D0-D7 A0-A2
30-21 5-12 AEN# IRQ3 IRQ4 A0-A2
A8-A15
IOR# IOW# IOCHRDY IRQB (UART-B)
A3-A10
UART-A
IRQA (UART-A) IRQC (1284 Port)
UART-B XR16C872
IRQ7
DREQ (1284 Port)
DREQ3
1284 Parallel Port
DACK# (1284 Port)
DACK3#
MAN#
Port Configuration Logic
Mapped with Address A8-A15: UART-A 0x7F00-7F08 IRQA UART-B 0x5F00-6F08 IRQB 1284 Port 0x6F00-6F08 with IRQC, DREQ DACK#
Figure Manual Configuration Interface Embedded Application
Rev. P1.00
XR16C872
UART
UART Internal Registers Each UART internal registers monitoring control. These resisters summarized Table below. Twelve registers compatible those already standard 16C550. These registers function data holding registers (THR/RHR), interrupt status control registers (IER/ISR), FIFO control register (FCR), line control register line status register, (LCR/LSR), modem control status registers (MCR/MSR), programmable baud rate control registers (DLL/DLM), user defined scratch register (SPR). Beyond basic 16C550 features capabilities, UART offers enhanced feature register called TRG, FCTR, EFR, Xon1/2, Xoff1/2, EMSR, TXCNT,RXCNT, DID, Register functions fully described following paragraphs.
UARTs software compatible with industry standard 16C550 power reset. Each UART offers enhancements that enabled through Enhanced Features Registers. These features include transmit receive FIFOs bytes, programmable transmit receive FIFO trigger level from 128, baud rates with clock pre-scaler, automatic flow control level with trigger hysteresis, automatic flow control, automatic software flow control, modem general interface control, infrared IrDA encoder/decoder select with software option inverting decoder input logic level, sleep mode, device revision. baud rate generator input clock both UARTs supplied 7.3728 clock. This clock comes from internal divided circuit that crystal oscillator external clock input 22.1184 MHz. Hence, maximum operating data rate 460.8 Kbps. Each UART provides bytes transmit receive FIFO memory instead 16C550. larger FIFO greatly reduces bandwidth requirement controlling CPU, increases system performance without increasing speed CPU, reduces overall power consumption. byte FIFOs also simplify software manipulation flash memory data transfer where data page size bytes. Increased performance realized larger transmit receive FIFOs, FIFO counters, programmable FIFO trigger level. This allows processor handle more networking tasks within given time. example, 16C550 with byte receive FIFO, will require 1.39 milliseconds unload FIFO (This example uses character length bits, including start/stop bits 115.2Kbps, [1/115200]x10x16). This means external will have service receive FIFO every 1.39 milliseconds. However with byte FIFO UART, data buffer will require unloading/loading 11.12 milliseconds. This increases service interval giving additional time other applications reducing overall UART interrupt servicing time. addition, FIFO counters programmable FIFO trigger level interrupt uniquely provided maximum data throughput performance especially when operating multi-channel environment.
Rev. P1.00
XR16C872
Read Mode
Write Mode
Basic Registers (THR/RHR, FCR, IER/ISR, MCR/MSR, LCR/LSR, SPR/FCNT), accessible only when bit-7 logic Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register FIFO Counter (with FCTR bit-6=1) Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register
Baud Rate Registers (DLL, DLM), accessible only when bit-7 logic Divisor Latch Device Revision (see text) Divisor Latch Device Identification (see text) Divisor Latch Divisor Latch
Enhanced Registers (TRG, FCTR, EFR, Xon/Xoff 1-2), accessible only when 0xBF. FIFO Trigger Register Feature Control Register Enhanced Feature Register Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word FIFO trigger counter Feature Control Register Enhanced Feature Register Xon-1 Word Xon-2 Word Xoff-1 Word Xoff-2 Word
Enhanced Mode Select Register (EMSR), accessible only when FCTR bit-6 logic -Enhanced Mode Select Register
Table Internal Registers
Rev. P1.00
XR16C872
FIFO Operation
Hardware (RTS/CTS) Flow Control Operation Automatic hardware flow control used prevent data overrun local receiver FIFO remote receiver FIFO. RTS# output used request remote unit suspend/restart data transmission while CTS# input monitored suspend/restart local transmitter. auto auto flow control features individually selected specific application requirements enabled through bit-6 auto function must started asserting RTS# (MCR bit-1=1) after enabled.
byte transmit receive data FIFOs enabled FIFO Control Register (FCR) bit-0. standard 16C550 provides only receive FIFO bytes with selectable trigger levels there transmit trigger level selection. UART provides independent programmable trigger levels from both receiver transmitter. When receive transmit data reached preset trigger level UART generates interrupt call service. receive FIFO section includes time-out function ensure data delivered CPU. receive data time-out interrupt generated when there receive data period about 4-characters Receive Holding Register (RHR) full data reach receive trigger level. timing diagram area FIFO operation.
Local UART UARTA
Remote UART UARTB
Receiver FIFO Trigger Reached
Transmitter
Auto Trigger Level
RTSA#
CTSB#
Auto Monitor
Transmitter
Receiver FIFO Trigger Reached
Auto Monitor
CTSA#
RTSB#
Auto Trigger Level
Assert RTS# Begin Transmission RTSA# CTSB#
CHAR CHAR CHAR CHAR CHAR CHAR CHAR CHAR CHAR CHAR CHAR CHAR CHAR
Starts
Restart Suspend
CHAR
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
CHAR BYTE
FIFO Receive Data INTA (RXA FIFO Interrupt)
FIFO Trigger Level
High Threshold
Threshold
FIFO Trigger Level
Figure
Rev. P1.00
Referring Figure local UART (UARTA) starts data transfer asserting RTSA# (1). RTSA# normally connected CTSB# remote UART (UARTB). CTSB# allows transmitter send data (3). data arrives fills UART-A receive FIFO (4). When data fills receive FIFO trigger level, UARTA activates data ready interrupt continues receive data into FIFO. interrupt service latency long data being unloaded, UARTA monitors receive data fill level match upper threshold delay de-assert RTSA# (6). CTSB# follows request UARTB transmitter suspend data transfer. UART-B stops finishes sending data bits transmit shift register (8). When receive FIFO data UARTA unloaded match lower threshold delay (9), UARTA re-assert RTSA# (10) CTSB# recognizes change (11) restarts transmitter data flow again until next trigger (12). This same event applies reverse direction when UARTA sends data UARTB with RTSB# CTSA# controlling data flow. interrupts associated with flow control have been added give indication when RTS# CTS# de-asserted during operation. interrupts must first enabled bit-4, then enabled individually bit-6 Automatic hardware flow control selected setting bits (RTS) (CTS) register logic CTS# transitions from logic logic indicating flow control request, bit-5 will logic enabled 6-7), UART will suspend transmissions soon stop character process shifted out. Transmission resumed after CTS# input returns logic indicating more data sent. UART offers programmable flow control trigger hysteresis while maintains compatibility 16C650A. With Auto function enabled, interrupt generated when receive FIFO reaches programmed trigger level. RTS# will forced logic (RTS Off) until reached upper limit hysteresis level. This delay action suspending remote transmitter increases data
XR16C872
throughput. RTS# will return logic (RTS after data buffer (FIFO) unloaded lower limit hysteresis level. Under these described conditions UART will continue accept data until receive FIFO gets full. Auto function must started asserting RTS# logic (RTS On). full description hysteresis selection, EMSR descriptions. Software Flow Control When software flow control enabled, UART compares sequential receive data characters with programmed Xoff-1,2 character value(s). receive character(s) match programmed values, transmitter will halt transmission soon current character completed sent out. When match occurs, Xoff-det interrupt enabled bit-5) flag will interrupt output will activated. Following suspension match Xoff characters values, UART will monitor receive data stream match Xon-1,2 character value(s). match found, UART will resume operation clear Xoff-det flag (ISR bit-4). Reset initially sets contents Xon/Xoff 8-bit flow control registers logic Following reset user writes Xon/Xoff value desired software flow control. Different conditions detect Xon/Xoff characters suspend/resume transmissions. When double 8-bit Xon/Xoff characters selected, UART compares consecutive receive characters with software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) controls transmissions accordingly. Under above described flow control mechanisms, flow control characters placed (stacked) user accessible data FIFO. receive FIFO overfilling flow control needs executed, UART automatically sends Xoff message serial output remote modem. UART sends Xoff-1,2 characters soon received data passes programmed FIFO trigger level. clear this condition, UART will transmit programmed Xon-1,2 characters soon receive data FIFO drops below programmed FIFO trigger level.
Rev. P1.00
XR16C872
Special Feature Software Flow Control
special feature provided detect 8-bit character when bit-5 Enhanced Feature Register (EFR). When this character detected, will placed user accessible data stack along with normal incoming data. This condition selected conjunction with bits 0-3. Note that regular software flow control should turned when using this special mode setting logic UART compares each incoming receive character with Xoff-2 data. match exists, received data will transferred FIFO bit-4 will indicate detection special character. Although Internal Register Table shows each register with eight bits character information, actual number bits dependent programmed word length. Line Control Register (LCR) bits defines number character bits, i.e., either bits, bits, bits, bits. word length selected bits also determines number bits that will used special character comparison. Bit-0 X-registers corresponds receive character. Interrupts Interrupt conditions priorities indicated interrupt status register (ISR), Table When transmitter interrupt enabled UART will issue interrupt indicate that transmit holding register (THR) empty. This interrupt must serviced before continuing operations. register provides current singular highest priority interrupt only. could noted that interrupts have lowest interrupt priority. condition exist where higher priority interrupt mask lower priority CTS/RTS interrupt(s). Only after servicing higher pending interrupt will lower priority CTS/ interrupt(s) reflected status register. Servicing interrupt without investigating further interrupt conditions result data errors. When interrupt conditions have same priority, important service these interrupts correctly. Receive Data Ready Receive Time have same interrupt priority (when enabled bit-0).
receiver issues interrupt after number characters have reached programmed trigger level. this case receive FIFO hold more characters than programmed trigger level. Following removal data byte, user should recheck bit-0 additional characters. Receive Time will occur receive FIFO empty. time counter reset center each stop received each time receive holding register (RHR) read. actual time value (Time length bits) (Programmed word length) convert time value character value, user consider complete word length, including data information length, start bit, parity bit, size stop bit, i.e., 1.5X, times. Example user programs word length with parity stop bit, time will 7(programmed word length) times. Character time (programmed word length (parity (stop (start characters. Programmable Baud Rate Generator UART supports high speed modem technologies that have increased input data rate employing data compression schemes. example 33.6 Kbps modem that employs data compression require 115.2 Kbps input data rate. 128.0 Kbps ISDN modem that supports data compression need input data rate 460.8 Kbps. UART supports standard data rate from 460.8 Kbps with main clock 7.3728 which internally derived from external crystal clock 22.1184 MHz. single baud rate generator provides each UART transmitter receiver. UART configured internal external clock operation. internal clock oscillator operation, industry standard microprocessor crystal (parallel resonant, 20-33pF loading capacitance) connected externally between XTAL1 XTAL2 pin, Figure Alternatively, external clock connected XTAL1 clock internal baud rate generator standard custom rates.
Rev. P1.00
XR16C872
XR16C872
XTAL1
XTAL2
22.1184MHz *22-33pF *22-33pF
*Consult with crystal manufacturer proper loading capacitance
Figure Crystal Osc. Ext. Components
Output Baud Rate BIT-7=1 1200 2400 4800 7200 9600 19.2k 38.4k 57.6k 115.2k
Output Baud Rate Bit-7=0 1200 2400 4800 9600 19.2K 28.8K 38.4k 76.8k 153.6k 230.4k 460.8k
User Clock Divisor (Decimal) 2304 1536
User Clock Divisor (HEX)
Program Value (HEX)
Program Value (HEX)
Table Baud Rate Generator Standard Programming Table with 7.3728 Clock
Rev. P1.00
XR16C872
Registers Bit-7=0 (default)
Pre-scaler Divides 7.3728 MHz. Clock from Osc. Divider Pre-scaler Divides
Baud Rate Generator
Baud Clock Transmitter Receiver
Bit-7=1
Figure Clock Pre-scaler Baud Rate Generator Circuitry
generator divides input clock divisor from UART divides input clock Further division this clock provides table rates support high data rate applications using same system design. rate tables selectable through internal register, bit-7. Setting bit-7 logic provides additional divide whereas, setting bit-7 logic only divides (See Table Figure frequency internal sampling rate exactly times) selected baud rate. Customized Baud Rates achieved selecting proper divisor values sections baud rate generator. Programming Baud Rate Generator Registers (MSB) (LSB) provides user capability selecting desired serial baud rate. Table shows selectable baud rate tables available with 7.3728 clock. output data rate tolerance determined frequency accuracy 22.1184MHz crystal external clock. Operation FIFO trigger level provides additional flexibility user data block transfer operation. bits
provide indication when transmitter empty empty location(s). user optionally operate transmit receive FIFOs mode (FCR bit-3). When transmit receive FIFOs enabled mode deactivated (DMA Mode "0"), UART activates interrupt output each data transmit receive operation. When mode activated (DMA Mode "1"), user takes advantage block mode operation loading unloading FIFO block sequence determined preset trigger level. this mode, UART asserts interrupt output when characters transmit FIFOs below transmit trigger level, number characters receive FIFOs above receive trigger level. Transmit receive operation selected EMSR register Sleep Mode UARTs designed operate with power consumption. sleep mode included further reduce power consumption when chip being used. operating parameters maintained while sleep. With bit-4 bit-4 enabled (set logic UART enters sleep mode when interrupt pending activities modem port. external clock supplied UART,
Rev. P1.00
want stop UART resumes normal operation when character's start detected, change state modem input pins RI#, CTS#, DSR#, CD#, transmit data loaded into FIFO user. typically takes 30us crystal oscillator restart from sleep mode depending crystal properties. This delay must taken into consideration during design receive character(s) lost. number characters lost depends operating data rate, more higher data rate. sleep mode enabled UART awakened conditions described above, will return sleep mode automatically after last character transmitted read user interrupt pending. chip will enter sleep mode while interrupt(s) still pending oscillator would still running. UART stays sleep mode operation until disabled setting bit-4 logic Example Sleep mode enable during initialization:
Write with 0xBF bit-4 logic Write with Op.value bit-4 logic access registers enable non-550 functions IER, registers point basic registers sleep mode service pending interrupts modem port activity enters sleep mode stop oscillator
XR16C872
Loopback Mode internal loopback capability allows board diagnostics. this mode, normal modem interface pins disconnected re-configured loopback internally. bits also disconnected. However, register bits used controlling loopback diagnostic testing. this mode, register (bits 0-1) control modem inputs respectively. signals DTR# RTS# (bits 0-1) used control modem CTS# DSR# inputs respectively. transmitter output (TX) receiver input (RX) disconnected from their associated interface pins, instead connected together internally (See Figure CTS#, DSR#, CD#, disconnected from their normal modem control inputs pins, instead connected internally DTR#, RTS#, OP1# OP2#. Loopback test data enters transmit holding register user data interface, D0-D7. transmitter serializes data passes serial data receive UART internal loopback connection. receive UART converts serial data back into parallel data that then made available user data interface, D0-D7. user optionally compares received data initial transmitted data verifying error free operation UART TX/RX circuits. this mode, receiver, transmitter modem control interrupts fully operational. However, interrupts only read using lower four bits Modem Control Register (MCR bits 0-3) instead four Modem Status Register bits 4-7. interrupts still controlled IER. Please note that OP1# OP2# pins brought available.
lowest sleep current following pins should idle logic state: should logic data should pull-down with ~47K resistors controller puts data tri-state condition. input pins should left floating.
Rev. P1.00
XR16C872
Transmit D0-D7 IOW# IOCHRDY RESET Control Logic Data IOR# FIFO Registers
Transmit Shift Register
IrDA Encoder
Control Logic
Receive
Receive Shift Register
Inter Connect Lines Control Signals
Register A0-A2 Select Logic
FIFO Registers
Flow Control Logic
IrDA Decoder
IRQn
Interrupt Control Logic
Bit-4=1
Flow
RTS#
DTR#
Modem Control Logic
EEDIO EECLK EECS
EEPROM Controller
(OP1#)
CLOCK
Baud Rate Generator
DSR#
(OP2#)
CTS#
Figure Internal Loop-Back Mode Diagram
Rev. P1.00
UART INTERNAL REGISTERS
following table delineates assigned functions internal registers. UART same register independently control. assigned functions defined following paragraphs.
REGISTER FUNCTIONAL DESCRIPTIONS
Basic Registers accessible when bit-7 logic (Shaded bits enabled bit-4)
Baud Rate Generator Registers accessible only when bit-7 logic
76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321
3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321
210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321
210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321
10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 0987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321
10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 10987654321 3210987654321 210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321
210987654321 10987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321
210987654321 10987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321 210987654321
Rev. P1.00
[FF] FIFO Count [XX] [XX] [00] [XX] [00] Register [Default] Note [XX] [00] [00] [60] [00] [01] CTS# RTS# Xoff interrupt interrupt interrupt FIFO's FIFO's enabled enabled divisor latch enable RCVR trigger (MSB) Clock select bit-15 BIT-7 FIFO error bit-7 bit-7 bit-7 bit-7 trans. trans. break shift reg. holding interrupt empty reg. empty IRRT enable RCVR trigger (LSB) bit-14 break BIT-6 bit-6 bit-6 bit-6 bit-6
Xon-Any
0/TX trigger (MSB)
RTS#, CTS#
DSR#
bit-13
parity
BIT-5
bit-5
bit-5
bit-5
bit-5
0/TX trigger (LSB) Sleep mode bit-12 CTS# even parity BIT-4 loop back bit-4 bit-4 bit-4 bit-4 Xoff Det. modem status interrupt framing error (OP2#) parity enable priority bit-2 mode select bit-11 BIT-3 delta bit-3 bit-3 bit-3 bit-3 receive line status interrupt (OP1#) priority bit-1 bit-10 parity error BIT-2 XMIT FIFO reset delta bit-2 bit-2 bit-2 bit-2 stop bits
XR16C872
transmit holding register
overrun error
priority bit-0
RCVR FIFO reset
word length bit-1
delta DSR#
RTS#
BIT-1
bit-9 bit-1 bit-1 bit-1 bit-1
receive holding register
receive data ready
FIFO enable
word length bit-0
DTR#
status
delta CTS#
BIT-0
bit-8 bit-0 bit-0 bit-0 bit-0
XR16C872
UART INTERNAL REGISTERS (CONT'D)
Register [Default] Note
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
Enhanced Registers accessible only when 0xBF. [00] FCTR [00] Trig/ Rx/Tx Mode Auto Trig/
SPR/EMSR
Trig/ Trig bit-1 Special Char. select
Trig/ Trig bit-0
3210987654321 3210987654321 321098765432 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321 3210987654321
Trig RS485 Auto control Cont-3 Tx,Rx Control
Trig/ IrRx Inv. Cont-2 Tx,Rx Control
Trig/ bit-1 Cont-1 Tx,Rx Control
Trig/ bit-0 Cont-0 Tx,Rx Control
Select Auto
Hysteresis Hysteresis
[00]
Enable bits 4-7, ISR, bits 4-5, bits bit-4 bit-12 bit-4 bit-12
Xon-1[00] Xon-2[00] Xoff-1[00] Xoff-2[00]
bit-7 bit-15 bit-7 bit-15
bit-6 bit-14 bit-6 bit-14
bit-5 bit-13 bit-5 bit-13
bit-3 bit-11 bit-3 bit-11
bit-2 bit-10 bit-2 bit-10
bit-1 bit-9 bit-1 bit-9
bit-0 bit-8 bit-0 bit-8
EMSR Register accessible only when FCTR logic EMSR [00] Used Used bit-3 bit-2 Reserved Reserved
Hysteresis Hysteresis
ALT. Rx/Tx FIFO Count
Rx/Tx FIFO Count
Note:
value represents register's initialized value. signifies 4-bit un-initialized nibble.
Rev. P1.00
UARTs have Device Identification Device Revision code distinguish part with others. suggested user read identification revision information from part only during power initialization routine avoid disturbing baud rate generator during normal operation. read identification number from device, required baud rate generator divisor latch Logic (LCR bit-7 logic content baud rate generator registers 0x00. Then read content DLM=0x10 XR16C850 type content device revision with 0x01 represents revision-A 0x02 revision-B, forth. beginning UART Initiation routine: Write bit-7=1 Write 0x00 Write 0x00 Read UART type number (0x10) Read UART revision number (0x02) Transmit Receive Data Register serial transmitter section consists 8-bit Transmit Hold Register (THR) which part transmit FIFO Transmit Shift Register (TSR). status provided Line Status Register (LSR). Writing address location transfers contents data (D7-D0) THR, providing that flag set. empty flag logic when transmit FIFO room more data. flag indicates either that transmit holding register becomes empty nonFIFO mode preset transmit trigger level when transmit FIFO enabled. flag always indicates transmitter empty nothing shift out. This flag directional control half duplex operations. serial receive section also contains 11-bit Receive Holding Register (RHR) which part receive FIFO. Receive data unloaded reading register address location. receive section
XR16C872
provides mechanism detect false starts. falling edge start false start input, internal sampling counter starts counting clocks operating data rate. After clocks incoming start time should center time. this time start sampled still logic validated. false, detection sequence starts over again. Evaluating start this manner validating data bits stop also middle time helps ensure integrity receiving character. Receive errors such Framing, Parity, Overrun saved receive FIFO posted each data byte becomes available CPU. receive FIFO actually 11-bit wide FIFO including receive error bits. receiver FIFO pointer bumped upon data byte read operation. Therefore, necessary user read error bits prior reading data byte. Interrupt Enable Register (IER) Interrupt Enable Register (IER) masks interrupts receiver ready, transmitter empty, line status, modem status. also optionally includes CTS#, RTS# Xoff interrupts when enabled register bit-4. These interrupts wired Or'ed output pin. register description more detail. Receive FIFO Interrupt Mode Operation When receive FIFO (FCR bit-0 logic receive interrupt (IER bit-0 logic enabled, receive interrupt register status will reflect following: receive data interrupt issued when receive FIFO reached programmed trigger level. interrupt clears when upon reading register FIFO content drops below programmed trigger level. Receive FIFO status also reflected register when FIFO trigger level reached programmed level. register status will clear only when FIFO content drops below programmed trigger level.
Rev. P1.00
XR16C872
BIT-2: Logic Disable receiver line status interrupt. (normal default condition) Logic Enable receiver line status interrupt. receiver line interrupt cleared when read. BIT-3: Logic Disable modem status register interrupt. (normal default condition) Logic Enable modem status register interrupt. modem status interrupt cleared when read. Logic Disable sleep mode. (normal default condition) Logic Enable sleep mode. Sleep Mode section details. BIT-5: Logic Disable software flow control, receive Xoff-det interrupt. (normal default condition) Logic Enable software flow control, receive Xoff-det interrupt. Xoff-det interrupt cleared reading register upon receiving character. Also, when Special Character mode enabled (EFR-bit reading register following received character will clear interrupt. BIT-6: Logic Disable interrupt. (normal default condition) Logic Enable interrupt. UART issues interrupt when RTS# transitions from logic logic reported bit-register. interrupt cleared reading register. BIT-7: Logic Disable interrupt. (normal default condition) Logic Enable interrupt. UART issues interrupt when CTS# transitions from logic logic reported register. interrupt cleared reading register.
receive data ready (LSR bit-0) soon character transferred from receive shift register receive FIFO. This reset when FIFO becomes empty. Receive/Transmit FIFO Polled Mode Operation When BIT-0 equals logic resetting bits enables FIFO polled mode operation. Since receiver transmitter have separate bits either both used polled mode selecting respective transmit receive control bit(s). BIT-0 will logic long there byte receive FIFO. will indicate overrun error occurred receiver. BIT-5 will indicate when transmit FIFO empty. BIT-6 will indicate when both transmit FIFO transmit shift register empty. BIT-7 will indicate data errors within receive FIFO. This will clear when error byte unloaded. BIT-0: Logic Disable receiver ready interrupt. (normal default condition) Logic Enable receiver ready interrupt. receiver ready interrupt cleared when read. BIT-1: Logic Disable transmitter empty interrupt. (normal default condition) Logic Enable transmitter empty interrupt. transmitter empty interrupt cleared when read.
Rev. P1.00
FIFO Control Register (FCR) This register used enable FIFOs, clear FIFOs, transmit/receive FIFO trigger levels, select mode. DMA, FIFO modes defined follows: MODE
XR16C872
BIT-3: Logic mode "0". (normal default condition) Logic mode "1." Transmit operation mode "0": This selects single character interrupt operation. transmit empty interrupt will when UART this 16C450 single character simulation mode (FIFOs disabled, bit-0 logic FIFO mode (FIFOs enabled, bit-0 logic bit-3 logic when there characters transmit FIFO transmit holding register. Receive operation mode "0": When UART mode (FCR bit-0 logic FIFO mode (FCR bit-0 logic bit-3 logic there character RHR, receive ready interrupt generated. Receive operation mode "1": When UART FIFO mode (FCR bit-0 logic bit-3 logic receive trigger level been reached, Receive Time occurred, receive ready interrupt generated. 4-5: (logic cleared default condition, trigger level none) XR16C850 provide user selectable trigger levels, FCTR Bits selects following table. These bits used trigger level transmit FIFO interrupt. UART will issue transmit empty interrupt when number characters FIFO drops below selected trigger level.
Mode enable interrupt each single character transmit receive operation. Transmit empty interrupt will generated whenever Transmit Holding Register (THR) empty receive ready interrupt will generated whenever Receive Holding Register (RHR) loaded with character. However, FIFO continues receive data limit. Mode Enable interrupt block transfer mode operation. transmit empty interrupt when transmit FIFO trigger level reached. receive interrupt when receive FIFO fills programmed trigger level. However FIFO continues fill regardless programmed level until FIFO completely full.
BIT-0: Logic Disable transmit receive FIFO. (normal default condition) Logic Enable transmit receive FIFO. This must when other bits written they will programmed. BIT-1: Logic FIFO receive reset. (normal default condition) Logic Clears FIFO counter resets pointers logic (the receive shift register cleared altered). This will return logic after clearing FIFO. BIT-2: Logic FIFO transmit reset. (normal default condition) Logic Clears FIFO counter resets pointers logic (the transmit shift register cleared altered). This will return logic after clearing FIFO.
Rev. P1.00
XR16C872
Trigger Table-A (Receive) "Default setting after reset, ST16C550 mode"
BIT-7 BIT-6 FIFO trigger level
Trigger Table-A (Transmit) "Default setting after reset, ST16C550 mode"
BIT-5 BIT-4 FIFO Trigger Level None
Trigger Table-B (Transmit)
BIT-5 BIT-4 FIFO Trigger Level
Trigger Table-B (Receive)
BIT-7 BIT-6 FIFO trigger level
Trigger Table-C (Transmit)
BIT-5 BIT-4 FIFO Trigger Level
Trigger Table-C (Receive)
BIT-7 BIT-6 FIFO trigger level
Trigger Table-D (Transmit)
BIT-5 BIT-4 FIFO trigger level User programmable trigger levels
Trigger Table-D (Receive)
BIT-7 BIT-6 FIFO trigger level User programmable trigger levels
6-7: (logic cleared default condition, trigger level These bits used trigger level receiver FIFO interrupt. interrupt will trigger again when data unloaded below threshold incoming data fills back trigger level. FCTR Bits selects following table.
Rev. P1.00
example program FIFO trigger level:
write with 0xBF FCTR bit-7 logic write with 0x60 FCTR bit-7 logic write with 0x08 write with 0x03 point enhanced registers program FIFO trigger level your trigger level program FIFO trigger level your trigger level operating parameters
XR16C872
Interrupt Status Register (ISR) UART provides levels prioritized interrupts minimize external software interaction. Interrupt Status Register (ISR) provides user with interrupt status bits. Performing read cycle will provide user with highest pending interrupt level serviced. other interrupts acknowledged until pending interrupt serviced. Whenever interrupt status register read, interrupt status cleared. However should noted that only current pending interrupt cleared read. lower level interrupt seen after re-reading interrupt status bits. Interrupt Source Table (below) shows data values (bit 0-5) prioritized interrupt levels, interrupt sources associated with each these interrupt levels, clear each interrupt (INT).
FCTR bit4-5 logic select trigger Table-D
Receive data ready interrupt will activates when FIFO fills data bytes while transmit empty interrupt gets when data empty bytes.
Priority Level
BITS Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source Interrupt (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time out) TXRDY Transmitter Holding Register Empty) (Modem Status Register) RXRDY (Rcv. Xoff signal Special character) CTS, change state
Clears After read read read read read read read
Table Interrupt Priority Source
Rev. P1.00
XR16C872
BIT-0: Logic interrupt pending contents used pointer appropriate interrupt service routine. Logic interrupt pending. (normal default condition) 1-3: (logic cleared default condition) These bits indicate source pending interrupt interrupt priority levels (See Interrupt Source Table). 4-5: (logic cleared default condition) These bits enabled when bit-4 logic bit-4 indicates that matching Xoff character(s) have been received. bit-5 indicates that CTS# RTS# condition have changed. Note that once logic bit-4 will stay logic until character(s) received upon read register ISR. 6-7: (logic cleared default condition) These bits logic when FIFO being used. They logic when FIFOs enabled. Line Control Register (LCR) Line Control Register used specify asynchronous data communication format. word length, number stop bits, parity selected writing appropriate bits this register. This register also secondary function select other register sets. first setting bit-7 select baud rate divisor (DLL DLM) registers, second registers selected when "BF" written select enhanced register set. 0-1: (logic cleared default condition). These bits specify word length transmitted received. upper unused bit(s) received data byte zero.
BIT-1
BIT-0
Word Length
BIT-2: (logic cleared default condition) length stop specified this conjunction with programmed word length.
BIT-2 Word Stop Length (Bit Time(s)) 1-1/2
5,6,7,8 6,7,8
BIT-3: Parity parity selected this bit. Logic parity (normal default condition) Logic parity generated during transmission, receiver checks reports parity error register. parity presented received data byte. BIT-4: parity enabled with bit-3 logic BIT-4 selects even parity format. Logic Parity generated forcing number logic transmitted data. receiver must programmed check same format. (normal default condition) Logic EVEN Parity generated forcing even number logic transmitted data. receiver must programmed check same format. BIT-5: parity enabled, BIT-5 selects forced parity format. BIT-5 logic parity forced (normal default condition) BIT-5 logic BIT-4 logic parity forced logical transmit receive data.
Rev. P1.00
BIT-5 logic BIT-4 logic parity forced logical transmit receive data.
Bit-3 Bit-4 Bit-5 parity parity Even parity Forced parity="1" Forced parity= Parity Selection
XR16C872
BIT-1: Logic Force RTS# output logic (normal default condition) Logic Force RTS# output logic Automatic used hardware flow control enabling bit-6 (See bit-6). BIT-2: *OP1# output available 872. Logic OP1# output logic (normal default condition) Logic OP1# output logic BIT-3: *OP2# output available Logic OP2# output logic (normal default condition) Logic OP2# output logic BIT-4: Logic Disable loop-back mode. (normal default condition) Logic Enable local loop-back mode (diagnostics). BIT-5: Logic Disable Xon-Any function (normal default condition) Logic Enable Xon-Any function. this mode character received will enable Xon. BIT-6: Logic Enable Modem receive transmit input/ output interface. (normal default condition) Logic Enable infrared IrDA receive transmit inputs/outputs. While this mode, TX/RX output/ inputs routed infrared encoder/decoder. data input output levels will conform IrDA infrared interface requirement. such, while this mode infrared output will logic during idle data conditions. Care must taken into consideration design over heat during power initialization state while output still logic
BIT-6: When enabled Break control causes break condition transmitted (the output forced logic state). This condition exists until disabled setting bit-6 logic Logic break condition. (normal default condition) Logic Forces transmitter output (TX) logic alerting remote receiver line break condition. BIT-7: internal baud rate counter latch Enhance Feature mode enable. Logic Divisor latch disabled. (normal default condition) Logic Select baud rate divisors (DLL DLM) enhanced feature register enabled Modem Control Register (MCR) This register controls interface with modem peripheral device. BIT-0: Logic Force -DTR output logic (normal default condition) Logic Force -DTR output logic
Rev. P1.00
XR16C872
Example enable encoder decoder:
Write with 0xBF bit-4 logic access "shadow" register enable non-550 bits IER,
Write with value point base register bit-6 logic enable mode, output goes logic
BIT-3: Logic framing error (normal default condition). Logic Framing error. receive character have valid stop bit(s). FIFO mode this error associated with character FIFO. BIT-4: Logic break condition (normal default condition) Logic receiver received break signal logic character frame time). FIFO mode, only break character loaded into FIFO. BIT-5: This Transmit Holding Register Empty indicator. This indicates that UART ready accept character transmission. addition, this causes UART issue interrupt when interrupt enable set. logic when character transferred from transmit holding register into transmitter shift register. reset logic concurrently with loading transmitter holding register CPU. FIFO mode this when transmit FIFO empty; cleared when least byte written transmit FIFO. BIT-6: This Transmit Empty indicator. This logic whenever transmit holding register transmit shift register both empty. reset logic whenever either contains data character. FIFO mode this whenever transmit FIFO transmit shift register both empty. BIT-7: Logic Error (normal default condition) Logic There least parity error, framing error break indication current FIFO data. This cleared when register read. When read, reflects error bits character FIFO, next character read RHR. Therefore, errors character identified reading then reading data character RHR.
BIT-7: Logic Divide one. input clock (crystal external) divided sixteen then presented Programmable Baud Rate Generator (BGR) without further modification, i.e., divide one. (normal, default condition) Logic Divide four. divide clock described bit-7 equals logic further divided four (also Programmable Baud Rate Generator section). Line Status Register (LSR) This register provides status data transfers between UART CPU. BIT-0: Logic data receive holding register FIFO. (normal default condition) Logic Data been received saved receive holding register FIFO. BIT-1: Logic overrun error. (normal default condition) Logic Overrun error. data overrun error occurred receive shift register. This happens when additional data arrives while FIFO full. this case previous data shift register overwritten. Note that under this condition data byte receive shift register transfer into FIFO, therefore data FIFO corrupted error. BIT-2: Logic parity error (normal default condition) Logic Parity error. receive character does have correct parity information suspect. FIFO mode, this error associated with character FIFO.
Rev. P1.00
XR16C872
Modem Status Register (MSR) This register provides current state control interface signals from modem, other peripheral device that UART connected. Four bits this register used indicate changed information. These bits logic whenever control input from modem changes state. These bits logic whenever reads this register. BIT-0: Logic CTS# Change (normal default condition) Logic CTS# input UART changed state since last time read. modem Status Interrupt will generated. BIT-1: Logic DSR# Change (normal default condition) Logic DSR# input UART changed state since last time read. modem Status Interrupt will generated. BIT-2: Logic Change (normal default condition) Logic input UART changed from logic logic modem Status Interrupt will generated. BIT-3: Logic Change (normal default condition) Logic Indicates that input UART changed state since last time read. modem Status Interrupt will generated. BIT-4: CTS# functions hardware flow control signal input enabled bit-7. transmit holding register flow control enabled/disabled bit-4. Flow control (when enabled) allows suspending resuming data transmissions based external modem CTS# signal. logic CTS# will suspend transmissions soon current character finished transmission. Normally bit-4 complement CTS# input. However loop-back mode, this equivalent register.
BIT-5: (active high, logical Normally this complement DSR# input pin. loop-back mode, this complement register. BIT-6: (active high, logical Normally this complement input. loop-back mode this equivalent OP1# register. BIT-7: (active high, logical Normally this complement input. loop-back mode this equivalent OP2# register. Scratch Register (SPR) UART temporary data register store bits user information. register content 0xFF upon power hardware reset. This register alternately used FIFO counter register, when FCTR bit-6=1 with EMSR bit-0 defining TXCNT RXCNT. Enhanced Feature Register (EFR) This register only accessible when 0xBF. Enhanced feature functions 16C550 base register area enabled using this register bit-4. These bits 4-7, bits 4-5, bits 5-7. Bits-0 through provide single dual character software flow control selection. When Xon1 Xon2 and/or Xoff1 Xoff2 modes selected (see Table double 8-bit words concatenated into sequential characters. 0-3: (logic cleared default condition) Combinations software flow control selected programming these bits.
Rev. P1.00
XR16C872
Cont-3
Cont-2
Cont-1
Cont-0
software flow controls transmit flow control Transmit Xon1/Xoff1 Transmit Xon2/Xoff2 Transmit Xon1 Xon2/Xoff1 Xoff2 receive flow control Receiver compares Xon1/Xoff1 Receiver compares Xon2/Xoff2 Transmit Xon1/ Xoff1. Receiver compares Xon1 Xon2, Xoff1 Xoff2 Transmit Xon2/Xoff2 Receiver compares Xon1 Xon2/Xoff1 Xoff2 Transmit Xon1 Xon2/Xoff1 Xoff2 Receiver compares Xon1 Xon2/Xoff1 Xoff2 transmit flow control Receiver compares Xon1 Xon2/Xoff1 Xoff2
Table Software Flow Control Registers
BIT-4: Enhanced function control bit. content bits 4-7, bits 4-5, bits 4-5, bits modified latched. After modifying bits enhanced registers, bit-4 logic latch values. This feature prevents existing software from altering overwriting UART enhanced functions. Logic disable/latch enhanced features. bits bits 4-5, bits 4-5, bits saved retain user settings, then bits 4-7, bits 4-5, bits 4-5, bits initialized default values shown Internal Resister Table. After reset, bits 4-7, bits 4-5, bits 4-5, bits logic compatible with ST16C550 mode. (normal default condition). Logic Enables enhanced functions. When this logic enhanced features UART enabled user settings stored during reset will restored.
BIT-5: Logic Special Character Detect Disabled (normal default condition) Logic Special Character Detect Enabled. UART compares each incoming receive character with Xoff-2 data. match exists, received data will transferred FIFO bit-4 will indicate detection special character. Bit-0 X-registers corresponds with receive character. When this feature enabled, normal software flow control must disabled (EFR bits must logic BIT-6: Automatic used hardware flow control enabling bit-6. user must assert RTS# initiate this function. When AUTO selected, interrupt will generated when receive FIFO filled programmed trigger level RTS# will logic when reaches upper limit hysteresis level. RTS# will return logic when data
Rev. P1.00
unloaded lower limit hysteresis. state this register changes with status hardware flow control. RTS# functions normally when hardware flow control disabled. Automatic flow control disabled. (normal default condition) Enable Automatic flow control. bit-7: Automatic Flow Control. Logic Automatic flow control disabled. (normal default condition) Logic Enable Automatic flow control. Transmission stops when CTS# goes logical Transmission resumes when CTS# returns logical FEATURE CONTROL REGISTER (FCR) This register only accessible when 0xBF. FCTR 0-1: User selectable RTS# delay hysteresis hardware flow control application. After reset, these bits logic select next trigger level FIFO trigger level (FCR 6-7,Table-A). These bits also associated with EMSR bit-4 hysteresis control. EMSR register more details. FCTR BIT-2: Select input encoded IrDa data. Select input active high encoded IrDa data. FCTR BIT-3: Auto RS485 Half Duplex Direction control. *OP1# output available 872, however, does change behavior transmit empty interrupt.
XR16C872
Transmitter generates interrupt when transmit holding register becomes empty while transmit shift register still shifting data out. Enable Auto RS485 Half Duplex Direction Control. transmit empty interrupt generation delayed until Transmitter Shift Register (TSR) becomes empty. FCTR 4-5: Transmit receive trigger table select.
FCTR Bit-5 FCTR Bit-4 Trigger Table Table-A (TX/RX) Table-B (TX/RX) Table-C (TX/RX) Table-D (TX/RX)
FCTR BIT-6: Scratch Register (SPR) EMSR select. Scratch Register (SPR) selected general read write register. 16C550 compatible mode. FIFO count register, Enhanced Mode Select Register (EMSR). Number characters transmit receive holding register read Scratch Register when this set. Enhanced Mode selected when written into FCTR BIT-7: Programmable trigger register select. Receiver programmable trigger level register (TRG) selected. Transmitter programmable trigger level register (TRG) selected.
Rev. P1.00
XR16C872
TRIGGER LEVEL/FIFO COUNT REGISTER (TRG) This register only accessible when 0xBF. This register provides user programmable transmit receive trigger level from byte (0xFF), reading number data bytes transmit receive FIFO. 0-7: Write only. This register sets user programmable transmit receive FIFO trigger levels. FCTR bit-7 must point transmitter receiver prior programming trigger level. 0-7: Read only. Transmit receive FIFO count. Number characters transmit receive FIFO read this register. FCTR bit-7 must point transmitter receiver prior reading FIFO count. ENHANCED MODE SELECT REGISTER (EMSR) This register only accessible when 0xBF FCTR Bit-6 logic EMSR BIT-0: Write only Receive FIFO count register. Scratch Register (SPR) used provide receive FIFO count when read. Transmit FIFO count register. Scratch Register (SPR) used provide transmit FIFO count when read. Example read number character count FIFO.
Initialization routine: 0xBF FCTR bit-6 logic point enhanced registers swap FIFO counters point EMSR register operating parameters routine EMSR bit-0 logic read routine EMSR bit-0 logic read read FIFO count obtain FIFO Count read FIFO count obtain FIFO count
EMSR BIT-1: Write only Normal. Alternate receive transmit FIFO count. When EMSR Bit-0=1 EMSR Bit-1=1, Scratch Register used provide receive transmit FIFO count when read every alternate read cycle. Bit-7 will provide FIFO count mode information, Bit-7=0 receive mode, Bit-7=1 transmit mode. EMSR BIT-2: Write only This available 872. EMSR BIT4 Write only These bits select flow control hysteresis associated with FCTR hysteresis reference FIFO trigger level. Below table shows selectable hysteresis.
EMSR Bit-5 EMSR Bit-4 FCTR Bit-1 FCTR Bit-0 Hysteresis (characters)
Next level
EMSR 6-7: Reserved future use.
Rev. P1.00
1284 Controller bi-directional parallel data port controller compatible IEEE Standard 1284 interface. 1284 interface programmed standard printer port bi-directional parallel port high speed data transfer systems. 1284 interface provides 1284 Level electrical interface, needing external transceivers interface parallel port cable. Hence, connect directly printer high speed bi-directional parallel device. 1284 controller supports following modes operation. Standard Centronics interface, forward only. Bi-directional Centronics. Parallel port with data FIFO. ECP, Extended Capabilities Port, with byte data FIFO Forward Reverse modes, supports Length Encoded (RLE) de-compression reverse mode, however, compression supported forward mode, Direct Memory Access transfer capability. EPP, Enhanced Parallel Port.
XR16C872
reset, device defaults compatible mode which standard Centronics printer mode computers. EPP, modes only activated programming Extended Control Register (ECR), this requires address A10=1, which outside normal parallel port address space. internal timing designed operate from 22.1184 clock which supplied from external source XTAL1 built-in oscillator circuit with appropriate crystal. Optional capabilities specification follows: defined interrupts pulsed, true (Centronics ACK# non-pulsed, true). PWord size forced byte. There byte transmitter that does affect FIFO full (ECP modes). compression supported hardware. channel selectable channel selectable FIFO THRESHOLD (used only non-DMA access FIFO).
Port DATA ECP-AFIFO EPP-APort EPP-DPort C-FIFO ECP-DFIFO T-FIFO Cnfg-A Cnfg-B
Address 004-007
Read/Write R-R/W
Mode
Function Data port FIFO (Address) Status Register Control Register Port (Address) Port (Data) Parallel Port Data FIFO FIFO (Data) Test FIFO Configuration Register Configuration Register Extended Control Register
Table Parallel Data Port Internal Register
Rev. P1.00
XR16C872
STANDARD DEFINITIONS
Bit-0: mode selected, this returns logic one. During mode, bit-0 will return high msecond TimeOut elapsed during last read write cycle (this TimeOut also aborts cycle). This status cleared exiting mode host writing high bit-0 this register. 1-2: Reserved, logic one. Bit-3: true state ERR# pin. Bit-4: true state SELECT pin. Bit-5: true state pin. Bit-6: true state ACK# pin. Bit-7: complement BUSY pad. DATA CONTROL REGISTER Bit-0: complement this drives STROBE#, complement state returned read. Bit-1: complement this drives AUTOFD#, complement state returned read. Bit-2: This drives INIT#, state returned read. Bit-3: complement this drives SELCTIN#, complement state returned read.
Forward direction only. Compatible Mode, "Centronics" standard mode (SPP). Reverse direction only. Nibble mode: bits time using status lines data "Hewlett Packard Bi-tronics". Bi-directional. EPP: Enhanced Parallel Port, used primarily nonprinter peripherals. ECP: Extended Capability Port, used primarily latest generation printers, scanners external storage drives higher data transfer rate. DATA REGISTER (DATA DATA 0-7: host output cycles mode (ECR mode 000) PS/2 mode (ECR mode 001), data from host registered trailing edge IOW#. host input cycles, data peripheral port passed through host data bus. FIFO ADDRESS ECP-AFIFO ECP-AFIFO 0-7: This port only available programmed (nonDMA), only significance host write. Data written this port stored FIFO FIFO-F will lost FIFO-F FIFO (tag) write. read from this port same read 400. DATA STATUS REGISTER This status register read-only except bit-0, bits latched duration IOR#.
Rev. P1.00
Bit-4: Interrupt Enable high will generate interrupt when ACK# low. When either returns high state, this interrupt source will in-active. This interrupt pulsed. Bit-5: Peripheral port direction, This forced logic zero modes 010. written only mode 001, will maintain that state mode changed 011, 100, 110. This must mode, which allows host control direction with IOR# IOW#. final port direction also drives PDIR. Bits 6-7: Reserved, logic zero. ADDRESS PORT EPP-APort When mode enabled, host read write with this port will result data transfer directly to/from peripheral with SLCTIN# active. Direction host read/write will drive STROBE# during write (DIR) high. DATA PORT (EPP-DPort When mode enabled, host read write with this port will result data transfer directly to/from peripheral with AUTOFD# active. Direction host read/write will drive STROBE# during write (DIR) high. PARALLEL PORT DATA C-FIFO This port available programmed access. Data written this port stored FIFO FIFO-F will lost FIFO-F Data written this port will automatically transferred peripheral with STROBE# handshaking with BUSY. This port only defined write, host reads will interfere with FIFO read sequencing.
XR16C872
DATA FIFO ECP-DFIFO This port available programmed access. Data written this port stored FIFO FIFO-F will lost FIFO-F FIFO (tag) high write. Data read from this port will undergo de-compression FIFO data bit-7 both low. byte containing count loaded into counter succeeding byte FIFO will returned host count times before FIFO read address incremented. FIFO under-run incurred during host read, last data byte returned FIFO-E remains coherent. TEST FIFO T-FIFO This port available programmed access. Data written this port stored FIFO FIFO-F will lost FIFO-F During read cycle from this port FIFO under-run will return last data read FIFO-E remains coherent. CONFIGURATION REGISTER Cnfg-A This read-only register available mode only. Cnfg-A 0-1: Forced logic zero, this field don't care PWord byte. Cnfg-A Bit-2: When transmitting, there byte waiting transmitted that does affect FIFO-F. Cnfg-A Bit-3: Reserved, logic zero. Cnfg-A 4-6: Indicates PWord byte (8-bit implementation). Cnfg-A Bit-7: Indicates interrupts pulsed.
Rev. P1.00
XR16C872
CONFIGURATION REGISTER Cnfg-B
This register available mode only, returns bits logic zero. Cnfg-B 0-2: mode channel assigned through auto configuration. defaults manual mode.
IOR# (default)
least byte data contains FIFO. FIFO empty. Bit-1: This read-only returns FIFO full status (FIFO-F) forced unless PPF, ECP, mode selected. least empty location available FIFO. FIFO full. Bit-2: When low, this (ServiceIntr) enables pulsed interrupt enables requests bit-3 set). enabled interrupt occurs, this automatically returned high. interrupt conditions are: Bit-3
Cnfg-B 3-5: mode assignment made through auto configuration. Manual mode defaults
IOW# IOR# (default)
Bit-5 DIRection
CONDITION empty bytes FIFO filled bytes FIFO Terminal Count (TC)
Cnfg-B Bit-6: Returns true value selected pad. Cnfg-B Bit-7: Indicates compression supported. EXTENDED CONTROL REGISTER Extended Control Register system RESET state 10010101. significance bits defined specification Bit-0: This read-only returns FIFO empty status (FIFO-E) forced high unless PPF, ECP, mode selected.
BIT-3: This disables when low. When high, ServiceIntr will enable requests. disabled, DRQx three-stated. enabled Bit-4: When low, this (ErrIntrEn#) enables pulsed interrupt ERR# (Fault#) low. interrupt only enabled mode.
Rev. P1.00
5-7: This field value current value 001. current value 001, then field only written 001. modes defined MODE
XR16C872
Mode
Name
Description Standard, output only. bit-5 forced "0". Bi-directional PS/2 parallel port. FIFO disabled FIFOed, output only. bit-5 forced "0". FIFOed port with decompression. FIFO direction controlled Bit-5. mode. reserved FIFO test mode. FIFO accessible TFIFO register. Configuration register enable.
This mode 010. this output-only mode host data written FIFO with writes address writes; PDIR driven low. FIFO data automatically registered PD[7:0] whenever FIFO-E (data available), timing generated controller logic that handshakes STROBE# (controller) with BUSY (peripheral). MODE This mode 011. this bi-directional mode host data written FIFO with writes address 000, DMA; PDIR driven (can only mode 001); AUTOFD#, INIT, SELCTIN# totem-pole. writes address will write into FIFO bit, while writes address will insert high. FORWARD MODE (PDIR
OPERATION MODE This mode (system RESET mode). this output-only mode host data registered PD[7:0] trailing edge IOW#; PDIR driven low; STROBE#, AUTOFD#, INIT#, SELCTIN# open-drain; timing managed host through registers. MODE This mode 001. this bi-directional mode host output data registered PD[7:0] trailing edge IOW#, PDIR driven allow peripheral data input, AUTOFD#, INIT#, SELCTIN# totem-pole, timing managed host through registers. FIFO data automatically registered PD[7:0] whenever FIFO-E (data available), timing generated controller logic that handshakes STROBE# (controller) with BUSY (peripheral). Data from FIFO output AUTOFD# after being registered simultaneous with FIFO data. REVERSE MODE (PDIR PD[7:0] data BUSY latched into FIFO respectively trailing edge AUTOFD# FIFO-F Timing generated controller logic that handshakes ACK# (peripheral) with AUTOFD# (controller). MODE This mode 100. this bi-directional mode, writes will latch host output data trailing edge IOW#, peripheral input data will latched trailing edge SELCTIN# AUTOFD#. PDIR, STROBE# driven state IOW# (DCR bits must low).
Rev. P1.00
XR16C872
When (AIE) high ACK# interrupt active. When mode active, when ERROR transitions transitions when Fault# interrupt pulse least 200n seconds will generated. FIFO modes (PPF, ECP, TST) with (DMA) low, interrupt pulse least 200n seconds will generated when (SI) there least empty bytes FIFO PDIR there least filled bytes FIFO PDIR This interrupt will automatically disable itself setting high. FIFO modes (PPF, ECP, TST) with (DMA request enabled), interrupt pulse least 200n seconds will generated when received PD-ACK low. This interrupt will automatically disable itself request setting high. cycles occur only between host FIFO data port (address 400) PPF, ECP, modes. DRQ(1, selected through auto configuration mode they will driven high (DMA) high (SI) when {PDIR FIFO-F {PDIR FIFO-E mode active. Manual mode defaults DRQ3. When selected DACKn#(1, low, IOW# will transfer host data FIFO IOR# will transfer FIFO data host. selected DREQn will driven terminate channel when {PDIR FIFO-F {PDIR FIFO-E (SI) goes high (interrupt condition above) more than consecutive data cycles (read write) have occurred. FIFO-F FIFO-E terminated cycles will automatically restart when their state returns low. Consecutive cycle termination will automatically restart because counter reset when selected DACKn# goes high. terminated cycles only restarted host setting (SI) again.
mode allows buffered access between peripheral with timing provided peripheral BUSY handshake into IOCHRDY. cycles with address will immediately drive IOCHRDY low. STROBE# will PD[7:0] allowed change (write cycles) after BUSY been least second. (This delay have elapsed prior cycle initiation). immediately followed driven SELCTIN# address AUTOLF# (DATASTB*) address (read write cycles). When BUSY returns high minimum second, IOCHRDY active strobe will driven high -allowing host complete transaction. prevent system stall, msecond TimeOut aborts cycle expires before BUSY returns high. This TimeOut also sets DCR, which cleared disabling mode writing high MODE This mode 110. This mode allows data transferred (read write direction) between FIFO host address without activating control interface data transferred to/from peripheral). PDIR driven (can only mode 001). Performing cycles this mode allows software test value FIFOThreshold (FT) both output input directions. MODE This mode 111. This mode enables access configuration registers CONF-A CONF-B disables access FIFO. module four sources interrupt which directed IRQ5, IRQ7, IRQ9 (see CONF-B). mode assignment made through auto configuration.
Rev. P1.00
module does support Length Encoding (RLE) compression (indicated CONF-B does support de-compression receiving side. host send compressed data peripheral writing length byte (bit address (NOTE: cannot used this byte) which will place zero into FIFO bit. This must followed immediately data byte being written
XR16C872
FIFO address 400. These bytes will transferred peripheral normal manner. De-compression takes place PDIR when data read from FIFO address 000, DMA. When byte read from FIFO, bits (length) placed counter data bit-7 FIFO both low. subsequent byte FIFO (data) presented host count times before FIFO read pointer advanced.
Register Data ECP-AFIFO
Busy
ACKE
Select
ERR#
INIT#
AutoFD#
Strobe#
SelectIN# enable AP-4 PDA-4 PDB-4 PDC-4 PDD-4 AP-3 PDA-3 PDB-3 PDC-3 PDD-3
EPP-APort EPP-DPort EPP-DPort EPP-DPort EPP-DPort CONF-A
AP-7 PDA-7 PDB-7 PDC-7 PDD-7 type
AP-6 PDA-6 PDB-6 PDC-6 PDD-6
AP-5 PDA-5 PDB-5 PDC-5 PDD-5
AP-2 PDA-2 PDB-2 PDC-2 PDD-2 FIFO-F
AP-1 PDA-1 PDB-1 PDC-1 PDD-1
AP-0 PDA-0 PDB-0 PDC-0 PDD-0
CONF-B
input Mode Sel-1
Sel-2 Mode Sel-0
Sel-1 Fault enable
Sel-0 En/Dis
Sel-2 Service
Sel-1 FIFO full
Sel-0 FIFO empty
Mode Sel-2
Table 1284 Control Register Description
Rev. P1.00
XR16C872
Signal Name STROBE# AUTOFD# SELCTIN# INIT# ACK# BUSY SELECT ERR# PD0-PD7 Signal Type Description
Active low. Indicates valid data data lines. Active low. Instructs printer automatically insert line feed each carriage return. Active low. Used indicate printer that selected. Active low. Used reset printer. asserted pulse used indicate that last character received. high signal asserted printer indicate that busy cannot take data. high signal indicates that printer paper empty. high signal indicates that printer online. Asserted indicate that some error condition exists. Data.
Table Centronics, Signal Description
Signal Name STROBE# AUTOFD#
Signal Type
Nibble mode Name STROBE# HostBusy
Description
used reverse data transfer. Host nibble mode handshake signal. indicate host ready nibble. high indicate nibble been received. high when host 1284 transfer mode. used reverse data transfer. indicate valid nibble data, high response "HostBusy" going high. Used Data Bit-3, then Bit-7. Used Data Bit-2, then Bit-6. Used Data Bit-1, then Bit-5. Used Data Bit-0, then Bit-4. used.
SELCTIN# INIT# ACK#
1284Active INIT# PtrClk
BUSY SELECT ERR# PD0-PD7
PtrBusy AckDataReq Xflag DataAvail#
Table Nibble Mode Signal Description
Rev. P1.00
Nibble Mode Data Transfer Cycle
XR16C872
Host signals ability take data asserting HostBusy low. Peripheral responds placing first nibble status lines. Peripheral signals valid nibble asserting PtrClk low. Host sets HostBusy high indicate that received nibble ready another nibble. Peripheral sets PtrClk high acknowledge host.
Signal Name STROBE# AUTOFD#
Signal Type
mode Name Write# DataStb#
Description
Active low. Indicates write operation, high read cycle. Active low. Indicates Data-Read Data-Write operation process. Active low. Indicates Address-Read Address-Write operation process. Active low. Peripheral reset. Peripheral interrupt. Used generate interrupt host. Handshake signal. When indicates that okay start cycle, when high indicates that okay cycle. used. used. used. Bi-directional address data lines.
SELCTIN#
AddrStb#
INIT# ACK# BUSY
Reset# Intr# Wait#
SELECT ERR# PD0-PD7
User defined User defined User defined AD0-AD7
Table Mode Signal Description
Mode Data Transfer Cycle Program executes write cycle Data Port-4. Write# line asserted data output parallel port. DataStb# asserted, since Write# asserted low. port waits acknowledge from peripheral, Write# deasserted. DataStr# deasserted cycle ends. Write# asserted indicate that next cycle begin.
Rev. P1.00
XR16C872
Signal Name STROBE# Signal Type mode Name HostClk
Description
Used with PeriphAck transfer data address information forward direction. Provides Command Data status forward direction. Used with PeriphClk transfer data reverse direction. high when host 1284 transfer mode. Driven channel reverse direction. Used with HostAck transfer data reverse direction. Used with HostClk transfer data address information forward direction. Provides Command Data status reverse direction. Driven acknowledge ReverseRequest. Extensibility flag. peripheral indicate that reverse available. Bi-directional data lines.
AUTOFD#
HostAck
SELCTIN# INIT# ACK# BUSY
1284Active ReverseReq# PeriphClk PeriphAck
SELECT ERR# PD0-PD7
AckReverse# Xflag PeriphReq# D0-D7
Table Mode Signal Description
Mode Forward Data Command Transfer Cycle Host places data data lines indicates data cycle setting HostAck high. Host asserts HostClk indicate valid data. Peripheral acknowledge host setting PeriphAck high. Host sets HostClk high. This edge that should used clock data peripheral. Peripheral sets PeriphAck indicate that ready next byte. cycle repeats, this time command cycle because HostAck low. Mode Reverse Data Command Transfer Cycle Host requests reverse channel transfer setting ReverseReq# low. peripheral signals that okay proceed setting AckReverse# low. peripheral places data data lines indicates data cycle setting PeriphAck high. Peripheral asserts PeriphClk indicate valid data. Host acknowledges setting HostAck high. Peripheral sets PeriphClk high. This edge that should used clock data host. Host sets HostAck indicate that ready next byte. cycle repeats, this time Command cycle because PeriphAck low.
Rev. P1.00
UART Registers Reset Conditions
Register FCTR Xon-1 Xon-2 Xoff-1 Xoff-2 EMSR Reset State 0xXX, X=random 0xXX, X=random 0x00 0x00 0x01 0x00 0x00 0x60 0xX0, X=state input pins 0xFF 0xXX, X=random 0xXX, X=random 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
XR16C872
Output Signals RTS# DTR#
Reset State
logic logic logic
1284 Controller Register Reset Conditions
Register ECP-AFIFO EPP-APort EPP-DPortA EPP-DPortB EPP-DPortC EPP-DPortD CONF-A CONF-B Reset State
0xXX, X=state input pins 0-4=0
0-7=0 0-5=0 0x95
Rev. P1.00
XR16C872
A0-A15
Valid
Address
T3AS T5RD IOR# Active
T4AH
T6DY
T8DH T7DA
D0-D7
Valid
Data
XR872RD
Figure Read Timing
T1CW
T1CW
EXTERNAL CLOCK
T2FQ
Figure External Clock Timing
Rev. P1.00
XR16C872
A0-A15
Valid
Address T4AH
T3AS T9WR IOW# T6DY
Active
T10DS
T11DH
D0-D7
Valid Data XR872WR
Figure Write Timing
IOW#
Active
T12D RTS# DTR# Outputs Change state Change state
CTS# DSR# Inputs T13D
Change state
Change state T13D
Active T14D
Active
Active
IOR# Active Active Active
T13D Change state XR872MD
Figure Modem Input/Output Timing
Rev. P1.00
XR16C872
START
STOP
DATA BITS (5-8)
PARITY NEXT DATA START T15D
DATA BITS
DATA BITS
DATA BITS Active T16D IOR#
BAUD RATE CLOCK XR872RX
Figure Receive Data Timing Mode
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Data fills FIFO
FIFO fills Trigger Level Characters Delay
Active
Receive Data Time-Out
Receive Data Ready
IOR#
Unload FIFO Data XR872RFIFO
Figure Receive Data Timing FIFO Mode
Rev. P1.00
Active
Byte
(THR Empty Interrupt) Active T18D IOW# Active T19D
XR16C872
Active
T17D Active
Active
Active
D0-D7
Data Byte
Data Byte
Data Byte
START DATA BITS (5-8)
PARITY
STOP NEXT DATA START
DATA BITS
DATA BITS
DATA BITS
BAUD RATE CLOCK XR872TX
Figure Transmit Data Timing
(THR Empty Interrupt)
IOW#
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Data Fills FIFO
Sent FIFO Gets Empty Trigger Level
FIFO Gets More Data XR872TFIFO
Figure Transmit FIFO Operation
Rev. P1.00
Byte
XR16C872
Character
Data Bits Start Stop
Time
IRTX Time 3/16 Time
Figure Infrared Transmit Timing
IRRX
Time Clock Delay
Start
Data Bits
Stop
Character XR16IR
Figure Infrared Receive Timing
Rev. P1.00
XR16C872
IOW# PD0-7
ACK# IRQx
7836SPP
Figure Parallel Port Timing SPP, PS/2 Mode
DRQx
DACKx#
IOW#, IOR# 7836DMA
Figure Host Timing Mode
Rev. P1.00
XR16C872
PD0-PD7 STROBE#
BUSY
7836PPF
Figure Parallel Port FIFO Timing
PD0-7
AUTOFD# STROBE# BUSY
7836ECF
Figure Parallel Port Forward Timing Mode
Rev. P1.00
XR16C872
PD0-7
BUSY ACK# AUTOFD# 7836ECR
Figure Parallel Port Reverse Timing Mode
A0-2, D0-D7 IOW# IOCHRDY 7836EPW
Figure Address Data Write Timing Mode
Rev. P1.00
XR16C872
A0-2, D0-D7 IOR# IOCHRDY 7836EPR
Figure Address Data Read Timing Mode
Rev. P1.00
XR16C872
Rev. P1.00
XR16C872
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed accuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 1999 EXAR Corporation Datasheet June 1999 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. P1.00
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