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XRT8001 Clock August 1999-3 FEATURES APPLICATIONS


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XRT8001
XRT8001 Clock
August 1999-3
FEATURES
APPLICATIONS
Programmable Output Frequencies Generates Output Clock Frequencies Ranging
From 56kHz 16.384MHz Power Operation (3.3V Lock Detect Indication Cascadable External Components Needed Compatible with XRT8000 Device Operates Over Industrial Temperature Range Available 18-Pin PDIP SOIC Package
DSU's, CSU's Access Equipment ISDN Terminals Concentrators Multiplexers
GENERAL DESCRIPTION XRT8001 Clock dual-phase-locked loop chip that generates very jitter output clock signals that used synchronization applications wide area networking systems. XRT8001 Clock device configured operate modes: Forward/Master Mode Reverse/Master Mode "Fractional T1/E1" Reverse/Master Mode Forward/Master" Mode "High Speed Reverse" Mode "Slave" Mode
These modes briefly discussed pages
ORDERING INFORMATION
Part Number XRT8001IP XRT8001ID
Package 18-Lead PDIP 18-Lead JEDEC SOIC
Operating Temperature Range -40°C +85°C -40°C +85°C
Rev. P1.00
EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017 www.exar.com
XRT8001
Analog Phase Locked Loop
Post Divider
Driver
CLK2
Feedback Divider
PLL2
LDETDIS1 LDETDIS2 Lock Detector LOCKDET
SYNC
Input Divider
Analog Phase Locked Loop
Post Divider
Driver
CLK1
Feedback Divider 100K
PLL1
100K
SCLK Serial Interface Mode Frequency Select Control
Figure XRT8001 Block Diagram
Rev. P1.00
XRT8001 DEVICE
XRT8001
SYNC CLK1
SCLK
XRT8001
CLK2 LOCKDET
DESCRIPTION
Name Type Description Serial Data Output from Microprocessor Serial Interface This will serially output contents specified Command Register, during "Read" Operations. data, this pin, will updated falling edge SCLK input signal. This will tristated upon completion data transfer. Sync Output XRT8001 will typically output 8kHz clock signal this output pin. However, when XRT8001 Device operating "High Speed Reverse" Mode, then this device will simply output 64kHz clock signal. Reference Clock Input Reference Timing signal (from which CLK1 CLK2 output signals derived) input this pin. Digital Ground Digital Ground Clock Output XRT8001 device will drive desired "synthesized" signal this output pin. This output signal will have 50+5% duty cycle.
SYNC
CLK1
Note: This output tri-stated unless "CLK1EN" bit-field (within Command Register CR4) been "1".
Digital Power Supply
Rev. P1.00
XRT8001
DESCRIPTION (CONT'D)
Name Type
Description Master/Slave Mode Select Input Setting this input "HIGH" configures XRT8001 device operate "MASTER" Mode. Conversely, setting this input "LOW" configures XRT8001 device operate "SLAVE" Mode. Analog Ground Analog Power Supply Lock Detect Output This output indicates whether "selected" internal PLL(s) "in-lock" "out-of-lock". default, this output "high" when both PLLs in-lock" will toggle "low" either PLLs "out-of-lock". However, XRT8001 device also permits user configure this output reflect state PLLs within chip. (See Table
LOCKDET
CLK2
Digital Power Supply Clock Output XRT8001 device will drive desired "synthesized" signal this output pin. This output signal will have 50+5% duty cycle.
Note: This output tri-stated unless "CLK1EN" bit-field (within Command Register CR4) been "1".
Digital Ground Digital Power Supply Microprocessor Serial Interface Serial Data Input Whenever, user wishes read write data into Command Registers, over Microprocessor Serial Interface, user expected apply "Read/Write" bit, Address Values Command Registers) Data Value written (during "Write" Operations) this pin. This input will sampled rising edge SCLK (pin 18). Microprocessor Serial Interface Chip Select Input: Local Microprocessor must assert this (e.g., "0") order enable communication with XRT8001 Microprocessor Serial Interface.
Note: This internally pulled "high".
SCLK Microprocessor Serial Interface-Clock Signal This signal will used sample data, pin, rising edge this signal. Additionally, during "Read" operations, Microprocessor Serial Interface will update output falling edge this signal.
Rev. P1.00
ELECTRICAL CHARACTERISTICS (Except Microprocessor Serial Interface)
Symbol Parameter Input Level Input High Level Output Level (CLK1, CLK2) Output High Level (CLK1, CLK2) Output Level (LOCKDET, SYNC) Output High Level (LOCKDET, SYNC) Input Current (CSB, MSB) Input High Current (CSB, MSB) Input Current (except CSB, MSB) Input High Current (except CSB, MSB) Operating Current Internal Pull-up Resistance (CSB, MSB) Min. -150 Typ. Max. Units
XRT8001
Condition
-6.0mA 6.0mA -3.0mA 3.0mA Load, CLk1, CLK2 2.048MHz
ELECTRICAL CHARACTERISTICS (See Figure 2A.)
Symbol
Parameter Input Frequency Minimum Input Signal "High" "Low" Duration Output Frequency Duty Cycle Jitter Added 8kHz 40kHz Jitter Added 10Hz 40kHz Broadband Jitter Jitter Added 20Hz 100kHz Jitter Added 18kHz 100kHz Capture Time Clock Output Rise Time Clock Output Fall Time SYNC Output Signal Duty Cycle SYNC Ouput Signal Cycle SYNC Output Signal Cycle Delay Time between rising edge SYNC Rising edge CLK1 CLK2
Min. 47.5
Typ.
Max.
Units
Conditions
16.384 52.5 10ns 10ns
30pF load measured 20/80% 30pF load measured 20/80% VCC/2 switch point VCC/2 switch point, 30pF Load Output =1.544MHz (0.025 Output 1.544MHz (0.025 UI)3 Output 1.544MHz (0.05 Output 2.048MHz (1.5
Output 2.048MHz (0.2 UI)3
t-20
t+20
Table values
Notes:
(t12 t13)
Specifications from AT&T Publication 62411 ITU-T Recommendations G-823 (for 1.544MHz (2.048MHz, respectively). guaranteed characterization, tested.
Rev. P1.00
XRT8001
ELECTRICAL CHARACTERISTICS (CONT'D)
Symbol
Parameter Rising Edge SCLK Setup Time High Rising Edge SCLK Hold Time Rising Edge SCLK Setup Time Rising Edge SCLK Hold Time SCLK "Low" Time SCLK "High" Time SCLK Period Rising Edge SCLK Hold Time "Inactive" Time Falling Edge SCLK Valid Time Falling Edge SCLK Invalid Time Falling Edge SCLK, rising edge High Rise/Fall time Output
Min.
Typ.
Max.
Units
Microprocessor Serial Interface Timing (see Figure 2B.)
Specifications subject change without notice
ABSOLUTE MAXIMUM RATINGS Supply Range Voltage -0.3V Vcc+0.3V
Operating Temperature. 40°C +85°C Storage Temperature 40°C +85°C Package Dissipation 500mW
Rev. P1.00
XRT8001
Figure Timing Diagram Clocks
SCLK
SCLK
Hi-Z
Hi-Z
Figure Timing Diagram Microprocessor Serial Interface
Rev. P1.00
XRT8001
Forward/Master Mode
Forward/Master Mode, XRT8001 Device will accept either 1.544MHz" 2.048MHz" clock signal input (where: 16). From this "reference signal" XRT8001 device will generate either 56kHz" 64kHz" clock signal (where: 32).
Figure presents simple illustration XRT8001 Clock device operating "Forward Master/ Mode."
1.544MHz 2.048MHz Where
CLK1
56kHz 64kHz Where
XRT8001 Clock
XRT8001 Clock
CLK2
56kHz 64kHz Where
Figure Illustration XRT8001 Clock Device Operating Forward/Master Mode
Rev. P1.00
Reverse/Master Mode Reverse/Master Mode, XRT8001 Device will accept either 56kHz 64kHz clock signal input pin, will generate either 1.544MHz 2.048MHz clock signal Clock Output signals.
XRT8001
Figure presents simple illustration XRT8001 Clock device operating "Reverse/Master Mode."
56kHz 64kHz
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Device Operating Reverse/Master Mode
Rev. P1.00
XRT8001
Fractional T1/E1 Reverse/Master Mode Fractional T1/E1 Reverse/Master Mode, XRT8001 Device will accept either 56kHz" 64kHz" clock signal input (where: 32). From this "reference signal" XRT8001 device will generate either 1.544MHz 2.048MHz clock signal. Figure presents simple illustration XRT8001 Clock device operating "Fractional T1/E1 Reverse/Master" Mode.
56kHz 64kHz Where:
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Device Operating "Fractional T1/E1 Reverse/Master" Mode
Rev. P1.00
Forward/Master" Mode Forward/Master" Mode, XRT8001 Device will accept 2.048MHz" clock signal "Reference Clock Input" (FIN), will output "1.544MHz" clock signal CLK1 and/or CLK2 output pins.
Note: value range between
XRT8001
Figure presents simple illustration XRT8001 Clock device operating Forward/Master" Mode.
2.048MHz Where:
CLK1
1.544MHz
XRT8001 XRT8001 Clock
CLK2
1.544MHz
Figure Illustration XRT8001 Clock Device Operating Forward/Master" Mode
Rev. P1.00
XRT8001
"High Speed Reverse" Mode
"High Speed Reverse" Mode, XRT8001 Device will accept 64kHz clock signal "Reference Clock Input" (FIN), will output 2.048MHz" clock signal (where equal CLK1 and/or CLK2 output pins.
Note: XRT8001 Device will accept sythesze these clock frequencies independent whether been configured operate "Master" "Slave" Modes.
Figure presents simple illustration XRT8001 Clock device operating "High Speed Reverse" Mode.
64kHz
CLK1
2.048MHz
XRT8001 Clock
2.048MHz CLK2
Figure Illustration XRT8001 Clock Device Operating "High Speed Reverse" Mode
Rev. P1.00
XRT8001
"Forward/Slave" Mode "Forward/Slave" Mode, XRT8001 device will accept 8kHz clock signal Reference Clock Input (FIN), will output 64kHz 56kHz" clock signal (where range from CLK1 CLK2 output pins. Figure presents simple illustration XRT8001 Clock device operating "Forward/Slave" Mode.
8kHz
CLK1
56kHz 64kHz Where
XRT8001 Clock
CLK2
56kHz 64kHz Where
Figure Illustration XRT8001 Clock Device Operating "Forward/Slave" Mode
Rev. P1.00
XRT8001
SYSTEM DESCRIPTION
Description Command Registers Address "On-Chip" Command Registers
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
Command Register
Type
IOC4 SEL14 SEL24 SYNCEN Reserved Reserved Reserved
IOC3 SEL13 SEL23 CLK1EN Reserved Reserved Reserved
Register Bit-Format IOC2 SEL12 SEL22 CLK2EN Reserved Reserved Reserved
IOC1 SEL11 SEL21 LDETDIS2 Reserved Reserved Reserved
PL1EN PL2EN SEL10 SEL20 LDETDIS1 Reserved Reserved Reserved
Command Register Description
1.2.1 Command Register (Address 0x00)
(Configuration Mode Select Bits) These four-bit fields permit user select which mode XRT8001 Device will operate Specifically, these four bit-fields make following configuration selections: Whether XRT8001 Device will operating "Forward/Master", "Reverse/Master", "Fractional T1/E1 Reverse/Master", Forward/Master" "High Speed Reverse" Modes. What kind input signals applied Reference Clock Input (FIN). What kind signals will output CLK1 CLK2 output pins. Table relates value these four bit-fields four Master Modes Table relates three Slave Modes XRT8001 Device.
Rev. P1.00
D[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Mode Forward/Master Forward/Master Forward/Master Reverse/Master Forward/Master Forward/Master Forward/Master Reverse/Master Forward/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master Fract. T1/E1 Reverse/Master High Speed Reverse Reserved Reserved Input Frequency input) 1.544MHz 1.544MHz 1.544MHz 56kHz 2.048MHz 2.048MHz 2.048MHz 64kHz 2.048MHz 56kHz 56kHz 64kHz 64kHz Reserved Reserved CLK1 Output Signal 56kHz 56kHz 64kHz 1.544MHz 56kHz 56kHz 64kHz 1.544MHz 1.544MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz 2.048MHz Reserved Reserved
XRT8001
CLK2 Output Signal 56kHz 64kHz 64kHz 2.048MHz 56kHz 64kHz 64kHz 2.048MHz 1.544MHz 2.048MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz Reserved Reserved
Table Relationship between value (within Command Register CR0) Operating Modes XRT8001 Clock Device Master Modes
D[4:1] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mode Forward/Slave Forward/Slave Forward/Slave Reverse/Slave Forward/Slave Forward/Slave Forward/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave Reverse/Slave High Speed Reverse Reserved Reserved
Input Frequency input) 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 8kHz 64kHz Reserved Reserved
CLK1 Output Signal 56kHz 56kHz 64kHz 1.544MHz 56kHz 56kHz 64kHz 1.544MHz 1.544MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz 2.048MHz Reserved Reserved
CLK2 Output Signal 56kHz 64kHz 64kHz 2.048MHz 56kHz 64kHz 64kHz 2.048MHz 1.544MHz 2.048MHz 1.554MHz 1.544MHz 2.048MHz 2.048MHz Reserved Reserved
Table Relationship between value (within Command Register CR0) Operating Modes XRT8001 Clock Device Slave Modes
Rev. P1.00
XRT8001
PL1EN (PLL Enable Select)
1.2.3 Command Register (Address 0x02) (SEL1[4:0]) These bit-fields used support configuration implementation both "Forward/Master", "Fractional T1/E1 Reverse/Master" "High Speed Reverse" Modes. Forward/Master Mode
This bit-field permits user enable disable within XRT8001 Clock Device. Setting this bit-field enables Frequency Synthesis. Conversely, setting this bit-field disables Frequency Synthesis. 1.2.2 Command Register (Address 0x01) These bit-fields used support configuration implementation both "Forward/Master" Forward/Master" Modes. both "Forward/ Master" Forward/Master" Modes, XRT8001 Clock device will receiving either 1.544MHz" 2.048MHz" clock signal. through bit-fields, within this register, permit user specify value "N". consequence, XRT8001 device configured accept maximum frequency 1.544MHz" 2.048MHz". PL2EN (PLL Enable Select) This bit-field permits user enable disable within XRT8001 Clock Device. Setting this bit-field enables Frequency Synthesis. Conversely, setting this bit-field disables Frequency Synthesis.
"Forward/Master" Mode, XRT8001 Clock will output either 56kHz" 64kHz" clock signal CLK1 output pin. These five bitfields within Command Register used define value CLK1 Output. consequence, XRT8001 device configured generate maximum frequency 56kHz" 64kHz" CLK1 output pin. "Fractional T1/E1 Reverse/Master" Mode "Fractional T1/E1 Reverse/Master" Mode, XRT8001 Clock will receiving either 56kHz" 64kHz" clock signal "FIN" input pin. XRT8001 Clock device will, response, generate either 1.544MHz 2.048MHz clock signal CLK1 and/or CLK2 output pins. These five bit-fields used define value "P". consequence, XRT8001 device configured accept maximum frequency 56kHz" 64kHz".
Rev. P1.00
"High Speed Reverse" Mode "High Speed Reverse" Mode, XRT8001 Clock will receiving 64kHz clock signal "FIN" input pin. XRT8001 Clock device will, response, generate 2.048MHz" clock CLK1 CLK2 output pins. These five bitfields within Command Register used define value CLK1 output.
Note: only acceptable values
XRT8001
1.2.5 Command Register (Address 0x04) SYNCEN (SYNC Output Driver Enable Select) This "read/write" bit-field permits user enable disable Driver associated with SYNC output pin. Setting this bit-field enables this Driver. Setting this bit-field disables this Driver. CLK1EN (CLK1 Output Driver Enable Select) This "read/write" bit-field permits user enable disable Driver associated with CLK1 output pin. Setting this bit-field enables this Driver. Setting this bit-field disables this Driver. CLK2EN (CLK2 Output Driver Enable Select) This "read/write" bit-field permits user enable disable Driver associated with CLK2 output pin. Setting this bit-field enables this Driver. Setting this bit-field disables this Driver. LDETDIS[2:1] Lock Detector Output Control combination these bit-fields permit user specify signal that will output LOCKDET output pin. user's options shown Table
1.2.4 Command Register (Address 0x03) (SEL2[4:0]) These bit-fields used support configuration implementation "Forward/Master" "High Speed Reverse" Modes operation. "Forward/Master" Mode "Forward/Master" Mode, XRT8001 Clock will output either 56kHz" 64kHz" clock signal CLK2 output pin. These five bitfields within Command Register used define value CLK2 Output. consequence, XRT8001 device configured generate maximum frequency 56kHz" 64kHz" CLK2 output pin. "High Speed Reverse" Mode "High Speed Reverse" Mode, XRT8001 Clock will receiving 64kHz clock signal "FIN" input pin. XRT8001 Clock device will, response, generate 2.048MHz" clock CLK1 CLK2 output pins. These five bitfields within Command Register used define value CLK2 output.
Note: only acceptable values
Rev. P1.00
XRT8001
LDETDIS[2:1]
Signal output LOCKDET Signal LOCK Condition PLL1 PLL2 With this selection, LOCKDET output will "high" either following conditions true. both PLL1 PLL2 "LOCK" condition, (applies both PLL1 PLL2 enabled) only enabled "LOCK" condition (applies only PLLs enabled). LOCK Condition PLL2 Only With this selection, only "LOCK" state PLL2 will reflected LOCKDET output pin. LOCKDET "high" PLL2 "LOCK". LOCKDET "low" PLL2 "LOCK". LOCK Condition PLL1 Only With this selection, only "LOCK" state PLL1 will reflected LOCKDET output pin. LOCKDET "high" PLL1 "LOCK". LOCKDET "low" PLL1 "LOCK". LOCKDET will unconditionally pulled "LOW"
Table Relationship Between Values LDETDIS[2:1] Bit-Fields Meaning LOCKDET Output Signal
Instructions Configuring XRT8001 Clock Device mentioned earlier, XRT8001 Clock Device configured operate following modes:
"Forward/Master" Mode "Reverse/Master" Mode "Fractional T1/E1 Reverse/Master" Mode Forward/Master" Mode "High Speed Reverse" Mode "Forward/Slave" Mode
"Forward/Master" Mode. When XRT8001 Clock Device been configured operate "Forward/Master" Mode, then will accept 1.544MHz" 2.048MHz" clock signal "Reference Clock" input (pin where range anywhere between response this clock signal, XRT8001 Clock Device will output either 56kHz" 64kHz" clock signal, Clock Output pins (CLK1 and/or CLK2). simple illustration XRT8001 Clock device, operating "Forward/Master" Mode shown figure
detailed description operation configuration steps each these configurations follows.
Rev. P1.00
XRT8001
1.544MHz 2.048MHz Where
CLK1
56kHz 64kHz Where
XRT8001 Clock
CLK2
56kHz 64kHz Where
Figure Illustration XRT8001 Clock Device Operating "Forward/Master" Mode
Configuring XRT8001 Clock Device into "Forward/Master" Mode user configure XRT8001 Clock Device operate "Forward/Master" Mode, executing following steps:
Step Configure XRT8001 device operate "MASTER" Mode, pulling (pin VDD. Step Review Table determine which combination "Input Frequency" "Output Frequencies" (via PLL1 PLL2) correlate with desired configuration.
PLL2 Output Frequency 56kHz 64kHz 64kHz 56kHz 64kHz 64kHz Value Write D4-D1 0000 0001 0010 0100 0101 0110
Input Frequency 1.544MHz 1.544MHz 1.544MHz 2.048MHz 2.048MHz 2.048MHz
PLL1 Output Frequency 56kHz 56kHz 64kHz 56kHz 56kHz 64kHz
Table Listing "Input Frequency "Output Frequency" Cases "Forward/Master" Mode Operation
Rev. P1.00
XRT8001
order specify value "K", needs write value binary format) into Command Register CR2, illustrated below.
Command Register, (Address 0x02)
SEL14 SEL13 SEL12 SEL11 SEL10 Value Binary Format).
Step Upon reviewing Table write listed value (under "Value Write CR0" Register) into through bit-fields within Command Register CR0, illustrated below.
Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 Value Write PL1EN
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0.
example, wishes configure XRT8001 device output clock signal either "56kHz" "64kHz" (e.g., where CLK1 output pin, then he/she should write value "0", into Command Register CR2.
This step configures XRT8001 device operate "Forward/Master" Mode.
Step Specify value (e.g., 56kHz" 64kHz" clock signal which output CLK2 output signal).
order specify value "K", needs write value (binary format) into Command Register CR3, illustrated below.
Step Next, need specify value (e.g., 1.544MHz" 2.048MHz" clock signal which applied "FIN" input pin.)
order specify value "N", needs write value binary format) into through bits within Command Register CR1, illustrated below. Command Register, (Address 0x01)
Value Binary Format) PL2EN
Command Register, (Address 0x03)
SEL24 SEL23 SEL22 SEL21 SEL20 Value Binary Format).
example, user wishes configure XRT8001 device accept 1.544MHz clock signal, "FIN" input (e.g., then user should write value "0", into Command Register CR1.
Note: user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
example, wishes configure XRT8001 device output clock signal either "1.792MHz" "2.048MHz" (e.g., where CLK2 output pin, then he/she should write value "31" binary format) into Command Register CR3.
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET". This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below.
Command Register CR4, (Address 0x04)
SYNCEN
Step Specify value (e.g., 56kHz" 64kHz" clock signal which output CLK1 output signal).
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
Note: information "LDETDIS1" "LDETDIS2" bit-fields, please Table
Rev. P1.00
"Reverse/Master" Mode When XRT8001 Clock Device been configured operate "Reverse/Master" Mode, then will accept either "56kHz" "64kHz" clock signal "Reference Clock" input (pin response this clock signal, XRT8001 Clock Devicewill output either "1.544MHz" "2.048MHz" clock signal, Clock Output pins (CLK1 and/or CLK2).
XRT8001
simple illustration XRT8001 Clock device, operating "Reverse/Master" Mode presented Figure
56kHz 64kHz
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Device operating "Reverse/Master" Mode
Configuring XRT8001 Clock Device into "Reverse/Master" Mode user configure XRT8001 Clock Device operate "Reverse/Master" Mode, executing following steps:
Step Review Table determine which combination "Input Frequency" "Output Frequencies" (via PLL1 PLL2) correlate with desired configuration.
Step Configure XRT8001 Device operate "MASTER" Mode pulling "MSB" (pin VDD. Rev. P1.00
XRT8001
Input Frequency 56kHz 64kHz
PLL1 Output Frequency 1.544MHz 1.544MHz PLL2 Output Frequency 2.048MHz 2.048MHz Value Write 0011 0111
Table Listing "Input Frequency" "Output Frequency" Cases "Reverse/Master" Mode Operation
Step Upon reviewing Table write listed value (under "Value Write CR0" register) into through bit-fields within Command Register CR0, illustrated below:
Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 Value Write PL1EN
Step Enable following output signals appropriate: SYNC", CLK1, CLK2 LOCKDET. This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below:
Command Register CR4, (Address 0x04)
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0.
Note: information "LDETDIS1" "LDETDIS2" bit-fields, please Table
This step configures XRT8001 device operate "Reverse/Master" Mode. Step Write into "PL2EN" bit-field within Command Register wish output clock signal "CLK2" output pin), illustrated below:
Command Register, (Address 0x01)
Don't Care PL2EN
"Fractional T1/E1 Reverse/Master" Mode When XRT8001 Clock Device been configured operate "Fractional T1/E1 Reverse/Master" Mode, then will accept either 56kHz" 64kHz" clock signal "FIN" input (pin response, XRT8001 device will output either 1.544MHz 2.048MHz clock signal CLK1 and/or CLK2 outputs. simple illustration XRT8001 Clock device, operating "Fractional T1/E1 Reverse/ Master" Mode presented Figure
Notes: value through bit-fields within Command Register, "Don't Care". contents Command Registers "Don't Care".
Rev. P1.00
XRT8001
56kHz 64kHz Where:
CLK1
1.544MHz 2.048MHz
XRT8001 XRT8001 Clock Clock
CLK2
1.544MHz 2.048MHz
Figure Illustration XRT8001 Clock Device Operating "Fractional T1/E1 Reverse/Master" Mode
Configuring XRT8001 Clock Device into "Fractional T1/E1 Reverse/Master" Mode user configure XRT8001 Clock device operate "Fractional T1/E1 Reverse/ Master" Mode executing following steps.
Step Review Table determine which combination "Input Frequency" "Output Frequencies" (via PLL1 PLL2) correlate with desired configuration.
Step Configure XRT8001 Device operate "MASTER" Mode, pulling "MSB" input (pin VDD.
Input Frequency 56kHz 56kHz 64kHz 64kHz PLL1 Output Frequency 1.544MHz 1.544MHz 2.048MHz 2.048MHz PLL2 Output Frequency 2.048MHz 1.544MHz 1.544MHz 2.048MHz Value Write 1001 1010 1011 1100
Table Listing "Input Frequency" "Output Frequency" Cases "Fractional T1/E1 Reverse/Master" Mode Operation
Rev. P1.00
XRT8001
Step Write binary expression "11111" into Command Register CR3.
This step necessary order insure proper operation XRT8001 Device. This step also illustrated below:
Command Register, (Address 0x03)
SEL24 SEL23 SEL22 SEL21 SEL20
Step Upon reviewing Table write listed value (under "Value Write CR0" register) into through bit-fields within Command Register CR0, illustrated below:
Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 Value Write PL1EN
Notes: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0. contents bit-fields through (within Command Register CR1) "Don't Care" user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET".
This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below:
Command Register CR4, (Address 0x04)
SYNCEN
This step configures XRT8001 device operate "Fractional T1/E1 Reverse/Master" Mode.
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
Step Specify value (e.g., 56kHz" 64kHz" clock signal which input Reference Clock input).
order specify value "P", needs write value (binary format) into Command Register CR2, illustrated below:
-Forward/Master" Mode When XRT8001 Clock Device been configured operate Forward/ Master" Mode, then will accept 2.048MHz" clock signal "Reference Clock" input (pin where range anywhere between response this clock signal, XRT8001 Clock device will output 1.544MHz clock signal Clock Output pins (CLK1 and/or CLK2). simple illustration XRT8001 Clock device, operating Forward/Master" Mode presented Figure
Command Register, (Address 0x02)
SEL14 SEL13 SEL12 SEL11 SEL10 Value Binary Format).
other words, intends input either "56kHz" "64kHz" clock signal "FIN" input (e.g., where then he/she should write into Command Register CR2.
Rev. P1.00
XRT8001
2.048MHz Where:
CLK1
1.544MHz
XRT8001 XRT8001 Clock
CLK2
1.544MHz
Figure Illustration XRT8001 Clock Device Operating Forward/Master" Mode Configuring XRT8001 Clock Device into Forward/Master" Mode user configure XRT8001 Clock Device operate Forward/Master" Mode executing following steps: This step configures XRT8001 Clock device operate Forward/ Master" Mode.
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register, CR0.
Step Configure XRT8001 Device operate "MASTER" Mode, pulling "MSB" input (pin VDD. Step Write binary value "1000" into Command Register CR0, illustrated below:
Step Next, need specify value *(e.g., 2.048MHz" clock signal which will applied "FIN" input pin).
user accomplishes this writing binary expression into Command Register, CR1, illustrated below.
Command Register, (Address 0x01)
Value Binary Format) PL2EN
Command Register (Address 0x00)
IOC4 IOC3 IOC2 IOC1 PL1EN
Rev. P1.00
XRT8001
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET".
This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below.
Command Register CR4, (Address 0x04)
SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
example, user wishes input clock signal 2.048MHz, "FIN" input (e.g., where then he/she should write into Command Register CR1.
Note: user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
Step Write binary expression "11111" into Command Register CR2, illustrated below. This step necessary order insure proper operation XRT8001 Device. This step also illustrated below:
"High Speed Reverse" Mode
Command Register, (Address 0x02) SEL14 SEL13 SEL12 SEL11 SEL10
Step Write binary expression "11111" into Command Register CR3, illustrated below. This step necessary order insure proper operation XRT8001 Device. This step also illustrated below.
When XRT8001 Clock Device been configured operate "High Speed Reverse" Modes, operation independent whether been configured "Master" "Slave" Mode. When XRT8001 Clock Device been configured operate "High Speed Reverse" Modes, then will accept "64kHz" clock signal "Reference Clock" input (pin response, this clock signal, XRT8001 Clock Device will output 2.048MHz" clock signal Clock Output pins (CLK1 and/or CLK2); where only have values simple illustration XRT8001 Clock Device, operating "High Speed Reverse" Mode presented Figure
Command Register, (Address 0x03) SEL24 SEL23 SEL22 SEL21 SEL20
Rev. P1.00
XRT8001
64kHz
CLK1
2.048MHz
XRT8001 Clock
2.048MHz CLK2
Figure Illustration XRT8001 Clock Device Operating "High Speed Reverse" Mode
Configuring XRT8001 Clock Device into "High Speed Reverse" Mode. user configure XRT8001 Clock Device operate "High Speed Reverse" Mode, executing following steps.
Step Write binary expression "0000" into bitfields through within Command Register, CR1, illustrated below.
Command Register, (Address 0x01) PL2EN
Note: user wishes output clock signal CLK2 output signal, then he/she should also write into "PL2EN" bit-field within Command Register CR1.
Step Configure XRT8001 Device operate "SLAVE" Mode, pulling "MSB" input (pin GND.
Command Register (Address 0x00) IOC4 IOC3 IOC2 IOC1 PL1EN
Note: user wishes output clock signal CLK1 output signal, then he/she should also write into "PL1EN" bit-field within Command Register CR0.
Step Specify value (e.g., 2.048MHz" clock signal) which output "CLK1" output pin.
This accomplished reviewing Table determining binary value which corresponds with desired value "M". Afterwards, user should write this value into Command Register CR2.
This step configures XRT8001 device operate "High Speed Reverse" Mode.
Rev. P1.00
XRT8001
Value
Command Register, (Address 0x03)
SEL24 SEL23 SEL22 SEL21 Value from Table SEL20
Value Written into Command Register 0000X 0001X 001XX X1XX 1XXX
Table Relationship Between Value Value Written into Command Register Order Configure "CLK1" Output Frequency)
Note: expression indicates "Don't Care" value that particular bit-field.
Step Enable following output signals appropriate: "SYNC", "CLK1", "CLK2" "LOCKDET".
This accomplished writing into corresponding bit-fields, within Command Register CR4, illustrated below:
Command Register CR4, (Address 0x04)
Command Register, (Address 0x02)
SEL14 SEL13 SEL12 SEL11 Value from Table SEL10
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
"Forward/Slave" Mode
Step Specify value (e.g., 2.048MHz" clock signal) which output "CLK2" output pin.
This accomplished reviewing Table determining 5-bit binary value which corresponds with desired value "M". Afterwards, user should write this value into Command Register, CR3.
Value Value Written into Command Register 0000X 0001X 001XX X1XXX 1XXXX
When XRT8001 Clock Device been configured operate "Forward/Slave" Mode, then will accept 8kHz clock signal "Reference Clock" input (pin response this clock signal, XRT8001 Clock device will output either 56kHz" 64kHz" clock signal "Clock Output pins" (CLK1 CLK2); where range value from simple illustration XRT8001 Clock device operating "Forward/Slave" Mode" presented Figure
Table Relationship Between Value Value Written into Command Register Order Configure "CLK2" Output Frequency)
Note: expression indicates "Don't Care" value that particular bit-field.
Rev. P1.00
XRT8001
8kHz
CLK1
56kHz 64kHz
XRT8001 Clock
CLK2
56kHz 64kHz
Figure Illustration XRT8001 Clock Device operating "Forward/Slave" Mode
Configuring XRT8001 Clock Device into "Forward/Slave" Mode. user configure XRT8001 Clock device operate "Forward/Slave Mode" executing following steps:
STEP Define value CLK2 output writing appropriate value into register. This achieved writing value into this register.
Note: user intends output data CLK2, then must ensure that PL2EN bit-field within Command Register "1".
STEP Configure XRT8001 device operate "SLAVE" Mode pulling input (pin GND. STEP Refer Table write value that corresponds desired "Forward/Slave" Mode into Bits D[4:1] within Command Register CR0. STEP Define values CLK1 output writing appropriate value into register. This achieved writing value into this register.
Notes: example, user writes "00000" into this register, then XRT8001 device will output 64kHz signal CLK1 output pin. user intends output data CLK1, then he/she must ensure that PL1EN bit-field within Command Register "1".
STEP CLK1EN CLK2EN bit-fields, within Command Register order enable output drivers CLK1 CLK2, illustrated below. Command Register
SYNCEN CLK1EN CLK2EN
Rev. P1.00
XRT8001
Table presents information delay between rising edge SYNC CLK1 CLK2 output signals. important Note that this delay behaves function settings within register.
SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Values (nS) Kx56 MODE
Kx64 MODE
Table Delay Time Between SYNC CLK1 CLK2
Note: This table only applies when XRT8001 Device configured operate "Forward/Master" "Forward/Slave" Modes.
Rev. P1.00
Operating Microprocessor Serial Interface XRT8001 Serial Interface simple four-wire interface that compatible with many microcontrollers available market. This interface consists following signals: SCLK Chip Select (Active Low) Serial Clock Serial Data Input Serial Data Output
XRT8001
Bits Through Four Address Values (Labeled next four rising edges SCLK signal will clock 4-bit address value this particular Read Write) operation. address selects Command Register, within XRT8001 device, that user will either reading data from, writing data user must supply address bits input ascending order with (least significant bit) first. Bits next bits, must "0", shown Figure value "A6" "don't care". Once these first eight bits have been written into Microprocessor Serial Interface, subsequent action depends upon whether current operation "Read" "Write" operation. Read Operation Once last address (A3) been clocked into input, "Read" operation will proceed through idle period, lasting three SCLK periods. falling edge SCLK Cycle (see Figure serial data output signal (SDO) becomes active. this point user begin reading data contents addressed Command Register Address [A3, A0]) output pin. Microprocessor Serial Interface will output this 5-bit data word through ascending order (with first), falling edges SCLK pin. consequence, data output pin) will sufficiently stable reading Microprocessor), very next rising edge SCLK pin.
Using Microprocessor Serial Interface following instructions, using Microprocessor Serial Interface, best understood referring diagram Figure page order Microprocessor Serial Interface user must first provide clock signal SCLK input pin. Afterwards, user will initiate "Read" "Write" operation asserting "activelow" Chip Select input (CSB). important assert (e.g., toggle "low") least 50ns prior very first rising edge clock signal. Once input been asserted, type operation target register address must specified user. user provides this information Microprocessor Serial Interface writing eight serial bits data into input. Note: each these bits will "clocked" into input rising edge SCLK. These eight bits identified described below. "R/W" (Read/Write) This will clocked into input first rising edge SCLK (after been asserted). This indicates whether current operation "Read" "Write" operation. this specifies "Read" operation; whereas, this specifies "Write" operation.
Rev. P1.00
XRT8001
Write Operation
Once last address (A3) been clocked into input, "Write" operation will proceed through idle period, lasting three SCLK periods. Prior rising edge SCLK Cycle (see Figure user must begin apply 8-bit data word, that he/she wishes write Microprocessor Serial Interface,
onto input pin. Microprocessor Serial Interface will latch value input pin, rising edge SCLK. user must apply this word through serially, ascending order with first.
SCLK
High
Notes: always "0". "Read" Operations "Write" Operations Denotes "don't care" value
Figure Microprocessor Serial Interface Data Structure
Simplified Interface Option user simplify design circuitry connecting Microprocessor Serial Interface tying both pins together, reading data from and/or writing data this "combined" signal. This simplification possible because only these signals active given time. inactive signal will tri-stated.
Rev. P1.00
XRT8001
Rev. P1.00
XRT8001
Rev. P1.00
Preliminary Notes
XRT8001
Rev. P1.00
XRT8001
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed accuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 1999 EXAR Corporation Datasheet August 1999 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. P1.00

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