16-Bit Digital Signal Processor MSC8101RM/D Revision April 2001

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MSC8101 Reference Manual
16-Bit Digital Signal Processor
MSC8101RM/D Revision April 2001
StarCore, PowerQUICC OnCE, DigitalDNA, DigitalDNA logo trademarks Motorola, Inc. PowerPC name trademark International Business Machines Corporation used Motorola under license from International Business Machines Corporation.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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USA/EUROPE Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 JAPAN Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate N.T., Hong Kong 852-26668334 MOTOROLA INC. 2001 Home Page http://www.mot.com/SPS/DSP Helpline email: dsphelp@dsp.sps.mot.com
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Technical Information Center 1-800-521-6274
MSC8101 Overview SC140 Core Overview External Signals System Interface Unit (SIU) Reset Boot Clocks Memory Internal Memory System Reservation Operation Memory Controller QBus PowerPC System PowerPC System Signals Host Interface (HDI16) Direct Memory Access (DMA) Interrupt Scheme JTAG IEEE 1149.1 Test Access Port Enhanced Filter Coprocessor (EFCOP) Communications Processor Module Overview Serial Interface with Time-Slot Assigner Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels Serial Communications Controllers (SCCs) UART Mode HDLC Mode BISYNC Mode Transparent Mode Ethernet Mode AppleTalk Mode Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) AController Fast Ethernet Controller HDLC Controller Transparent Controller Serial Peripheral Interface (SPI) Controller Parallel Ports Programming Reference Glossary Bootloader Program Acronyms Abbreviations Index
MSC8101 Overview SC140 Core Overview External Signals System Interface Unit (SIU) Reset Boot Clocks Memory Internal Memory System Reservation Operation Memory Controller QBus PowerPC System PowerPC System Signals Host Interface (HDI16) Direct Memory Access (DMA) Interrupt Scheme JTAG IEEE 1149.1 Test Access Port Enhanced Filter Coprocessor (EFCOP) Communications Processor Module Overview Serial Interface with Time-Slot Assigner Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels Serial Communications Controllers (SCCs) UART Mode HDLC Mode BISYNC Mode Transparent Mode Ethernet Mode AppleTalk Mode Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) AController Fast Ethernet Controller HDLC Controller Transparent Controller Serial Peripheral Interface (SPI) Controller Parallel Ports Programming Reference Glossary Bootloader Program Acronyms Abbreviations Index
Contents
Part Overview
Chapter MSC8101 Overview
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.13 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.7.1 1.3.7.2 1.4.1 1.4.2 1.4.3 1.4.4 Target Markets. Features High-performance StarCore SC140 Core On-Device Memories. PowerPC System Eight-bank Memory Controller System Interface Unit On-Device Peripherals Engine Communications Processor Module (CPM) Separate PLLs SC140 Core, PowerPC Bus, Reduced Power Dissipation Packaging. Software Development Tools Hardware Development Tools Architecture SC140 Core SRAM System Interface Unit (SIU) Engine Host Interface (HDI16) 1-10 Enhanced Filter Coprocessor (EFCOP) 1-10 Communications Processor Module 1-10 Serial Protocol 1-11 Configurations 1-12 MSC8101 Application Examples 1-13 Media (Voice/Fax/Data) over Packet (ATM/FR/IP) 1-13 Infrastructure Cellular 1-15 Centralized Architecture 1-15 Distributed Architecture 1-16 Software Development 1-18
Chapter SC140 Core Overview
Architecture
MSC8101 Reference Manual
Contents
2.1.1 2.1.1.1 2.1.1.2 2.1.1.3 2.1.2 2.1.2.1 2.1.2.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2.1 2.2.2 2.2.3
Data Arithmetic Logic Unit (Data ALU). Data Registers Multiply-Accumulate (MAC) Unit Bit-Field Unit (BFU) Address Generation Unit (AGU) Stack Pointer Registers. Mask Unit (BMU) Program Sequencer Unit (PSEQ) Enhanced On-Chip Emulation (EOnCE) Instruction Accelerator On-Chip Memory. Programming Model Address Generation Programming Model Data Arithmetic Logic Programming Model. 2-12 Program Control Unit Programming Model 2-13 Instruction Overview 2-14
Chapter External Signals
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.6.1 3.2.6.2 3.2.6.3 3.2.6.4 3.2.7 3.2.8 Functional Pinout. Signal Descriptions Power Signals Clock Signals Reset, Configuration, EOnCE Event Signals PowerPC System Bus, HDI16, Interrupt Signals Memory Controller Signals 3-15 Port Signals. 3-17 Port Signals. 3-18 Port Signals. 3-26 Port Signals. 3-31 Port Signals. 3-40 JTAG Test Access Port Signals 3-44 Reserved Signals 3-45 Part Configuration Reset
Chapter System Interface Unit (SIU)
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 Architecture Monitor Timers Clock Time Counter (TMCNT) Periodic Interrupt Timer (PIT). Software Watchdog Timer.
MSC8101 Reference Manual
Contents
4.1.6 4.2.1 4.2.2
Multiplexing. Programming Model. System Configuration Protection Registers Periodic Interrupt Registers 4-26
Chapter Reset
5.1.1 5.1.1.1 5.1.1.2 5.1.2 5.1.3 5.2.1 5.2.2 5.2.2.1 5.2.2.2 5.2.2.3 5.2.2.4 5.2.2.5 5.2.2.6 5.2.2.7 5.3.1 5.3.2 Reset Operation Power-On Reset Flow Host Reset Configuration Hardware Reset Configuration. HRESET Flow SRESET Flow Hardware Reset Configuration Multi-MSC8101 System Configuration. Hard Reset Configuration Examples Single MSC8101 With Default Configuration. Single MSC8101 Configured From Boot EPROM Multiple MSC8101s Configured From Boot EPROM. Multiple MSC8101s System With EPROM MSC8101 Host Reset Configuration Mode (Host MSC8101) MSC8101 Host Reset Configuration Mode With MSC8101 Host 5-10 Multiple MSC8101s Host Reset Configuration Mode. 5-12 Reset Programming Model 5-13 Hard Reset Configuration Word 5-13 Reset Status Register 5-15
Chapter Boot
6.1.1 6.1.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.1.4 6.1.4.1 6.1.4.2 6.1.5 6.2.1 6.2.2 Standard Bootloader Operation Interrupts During Boot Procedure External Memory Boot Procedure Host Interface Boot Procedure. Broadcast Boot Facility Disabling Software Watchdog Host Port Size Configuration Check Source Program Data Stream Structure Host Interface 8-Bit/16-Bit Load Procedure Source Program Block Structure Default Programming During Boot Bootloader Operation Multi-Processor Environment Multi-Processor Booting Through Host Port Multi-Processor Booting From External Memory. 6-10
MSC8101 Reference Manual
Contents
Chapter Clocks
Part III: Data Operation Exception Processing
Chapter Memory
8.3.1 8.3.2 SC140 Core Address Space QBus Address Space Address Space. PowerPC Local Address Space PowerPC System Address Space
Chapter Internal Memory System Reservation Operation
9.5.1 9.5.2 9.5.3 9.6.1 9.6.2 9.6.3 Memory Groups. Memory Organization Control Unit Memory Contentions Errors Exceptions Errors Exceptions Big/Little Endian Support Reservation Operation Reservation Operation Instruction Snooper PowerPC Interface Snooper
Chapter Memory Controller
10.1 Features 10-3 10.2 Architecture 10-4 10.3 SDRAM Machine 10-12 10.3.1 SDRAM Power-On Initialization 10-15 10.3.2 JEDEC-Standard SDRAM Interface Commands 10-15 10.3.3 Page-Mode Support Pipeline Accesses. 10-16 10.3.4 Bank Interleaving 10-16 10.3.5 SDRAM Address Multiplexing (SDAM BSMA). 10-17 10.3.6 SDRAM Read/Write Transactions 10-17 10.3.7 SDRAM Refresh 10-18 10.3.8 SDRAM Signals: Device-Specific Parameters 10-18 10.3.9 SDRAM Signals: General Interface Timing 10-23 10.3.10 SDRAM Signals: Mode-Set Command Timing 10-27
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10.3.11 SDRAM Signals: Refresh Timing 10.3.12 SDRAM Configuration Examples 10.3.12.1 SDRAM Configuration Example (Page-Based Interleaving) 10.3.12.2 SDRAM Configuration Example (Bank-Based Interleaving) 10.4 General-Purpose Chip-Select Machine (GPCM). 10.4.1 GPCM Signals: Timing Configuration 10.4.1.1 Chip-Select Assertion Timing 10.4.1.2 Chip-Select Write Enable Deassertion Timing 10.4.1.3 Relaxed Timing 10.4.1.4 Output Enable (POE) Timing. 10.4.1.5 Programmable Wait State Configuration 10.4.1.6 Extended Hold Time Read Accesses 10.4.2 GPCM Signals: External Access Termination. 10.4.3 Boot Chip-Select Operation. 10.4.4 Differences Between MPC8xx GPCM MSC8101 GPCM 10.5 User-Programmable Machines (UPMs). 10.5.1 Requests 10.5.1.1 Memory Access Requests 10.5.1.2 Refresh Timer Requests 10.5.1.3 Software Requests-run Command 10.5.1.4 Exception Requests 10.5.2 Programming UPMs 10.5.3 Clock Timing 10.5.4 Array 10.5.4.1 Words 10.5.4.2 Last Word (LAST) 10.5.4.3 Address Multiplexing 10.5.4.4 Data Valid Data Sample Control 10.5.4.5 Disable Timer Mechanism (TODT) 10.5.4.6 Signals Negation 10.5.4.7 Wait Mechanism 10.5.4.8 Extended Hold Time Read Accesses 10.5.5 DRAM Configuration Example. 10.5.6 Interface Examples 10.5.6.1 Memory System Interface Example Using UPM. 10.5.6.2 Interface Example 10.5.7 Differences Between MPC8xx MSC8101 UPM. 10.6 Handling Devices With Slow Variable Access Times 10.7 External Master Support (Multi-Master Mode) 10.7.1 60x-Compatible External Masters (non-MSC8101) 10.7.2 MSC8101 External Masters. 10.7.3 Extended Controls Multi-Master Mode 10.7.4 Using BNKSEL Signals Single-Master Mode 10.7.5 Address Incrementing External Bursting Masters 10.7.6 External Masters Timing 10.8 Internal SRAM Peripherals Support
10-27 10-28 10-28 10-30 10-31 10-32 10-33 10-34 10-36 10-37 10-37 10-38 10-41 10-41 10-42 10-42 10-44 10-45 10-46 10-46 10-46 10-47 10-47 10-48 10-50 10-58 10-58 10-59 10-59 10-60 10-60 10-61 10-61 10-62 10-62 10-73 10-81 10-81 10-82 10-83 10-83 10-83 10-83 10-84 10-84 10-88
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10.8.1 Performance Summary-Transfers SRAM 10.8.1.1 Example 1.5:1 Clock Ratio 10.8.1.2 Example Clock Ratio 10.8.2 Performance Summary-Transfers Peripherals 10.8.3 Flyby Mode 10.9 Memory Controller Programming Model
10-88 10-89 10-91 10-92 10-92 10-93
Chapter QBus
11.1 11.2 11.3 11.4 11.5 Extended Core Memory. Switch (QBS) Operating Modes Banks Reservation Process 11-2 11-3 11-3 11-4 11-7
Chapter PowerPC System
12.1 Operating Modes 12-1 12.1.1 Single-Master Mode 12-1 12.1.2 Multi-Master Mode. 12-2 12.1.3 PowerPC System Protocols 12-3 12.1.3.1 Arbitration Phase 12-4 12.1.3.2 Address Pipelining Split-Bus Transactions 12-5 12.1.3.3 Memory Coherency 12-6 12.2 Address Tenure Operations 12-6 12.2.1 Address Arbitration 12-6 12.2.2 Address Pipelining. 12-8 12.2.3 Address Transfer Attribute Signals 12-9 12.2.3.1 Transfer Type Signal (TT[0-4]) Encoding 12-9 12.2.3.2 Transfer Code Signals TC[0-2] 12-10 12.2.3.3 TBST TSIZ[0-3] Signals Size Transfer 12-11 12.2.3.4 Burst Ordering During Data Transfers. 12-11 12.2.3.5 Effect Alignment Data Transfers 12-12 12.2.3.6 Effect Port Size Data Transfers. 12-14 12.2.3.7 Multi-Master Mode-Size Calculation. 12-17 12.2.3.8 Extended Transfer Mode 12-19 12.2.4 Address Transfer Termination 12-21 12.2.4.1 Address Retried With ARTRY 12-21 12.2.4.2 Address Tenure Timing Configuration 12-23 12.2.5 Pipeline Control 12-24 12.3 Data Tenure Operations 12-24 12.3.1 Data Arbitration 12-24 12.3.2 Data Streaming Mode 12-25 12.3.3 Data Transfers Normal Termination 12-25
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12.3.4 12.3.5 12.3.6
Effect ARTRY Assertion Data Transfer Arbitration. 12-26 Port Size Data Transfers PSDVAL Termination. 12-27 Data Termination Assertion 12-29
Chapter PowerPC System Signals
13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 Signal Configuration 13-2 Signal Descriptions 13-3 Address Arbitration 13-3 Address Start 13-6 Address 13-6 Address Transfer Attribute 13-7 Address Transfer Termination 13-8 Data Arbitration 13-9 Data Transfer 13-11 Data Transfer Termination. 13-12
Chapter Host Interface (HDI16)
14.1 14.2 14.2.1 14.2.2 14.2.3 14.2.3.1 14.2.3.2 14.2.3.3 14.2.4 14.3 14.4 14.5 Overview 14-1 Host Interface Operation 14-6 Polling 14-6 Interrupts 14-7 Host 14-9 Select Host Mode 14-9 Select Transfer Acknowledge Input 14-10 Select Size Host Word 14-10 Reset. 14-11 8-Bit Mode. 14-13 Core-Side Programming Model. 14-14 External Host-Side Programming Model 14-23
Chapter Direct Memory Access (DMA)
15.1 15.2 15.3 15.3.1 15.3.2 15.4 15.4.1 15.4.2 15.4.3 Features 15-1 Architecture 15-2 Signals: Requestors Interface 15-4 Signal Functionality. 15-4 Peripheral Access Timing 15-5 Operating Modes: Transfer Types. 15-9 Transfer Size Peripheral Port Size 15-9 Access Modes 15-9 Transfers Between External Memory External Peripheral 15-10
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15.4.4 Transfers Between External Peripheral Internal Memory (SRAM) 15.4.5 Transfers Between External Memory External Memory 15.4.6 Transfers Between External Memory SRAM 15.4.7 Transfers Between Internal Peripheral SRAM. 15.4.8 Transfers from Internal Memory SRAM 15.4.9 Transfers Between External Peripheral External Memory (Flyby Mode) 15.4.10 Transfers Between Internal Peripheral Internal Memory (Flyby Mode) 15.4.11 Operating Modes: Buffer Types 15.4.11.1 Simple Buffer 15.4.11.2 Cyclic Buffer 15.4.11.3 Incremental Buffer 15.4.11.4 Chained Buffer 15.4.11.5 Complex Buffers-Dual Cyclic Buffers 15.5 Transfer Programming. 15.5.1 Peripheral Memory Transfer (Simple Buffer) 15.5.2 Transfer from Cyclic Memory Simple Memory 15.5.3 Transfer from Peripheral Continuous Memory. 15.5.4 Transfer From Internal Peripheral Memory (Flyby Mode) 15.5.5 Terminating Transfer 15.6 Programming Model 15.6.1 Configuration Registers 15.6.2 Status Interrupt Registers 15.6.3 Error Registers
15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-18 15-20 15-21 15-21 15-23 15-24 15-26 15-27 15-28 15-30 15-32 15-33 15-34 15-35 15-42 15-44
Chapter Interrupt Scheme
16.1 Interrupt Architecture 16-1 16.2 Interrupt Controllers 16-3 16.2.1 SIU-CPM Interrupt Controller. 16-3 16.2.1.1 Interrupt Source Priorities 16-3 16.2.1.1.1 SCC, FCC, Relative Priority 16-6 16.2.1.1.2 PIT, TMCNT, Relative Priority 16-6 16.2.1.1.3 Highest Priority Interrupt 16-7 16.2.1.2 Masking Interrupt Sources 16-7 16.2.1.3 Interrupt Vector Generation Calculation 16-8 16.2.1.4 Port External Interrupts 16-10 16.2.2 Programmable Interrupt Controller (PIC) 16-10 16.2.2.1 Peripheral (QBus) Interface 16-11 16.2.2.2 Interrupt Request Generation 16-12 16.2.2.3 Interrupt Routing 16-12 16.3 Interrupt Programming Examples 16-14 16.3.1 Initialization 16-15 16.3.2 Programming 16-15 16.3.3 Clearing Pending Requests 16-16 16.4 Interrupts Programming Model 16-17
MSC8101 Reference Manual
Contents
16.4.1 16.4.2 16.4.2.1 16.4.2.2 16.4.2.3
SIU-CPM Registers Edge/Level-Triggered Interrupt Priority Registers Interrupt Priority Structure Mode Interrupt Pending Registers
16-17 16-26 16-26 16-27 16-29
Chapter JTAG IEEE 1149.1 Test Access Port
17.1 17.2 17.3 17.4 17.5 17.6 Overview 17-1 Controller 17-3 Boundary Scan Register. 17-4 Shift Registers 17-23 Instruction Decoding 17-24 MSC8101 Restrictions. 17-29 Part Coprocessors
Chapter Enhanced Filter Coprocessor (EFCOP)
18.1 18.2 18.2.1 18.2.2 18.3 18.4 Features Architecture Overview. QBus Interface EFCOP Memory Banks Filter Multiplier Accumulator (FMAC) EFCOP Programming Model. Part Communications Processor Module 18-1 18-2 18-3 18-4 18-5 18-5
Chapter Communications Processor Module Overview
19.1 19.2 19.3 19.3.1 19.3.2 19.3.3 19.4 19.4.1 19.4.2 19.5 19.5.1 19.5.2 19.5.3 Features 19-1 MSC8101 Serial Configurations 19-3 Communications Processor (CP) 19-4 Features 19-4 SC140 Core Interface. 19-6 Peripheral Interface 19-6 Dual-Port 19-7 Buffer Descriptors (BDs). 19-9 Parameter 19-11 RISC Timer Tables 19-13 RISC Timer Table Parameter 19-13 RISC Timer Table Entries 19-15 RISC Timer Initialization Sequence 19-15
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19.5.4 19.5.5 19.5.6 19.5.7 19.6 19.6.1 19.6.2
RISC Timer Initialization Example RISC Timer Interrupt Handling RISC Timer Table Scan Algorithm Using RISC Timers Track Loading Programming Model. Control Configuration Registers RISC Timer Registers
19-16 19-17 19-17 19-17 19-18 19-18 19-26
Chapter Serial Interface with Time-Slot Assigner
20.1 20.2 20.3 20.4 20.4.1 20.4.2 20.4.3 20.4.4 20.4.5 20.5 20.5.1 20.5.2 20.6 20.6.1 20.6.2 20.6.2.1 20.6.2.2 20.7 Features 20-1 Operation. 20-3 Enabling Connections 20-6 Serial Interface RAM. 20-7 Multiplexed Channel With Static Frames 20-8 Multiplexed Channel With Dynamic Frames 20-8 Programming Entries 20-9 Programming Example 20-13 Static Dynamic Routing 20-14 Serial Interface Interface Support 20-17 Interface Example 20-17 Interface Programming. 20-20 Serial Interface Support 20-21 Activation/Deactivation Procedure 20-23 Serial Interface Programming 20-24 Normal Mode Programming 20-24 SCIT Programming 20-24 Serial Interface Programming Model 20-26
Chapter Multiplexing
21.1 21.2 21.3 21.4 Features Enabling Connections NMSI NMSI Configuration Multiplexing Programming Model. 21-2 21-3 21-4 21-7
Chapter Baud-Rate Generators (BRGs)
22.1 22.2 22.3 Autobaud Operation UART 22-2 UART Baud Rate Examples 22-3 Programming Model. 22-5
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Chapter Timers
23.1 23.2 23.3 23.4 23.5 Features Timer Clock Timer Modes Cascading Timers Timer Programming Model 23-2 23-2 23-3 23-3 23-4
Chapter SDMA Channels
24.1 24.2 SDMA Arbitration Transfers 24-3 SDMA Programming Model 24-4
Chapter Serial Communications Controllers (SCCs)
25.1 25.2 25.3 25.4 25.4.1 25.4.2 25.4.2.1 25.4.2.2 25.4.3 25.4.3.1 25.4.4 25.4.5 25.4.5.1 25.4.5.2 25.4.5.3 25.4.5.4 25.4.5.5 25.5 Features 25-3 Buffer Descriptors (BDs) 25-4 Parameter RAM. 25-6 Interrupt Handling 25-9 Initializing SCCs 25-10 Controlling Timing with RTS, CTS, 25-10 Synchronous Protocols 25-10 Asynchronous Protocols. 25-13 Digital Phase-Locked Loop (DPLL) Operation. 25-14 Encoding Data with DPLL 25-16 Clock Glitch Detection 25-17 Reconfiguring SCCs 25-17 General Reconfiguration Sequence Transmitter 25-18 Reset Sequence Transmitter 25-18 General Reconfiguration Sequence Receiver 25-18 Reset Sequence Receiver 25-19 Switching Protocols Saving Power 25-19 Programming Model 25-19
Chapter UART Mode
26.1 26.2 26.2.1 26.2.2 26.2.3 26.2.4 Features UART Operations Normal Asynchronous Mode. Synchronous Mode Hunt Mode Receiving Control Characters 26-2 26-3 26-3 26-4 26-4 26-4
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26.2.5 26.2.6 26.3 26.4 26.5 26.6 26.7 26.8 26.9
Transmitting Control Characters 26-6 Data-Handling Methods: Character- Message-Based 26-7 Parameter 26-8 Commands 26-10 Multidrop Systems Address Recognition 26-12 Handling Errors UART Controller 26-13 Programming Example 26-14 S-Records Loader Application. 26-15 UART Programming Model 26-16
Chapter HDLC Mode
27.1 27.2 27.2.1 27.2.2 27.3 27.4 27.5 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.6.5 27.6.6 27.6.6.1 27.6.6.2 27.7 27.7.1 27.7.2 27.8 Features 27-2 HDLC Operations 27-2 Channel Frame Transmission 27-2 Channel Frame Reception 27-3 Parameter 27-6 Commands 27-8 Handling Errors HDLC Controller 27-9 HDLC Mode with Collision Detection. 27-10 HDLC Features. 27-12 Accessing HDLC 27-13 Increasing Performance 27-14 Delayed Mode 27-15 Using Time-Slot Assigner (TSA) 27-16 HDLC Protocol Programming 27-16 Programming GSMR PSMR HDLC Protocol 27-16 HDLC Controller Programming Example 27-17 Programming Examples. 27-17 Example 27-17 Example 27-19 HDLC Programming Model 27-20
Chapter BISYNC Mode
28.1 28.2 28.2.1 28.2.2 28.3 28.4 28.5 28.6 28.7 Features BISYNC Operations Channel Frame Transmission Channel Frame Reception Parameter Commands Control Character Recognition Sending Receiving Synchronization Sequence. Handling Errors BISYNC 28-2 28-2 28-2 28-3 28-4 28-5 28-6 28-8 28-9
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28.8 28.9 28.10
Programming BISYNC Controller 28-9 BISYNC Programming Example 28-11 BISYNC Programming Model 28-12
Chapter Transparent Mode
29.1 29.2 29.2.1 29.2.2 29.2.3 29.2.3.1 29.2.3.2 29.2.4 29.3 29.4 29.5 29.6 29.7 Features 29-2 Transparent Operations 29-2 Channel Frame Transmission 29-2 Channel Frame Reception 29-3 Synchronization 29-3 Synchronization NMSI Mode 29-3 Synchronization 29-5 Calculation 29-6 Parameter 29-6 Commands 29-7 Handling Errors Transparent Controller 29-8 Programming Example 29-9 Transparent Programming Model 29-10
Chapter Ethernet Mode
30.1 30.2 30.3 30.3.1 30.3.1.1 30.3.1.2 30.3.2 30.4 30.4.1 30.4.2 30.4.3 30.4.4 30.4.5 30.4.6 30.4.7 30.5 30.6 30.7 30.8 30.9 Features 30-3 Connecting MSC8101 Ethernet 30-5 Ethernet Data Movement Operations 30-6 Channel Frame Transmission 30-7 Collisions 30-7 Interrupts Graceful Stops. 30-7 Channel Frame Reception 30-8 Ethernet Controller Operations 30-9 Address Recognition 30-9 Hash Table Algorithm 30-10 Interpacket Time 30-11 Handling Collisions 30-11 Internal External Loopback. 30-11 Full-Duplex Ethernet Support 30-12 Interface 30-12 Parameter 30-13 Commands 30-15 Ethernet Error Handling. 30-17 Programming Example 30-18 Ethernet Programming Model. 30-19
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Chapter AppleTalk Mode
31.1 31.2 31.3 31.4 31.4.1 31.4.2 31.4.3 31.4.4 Operating LocalTalk Bus. Features Connecting AppleTalk. Programming AppleTalk Mode Programming GSMR Programming PSMR Programming TODR AppleTalk Programming Example 31-1 31-2 31-3 31-3 31-4 31-4 31-5 31-5
Chapter Serial Management Controllers (SMCs)
32.1 32.2 32.2.1 32.2.2 32.2.3 32.2.3.1 32.2.3.2 32.2.3.3 32.2.3.4 32.2.3.5 32.2.4 32.2.5 32.3 32.3.1 32.3.2 32.3.3 32.3.4 32.3.5 32.3.6 32.4 32.4.1 32.4.2 32.4.3 32.4.4 32.4.5 32.4.6 32.4.7 32.5 32.5.1 32.5.2 32.5.3 Features 32-2 Common Settings Configurations 32-3 Buffer Descriptor Operation. 32-3 Parameter 32-4 Disabling SMCs On-the-Fly 32-6 Transmitter Full Sequence 32-6 Transmitter Shortcut Sequence 32-7 Receiver Full Sequence 32-7 Receiver Shortcut Sequence 32-7 Switching Protocols 32-7 Saving Power 32-7 Handling Interrupts SMC. 32-8 UART Mode. 32-8 UART Channel Transmission Reception Processes 32-9 UART Transmit Receive Commands 32-10 Sending Break 32-11 Sending Preamble 32-11 UART Error Handling 32-11 UART Controller Programming Example 32-12 Transparent Mode 32-13 Transparent Channel Transmission Process 32-14 Transparent Channel Reception Process 32-14 Using SMSYN Synchronization 32-15 Using Time-Slot Assigner (TSA) Synchronization 32-15 Transparent Commands 32-18 Transparent Error Handling 32-18 Transparent NMSI Programming Example 32-19 Mode 32-20 Parameter 32-20 Monitor Channel 32-21 Commands 32-22
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32.6 32.6.1 32.6.2 32.6.3 32.6.4
Programming Model. General Registers UART Registers. Transparent Registers Registers
32-22 32-23 32-27 32-34 32-38
Chapter Multi-Channel Controllers (MCCs)
33.1 33.2 33.3 33.4 33.5 33.6 33.7 33.8 33.9 33.10 33.10.1 33.10.2 33.11 33.12 Features 33-1 Data Structure Organization 33-2 Global Parameters 33-3 Channel Extra Parameters 33-5 Super Channel Table 33-5 Channel-Specific HDLC Parameters 33-8 Channel-Specific Transparent Parameters. 33-9 Commands 33-11 Exceptions 33-12 Initialization Start/Stop Sequence 33-13 Single-Channel Initialization 33-13 Super Channel Initialization 33-14 Latency Performance 33-15 Programming Model 33-15
Chapter Fast Communications Controllers (FCCs)
34.1 34.2 34.2.1 34.2.2 34.3 34.4 34.4.1 34.4.2 34.4.3 34.5 34.6 34.7 34.8 34.8.1 34.8.2 34.8.3 34.8.4 34.8.5 34.9 Overview 34-2 Buffer Descriptors 34-3 Processing TxBDs 34-4 Processing RxBDs 34-5 Parameter RAM. 34-5 Interrupts from FCCs 34-7 Event Registers (FCCEx) 34-8 Mask Registers (FCCMx) 34-8 Status Registers (FCCSx) 34-8 Initialization 34-8 Interrupt Handling 34-9 Timing Control 34-10 Disabling FCCs On-the-Fly 34-12 Transmitter Full Sequence 34-13 Transmitter Shortcut Sequence 34-13 Receiver Full Sequence 34-14 Receiver Shortcut Sequence 34-14 Switching Protocols Saving Power 34-14 Programming Model 34-15
MSC8101 Reference Manual
Contents
Chapter AController
35.1 35.2 35.2.1 35.2.2 35.2.3 35.2.4 35.3 35.3.1 35.3.2 35.3.3 35.3.4 35.3.5 35.3.6 35.4 35.4.1 35.4.2 35.4.2.1 35.4.2.2 35.4.3 35.5 35.5.1 35.5.1.1 35.5.1.2 35.5.1.3 35.5.2 35.5.3 35.6 35.6.1 35.6.2 35.6.3 35.6.4 35.6.5 35.6.6 35.6.6.1 35.6.6.2 35.6.6.3 35.6.6.4 35.7 35.8 35.9 35.9.1 35.9.2 35.9.3 Features 35-2 AController Architecture 35-5 Transmitter. 35-5 Receiver 35-7 Performance Monitoring 35-9 Flow Control. 35-9 APace Control (APC) Unit Architecture 35-9 Modes AService Types 35-9 Unit Scheduling Mechanism 35-10 Scheduling Table Size 35-11 Channel Time-Slot Scheduling Rate 35-12 ATraffic Type 35-12 AChannel Priority 35-14 VCI/VPI Address Lookup Mechanism 35-14 External Lookup 35-15 Address Compression 35-16 VP-Level Address Compression Table (VPLT) 35-18 VC-Level Address Compression Tables (VCLTs) 35-19 Receive Cell Queue 35-19 Available Rate (ABR) Flow Control 35-21 Model 35-21 Flow Control Source End-System Behavior. 35-22 Flow Control Destination End-System Behavior 35-22 Flowcharts 35-23 Cell Structure 35-27 Flow Control Setup. 35-28 Support 35-28 ATM-Layer Definitions. 35-29 Virtual Path (F4) Flow Mechanism 35-29 Virtual Channel (F5) Flow Mechanism 35-30 Receiving Cells 35-30 Transmitting Cells 35-30 Performance Monitoring 35-30 Running Performance Block Test 35-32 Block Monitoring 35-32 Block Generation. 35-33 Performance Calculations 35-33 User-Defined Cells (UDC) 35-34 ALayer Statistics. 35-35 ATM-to-TDM Interworking 35-36 Automatic Data Forwarding 35-36 Using Interrupts Automatic Data Forwarding 35-37 Timing Issues 35-37
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35.9.4 Clock Synchronization (SRTS Adaptive FIFOs) 35.9.5 Mapping Time Slots 35.9.6 Support 35.9.7 Trunk Condition. 35.9.8 ATM-to-AData Forwarding 35.10 AMemory Structure 35.10.1 Parameter 35.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only) 35.10.1.2 Filtering (VCIF) 35.10.1.3 Global Mode Entry (GMODE) 35.10.2 Connection Tables (RCT, TCT, TCTE) 35.10.2.1 AChannel Code 35.10.2.2 Receive Connection Table (RCT) 35.10.2.3 Transmit Connection Table (TCT). 35.10.3 Performance Monitoring Tables 35.10.4 Data Structure 35.10.4.1 Parameter Tables 35.10.4.2 Priority Table. 35.10.4.3 Scheduling Tables 35.10.5 AController Buffer Descriptors (BDs) 35.10.5.1 Transmit Buffer Operations 35.10.5.2 Receive Buffer Operations 35.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only) 35.10.7 Statistics Table. 35.11 AExceptions 35.11.1 Interrupt Queues 35.11.2 Interrupt Queue Entry 35.11.3 Interrupt Queue Parameter Tables 35.12 UTOPIA Interface 35.12.1 UTOPIA Interface Master Mode 35.12.2 UTOPIA Interface Slave Mode 35.13 ATransmit Command 35.14 SRTS Generation Clock Recovery 35.15 Configuring AController Maximum Performance 35.15.1 Using Transmit Internal Rate Mode 35.15.2 Configuration 35.15.3 Buffer Configuration 35.16 AProgramming Model 35.16.1 AMode Registers 35.16.2 AController Buffers
35-38 35-38 35-38 35-39 35-39 35-39 35-39 35-42 35-43 35-43 35-44 35-45 35-46 35-54 35-67 35-70 35-70 35-71 35-72 35-72 35-73 35-74 35-78 35-78 35-79 35-79 35-80 35-81 35-82 35-82 35-84 35-86 35-87 35-89 35-89 35-89 35-90 35-90 35-91 35-96
Chapter Fast Ethernet Controller
36.1 36.2 Features 36-2 Connecting MSC8101 Fast Ethernet 36-4
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36.3 36.3.1 36.3.2 36.3.3 36.4 36.5 36.6 36.7 36.8 36.9 36.10 36.11 36.12 36.13 36.14 36.15 36.16
Channel Frame Transmission 36-5 Out-of-Sequence Flow Control 36-6 Collisions 36-6 Interrupts Graceful Stops 36-6 Channel Frame Reception 36-7 Flow Control 36-8 Interface 36-9 Parameter 36-9 Ethernet Command 36-14 RMON Support 36-15 Ethernet Address Recognition 36-17 Hash Table Algorithm 36-19 Interpacket Time 36-19 Collision Handling. 36-20 Internal External Loopback. 36-20 Ethernet Error-Handling Procedure 36-20 Fast Ethernet Programming Model 36-21
Chapter HDLC Controller
37.1 37.2 37.3 37.4 37.5 37.6 37.7 37.8 Features 37-2 HDLC Channel Frame Transmission Processing 37-2 HDLC Channel Frame Reception Processing 37-3 Parameter 37-4 Command Set. 37-6 Error Handling 37-7 Receive Transmit Buffer Descriptors 37-8 HDLC Programming Model 37-10
Chapter Transparent Controller
38.1 38.2 38.3 38.3.1 38.3.2 38.3.3 Features Transparent Channel Operation Achieving Synchronization Transparent Mode In-Line Synchronization Pattern External Synchronization Signals Transparent Synchronization Example 38-2 38-2 38-2 38-3 38-3 38-4
Chapter Serial Peripheral Interface (SPI)
39.1 39.2 39.3 Features 39-1 Clocking Signal Functions 39-2 Configuring Controller 39-3
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39.3.1 39.3.2 39.3.3 39.4 39.5 39.6 39.6.1 39.7 39.8 39.9 39.10
Master Device 39-3 Slave Device 39-4 Multimaster Operation. 39-5 Parameter 39-7 Commands 39-8 Buffer Descriptor (BD) Table 39-9 Buffer Descriptors (BDs) 39-9 Master Programming Example 39-10 Slave Programming Example 39-11 Handling Interrupts 39-12 Programming Model 39-12
Chapter Controller
40.1 40.2 40.3 40.3.1 40.3.2 40.3.3 40.4 40.5 40.6 40.6.1 40.7 Features 40-2 Controller Clocking Signal Functions. 40-2 Controller Transfers. 40-3 Master Write (Slave Read) 40-4 Master Read (Slave Write) 40-5 Multi-Master Considerations. 40-6 Parameter 40-6 Commands 40-8 Buffer Descriptor (BD) Table 40-8 Buffer Descriptors (BDs). 40-9 Programming Model 40-10
Chapter Parallel Ports
41.1 41.2 41.3 41.4 41.5 Features 41-1 Port Block Diagram 41-2 Port Functions 41-3 Interrupts From Port 41-11 Parallel Ports Programming Model 41-12
Appendix Programming Reference
Interrupt Sources Priorities Programming Sheets
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Contents
Appendix Glossary Appendix Bootloader Program Appendix Acronyms Abbreviations
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Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 7-1. Figure 8-1. MSC8101 Block Diagram Media (Voice/Fax/Data) over Packet (ATM/FR/IP). 1-14 Infrastructure Cellular 1-15 Centralized Architecture 1-16 Distributed Architecture With Connection Through HDI16 Port. 1-17 Distributed Architecture With Connection Through Shared PowerPC Bus. 1-17 Software Development Flow. 1-18 Block Diagram Typical SC140 Device Data Architecture Block Diagram. SC140 Programming Model 2-11 MSC8101 External Signals Block Diagram System Configuration Protection Logic Timers Clock Generation TMCNT Block Diagram Block Diagram Software Watchdog Timer Service State Diagram Software Watchdog Timer Block Diagram. Host Reset Configuration Timing Hardware Reset Configuration Timing Configuring Single Device With Default Configuration Configuring Single Device From EPROM. Configuring Single Device From Host Other Than MSC8101. 5-10 Configuring Single Device From Host 5-10 Configuring Multiple MSC8101s 5-11 Multiple MSC8101s With Host. 5-12 External Memory Boot Procedure. Host Port Size Configuration Check Boot Code Stream Structure Host Interface Load Procedure MSC8101 Clocking Structure MSC8101 Buses
MSC8101 Reference Manual
Figures
Figure 8-2. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 9-7. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 10-5. Figure 10-6. Figure 10-7. Figure 10-8. Figure 10-9. Figure 10-10. Figure 10-11. Figure 10-12. Figure 10-13. Figure 10-14. Figure 10-15. Figure 10-16. Figure 10-17. Figure 10-18. Figure 10-19. Figure 10-20. Figure 10-21. Figure 10-22. Figure 10-23. Figure 10-24. Figure 10-25. Figure 10-26. Figure 10-27. Figure 10-28. Figure 10-29. Figure 10-30.
MSC8101 Memory SC140 Extended Core System. Memory Group Memory Interleaving Logical Memory Organization SC140 Memory Snoop Timing Example Failures. Architecture 10-2 Memory Controller Machine Selection 10-5 Simple System Configuration 10-6 Basic Memory Controller Operation 10-7 Port Size Data Valid 32-Bit Port Size Memory, Double-Word Transfer 10-12 128-MB SDRAM (Eight-Bank Configuration, Banks Shown) 10-14 PRETOACT Clock Cycles) 10-19 ACTTORW Clock Cycles) 10-19 Clock Cycles) 10-20 LDOTOPRE Clock Cycles) 10-20 Clock Cycles) 10-21 RFRC Clock Cycles) 10-21 EAMUX 10-22 BUFCMD 10-22 SDRAM Single-Beat Read, Page Closed, 10-23 SDRAM Single-Beat Read, Page Hit, 10-23 SDRAM Two-Beat Burst Read, Page Closed, 10-24 SDRAM Four-Beat Burst Read, Page Miss, 10-24 SDRAM Single-Beat Write, Page 10-25 SDRAM Three-Beat Burst Write, Page Closed 10-25 SDRAM Read-after-Read Pipeline, Page Hit, 10-26 SDRAM Write-after-Write Pipelined, Page 10-26 SDRAM Read-after-Write Pipelined, Page Hit. 10-26 SDRAM Mode-Set Command Timing 10-27 Mode Data Settings 10-27 SDRAM Bank-Staggered Refresh Timing. 10-28 GPCM-to-SRAM Configuration 10-32 GPCM Peripheral Device Interface. 10-34 GPCM Peripheral Device Basic Timing (ACS TRLX 10-34 GPCM Memory Device Interface 10-34
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Figures
Figure 10-31. Figure 10-32. Figure 10-33. Figure 10-34. Figure 10-35. Figure 10-36. Figure 10-37. Figure 10-38. Figure 10-39. Figure 10-40. Figure 10-41. Figure 10-42. Figure 10-43. Figure 10-44. Figure 10-45. Figure 10-46. Figure 10-47. Figure 10-48. Figure 10-49. Figure 10-50. Figure 10-51. Figure 10-52. Figure 10-53. Figure 10-54. Figure 10-55. Figure 10-56. Figure 10-57. Figure 10-58. Figure 10-59. Figure 10-60. Figure 10-61. Figure 10-62. Figure 10-63. Figure 10-64. Figure 10-65. Figure 10-66. Figure 10-67. Figure 10-68.
GPCM Memory Device Timing (ACS CSNT TRLX GPCM Memory Device Timing (ACS CSNT TRLX GPCM Relaxed Timing Read (ACS CSNT TRLX GPCM Relaxed-Timing Write (ACS CSNT 0,TRLX GPCM Relaxed-Timing Write (ACS CSNT TRLX GPCM Relaxed-Timing Write (ACS CSNT TRLX GPCM Read Followed Read (ORx[29-30] Fastest Timing) GPCM Read Followed Read (ORx[29-30] GPCM Read Followed Write (ORx[29-30] GPCM Read Followed Read (ORx[29-30] External Termination GPCM Access User-Programmable Machine Block Diagram Array Indexing Memory Refresh Timer Request Block Diagram Clock Scheme Integer (2:1/3:1 Clock Ratios Clock Scheme Non-Integer (2.5:1/3.5:1) Clock Ratios Signals Timing Example Array Signal Generation. Signal Selection. Signal Selection. Read Access Data Sampling Wait Mechanism Timing Internal External Synchronous Masters. DRAM Interface Connection PowerPC System (64-Bit Port Size). Single-Beat Read Access DRAM. Single-Beat Write Access DRAM Burst Read Access DRAM LOOP). Burst Read Access DRAM (LOOP). Burst Write Access DRAM LOOP) Refresh Cycle (CBR) DRAM. Exception Cycle. DRAM Burst Read Access (Data Sampling Falling Edge CLKIN) MSC8101/EDO Interface Connection PowerPC System Bus. Single-Beat Read Access DRAM Single-Beat Write Access DRAM Single-Beat Write DRAM, REDO Inserts Three Wait States Burst Read Access DRAM. Burst Write Access DRAM Refresh Cycle (CBR) DRAM
10-35 10-35 10-36 10-36 10-37 10-38 10-39 10-39 10-40 10-40 10-41 10-44 10-45 10-46 10-47 10-48 10-49 10-49 10-56 10-56 10-60 10-61 10-63 10-64 10-65 10-66 10-67 10-68 10-69 10-70 10-72 10-73 10-74 10-75 10-76 10-77 10-78 10-79
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Figures
Figure 10-69. Figure 10-70. Figure 10-71. Figure 10-72. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 13-1. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Figure 15-10. Figure 15-11.
Exception Cycle DRAM. 10-80 Pipelined Operation Memory Access Multi-Master Mode 10-85 External Master Access (GPCM) 10-86 External Master Configuration With SDRAM Device 10-87 SC140 Extended Core System. 11-1 MSC8101 Memory 11-2 Bank Memory Location. 11-5 Sequential Bank Transfers. 11-7 Single-Master Mode. 12-2 Multi-Master Mode 12-3 Basic Transfer Protocol 12-4 Address Arbitration With External PowerPC Master 12-8 Address Pipelining. 12-9 Interface Different Port Size Devices 12-15 Retry Cycle 12-23 Single-Beat Burst Data Transfers 12-27 128-Bit Extended Transfer 32-Bit Port Size 12-28 Burst Transfer 32-Bit Port Size 12-28 Data Tenure Terminated Assertion 12-29 MSC8101 PowerPC System Groupings. 13-2 HDI16 Block Diagram 14-5 HSR-HCR Operation. 14-8 HDI16 Host Request Structure 14-9 8-Bit Mode Diagram (DSP Host) 14-13 8-Bit Mode Diagram (Host DSP). 14-14 Single-Strobe 14-22 Dual-Strobe 14-22 System Diagram 15-3 Level-Triggered Request Expiration Timer 15-6 Edge-Triggered Request, Synchronous DREQ, DRACK 15-7 Level-Triggered Request, Asynchronous DREQ, DRACK 15-7 Simultaneous Assertion DACK DONE 15-8 Sequential Assertion DACK DONE 15-8 Transfer From External Memory External Peripheral 15-11 Transfer From External Peripheral Internal Memory (SRAM) 15-12 Transfer From External Memory External Memory 15-13 Transfer From External Memory SRAM 15-14 Transfer From Internal Peripheral SRAM 15-15
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Figures
Figure 15-12. Figure 15-13. Figure 15-14. Figure 15-15. Figure 15-16. Figure 15-17. Figure 15-18. Figure 15-19. Figure 15-20. Figure 15-21. Figure 15-22. Figure 15-23. Figure 15-24. Figure 15-25. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 17-1. Figure 17-2. Figure 17-3. Figure 17-4. Figure 17-5. Figure 17-6. Figure 17-7. Figure 17-8. Figure 17-9. Figure 18-1. Figure 19-1. Figure 19-2. Figure 19-3. Figure 19-4. Figure 19-5. Figure 19-6. Figure 20-1. Figure 20-2. Figure 20-3. Figure 20-4.
Transfer From Internal Memory SRAM 15-16 Transfer Between External Peripheral External Memory (Flyby Mode) 15-17 Transfer Between Internal Peripheral Internal Memory (Flyby Mode). 15-18 Simple Buffer 15-20 Cyclic Buffer 15-21 Incremental Buffer. 15-22 Chained Buffer 15-23 Dual Cyclic Buffers. 15-24 Configuration Flow 15-26 Transfer from External Peripheral Internal Memory 15-27 Transfer from Cyclic Memory Simple Memory 15-29 Transfer from Peripheral Continuous Memory 15-30 Transfer from Internal Peripheral Memory (Flyby Mode). 15-32 DCPRAM Structure. 15-39 MSC8101 Interrupt Structure 16-2 Interrupt Request Masking 16-7 Block Diagram 16-11 Interrupt Table Handling Example 16-24 Test Logic Block Diagram 17-2 Controller State Machine 17-3 Observe-Only Input Cell (I.OBS) 17-4 Output Cell (O.PIN) 17-4 Output Control Cell (IO.CTL). 17-5 General Arrangement Bidirectional Cells. 17-5 Bypass Register Configuration 17-23 Identification Register Configuration (ID) 17-24 Instruction Register (IR) Configuration 17-25 EFCOP Block Diagram 18-3 MSC8101 Block Diagram 19-3 Communications Processor (CP) Block Diagram 19-5 Dual-Port Block Diagram 19-8 Dual-Port Memory 19-9 Buffer Descriptor Structure 19-10 RISC Timer Table Usage 19-14 Block Diagram 20-2 Various Configurations Single Channel. 20-4 Dual Channel Example 20-5 Enabling Connections 20-7
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Figures
Figure 20-5. Figure 20-6. Figure 20-7. Figure 20-8. Figure 20-9. Figure 20-10. Figure 20-11. Figure 20-12. Figure 20-13. Figure 20-14. Figure 20-15. Figure 20-16. Figure 20-17. Figure 20-18. Figure 21-1. Figure 21-2. Figure 21-3. Figure 22-1. Figure 23-1. Figure 23-2. Figure 24-1. Figure 24-2. Figure 25-1. Figure 25-2. Figure 25-3. Figure 25-4. Figure 25-5. Figure 25-6. Figure 25-7. Figure 25-8. Figure 25-9. Figure 25-10. Figure 26-1. Figure 26-2. Figure 26-3. Figure 26-4. Figure 26-5. Figure 27-1.
Channel With Static Frames Independent Routes 20-8 Channel with Shadow Dynamic Route Change 20-9 Using SWTR Feature. 20-12 Example: Dynamic Changes, TDMa Same Size. 20-16 Dual Application Example 20-17 Terminal Adaptor. 20-18 Signals 20-19 Signals 20-22 One-Clock Delay From Sync Data (xFSD 20-30 Delay From Sync Data (xFSD 20-31 Falling Edge (FE) Effect When xFSD 20-31 Falling Edge (FE) Effect When xFSD 20-31 Falling Edge (FE) Effect When xFSD 20-32 Falling Edge (FE) Effect When xFSD 20-33 Multiplexing Logic (CMX) Block Diagram 21-2 Enabling Connections 21-4 Bank Clocks 21-5 Baud-Rate Generator (BRG) Block Diagram 22-2 Timer Block Diagram 23-1 Timer Cascaded Mode Block Diagram 23-4 SDMA Data Paths 24-2 SDMA Arbitration (Transaction Steal) 24-3 Block Diagram 25-2 Buffer Descriptors (BDs) 25-4 Buffer Memory Structure 25-5 Output Delay from Asserted Synchronous Protocols 25-11 Output Delay from Asserted Synchronous Protocols 25-11 Lost Synchronous Protocols 25-12 Using Control Synchronous Protocol Reception 25-13 DPLL Receiver Block Diagram 25-14 DPLL Transmitter Block Diagram 25-15 DPLL Encoding Examples 25-16 UART Character Format 26-1 Control Character Table 26-5 UART Receiving Using RxBDs 26-11 UART Multidrop Configurations 26-12 UART Interrupt Event Example 26-29 Typical HDLC Framing Structure. 27-2
MSC8101 Reference Manual
Figures
Figure 27-2. Figure 27-3. Figure 27-4. Figure 27-5. Figure 27-6. Figure 27-7. Figure 27-8. Figure 27-9. Figure 27-10. Figure 27-11. Figure 28-1. Figure 28-2. Figure 29-1. Figure 30-1. Figure 30-2. Figure 30-3. Figure 30-4. Figure 30-5. Figure 30-6. Figure 31-1. Figure 31-2. Figure 32-1. Figure 32-2. Figure 32-3. Figure 32-4. Figure 32-5. Figure 32-6. Figure 32-7. Figure 33-1. Figure 33-2. Figure 33-3. Figure 33-4. Figure 33-5. Figure 34-1. Figure 34-2. Figure 34-3. Figure 34-4. Figure 34-5.
HDLC Receiving Using RxBDs 27-4 HDLC Interrupt Event Example 27-5 HDLC Address Recognition 27-7 Typical HDLC Multimaster Configuration 27-12 Typical HDLC Single-Master Configuration. 27-13 Detecting HDLC Collision 27-14 Nonsymmetrical Clock Duty Cycle Increased Performance 27-14 HDLC Transmission Line Configuration. 27-15 Delayed Mode 27-15 HDLC Transmission Line Configuration. 27-16 Classes BISYNC Frames 28-1 Control Character Table RCCM. 28-7 Sending Transparent Frames Between MSC8101s 29-5 Ethernet Frame Structure. 30-1 Ethernet Block Diagram 30-3 Connecting MSC8101 Ethernet. 30-5 Ethernet Address Recognition Flowchart 30-10 Ethernet Receiving Using RxBDs 30-25 Ethernet Interrupt Events Example 30-30 LocalTalk Frame Format. 31-1 Connecting MSC8101 LocalTalk 31-3 Block Diagram 32-2 Memory Structure 32-3 UART Frame Format 32-8 Synchronization With SMSYNx 32-16 Synchronization With 32-17 RxBD Example 32-30 UART Interrupts Example 32-34 Structure MCC. 33-3 Transmitter Super Channel Example. 33-6 Receiver Super Channel with Slot Synchronization Example 33-7 Receiver Super Channel without Slot Synchronization Example 33-7 Interrupt Circular Table. 33-12 Block Diagram 34-3 Memory Structure 34-3 Buffer Descriptor Format 34-4 Output Delay from Asserted 34-10 Output Delay from Asserted 34-11
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Figures
Figure 34-6. Figure 34-7. Figure 35-1. Figure 35-2. Figure 35-3. Figure 35-4. Figure 35-5. Figure 35-6. Figure 35-7. Figure 35-8. Figure 35-9. Figure 35-10. Figure 35-11. Figure 35-12. Figure 35-13. Figure 35-14. Figure 35-15. Figure 35-16. Figure 35-17. Figure 35-18. Figure 35-19. Figure 35-20. Figure 35-21. Figure 35-22. Figure 35-23. Figure 35-24. Figure 35-25. Figure 35-26. Figure 35-27. Figure 35-28. Figure 35-29. Figure 35-30. Figure 35-31. Figure 35-32. Figure 35-33. Figure 35-34. Figure 35-35. Figure 35-36.
Lost 34-11
Using Control Reception 34-12 Scheduling Table Mechanism. 35-10 Pacing Using GCRA (Leaky Bucket Algorithm). 35-13 External Data Input 35-15 External Data Output. 35-16 Address Compression Mechanism 35-17 General VCOFFSET Formula Contiguous VCLTs. 35-18 Pointer Address Compression 35-19 Pointer Address Compression. 35-19 AAddress Recognition Flowchart 35-20 MSC8101's Basic Model 35-21 Transmit Flow 35-23 Transmit Flow (Continued) 35-24 Transmit Flow (Continued) 35-25 Receive Flow 35-26 Rate Format Cells 35-27 Rate Formula Cells 35-28 Performance Monitoring Cell Structure (FMCs BRCs) 35-31 FMC, Insertion 35-34 External Address Extended Address Mode 35-35 ATM-to-TDM Interworking 35-37 Example 1024-Entry Receive Connection Table 35-45 APace Control Data Structure 35-70 Scheduling Table Structure 35-72 Transmit Buffers Table Example 35-73 Receive Static Buffer Allocation Example 35-74 Receive Global Buffer Allocation Example 35-75 Free Buffer Pool Structure. 35-76 AAL1 Sequence Number (SN) Protection Table 35-78 Interrupt Queue Structure 35-80 UTOPIA Master Mode Signals 35-82 UTOPIA Slave Mode Signals 35-85 AAL1 SRTS Generation Using External Logic 35-87 AAL1 SRTS Clock Recovery Using External Logic 35-88 Transmit Internal Rate Clocking. 35-96 User-Defined Cell-RxBD Extension 35-102 User-Defined Cell-TxBD Extension. 35-107
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Figures
Figure 36-1. Figure 36-2. Figure 36-3. Figure 36-4. Figure 36-5. Figure 36-6. Figure 37-1. Figure 37-2. Figure 37-3. Figure 37-4. Figure 38-1. Figure 38-2. Figure 39-1. Figure 39-2. Figure 39-3. Figure 39-4. Figure 39-5. Figure 39-6. Figure 40-1. Figure 40-2. Figure 40-3. Figure 40-4. Figure 40-5. Figure 40-6. Figure 41-1. Figure 41-2.
Ethernet Frame Structure. 36-1 Fast Ethernet Block Diagram 36-3 Connecting MSC8101 Ethernet. 36-5 Ethernet Address Recognition Flowchart 36-18 Ethernet Interrupt Events Example 36-25 Ethernet Receiving Using RxBDs 36-29 Typical HDLC Framing Structure. 37-2 HDLC Address Recognition Example 37-6 HDLC Receiving Using RxBDs 37-9 HDLC Interrupt Event Example 37-18 In-Line Synchronization Pattern 38-3 Sending Transparent Frames Between MSC8101s 38-4 Block Diagram 39-2 Single-Master/Multi-Slave Configuration. 39-4 Multimaster Configuration 39-6 Memory Structure. 39-9 Transfer Format With SPMODE[CP] 39-14 Transfer Format with SPMODE[CP]=1 39-14 Controller Block Diagram 40-1 Master/Slave General Configuration 40-3 Transfer Timing 40-3 Master Write Timing 40-4 Master Read Timing 40-5 Memory Structure 40-9 Port Functional Operation 41-2 Primary Secondary Option Programming 41-4
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Figures
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Tables
Table Pref-1. Table Pref-2. Table 1-1. Table 1-2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. SC140 Data Types xlix Data Type Sizes MSC8101 Serial Protocols 1-11 MSC8101 Serial Performance 1-13 DALU Arithmetic Instructions 2-14 DALU Logical Instructions 2-16 Arithmetic Instructions 2-17 Move Instructions 2-17 Stack Support Instructions 2-18 Mask Instructions 2-18 Change-of-Flow Instructions 2-19 Loop Instructions 2-20 Program Control Instructions 2-20 MSC8101 Functional Signal Groupings. Power Ground Signal Inputs Clock Signals Reset, Configuration, EOnCE Event Signals. PowerPC System Bus, HDI16, Interrupt Signals. Memory Controller Signals 3-15 Port Signals 3-18 Port Signals 3-26 Port Signals 3-31 Port Signals 3-40 JTAG Test Access Port Signals 3-44 Reserved Signals. 3-45 System Configuration Protection Functions Pins Multiplexing Control Descriptions PPC_ACR Descriptions 4-12 LCL_ACR Descriptions 4-14 SIUMCR Descriptions 4-15 IMMR Descriptions 4-18 SYPCR Descriptions. 4-19 TESCR1 Descriptions 4-21 TESCR2 Descriptions 4-22 L_TESCR1 Descriptions 4-23
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Tables
Table 4-12. Table 4-13. Table 4-14. Table 4-15. Table 4-16. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 6-1. Table 6-2. Table 6-3. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 10-5. Table 10-6. Table 10-7. Table 10-8. Table 10-9. Table 10-10. Table 10-11. Table 10-12. Table 10-13. Table 10-14. Table 10-15. Table 10-16. Table 10-17. Table 10-18. Table 10-19. Table 10-20.
TMCNTSC Descriptions 4-24 TMCNTAL Descriptions 4-25 PISCR Descriptions 4-26 PITC Descriptions.

16-Bit Digital Signal Processor MSC8101RM/D Revision April 2001

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