MPC8260 PowerQUICC Manual PowerQUICC Mfax, DigitalDNA trademarks
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MPC8260UM/D 4/1999 Rev.
MPC8260 PowerQUICC Manual
PowerQUICC Mfax, DigitalDNA trademarks Motorola, Inc. PowerPC name, PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, PowerPC 604e, RS/6000 trademarks International Business Machines Corporation used Motorola under license from International Business Machines Corporation. registered trademark Philips Semiconductors
Information this document provided solely enable system software implementers PowerPC microprocessors. There express implied copyright licenses granted hereunder design fabricate PowerPC integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. parameters vary different applications. operating parameters, including must validated each customer application technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Action Employer. Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 1-303-675-2140 JAPAN: Nippon Motorola SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488 ASIA/PACIFC: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong; Tel.: 852-26629298 RMFAX0@email.sps.mot.com; TOUCHTONE 1-602-244-6609; Canada ONLY (800) 774-1848; World Wide Address: http://sps.motorola.com/mfax INTERNET: http://motorola.com/sps Technical Information: Motorola Inc. Customer Support Center; 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com. Document Comments: (512) 895-2638, Attn: RISC Applications Engineering. World Wide Addresses: http://www.mot.com/PowerPC http://www.mot.com/netcomm http://www.mot.com/HPESD
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Overview PowerPC Processor Core Memory System Interface Unit (SIU) Reset External Signals Signals Clocks Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Communications Processor Module Overview Serial Interface with Time-Slot Assigner Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels IDMA Emulation Serial Communications Controllers (SCCs) UART Mode HDLC Mode BISYNC Mode Transparent Mode Ethernet Mode AppleTalk Mode Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers AController Fast Ethernet Controller HDLC Controller Transparent Controller Serial Peripheral Interface (SPI) Controller Parallel Ports
Register Quick Reference Guide Glossary Index
Overview PowerPC Processor Core Memory System Interface Unit (SIU) Reset External Signals Signals Clocks Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Communications Processor Module Overview Serial Interface with Time-Slot Assigner Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels IDMA Emulation Serial Communications Controllers (SCCs) UART Mode HDLC Mode BISYNC Mode Transparent Mode Ethernet Mode AppleTalk Mode Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers AController Fast Ethernet Controller HDLC Controller Transparent Controller Serial Peripheral Interface (SPI) Controller Parallel Ports Register Quick Reference Guide Glossary Index
CONTENTS
Paragraph Number Title Page Number
About This Book
Before Using this Note. Audience Organization. Suggested Reading. MPC8xx Documentation PowerPC Documentation Conventions Acronyms Abbreviations PowerPC Architecture Terminology Conventions lxiv Chapter
Overview
1.2.1 1.2.2 1.2.3 1.3.1 1.6.1 1.6.2 1.7.1 1.7.1.1 1.7.1.2 1.7.1.3 1.7.1.4 1.7.1.5 1.7.1.6 Features Architecture Overview MPC603e Core System Interface Unit (SIU) Communications Processor Module (CPM) Software Compatibility Issues Signals. Differences between MPC860 MPC8260. Serial Protocol Table. MPC8260 Configurations 1-10 Configurations 1-10 Serial Performance. 1-10 MPC8260 Application Examples 1-11 Examples Communication Systems 1-11 Remote Access Server 1-11 Regional Office Router. 1-12 LAN-to-WAN Bridge Router 1-13 Cellular Base Station 1-14 Telecommunications Switch Controller 1-14 SONET Transmission Controller 1-15
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Paragraph Number 1.7.2 1.7.2.1 1.7.2.2 1.7.2.3 Title Page Number Configurations.1-15 Basic System .1-15 High-Performance Communication .1-16 High-Performance System Microprocessor .1-17 Chapter
PowerPC Processor Core
2.2.1 2.2.2 2.2.3 2.2.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.5 2.2.6 2.2.6.1 2.2.6.2 2.3.1 2.3.1.1 2.3.1.2 2.3.1.2.1 2.3.1.2.2 2.3.1.2.3 2.3.1.2.4 2.3.2 2.3.2.1 2.3.2.2 2.3.2.3 2.4.1 2.4.2 2.4.2.1 2.4.2.2 2.4.2.3 2.4.2.3.1 2.4.2.3.2 Overview .2-1 PowerPC Processor Core Features .2-3 Instruction Unit.2-5 Instruction Queue Dispatch Unit .2-5 Branch Processing Unit (BPU).2-6 Independent Execution Units .2-6 Integer Unit (IU).2-6 Load/Store Unit (LSU) .2-7 System Register Unit (SRU) .2-7 Completion Unit .2-7 Memory Subsystem Support .2-8 Memory Management Units (MMUs) .2-8 Cache Units .2-8 Programming Model.2-8 Register Set.2-8 PowerPC Register .2-9 MPC8260-Specific Registers .2-11 Hardware Implementation-Dependent Register (HID0) .2-11 Hardware Implementation-Dependent Register (HID1) .2-14 Hardware Implementation-Dependent Register (HID2) .2-15 Processor Version Register (PVR) .2-16 PowerPC Instruction Addressing Modes.2-16 Calculating Effective Addresses .2-16 PowerPC Instruction .2-16 MPC8260 Implementation-Specific Instruction .2-18 Cache Implementation.2-18 PowerPC Cache Model.2-18 MPC8260 Implementation-Specific Cache Implementation.2-19 Data Cache .2-19 Instruction Cache.2-21 Cache Locking.2-21 Entire Cache Locking.2-21 Locking .2-21 Exception Model.2-22
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Paragraph Number 2.5.1 2.5.2 2.5.3 2.6.1 2.6.2 Title Page Number
PowerPC Exception Model .2-22 MPC8260 Implementation-Specific Exception Model.2-23 Exception Priorities.2-26 Memory Management .2-26 PowerPC Model .2-27 MPC8260 Implementation-Specific Features .2-28 Instruction Timing.2-29 Differences between Core PowerPC 603e Microprocessor.2-30 Chapter
Memory
Chapter
System Interface Unit (SIU)
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.3 4.2.4 4.2.4.1 4.3.1 4.3.1.1 4.3.1.2 4.3.1.3 4.3.1.4 4.3.1.5 4.3.1.6 4.3.1.7 4.3.2 4.3.2.1 System Configuration Protection .4-2 Monitor .4-3 Timers Clock.4-4 Time Counter (TMCNT).4-4 Periodic Interrupt Timer (PIT) .4-5 Software Watchdog Timer .4-6 Interrupt Controller .4-7 Interrupt Configuration .4-8 Interrupt Source Priorities .4-9 SCC, FCC, Relative Priority .4-12 PIT, TMCNT, Relative Priority .4-12 Highest Priority Interrupt .4-13 Masking Interrupt Sources .4-13 Interrupt Vector Generation Calculation.4-14 Port External Interrupts .4-16 Programming Model .4-17 Interrupt Controller Registers .4-17 Interrupt Configuration Register (SICR) .4-17 Interrupt Priority Register (SIPRR) .4-18 Interrupt Priority Registers (SCPRR_H SCPRR_L) .4-19 Interrupt Pending Registers (SIPNR_H SIPNR_L).4-21 Interrupt Mask Registers (SIMR_H SIMR_L) .4-22 Interrupt Vector Register (SIVEC).4-23 External Interrupt Control Register (SIEXR) .4-24 System Configuration Protection Registers .4-25 Configuration Register (BCR) .4-25
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Paragraph Number 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.2.9 4.3.2.10 4.3.2.11 4.3.2.12 4.3.2.13 4.3.2.14 4.3.2.15 4.3.2.16 4.3.3 4.3.3.1 4.3.3.2 4.3.3.3 Title Page Number Arbiter Configuration Register (PPC_ACR) .4-28 Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) .4-28 Local Arbiter Configuration Register (LCL_ACR) .4-29 Local Arbitration Level Registers (LCL_ALRH LCL_ACRL).4-30 Module Configuration Register (SIUMCR) .4-31 Internal Memory Register (IMMR) .4-34 System Protection Control Register (SYPCR) .4-35 Software Service Register (SWSR).4-36 Transfer Error Status Control Register (TESCR1).4-36 Transfer Error Status Control Register (TESCR2).4-37 Local Transfer Error Status Control Register (L_TESCR1) .4-38 Local Transfer Error Status Control Register (L_TESCR2) .4-39 Time Counter Status Control Register (TMCNTSC) .4-40 Time Counter Register (TMCNT).4-41 Time Counter Alarm Register (TMCNTAL) .4-41 Periodic Interrupt Registers.4-42 Periodic Interrupt Status Control Register (PISCR).4-42 Periodic Interrupt Timer Count Register (PITC) .4-43 Periodic Interrupt Timer Register (PITR) .4-44 Multiplexing.4-44 Chapter
Reset
5.1.1 5.1.2 5.1.3 5.1.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 5.4.2.3 5.4.2.4 Reset Causes .5-1 Reset Actions.5-2 Power-On Reset Flow.5-2 HRESET Flow .5-3 SRESET Flow.5-3 Reset Status Register (RSR) .5-4 Reset Mode Register (RMR) .5-5 Reset Configuration.5-6 Hard Reset Configuration Word.5-8 Hard Reset Configuration Examples .5-9 Single MPC8260 with Default Configuration.5-9 Single MPC8260 Configured from Boot EPROM.5-10 Multiple MPC8260s Configured from Boot EPROM.5-10 Multiple MPC8260s System with EPROM.5-12 Chapter
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External Signals
Functional Pinout .6-1 Signal Descriptions .6-2 Chapter
Signals
7.2.1 7.2.1.1 7.2.1.1.1 7.2.1.1.2 7.2.1.2 7.2.1.2.1 7.2.1.2.2 7.2.1.3 7.2.1.3.1 7.2.1.3.2 7.2.2 7.2.2.1 7.2.2.1.1 7.2.2.2 7.2.3 7.2.3.1 7.2.3.1.1 7.2.3.1.2 7.2.4 7.2.4.1 7.2.4.1.1 7.2.4.1.2 7.2.4.2 7.2.4.3 7.2.4.4 7.2.4.4.1 7.2.4.4.2 7.2.4.5 7.2.4.6 7.2.5 7.2.5.1 7.2.5.1.1 7.2.5.1.2
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Signal Configuration .7-2 Signal Descriptions .7-3 Address Arbitration Signals.7-3 Request .7-3 Address Request .7-3 Address Request .7-4 Grant (BG) .7-4 Grant Grant .7-5 Address Busy (ABB) .7-5 Address Busy .7-5 Address Busy Address Transfer Start Signal .7-6 Transfer Start (TS) .7-6 Transfer Start .7-6 Transfer Start Address Transfer Signals .7-7 Address .7-7 Address .7-7 Address Address Transfer Attribute Signals.7-7 Transfer Type Transfer Type Transfer Type .7-8 Transfer Size .7-8 Transfer Burst (TBST) .7-8 Global (GBL) .7-9 Global .7-9 Global Caching-Inhibited Write-Through .7-9 Address Transfer Termination Signals.7-10 Address Acknowledge (AACK) .7-10 Address Acknowledge .7-10 Address Acknowledge
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Paragraph Number 7.2.5.2 7.2.5.2.1 7.2.5.2.2 7.2.6 7.2.6.1 7.2.6.1.1 7.2.6.1.2 7.2.6.2 7.2.6.2.1 7.2.6.2.2 7.2.7 7.2.7.1 7.2.7.1.1 7.2.7.1.2 7.2.7.2 7.2.7.2.1 7.2.7.2.2 7.2.8 7.2.8.1 7.2.8.1.1 7.2.8.1.2 7.2.8.2 7.2.8.2.1 7.2.8.2.2 7.2.8.3 7.2.8.3.1 7.2.8.3.2 Title Page Number Address Retry (ARTRY).7-11 Address Retry Address Retry .7-11 Data Arbitration Signals.7-12 Data Grant (DBG) .7-12 Data Grant .7-12 Data Grant Data Busy (DBB) .7-13 Data Busy .7-13 Data Busy Data Transfer Signals .7-13 Data .7-13 Data Data .7-14 Data Parity .7-14 Data Parity .7-14 Data Parity Data Transfer Termination Signals .7-15 Transfer Acknowledge (TA) .7-15 Transfer Acknowledge Transfer Acknowledge .7-16 Transfer Error Acknowledge (TEA) .7-16 Transfer Error Acknowledge Transfer Error Acknowledge .7-17 Partial Data Valid Indication (PSDVAL).7-17 Partial Data Valid .7-17 Partial Data Valid Chapter
8.2.1 8.2.2 8.3.1 8.3.2 8.4.1 8.4.2 8.4.3 Terminology .8-1 Configuration.8-2 Single MPC8260 Mode.8-2 60x-Compatible Mode.8-3 Protocol Overview.8-4 Arbitration Phase .8-5 Address Pipelining Split-Bus Transactions .8-7 Address Tenure Operations .8-7 Address Arbitration .8-7 Address Pipelining.8-9 Address Transfer Attribute Signals .8-10
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Paragraph Number 8.4.3.1 8.4.3.2 8.4.3.3 8.4.3.4 8.4.3.5 8.4.3.6 8.4.3.7 8.4.3.8 8.4.4 8.4.4.1 8.4.4.2 8.4.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.7.1 8.7.2 Title Page Number
Transfer Type Signal Encoding .8-10 Transfer Code Signals .8-13 TBST Signals Size Transfer.8-13 Burst Ordering During Data Transfers.8-14 Effect Alignment Data Transfers.8-14 Effect Port Size Data Transfers .8-16 60x-Compatible Calculation.8-19 Extended Transfer Mode.8-20 Address Transfer Termination .8-23 Address Retried with ARTRY .8-23 Address Tenure Timing Configuration .8-25 Pipeline Control .8-26 Data Tenure Operations .8-26 Data Arbitration .8-26 Data Streaming Mode .8-27 Data Transfers Normal Termination .8-27 Effect ARTRY Assertion Data Transfer Arbitration .8-28 Port Size Data Transfers PSDVAL Termination .8-28 Data Termination Assertion TEA.8-30 Memory Protocol.8-31 Processor State Signals.8-32 Support lwarx/stwcx. Instruction Pair .8-33 TLBISYNC Input.8-33 Little-Endian Mode .8-33 Chapter
Clocks Power Control
9.4.1 9.4.2 9.6.1 Clock Unit .9-1 Clock Configuration.9-2 External Clock Inputs.9-5 Main .9-5 Block Diagram .9-5 Skew Elimination .9-6 Clock Dividers.9-6 Internal Clock Signals.9-6 General System Clocks .9-7 Pins.9-7
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Paragraph Number 9.10 Title Page Number System Clock Control Register (SCCR) .9-8 System Clock Mode Register (SCMR) .9-9 Basic Power Structure .9-10 Chapter
Memory Controller
10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 10.2.10 10.2.11 10.2.12 10.2.13 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.3.10 10.3.11 10.3.12 10.3.13 10.3.14 10.4 10.4.1 10.4.2 10.4.3 10.4.4 Features.10-3 Basic Architecture .10-5 Address Address Space Checking .10-8 Page Checking.10-9 Error Checking Correction (ECC) .10-9 Parity Generation Checking.10-9 Transfer Error Acknowledge (TEA) Generation.10-9 Machine Check Interrupt (MCP) Generation .10-9 Data Buffer Controls (BCTLx) .10-10 Atomic Operation.10-10 Data Pipelining .10-10 External Memory Controller Support.10-11 External Address Latch Enable Signal (ALE).10-11 ECC/Parity Byte Select (PBSE) .10-11 Partial Data Valid Indication (PSDVAL).10-12 Register Descriptions.10-13 Base Registers (BRx) .10-14 Option Registers (ORx).10-16 SDRAM Mode Register (PSDMR) .10-21 Local SDRAM Mode Register (LSDMR) .10-24 Machine A/B/C Mode Registers (MxMR) .10-26 Memory Data Register (MDR).10-28 Memory Address Register (MAR) .10-29 Bus-Assigned Refresh Timer (PURT).10-30 Local Bus-Assigned Refresh Timer (LURT).10-30 Bus-Assigned SDRAM Refresh Timer (PSRT) .10-31 Local Bus-Assigned SDRAM Refresh Timer (LSRT).10-32 Memory Refresh Timer Prescaler Register (MPTPR) .10-32 Error Status Control Registers (TESCRx).10-33 Local Error Status Control Registers (L_TESCRx) .10-33 SDRAM Machine .10-33 Supported SDRAM Configurations .10-35 SDRAM Power-On Initialization .10-35 JEDEC-Standard SDRAM Interface Commands.10-35 Page-Mode Support Pipeline Accesses .10-36
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Paragraph Number 10.4.5 10.4.5.1 10.4.6 10.4.6.1 10.4.6.2 10.4.6.3 10.4.6.4 10.4.6.5 10.4.6.6 10.4.6.7 10.4.6.8 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 10.4.12 10.4.12.1 10.4.13 10.5 10.5.1 10.5.1.1 10.5.1.2 10.5.1.3 10.5.1.4 10.5.1.5 10.5.1.6 10.5.2 10.5.3 10.5.4 10.6 10.6.1 10.6.1.1 10.6.1.2 10.6.1.3 10.6.1.4 10.6.2 10.6.3 10.6.4 10.6.4.1 10.6.4.1.1 10.6.4.1.2 10.6.4.1.3 Title Page Number
Bank Interleaving .10-36 SDRAM Address Multiplexing (SDAM BSMA) .10-37 SDRAM Device-Specific Parameters .10-38 Precharge-to-Activate Interval .10-38 Activate Read/Write Interval .10-39 Column Address First Data Latency .10-40 Last Data Precharge .10-40 Last Data Recovery .10-41 Refresh Recovery Interval (RFRC).10-41 External Address Multiplexing Signal .10-41 External Address Command Buffers (BUFCMD) .10-42 SDRAM Interface Timing.10-42 SDRAM Read/Write Transactions.10-46 SDRAM Mode-Set Command Timing .10-46 SDRAM Refresh .10-47 SDRAM Refresh Timing .10-47 SDRAM Configuration Examples .10-48 SDRAM Configuration Example (Page-Based Interleaving) .10-48 SDRAM Configuration Example (Bank-Based Interleaving) .10-50 General-Purpose Chip-Select Machine (GPCM) .10-51 Timing Configuration.10-52 Chip-Select Assertion Timing.10-53 Chip-Select Write Enable Deassertion Timing .10-54 Relaxed Timing.10-55 Output Enable (OE) Timing.10-57 Programmable Wait State Configuration .10-57 Extended Hold Time Read Accesses .10-57 External Access Termination .10-60 Boot Chip-Select Operation .10-61 Differences between GPCM GPCM.10-62 User-Programmable Machines (UPMs) .10-62 Requests .10-64 Memory Access Requests .10-65 Refresh Timer Requests .10-65 Software Command.10-66 Exception Requests .10-66 Programming UPMs.10-66 Clock Timing .10-67 Array .10-69 Words .10-70 Chip-Select Signals (CxTx) .10-74 Byte-Select Signals (BxTx) .10-75 General-Purpose Signals (GxTx, GOx) .10-76
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Paragraph Number 10.6.4.1.4 10.6.4.1.5 10.6.4.2 10.6.4.3 10.6.4.4 10.6.4.5 10.6.4.6 10.6.5 10.6.6 10.7 10.7.0.1 10.8 10.8.1 10.8.2 10.9 10.9.1 10.9.2 10.9.3 10.9.4 10.9.5 10.9.6 10.9.6.1 Title Page Number Loop Control .10-76 Repeat Execution Current Word (REDO) .10-76 Address Multiplexing .10-77 Data Valid Data Sample Control .10-77 Signals Negation.10-78 Wait Mechanism .10-78 Extended Hold Time Read Accesses .10-79 DRAM Configuration Example.10-79 Differences between MPC8xx MPC8260 .10-80 Memory System Interface Example Using .10-81 Interface Example .10-92 Handling Devices with Slow Variable Access Times.10-100 Hierarchical Interface Example.10-100 Slow Devices Example.10-100 External Master Support (60x-Compatible Mode).10-101 60x-Compatible External Masters.10-101 MPC8260-Type External Masters.10-101 Extended Controls 60x-Compatible Mode.10-101 Using BNKSEL SIgnals Single-MPC8260 Mode .10-102 Address Incrementing External Bursting Masters .10-102 External Masters Timing .10-102 Example External Master Using SDRAM Machine .10-104 Chapter
Secondary (L2) Cache Support
11.1 11.1.1 11.1.2 11.1.3 11.2 11.3 11.4 11.5 Cache Configurations.11-1 Copy-Back Mode.11-1 Write-Through Mode.11-2 ECC/Parity Mode .11-4 Cache Interface Parameters.11-7 System Requirements When Using Cache Interface.11-7 Cache Operation.11-7 Timing Example .11-8 Chapter
IEEE 1149.1 Test Access Port
12.1 12.2 12.3 12.4 Overview .12-1 Controller .12-2 Boundary Scan Register .12-3 Instruction Register.12-28
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Paragraph Number 12.5 12.6 Title Page Number
MPC8260 Restrictions .12-30 Nonscan Chain Operation .12-30 Chapter
Communications Processor Module Overview
13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 13.3.9 13.4 13.4.1 13.4.1.1 13.4.2 13.4.3 13.5 13.5.1 13.5.2 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 13.6.6 13.6.7 13.6.8 13.6.9 13.6.10 Features .13-1 MPC8260 Serial Configurations .13-3 Communications Processor (CP) .13-4 Features .13-4 Block Diagram .13-4 PowerPC Core Interface.13-6 Peripheral Interface .13-6 Execution from RAM.13-7 RISC Controller Configuration Register (RCCR) .13-7 RISC Time-Stamp Control Register (RTSCR) .13-9 RISC Time-Stamp Register (RTSR).13-10 RISC Microcode Revision Number .13-10 Command .13-11 Command Register (CPCR) .13-11 Commands.13-13 Command Register Example.13-15 Command Execution Latency .13-15 Dual-Port .13-15 Buffer Descriptors (BDs) .13-17 Parameter .13-17 RISC Timer Tables.13-18 RISC Timer Table Parameter RAM.13-19 RISC Timer Command Register (TM_CMD) .13-20 RISC Timer Table Entries.13-21 RISC Timer Event Register (RTER)/Mask Register (RTMR) .13-21 timer Command .13-22 RISC Timer Initialization Sequence .13-22 RISC Timer Initialization Example .13-22 RISC Timer Interrupt Handling .13-23 RISC Timer Table Scan Algorithm.13-23 Using RISC Timers Track Loading .13-24
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Serial Interface with Time-Slot Assigner
14.1 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.5 14.5.1 14.5.2 14.5.3 14.5.4 14.5.5 14.6 14.6.1 14.6.2 14.7 14.7.1 14.7.2 14.7.2.1 14.7.2.2 Features.14-3 Overview .14-4 Enabling Connections .14-7 Serial Interface RAM.14-8 Multiplexed Channel with Static Frames.14-9 Multiplexed Channel with Dynamic Frames .14-9 Programming Entries .14-10 Programming Example .14-13 Static Dynamic Routing.14-14 Serial Interface Registers.14-17 Global Mode Registers (SIxGMR) .14-17 Mode Registers (SIxMR).14-17 Shadow Address Registers (SIxRSR).14-23 Command Register (SIxCMDR).14-24 Status Registers (SIxSTR) .14-25 Serial Interface Interface Support .14-25 Interface Example .14-26 Interface Programming .14-29 Serial Interface Support .14-31 Activation/Deactivation Procedure .14-33 Serial Interface Programming.14-33 Normal Mode Programming.14-33 SCIT Programming .14-33 Chapter
Multiplexing
15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 Features.15-2 Enabling Connections NMSI.15-3 NMSI Configuration.15-4 Registers .15-6 UTOPIA Address Register (CMXUAR).15-7 Clock Route Register (CMXSI1CR) .15-10 Clock Route Register (CMXSI2CR) .15-11 Clock Route Register (CMXFCR).15-12 Clock Route Register (CMXSCR).15-14 Clock Route Register (CMXSMR).15-17
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Baud-Rate Generators (BRGs)
16.1 16.2 16.3 Configuration Registers (BRGCx).16-2 Autobaud Operation UART .16-4 UART Baud Rate Examples .16-5 Chapter
Timers
17.1 17.2 17.2.1 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 Features .17-2 General-Purpose Timer Units.17-2 Cascaded Mode .17-3 Timer Global Configuration Registers (TGCR1 TGCR2) .17-4 Timer Mode Registers Timer Reference Registers Timer Capture Registers .17-8 Timer Counters Timer Event Registers .17-8 Chapter
SDMA Channels IDMA Emulation
18.1 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.3 18.4 18.5 18.5.1 18.5.1.1 18.5.1.2 18.5.2 18.5.2.1 18.5.2.1.1 18.5.2.1.2 18.5.2.2 18.5.2.2.1 18.5.2.2.2 SDMA Arbitration Transfers .18-2 SDMA Registers .18-3 SDMA Status Register (SDSR) .18-3 SDMA Mask Register (SDMR) .18-4 SDMA Transfer Error Address Registers (PDTEA LDTEA).18-4 SDMA Transfer Error MSNUM Registers (PDTEM LDTEM) .18-4 IDMA Emulation.18-5 IDMA Features.18-5 IDMA Transfers .18-6 Memory-to-Memory Transfers .18-6 External Request Mode .18-8 Normal Mode .18-9 Memory to/from Peripheral Transfers .18-9 Dual-Address Transfers .18-10 Peripheral Memory .18-10 Memory Peripheral .18-10 Single Address (Fly-By) Transfers .18-11 Peripheral-to-Memory Fly-By Transfers .18-11 Memory-to-Peripheral Fly-By Transfers .18-11
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Paragraph Number 18.5.3 18.6 18.7 18.7.1 18.7.1.1 18.7.1.2 18.7.2 18.8 18.8.1 18.8.2 18.8.2.1 18.8.2.2 18.8.2.3 18.8.3 18.8.4 18.8.5 18.9 18.9.1 18.9.2 18.10 18.10.1 18.11 18.12 18.12.1 18.12.2 Title Page Number Controlling Bandwidth.18-12 IDMA Priorities.18-12 IDMA Interface Signals.18-12 DREQx DACKx .18-13 Level-Sensitive Mode.18-13 Edge-Sensitive Mode .18-13 DONEx .18-14 IDMA Operation.18-14 Auto Buffer Buffer Chaining.18-15 IDMAx Parameter .18-16 Channel Mode (DCM) .18-18 Data Transfer Types Programmed .18-20 Programming STS.18-20 IDMA Performance .18-22 IDMA Event Register (IDSR) Mask Register (IDMR).18-22 IDMA .18-23 IDMA Commands .18-26 start_idma Command.18-26 stop_idma Command.18-26 IDMA Exceptions.18-27 Externally Recognizing IDMA Operand Transfers.18-27 Programming Parallel Registers.18-28 IDMA Programming Examples.18-29 Peripheral-to-Memory Mode (60x Local Memory-to-Peripheral Fly-By Mode (Both .18-30 Chapter
Serial Communications Controllers (SCCs)
19.1 19.1.1 19.1.2 19.1.3 19.1.4 19.2 19.3 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.5.1 Features.19-2 General Mode Registers .19-3 Protocol-Specific Mode Register (PSMR) .19-9 Data Synchronization Register (DSR).19-9 Transmit-on-Demand Register (TODR).19-9 Buffer Descriptors (BDs) .19-10 Parameter .19-13 Base Addresses .19-15 Function Code Registers (RFCR TFCR).19-15 Handling Interrupts .19-16 Initializing SCCs.19-17 Controlling Timing with RTS, CTS, .19-18 Synchronous Protocols .19-18
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Paragraph Number 19.3.5.2 19.3.6 19.3.6.1 19.3.7 19.3.8 19.3.8.1 19.3.8.2 19.3.8.3 19.3.8.4 19.3.8.5 19.3.9 Title Page Number
Asynchronous Protocols .19-21 Digital Phase-Locked Loop (DPLL) Operation.19-22 Encoding Data with DPLL .19-24 Clock Glitch Detection.19-26 Reconfiguring SCCs.19-26 General Reconfiguration Sequence Transmitter .19-26 Reset Sequence Transmitter.19-27 General Reconfiguration Sequence Receiver .19-27 Reset Sequence Receiver .19-27 Switching Protocols .19-27 Saving Power .19-27 Chapter
UART Mode
20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.10 20.11 20.12 20.13 20.14 20.15 20.16 20.17 20.18 20.19 20.20 20.21 20.22 Features .20-2 Normal Asynchronous Mode .20-3 Synchronous Mode.20-3 UART Parameter .20-4 Data-Handling Methods: Character- Message-Based.20-5 Error Status Reporting.20-6 UART Commands .20-6 Multidrop Systems Address Recognition.20-7 Receiving Control Characters .20-8 Hunt Mode (Receiver).20-10 Inserting Control Characters into Transmit Data Stream.20-10 Sending Break (Transmitter) .20-11 Sending Preamble (Transmitter).20-11 Fractional Stop Bits (Transmitter).20-11 Handling Errors UART Controller .20-12 UART Mode Register (PSMR) .20-13 UART Receive Buffer Descriptor (RxBD) .20-15 UART Transmit Buffer Descriptor (TxBD) .20-18 UART Event Register (SCCE) Mask Register (SCCM) .20-19 UART Status Register (SCCS).20-21 UART Programming Example .20-22 S-Records Loader Application .20-23
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Paragraph Number Title Chapter Page Number
HDLC Mode
21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.13 21.13.1 21.13.2 21.14 21.14.1 21.14.2 21.14.3 21.14.4 21.14.5 21.14.6 21.14.6.1 21.14.6.2 HDLC Features .21-2 HDLC Channel Frame Transmission.21-2 HDLC Channel Frame Reception .21-3 HDLC Parameter .21-3 Programming HDLC Mode .21-5 HDLC Commands .21-5 Handling Errors HDLC Controller .21-6 HDLC Mode Register (PSMR) .21-7 HDLC Receive Buffer Descriptor (RxBD).21-8 HDLC Transmit Buffer Descriptor (TxBD) .21-11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) .21-12 HDLC Status Register (SCCS) .21-14 HDLC Programming Examples .21-14 HDLC Programming Example .21-15 HDLC Programming Example .21-16 HDLC Mode with Collision Detection .21-17 HDLC Features .21-19 Accessing HDLC Bus.21-19 Increasing Performance .21-20 Delayed Mode .21-21 Using Time-Slot Assigner (TSA) .21-22 HDLC Protocol Programming .21-23 Programming GSMR PSMR HDLC Protocol .21-23 HDLC Controller Programming Example .21-23 Chapter
BISYNC Mode
22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 Features.22-2 BISYNC Channel Frame Transmission.22-2 BISYNC Channel Frame Reception .22-3 BISYNC Parameter RAM.22-3 BISYNC Commands.22-5 BISYNC Control Character Recognition.22-6 BISYNC SYNC Register (BSYNC).22-7 BISYNC Register (BDLE).22-8 Sending Receiving Synchronization Sequence.22-9 Handling Errors BISYNC .22-9 BISYNC Mode Register (PSMR).22-10
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Paragraph Number 22.12 22.13 22.14 22.15 22.16 22.17 Title Page Number
BISYNC Receive (RxBD) .22-12 BISYNC Transmit (TxBD) .22-14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) .22-15 Status Registers (SCCS) .22-16 Programming BISYNC Controller .22-17 BISYNC Programming Example .22-18 Chapter
Transparent Mode
23.1 23.2 23.3 23.4 23.4.1 23.4.1.1 23.4.1.2 23.4.1.2.1 23.4.1.3 23.4.2 23.4.2.1 23.4.2.2 23.4.3 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 Features .23-1 Transparent Channel Frame Transmission Process.23-2 Transparent Channel Frame Reception Process .23-2 Achieving Synchronization Transparent Mode .23-3 Synchronization NMSI Mode .23-3 In-Line Synchronization Pattern .23-3 External Synchronization Signals .23-4 External Synchronization Example.23-4 Transparent Mode without Explicit Synchronization .23-5 Synchronization .23-5 Inline Synchronization Pattern.23-6 Inherent Synchronization .23-6 Frame Detection .23-6 Calculation Transparent Mode.23-6 Transparent Parameter RAM.23-6 Transparent Commands .23-7 Handling Errors Transparent Controller .23-8 Transparent Mode PSMR .23-9 Transparent Receive Buffer Descriptor (RxBD) .23-9 Transparent Transmit Buffer Descriptor (TxBD).23-10 Transparent Event Register (SCCE)/Mask Register (SCCM).23-12 Status Register Transparent Mode (SCCS) .23-13 SCC2 Transparent Programming Example .23-13 Chapter
Ethernet Mode
24.1 24.2 24.3 24.4 24.5 Ethernet MPC8260 .24-2 Features .24-3 Connecting MPC8260 Ethernet .24-4 Ethernet Channel Frame Transmission.24-5 Ethernet Channel Frame Reception .24-6
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Paragraph Number 24.6 24.7 24.8 24.9 24.10 24.11 24.12 24.13 24.14 24.15 24.16 24.17 24.18 24.19 24.20 24.21 Title Page Number Content-Addressable Memory (CAM) Interface .24-7 Ethernet Parameter RAM.24-8 Programming Ethernet Controller .24-10 Ethernet Commands.24-10 Ethernet Address Recognition .24-11 Hash Table Algorithm .24-13 Interpacket Time .24-13 Handling Collisions .24-13 Internal External Loopback .24-14 Full-Duplex Ethernet Support .24-14 Handling Errors Ethernet Controller .24-14 Ethernet Mode Register (PSMR).24-15 Ethernet Receive BD.24-17 Ethernet Transmit Buffer Descriptor .24-19 Ethernet Event Register (SCCE)/Mask Register (SCCM).24-21 Ethernet Programming Example.24-23 Chapter
AppleTalk Mode
25.1 25.2 25.3 25.4 25.4.1 25.4.2 25.4.3 25.4.4 Operating LocalTalk Bus.25-1 Features.25-2 Connecting AppleTalk.25-3 Programming AppleTalk Mode .25-3 Programming GSMR.25-3 Programming PSMR.25-4 Programming TODR .25-4 AppleTalk Programming Example .25-4 Chapter
Serial Management Controllers (SMCs)
26.1 26.2 26.2.1 26.2.2 26.2.3 26.2.3.1 26.2.4 26.2.4.1 26.2.4.2 26.2.4.3 Features.26-2 Common Settings Configurations .26-3 Mode Registers (SMCMR1/SMCMR2) .26-3 Buffer Descriptor Operation .26-5 Parameter .26-6 Function Code Registers (RFCR/TFCR) .26-8 Disabling SMCs On-the-Fly.26-9 Transmitter Full Sequence .26-9 Transmitter Shortcut Sequence .26-9 Receiver Full Sequence.26-9
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Paragraph Number 26.2.4.4 26.2.4.5 26.2.5 26.2.6 26.3 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.3.6 26.3.7 26.3.8 26.3.9 26.3.10 26.3.11 26.3.12 26.4 26.4.1 26.4.2 26.4.3 26.4.4 26.4.5 26.4.6 26.4.7 26.4.8 26.4.9 26.4.10 26.4.11 26.5 26.5.1 26.5.2 26.5.2.1 26.5.2.2 26.5.3 26.5.3.1 26.5.3.2 26.5.4 26.5.5 26.5.6 26.5.7 26.5.8 26.5.9 Title Page Number
Receiver Shortcut Sequence .26-10 Switching Protocols .26-10 Saving Power .26-10 Handling Interrupts SMC.26-10 UART Mode .26-10 Features .26-11 UART Channel Transmission Process .26-11 UART Channel Reception Process.26-12 Programming UART Controller .26-12 UART Transmit Receive Commands .26-12 Sending Break .26-13 Sending Preamble.26-13 Handling Errors UART Controller .26-13 UART RxBD .26-14 UART TxBD .26-16 UART Event Register (SMCE)/Mask Register (SMCM) .26-18 UART Controller Programming Example.26-19 Transparent Mode.26-20 Features .26-21 Transparent Channel Transmission Process .26-21 Transparent Channel Reception Process .26-22 Using SMSYN Synchronization.26-22 Using Time-Slot Assigner (TSA) Synchronization.26-23 Transparent Commands .26-25 Handling Errors Transparent Controller.26-25 Transparent RxBD .26-26 Transparent TxBD .26-27 Transparent Event Register (SMCE)/Mask Register (SMCM) .26-28 Transparent NMSI Programming Example .26-29 Mode.26-30 Parameter .26-30 Handling Monitor Channel.26-31 Monitor Channel Transmission Process .26-31 Monitor Channel Reception Process .26-31 Handling Channel.26-31 Channel Transmission Process .26-31 Channel Reception Process .26-31 Commands .26-32 Monitor Channel RxBD.26-32 Monitor Channel TxBD .26-32 Channel RxBD.26-33 Channel TxBD .26-33 Event Register (SMCE)/Mask Register (SMCM) .26-34
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Paragraph Number Title Chapter Page Number
Multi-Channel Controllers (MCCs)
27.1 27.2 27.3 27.4 27.5 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.7 27.7.1 27.8 27.9 27.10 27.10.1 27.10.1.1 27.11 27.11.1 27.11.2 27.12 27.12.1 27.12.2 27.13 Features.27-1 Data Structure Organization .27-2 Global Parameters.27-3 Channel Extra Parameters .27-5 Super-Channel Table .27-5 Channel-Specific HDLC Parameters.27-8 Internal Transmitter State (TSTATE) .27-9 Interrupt Mask (INTMSK) .27-9 Channel Mode Register (CHAMR).27-10 Internal Receiver State (RSTATE).27-11 Channel-Specific Transparent Parameters.27-12 Channel Mode Register Mode .27-13 Configuration Registers (MCCFx) .27-15 Commands .27-16 Exceptions.27-17 Event Register (MCCE)/Mask Register (MCCM) .27-18 Interrupt Table Entry .27-19 Buffer Descriptors .27-21 Receive Buffer Descriptor (RxBD) .27-21 Transmit Buffer Descriptor (TxBD).27-23 Initialization Start/Stop Sequence.27-24 Single-Channel Initialization.27-25 Super Channel Initialization .27-26 Latency Performance .27-26 Chapter
Fast Communications Controllers (FCCs)
28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.7.1 28.8 28.8.1 28.8.2 Overview .28-2 General Mode Registers (GFMRx).28-3 Protocol-Specific Mode Registers (FPSMRx).28-7 Data Synchronization Registers (FDSRx) .28-7 Transmit-on-Demand Registers (FTODRx) .28-7 Buffer Descriptors.28-8 Parameter .28-10 Function Code Registers (FCRx).28-13 Interrupts from FCCs.28-13 Event Registers (FCCEx).28-14 Mask Registers (FCCMx) .28-14
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Paragraph Number 28.8.3 28.9 28.10 28.11 28.12 28.12.1 28.12.2 28.12.3 28.12.4 28.12.5 28.13 Title Page Number
Status Registers (FCCSx) .28-14 Initialization.28-14 Interrupt Handling .28-15 Timing Control .28-15 Disabling FCCs On-the-Fly.28-19 Transmitter Full Sequence.28-20 Transmitter Shortcut Sequence.28-20 Receiver Full Sequence .28-20 Receiver Shortcut Sequence .28-21 Switching Protocols .28-21 Saving Power.28-21 Chapter
AController
29.1 29.2 29.2.1 29.2.1.1 29.2.1.2 29.2.1.3 29.2.1.4 29.2.2 29.2.2.1 29.2.2.2 29.2.2.3 29.2.3 29.2.4 29.3 29.3.1 29.3.2 29.3.3 29.3.3.1 29.3.3.2 29.3.4 29.3.5 29.3.5.1 29.3.5.2 29.3.5.3 29.3.5.3.1 29.3.5.3.2 29.3.5.4 Features .29-2 AController Overview.29-4 Transmitter Overview .29-5 AAL5 Transmitter Overview .29-5 AAL1 Transmitter Overview .29-5 AAL0 Transmitter Overview .29-6 Transmit External Rate Internal Rate Modes .29-6 Receiver Overview.29-6 AAL5 Receiver Overview .29-7 AAL1 Receiver Overview .29-7 AAL0 Receiver Overview .29-8 Performance Monitoring .29-8 Flow Control .29-8 APace Control (APC) Unit.29-8 Modes AService Types.29-8 Unit Scheduling Mechanism .29-9 Determining Scheduling Table Size.29-10 Determining Cells Slot (CPS) Scheduling Table.29-10 Determining Number Slots Scheduling Table .29-11 Determining Time-Slot Scheduling Rate Channel.29-11 ATraffic Type.29-11 Peak Cell Rate Traffic Type.29-11 Determining Traffic Type Parameters .29-11 Peak Sustain Traffic Type (VBR) .29-12 Example Using Traffic Parameters .29-12 Handling Cell Loss Priority Type .29-13 Peak Minimum Cell Rate Traffic Type (UBR+).29-13
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Paragraph Number 29.3.6 29.4 29.4.1 29.4.2 29.4.2.1 29.4.2.2 29.4.3 29.4.4 29.5 29.5.1 29.5.1.1 29.5.1.2 29.5.1.3 29.5.2 29.5.2.1 29.5.3 29.6 29.6.1 29.6.2 29.6.3 29.6.4 29.6.5 29.6.6 29.6.6.1 29.6.6.2 29.6.6.3 29.6.6.4 29.7 29.7.1 29.8 29.9 29.9.1 29.9.2 29.9.3 29.9.4 29.9.5 29.9.6 29.9.7 29.9.8 29.10 29.10.1 29.10.1.1 29.10.1.2 Title Page Number Determining Priority AChannel .29-13 VCI/VPI Address Lookup Mechanism.29-14 External Lookup .29-14 Address Compression.29-15 VP-Level Address Compression Table (VPLT) .29-17 VC-Level Address Compression Tables (VCLTs) .29-18 Misinserted Cells .29-18 Receive Cell Queue.29-19 Available Rate (ABR) Flow Control .29-20 Model .29-20 Flow Control Source End-System Behavior .29-21 Flow Control Destination End-System Behavior.29-21 Flowcharts .29-22 Cell Structure.29-25 Cell Rate Representation.29-26 Flow Control Setup .29-27 Support .29-27 ATM-Layer Definitions .29-27 Virtual Path (F4) Flow Mechanism.29-28 Virtual Channel (F5) Flow Mechanism.29-28 Receiving Cells.29-28 Transmitting Cells .29-29 Performance Monitoring .29-29 Running Performance Block Test.29-30 Block Monitoring .29-30 Block Generation .29-31 Performance Calculations.29-32 User-Defined Cells (UDC) .29-32 Extended Address Mode (UEAD) .29-33 ALayer Statistics.29-33 ATM-to-TDM Interworking.29-34 Automatic Data Forwarding .29-34 Using Interrupts Automatic Data Forwarding.29-35 Timing Issues.29-36 Clock Synchronization (SRTS Adaptive FIFOs) .29-36 Mapping Time Slots .29-36 Support.29-36 Trunk Condition .29-37 ATM-to-AData Forwarding .29-37 AMemory Structure.29-37 Parameter RAM.29-37 Determining UEAD_OFFSET (UEAD Mode Only) .29-40 Filtering (VCIF).29-40
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Paragraph Number 29.10.1.3 29.10.2 29.10.2.1 29.10.2.2 29.10.2.2.1 29.10.2.2.2 29.10.2.2.3 29.10.2.2.4 29.10.2.3 29.10.2.3.1 29.10.2.3.2 29.10.2.3.3 29.10.2.3.4 29.10.2.3.5 29.10.2.3.6 29.10.3 29.10.4 29.10.4.1 29.10.4.2 29.10.4.3 29.10.5 29.10.5.1 29.10.5.2 29.10.5.2.1 29.10.5.2.2 29.10.5.2.3 29.10.5.2.4 29.10.5.3 29.10.5.4 29.10.5.5 29.10.5.6 29.10.5.7 29.10.5.8 29.10.5.9 29.10.5.10 29.10.5.11 29.10.6 29.10.7 29.11 29.11.1 29.11.2 29.11.3 29.12 Title Page Number
Global Mode Entry (GMODE) .29-41 Connection Tables (RCT, TCT, TCTE).29-41 AChannel Code .29-42 Receive Connection Table (RCT).29-43 AAL5 Protocol-Specific RCT.29-46 AAL5-ABR Protocol-Specific .29-47 AAL1 Protocol-Specific RCT.29-48 AAL0 Protocol-Specific RCT.29-50 Transmit Connection Table (TCT) .29-51 AAL5 Protocol-Specific TCT.29-54 AAL1 Protocol-Specific TCT.29-54 AAL0 Protocol-Specific TCT.29-55 Protocol-Specific TCTE .29-56 UBR+ Protocol-Specific TCTE .29-57 Protocol-Specific TCTE .29-58 Performance Monitoring Tables .29-60 Data Structure.29-61 Parameter Tables .29-62 Priority Table.29-63 Scheduling Tables .29-63 AController Buffer Descriptors (BDs).29-64 Transmit Buffer Operations .29-64 Receive Buffers Operation.29-65 Static Buffer Allocation .29-65 Global Buffer Allocation .29-66 Free Buffer Pools .29-67 Free Buffer Pool Parameter Tables.29-68 AController Buffers .29-69 AAL5 RxBD .29-69 AAL1 RxBD .29-71 AAL0 RxBD .29-72 AAL5, AAL1 User-Defined Extension.29-73 AAL5 TxBDs .29-74 AAL1 TxBDs .29-76 AAL0 TxBDs .29-77 AAL5, AAL1 User-Defined Extension.29-78 AAL1 Sequence Number (SN) Protection Table (AAL1 Only) .29-78 Statistics Table .29-78 AExceptions .29-79 Interrupt Queues.29-79 Interrupt Queue Entry .29-80 Interrupt Queue Parameter Tables .29-81 UTOPIA Interface.29-82
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Paragraph Number 29.12.1 29.12.1.1 29.12.2 29.12.2.1 29.12.2.2 29.12.2.3 29.13 29.13.1 29.13.2 29.13.3 29.13.4 29.14 29.15 29.16 29.16.1 29.16.2 29.16.3 Title Page Number UTOPIA Interface Master Mode.29-82 UTOPIA Master Multiple Operation .29-83 UTOPIA Interface Slave Mode .29-83 UTOPIA Slave Multiple Operation.29-84 UTOPIA Clocking Modes.29-84 UTOPIA Loop-Back Modes .29-85 ARegisters .29-85 General Mode Register (GFMR) .29-85 Protocol-Specific Mode Register (FPSMR) .29-85 AEvent Register (FCCE)/Mask Register (FCCM).29-87 Transmit Internal Rate Registers (FTIRRx) .29-88 ATransmit Command .29-90 SRTS Generation Clock Recovery Using External Logic.29-91 Configuring AController Maximum Performance .29-92 Using Transmit Internal Rate Mode .29-92 Configuration.29-93 Buffer Configuration .29-93 Chapter
Fast Ethernet Controller
30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 30.10 30.11 30.12 30.13 30.14 30.15 30.16 30.17 30.18 30.18.1 30.18.2 Fast Ethernet MPC8260.30-2 Features.30-3 Connecting MPC8260 Fast Ethernet .30-4 Ethernet Channel Frame Transmission.30-5 Ethernet Channel Frame Reception.30-7 Flow Control.30-8 Interface.30-8 Ethernet Parameter .30-9 Programming Model.30-12 Ethernet Command Set.30-12 RMON Support.30-14 Ethernet Address Recognition .30-15 Hash Table Algorithm .30-17 Interpacket Time .30-18 Handling Collisions .30-18 Internal External Loopback .30-18 Ethernet Error-Handling Procedure.30-19 Fast Ethernet Registers .30-19 Ethernet Mode Register (FPSMR).30-20 Ethernet Event Register (FCCE)/Mask Register (FCCM) .30-21
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Paragraph Number 30.19 30.20 Title Page Number
Ethernet RxBDs.30-23 Ethernet TxBDs.30-26 Chapter
HDLC Controller
31.1 31.2 31.3 31.4 31.5 31.5.1 31.5.2 31.6 31.7 31.8 31.9 31.10 Features.31-2 HDLC Channel Frame Transmission Processing.31-2 HDLC Channel Frame Reception Processing.31-3 HDLC Parameter RAM.31-4 Programming Model .31-5 HDLC Command .31-5 HDLC Error Handling.31-6 HDLC Mode Register (FPSMR).31-7 HDLC Receive Buffer Descriptor (RxBD).31-9 HDLC Transmit Buffer Descriptor (TxBD).31-12 HDLC Event Register (FCCE)/Mask Register (FCCM).31-14 Status Register (FCCS).31-16 Chapter
Transparent Controller
32.1 32.2 32.3 32.3.1 32.3.2 32.3.3 Features .32-2 Transparent Channel Operation .32-2 Achieving Synchronization Transparent Mode .32-2 In-Line Synchronization Pattern .32-3 External Synchronization Signals .32-3 Transparent Synchronization Example .32-4 Chapter
Serial Peripheral Interface (SPI)
33.1 33.2 33.3 33.3.1 33.3.2 33.3.3 33.4 33.4.1 33.4.1.1 33.4.2 Features .33-2 Clocking Signal Functions.33-2 Configuring Controller .33-3 Master Device .33-3 Slave Device .33-4 Multimaster Operation .33-4 Programming Registers .33-6 Mode Register (SPMODE) .33-6 Examples with Different SPMODE[LEN] Values.33-8 Event/Mask Registers (SPIE/SPIM) .33-9
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Paragraph Number 33.4.3 33.5 33.5.1 33.6 33.7 33.7.1 33.7.1.1 33.7.1.2 33.8 33.9 33.10 Title Page Number Command Register (SPCOM) .33-9 Parameter .33-10 Receive/Transmit Function Code Registers (RFCR/TFCR) .33-12 Commands .33-12 Buffer Descriptor (BD) Table.33-13 Buffer Descriptors (BDs).33-13 Receive (RxBD) .33-14 Transmit (TxBD).33-15 Master Programming Example .33-16 Slave Programming Example .33-17 Handling Interrupts .33-18 Chapter
Controller
34.1 34.2 34.3 34.3.1 34.3.2 34.3.3 34.3.4 34.4 34.4.1 34.4.2 34.4.3 34.4.4 34.4.5 34.5 34.6 34.7 34.7.1 34.7.1.1 34.7.1.2 Features.34-2 Controller Clocking Signal Functions.34-2 Controller Transfers.34-3 Master Write (Slave Read) .34-4 Loopback Testing .34-4 Master Read (Slave Write) .34-4 Multi-Master Considerations .34-5 Registers.34-6 Mode Register (I2MOD) .34-6 Address Register (I2ADD) .34-7 Baud Rate Generator Register (I2BRG) .34-7 Event/Mask Registers (I2CER/I2CMR) .34-8 Command Register (I2COM) .34-8 Parameter .34-9 Commands .34-11 Buffer Descriptor (BD) Table.34-12 Buffer Descriptors (BDs).34-12 Receive Buffer Descriptor (RxBD) .34-13 Transmit Buffer Descriptor (TxBD).34-14 Chapter
Parallel Ports
35.1 35.2 35.2.1 35.2.2 Features.35-1 Port Registers.35-2 Port Open-Drain Registers Port Data Registers
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Paragraph Number 35.2.3 35.2.4 35.2.5 35.3 35.4 35.4.1 35.4.2 35.5 35.6 Title Page Number
Port Data Direction Registers Port Assignment Register (PPAR).35-4 Port Special Options Registers Port Block Diagram.35-6 Port Pins Functions .35-6 General Purpose Pins .35-7 Dedicated Pins.35-7 Ports Tables .35-7 Interrupts from Port .35-19 Appendix
Register Quick Reference Guide
PowerPC Registers PowerPC Registers. MPC8260-Specific SPRs
Glossary Index
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Paragraph Number Title Page Number
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Figure Number Title Page Number
1-10 1-11 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19
MPC8260 Block Diagram MPC8260 External Signals. Remote Access Server Configuration. 1-11 Regional Office Router Configuration 1-12 LAN-to-WAN Bridge Router Configuration. 1-13 Cellular Base Station Configuration 1-14 Telecommunications Switch Controller Configuration. 1-14 SONET Transmission Controller Configuration 1-15 Basic System Configuration 1-16 High-Performance Communication. 1-16 High-Performance System Microprocessor Configuration 1-17 MPC8260 Integrated Processor Core Block Diagram. MPC8260 Programming 2-10 Hardware Implementation Register (HID0) 2-11 Hardware Implementation Register (HID1) 2-15 Hardware Implementation-Dependent Register (HID2) 2-15 Data Cache Organization 2-20 .SIU Block Diagram System Configuration Protection Logic. Timers Clock Generation. TMCNT Block Diagram. Block Diagram. Software Watchdog Timer Service State Diagram. Software Watchdog Timer Block Diagram MPC8260 Interrupt Structure Interrupt Request Masking 4-14 Interrupt Configuration Register (SICR). 4-17 Interrupt Priority Register (SIPRR). 4-18 High Interrupt Priority Register (SCPRR_H) 4-19 Interrupt Priority Register (SCPRR_L) 4-20 SIPNR_H Fields 4-21 SIPNR_L Fields. 4-21 SIMR_H Register 4-22 SIMR_L Register. 4-23 Interrupt Vector Register (SIVEC) 4-23 Interrupt Table Handling Example 4-24
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Figure Number 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 8-10 8-11 8-12 Page Number External Interrupt Control Register (SIEXR). 4-25 Configuration Register (BCR). 4-26 PPC_ACR 4-28 PPC_ALRH 4-29 PPC_AALRL. 4-29 LCL_ACR. 4-29 LCL_ALRH. 4-30 LCL_ALRL 4-31 Model Configuration Register (SIUMCR). 4-31 Internal Memory Register (IMMR). 4-34 System Protection Control Register (SYPCCR). 4-35 Transfer Error Status Control Register (TESCR1). 4-36 Transfer Error Status Control Register (TESCR2) 4-37 Local Transfer Error Status Control Register (L_TESCR1) 4-38 Local Transfer Error Status Control Register (L_TESCR2) 4-39 Time Counter Status Control Register (TMCNTSC) 4-40 Time Counter Register (TCMCNT) 4-41 Time Counter Alarm Register (TMCNTAL) 4-42 Periodic Interrupt Status Control Register (PISCR) 4-42 Periodic interrupt Timer Count Register (PITC) 4-43 Periodic Interrupt Timer Register (PITR). 4-44 Reset Status Register (RSR) Reset Mode Register (RMR) Hard Reset Configuration Word Single Chip with Default Configuration. 5-10 Configuring Single Chip from EPROM 5-10 Configuring Multiple Chips. 5-11 MPC8260 External Signals. PowerPC Signal Groupings Single MPC8260 Mode 60x-Compatible Mode. Basic Transfer Protocol Address Arbitration with External Master Address Pipelining. 8-10 Interface Different Port Size Devices 8-17 Retry Cycle 8-24 Single-Beat Burst Data Transfers 8-28 128-Bit Extended Transfer 32-Bit Port Size. 8-29 Burst Transfer 32-Bit Port Size 8-30 Data Tenure Terminated Assertion TEA. 8-31 Cache Coherency Diagram (WIM 001). 8-32 System Block Diagram. Filtering Circuit Title
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Figure Number 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 Title Page Number
System Clock Control Register (SCCR). System Clock Mode Register (SCMR). Relationships SCMR Parameters 9-10 Dual-Bus Architecture 10-3 Memory Controller Machine Selection 10-6 Simple System Configuration. 10-7 Basic Memory Controller Operation 10-8 Partial Data Valid 32-Bit Port Size Memory, Double-Word Transfer 10-13 Base Registers (BRx) 10-14 Option Registers Mode 10-16 Mode. 10-18 Mode. 10-20 60x/Local SDRAM Mode Register (PSDMR/LSDMR) 10-21 Machine Mode Registers (MxMR). 10-26 Memory Data Register (MDR) 10-29 Memory Address Register (MAR) 10-29 Bus-Assigned Refresh Timer (PURT) 10-30 Local Bus-Assigned Refresh Timer (LURT). 10-30 Bus-Assigned SDRAM Refresh Timer (PSRT) 10-31 Local Bus-Assigned SDRAM Refresh Timer (LSRT) 10-32 Memory Refresh Timer Prescaler Register (MPTPR). 10-32 128-Mbyte SDRAM (Eight-Bank Configuration, Banks Shown) 10-34 PRETOACT Clock Cycles) 10-39 ACTTORW Clock Cycles) 10-39 Clock Cycles). 10-40 LDOTOPRE Clock Cycles). 10-40 Clock Cycles). 10-41 RFRC Clock Cycles). 10-41 EAMUX 10-42 BUFCMD 10-42 SDRAM Single-Beat Read, Page Closed, 10-43 SDRAM Single-Beat Read, Page Hit, 10-43 SDRAM Two-Beat Burst Read, Page Closed, 10-43 SDRAM Four-Beat Burst Read, Page Miss, 10-44 SDRAM Single-Beat Write, Page 10-44 SDRAM Three-Beat Burst Write, Page Closed 10-44 SDRAM Read-after-Read Pipeline, Page Hit, 10-45 SDRAM Write-after-Write Pipelined, Page 10-45 SDRAM Read-after-Write Pipelined, Page Hit. 10-45 SDRAM Mode-Set Command Timing. 10-46 Mode Data Settings. 10-47 SDRAM Bank-Staggered Refresh Timing 10-48 GPCM-to-SRAM 10-52
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Figure Number 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-50 10-51 10-52 10-53 10-54 10-55 10-56 10-57 10-58 10-59 10-60 10-61 10-62 10-63 10-64 10-65 10-66 10-67 10-68 10-69 10-70 10-71 10-72 10-73 10-74 10-75 10-76 10-77 10-78 10-79 10-80 10-81 Page Number GPCM Peripheral Device Interface 10-53 GPCM Peripheral Device Basic Timing (ACS TRLX 10-53 GPCM Memory Device Interface. 10-54 GPCM Memory Device Basic Timing (ACS CSNT TRLX 10-54 GPCM Memory Device Basic Timing (ACS CSNT TRLX 10-55 GPCM Relaxed Timing Read (ACS CSNT TRLX 10-55 GPCM Relaxed-Timing Write (ACS CSNT 0,TRLX 10-56 GPCM Relaxed-Timing Write (ACS CSNT TRLX 10-56 GPCM Relaxed-Timing Write (ACS CSNT TRLX 10-57 GPCM Read Followed Read Fastest Timing) 10-58 GPCM Read Followed Read 10-59 GPCM Read Followed Write 10-59 GPCM Read Followed Read 10-60 External Termination GPCM Access 10-61 User-Programmable Machine Block Diagram 10-63 Array Indexing. 10-64 Memory Refresh Timer Request Block Diagram 10-66 Memory Controller Clock Scheme Integer Clock Ratios 10-67 Memory Controller Clock Scheme Non-Integer (2.5:1/3.5:1) Clock Ratios 10-68 Signals Timing Example. 10-69 Array Signal Generation 10-70 Word. 10-70 Signal Selection 10-75 Signal Selection 10-75 Read Access Data Sampling 10-78 Wait Mechanism Timing Internal External Synchronous Masters 10-79 DRAM Interface Connection (64-Bit Port Size) 10-82 Single-Beat Read Access DRAM. 10-83 Single-Beat Write Access DRAM 10-84 Burst Read Access DRAM LOOP) 10-85 Burst Read Access DRAM (LOOP) 10-86 Burst Write Access DRAM LOOP) 10-87 Refresh Cycle (CBR) DRAM. 10-88 Exception Cycle. 10-89 DRAM Burst Read Access (Data Sampling Falling Edge CLKIN) 10-91 MPC8260/EDO Interface Connection Bus. 10-92 Single-Beat Read Access DRAM. 10-93 Single-Beat Write Access DRAM. 10-94 Single-Beat Write Access DRAM Using REDO Insert Three Wait States. 10-95 Burst Read Access DRAM. 10-96 Burst Write Access DRAM 10-97 Title
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Figure Number 10-82 10-83 10-84 10-85 10-86 11-1 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 Title Page Number
Refresh Cycle (CBR) DRAM. 10-98 Exception Cycle DRAM 10-99 Pipelined Operation Memory Access 60x-Compatible Mode. 10-103 External Master Access (GPCM) 10-104 External Master Configuration with SDRAM Device. 10-105 Cache Copy-Back Mode 11-2 External Cache Write-Through Mode. 11-4 External Cache ECC/Parity Mode 11-6 Read Access with Cache 11-9 Test Logic Block Diagram. 12-2 Controller State Machine 12-3 Output Cell (O.Pin) 12-4 Observe-Only Input Cell (I.Obs). 12-4 Output Control Cell (IO.CTL). 12-5 General Arrangement Bidirectional Cells. 12-5 MPC8260 Block Diagram. 13-3 Communications Processor (CP) Block Diagram 13-5 RISC Controller Configuration Register (RCCR). 13-8 RISC Time-Stamp Control Register (RTSCR). 13-9 RISC Time-Stamp Register (RTSR) 13-10 Command Register (CPCR). 13-11 Dual-Port Block Diagram 13-15 Dual-Port Memory 13-16 RISC Timer Table Usage 13-19 RISC Timer Command Register (TM_CMD) 13-20 TM_CMD Field Descriptions. 13-21 RISC Timer Event Register (RTER)/Mask Register (RTMR). 13-21 Block Diagram 14-2 Various Configurations Single Channel 14-5 Dual Channel Example 14-6 Enabling Connections 14-8 Channel with Static Frames Independent Routes 14-9 Channel with Shadow Dynamic Route Change 14-10 Entry Fields 14-10 Using SWTR Feature. 14-12 Example: Dynamic Changes, TDMa Same Size 14-16 Global Mode Registers (SIxGMR) 14-17 Mode Registers (SIxMR) 14-18 One-Clock Delay from Sync Data (xFSD 01). 14-20 Delay from Sync Data (xFSD 14-20 Falling Edge (FE) Effect When xFSD 14-21 Falling Edge (FE) Effect When xFSD 14-21 Falling Edge (FE) Effect When xFSD 14-22
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Figure Number 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 16-1 16-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 19-1 Page Number Falling Edge (FE) Effect When xFSD 14-23 Shadow Address Registers (SIxRSR) 14-24 Command Register (SIxCMDR). 14-24 Status Registers (SIxSTR). 14-25 Dual Application Example. 14-26 Terminal Adaptor 14-27 Signals. 14-28 Signals 14-32 Multiplexing Logic (CMX) Block Diagram 15-2 Enabling Connections 15-4 Bank Clocks 15-5 UTOPIA Address Register (CMXUAR) 15-7 Connection Master Address 15-8 Connection Slave Address. 15-9 Multi-PHY Receive Address Multiplexing 15-10 Clock Route Register (CMXSI1CR). 15-11 Clock Route Register (CMXSI2CR). 15-12 Clock Route Register (CMXFCR). 15-13 Clock Route Register (CMXSCR). 15-15 Clock Route Register (CMXSMR) 15-18 Baud-Rate Generator (BRG) Block Diagram. 16-1 Baud-Rate Generator Configuration Registers (BRGCx) 16-2 Timer Block Diagram 17-1 Timer Cascaded Mode Block Diagram 17-4 Timer Global Configuration Register (TGCR1). 17-4 Timer Global Configuration Register (TGCR2). 17-5 Timer Mode Registers 17-6 Timer Reference Registers 17-7 Timer Capture Registers 17-8 Timer Counter Registers 17-8 Timer Event Registers 17-8 SDMA Data Paths. 18-1 SDMA Arbitration (Transaction Steal) 18-3 SDMA Status Register (SDSR) 18-3 SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM). 18-4 IDMA Transfer Buffer Dual-Port RAM. 18-7 Example IDMA Transfer Buffer States Memory-to-Memory Transfer (Size Bytes) 18-8 IDMAx Table. 18-15 Parameters 18-18 IDMA Event/Mask Registers (IDSR/IDMR) 18-23 IDMA Structure 18-23 Block Diagram 19-2 Title
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Figure Number 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 21-16 22-1 Title Page Number
Mode Register (High Order) 19-3 Mode Register (Low Order) 19-6 Data Synchronization Register (DSR). 19-9 Transmit-on-Demand Register (TODR). 19-9 Buffer Descriptors (BDs) 19-11 Buffer Memory Structure. 19-12 Function Code Registers (RFCR TFCR) 19-15 Output Delay from Asserted Synchronous Protocols 19-18 Output Delay from Asserted Synchronous Protocols 19-19 Lost Synchronous Protocols. 19-20 Using Control Synchronous Protocol Reception 19-21 DPLL Receiver Block Diagram. 19-22 DPLL Transmitter Block Diagram 19-23 DPLL Encoding Examples 19-25 UART Character Format 20-1 UART Multidrop Configurations. 20-8 Control Character Table 20-9 Transmit Out-of-Sequence Register (TOSEQ). 20-10 Asynchronous UART Transmitter. 20-11 Protocol-Specific Mode Register UART (PSMR). 20-14 UART Receiving using RxBDs 20-16 UART Receive Buffer Descriptor (RxBD). 20-17 UART Transmit Buffer Descriptor (TxBD) 20-18 UART Interrupt Event Example 20-20 UART Event Register (SCCE) Mask Register (SCCM). 20-20 Status Register UART Mode (SCCS) 20-21 HDLC Framing Structure 21-2 HDLC Address Recognition. 21-5 HDLC Mode Register (PSMR) 21-7 HDLC Receive Buffer Descriptor (RxBD). 21-8 HDLC Receiving Using RxBDs 21-10 HDLC Transmit Buffer Descriptor (TxBD) 21-11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) 21-12 HDLC Interrupt Event Example 21-13 HDLC Status Register (SCCS) 21-14 Typical HDLC Multimaster Configuration 21-18 Typical HDLC Single-Master Configuration 21-19 Detecting HDLC Collision 21-20 Nonsymmetrical Clock Duty Cycle Increased Performance 21-21 HDLC Transmission Line Configuration 21-21 Delayed Mode 21-22 HDLC Transmission Line Configuration 21-22 Classes BISYNC Frames. 22-1
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Figure Number 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 23-1 23-2 23-3 23-4 23-5 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 25-1 25-2 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 26-15 26-16 26-17 26-18 Page Number Control Character Table RCCM 22-6 BISYNC SYNC (BSYNC) 22-7 BISYNC (BDLE). 22-8 Protocol-Specific Mode Register BISYNC (PSMR) 22-10 BISYNC RxBD. 22-12 BISYNC Transmit (TxBD) 22-14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM). 22-15 Status Registers (SCCS). 22-16 Sending Transparent Frames between MPC8260s 23-5 Transparent Receive Buffer Descriptor (RxBD). 23-9 Transparent Transmit Buffer Descriptor (TxBD) 23-11 Transparent Event Register (SCCE)/Mask Register (SCCM) 23-12 Status Register Transparent Mode (SCCS). 23-13 Ethernet Frame Structure 24-1 Ethernet Block Diagram 24-2 Connecting MPC8260 Ethernet. 24-5 Ethernet Address Recognition Flowchart 24-12 Ethernet Mode Register (PSMR). 24-15 Ethernet Receive RxBD 24-17 Ethernet Receiving using RxBDs 24-19 Ethernet TxBD 24-20 Ethernet Event Register (SCCE)/Mask Register (SCCM). 24-21 Ethernet Interrupt Events Example. 24-22 LocalTalk Frame Format 25-1 Connecting MPC8260 LocalTalk 25-3 Block Diagram 26-2 Mode Registers (SMCMR1/SMCMR2). 26-3 Memory Structure 26-5 Function Code Registers (RFCR/TFCR) 26-8 UART Frame Format 26-11 UART RxBD. 26-14 RxBD Example. 26-16 UART TxBD 26-17 UART Event Register (SMCE)/Mask Register (SMCM). 26-18 UART Interrupts Example 26-19 Synchronization with SMSYNx. 26-23 Synchronization with TSA. 26-24 Transparent RxBD. 26-26 Transparent Event Register (SMCE)/Mask Register (SMCM). 26-28 Monitor Channel RxBD 26-32 Monitor Channel TxBD 26-32 Channel RxBD 26-33 Channel TxBD 26-33 Title
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Figure Number 26-19 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 Title Page Number
Event Register (SMCE)/Mask Register (SMCM). 26-34 Structure 27-3 Super Channel Table Entry. 27-5 Transmitter Super Channel Example. 27-6 Receiver Super Channel with Slot Synchronization Example 27-7 Receiver Super Channel without Slot Synchronization Example 27-7 TSTATE High Byte. 27-9 INTMSK Mask Bits. 27-10 Channel Mode Register (CHAMR) 27-10 Internal State (RSTATE) High Byte 27-12 Channel Mode Register Mode. 27-14 Configuration Register (MCCF) 27-15 Interrupt Circular Table 27-17 Event Register (MCCE)/Mask Register (MCCM) 27-18 Interrupt Circular Table Entry 27-20 Receive Buffer Descriptor (RxBD) 27-21 Transmit Buffer Descriptor (TxBD) 27-23 Block Diagram 28-3 General Mode Register (GFMR) 28-3 Memory Structure 28-9 Buffer Descriptor Format 28-9 Function Code Register (FCRx) 28-13 Output Delay from Asserted. 28-16 Output Delay from Asserted. 28-17 Lost. 28-18 Using Control Reception. 28-19 Scheduling Table Mechanism. 29-10 Pacing Using GCRA (Leaky Bucket Algorithm) 29-12 External Data Input Fields 29-14 External Output Fields. 29-14 Address Compression Mechanism 29-16 General VCOFFSET Formula Contiguous VCLTs 29-17 Pointer Address Compression 29-18 Pointer Address Compression 29-18 AAddress Recognition Flowchart. 29-19 Basic Model 29-20 Transmit Flow 29-22 Transmit Flow (Continued) 29-23 Transmit Flow (Continued) 29-24 Receive Flow 29-25 Rate Format Cells 29-26 Rate Formula Cells 29-26 Performance Monitoring Cell Structure (FMCs BRCs) 29-29
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Figure Number 29-18 29-19 29-20 29-21 29-22 29-23 29-24 29-25 29-26 29-27 29-28 29-29 29-30 29-31 29-32 29-33 29-34 29-35 29-36 29-37 29-38 29-39 29-40 29-41 29-42 29-43 29-44 29-45 29-46 29-47 29-48 29-49 29-50 29-51 29-52 29-53 29-54 29-55 29-56 29-57 29-58 29-59 29-60 Page Number FMC, Insertion. 29-32 Format User-Defined Cells 29-33 External Address Extended Address Mode 29-33 ATM-to-TDM Interworking 29-35 Filtering Enable Bits 29-40 Global Mode Entry (GMODE) 29-41 Example 1024-Entry Receive Connection Table 29-43 Receive Connection Table (RCT) Entry. 29-44 AAL5 Protocol-Specific 29-46 AAL5-ABR Protocol-Specific RCT. 29-47 AAL1 Protocol-Specific 29-48 AAL0 Protocol-Specific 29-50 Transmit Connection Table (TCT) Entry 29-51 AAL5 Protocol-Specific TCT. 29-54 AAL1 Protocol-Specific TCT. 29-54 AAL0 Protocol-Specific TCT. 29-55 Transmit Connection Table Extension Protocol-Specific 29-56 UBR+ Protocol-Specific TCTE. 29-57 Protocol-Specific TCTE 29-58 Performance Monitoring Table 29-60 APace Control Data Structure 29-62 Scheduling Table Structure. 29-63 Control Slot. 29-63 Transmit Buffers Table Example 29-65 Receive Static Buffer Allocation Example. 29-66 Receive Global Buffer Allocation Example 29-67 Free Buffer Pool Structure. 29-67 Free Buffer Pool Entry. 29-68 AAL5 RxBD. 29-69 AAL1 RxBD. 29-71 AAL0 RxBD. 29-72 User-Defined Extension. 29-74 AAL5 TxBD 29-74 AAL1 TxBD 29-76 AAL0 TxBDs. 29-77 User-Defined Extension 29-78 AAL1 Sequence Number (SN) Protection Table 29-78 Interrupt Queue Structure 29-80 Interrupt Queue Entry 29-80 UTOPIA Master Mode Signals 29-82 UTOPIA Slave Mode Signals. 29-83 AMode Register (FPSMR). 29-86 AEvent Register (FCCE)/FCC Mask Register (FCCM) 29-88 Title
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Figure Number 29-62 29-61 29-63 29-64 29-65 30-1 30-2 30-3 30-4 30-5 30-6 30-7 30-8 30-9 30-10 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 32-1 32-2 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 33-10 33-11 33-12 34-1 34-2 34-3 34-4 34-5 Title Page Number
Transmit Internal Rate Clocking 29-89 Transmit Internal Rate Registers (FTIRRx). 29-89 COMM_INFO Field 29-90 AAL1 SRTS Generation Using External Logic 29-91 AAL1 SRTS Clock Recovery Using External Logic 29-92 Ethernet Frame Structure 30-1 Ethernet Block Diagram 30-3 Connecting MPC8260 Ethernet. 30-5 Ethernet Address Recognition Flowchart 30-16 Ethernet Mode Registers (FPSMR) 30-20 Ethernet Event Register (FCCE)/Mask Register (FCCM) 30-22 Ethernet Interrupt Events Example. 30-23 Fast Ethernet Receive Buffer (RxBD) 30-24 Ethernet Receiving Using RxBDs 30-26 Fast Ethernet Transmit Buffer (TxBD). 30-27 HDLC Framing Structure 31-2 HDLC Address Recognition Example. 31-5 HDLC Mode Register (FPSMR) 31-8 HDLC Receiving Using RxBDs 31-10 HDLC Receive Buffer Descriptor (RxBD). 31-11 HDLC Transmit Buffer Descriptor (TxBD) 31-12 HDLC Event Register (FCCE)/Mask Register (FCCM) 31-14 HDLC Interrupt Event Example 31-16 Status Register (FCCS) 31-16 In-Line Synchronization Pattern. 32-3 Sending Transparent Frames between MPC8260s 32-4 Block Diagram 33-1 Single-Master/Multi-Slave Configuration 33-3 Multimaster Configuration 33-5 Mode Register. 33-6 Transfer Format with SPMODE[CP] 33-7 Transfer Format with SPMODE[CP] 33-7 Event/Mask Registers. 33-9 Command Register 33-10 Code Registers 33-12 Memory Structure 33-13 RxBD 33-14 TxBD. 33-15 Controller Block Diagram. 34-1 Master/Slave General Configuration 34-2 Transfer Timing 34-3 Master Write Timing. 34-4 Master Read Timing 34-5
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Figure Number 34-6 34-7 34-8 34-9 34-10 34-11 34-12 34-13 34-14 35-1 35-2 35-3 35-4 35-5 35-6 35-7 Page Number Mode Register (I2MOD). 34-6 Address Register (I2ADD) 34-7 Baud Rate Generator Register (I2BRG) 34-7 Event/Mask Registers (I2CER/I2CMR) 34-8 Command Register (I2COM) 34-9 Function Code Registers (RFCR/TFCR) 34-11 Memory Structure 34-12 RxBD 34-13 TxBD. 34-14 Port Open-Drain Registers 35-2 Port Data Registers 35-3 Port Data Direction Register (PDIR) 35-3 Port Assignment Register 35-4 Special Options Registers 35-5 Port Functional Operation. 35-6 Primary Secondary Option Programming. 35-8 Title
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Table Number Title Page Number
4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20
Acronyms Abbreviated Terms Terminology Conventions lxiv Instruction Field Conventions Acronyms Abbreviated Terms I-lxviii MPC8260 Serial Protocols MPC8260 Serial Performance 1-10 HID0 Field Descriptions. 2-12 HID1 Field Descriptions. 2-15 HID2 Field Descriptions. 2-15 Exception Classifications Processor Core. 2-24 Exceptions Conditions 2-24 Integer Divide Latency 2-30 Major Differences between Core MPC603e Manual. 2-30 Internal Memory Map. Acronyms Abbreviated Terms II-ii System Configuration Protection Functions Interrupt Source Priority Levels Encoding Interrupt Vector 4-14 SICR Field Descriptions 4-18 SIPRR Field Descriptions. 4-19 SCPRR_H Field Descriptions. 4-20 SCPRR_L Field Descriptions 4-20 SIEXR Field Descriptions 4-25 Field Descriptions. 4-26 PPC_ACR Field Descriptions. 4-28 LCL_ACR Field Descriptions 4-30 SIUMCR Register Field Descriptions 4-32 IMMR Field Descriptions. 4-34 SYPCR Field Descriptions 4-35 TESCR1 Field Descriptions 4-36 TESCR2 Field Descriptions 4-38 L_TESCR1 Field Descriptions 4-39 L_TESCR2 Field Descriptions 4-40 TMCNTSC Field Descriptions 4-40 TMCNTAL Field Descriptions. 4-42
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Table Number 4-21 4-22 4-23 4-24 8-10 8-11 8-12 8-13 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 Title Page Number PISCR Field Descriptions. 4-43 PITC Field Descriptions 4-44 PITR Field Descriptions 4-44 Pins Multiplexing Control. 4-45 Reset Causes Reset Actions Each Reset Source Field Descriptions Field Descriptions RSTCONF Connections Multiple-MPC8260 Systems Configuration EPROM Addresses. Hard Reset Configuration Word Field Descriptions Acronyms Abbreviated Terms .III-iii External Signals Signal Assignments. 7-15 Terminology Transfer Type Encoding 8-10 Transfer Code Encoding 8-13 Transfer Size Signal Encoding 8-13 Burst Ordering 8-14 Aligned Data Transfers. 8-15 Unaligned Data Transfer Example (4-Byte Example). 8-16 Data Requirements Read Cycle 8-18 Data Contents Write Cycles. 8-19 Address Size State Calculations. 8-20 Data Contents Extended Write Cycles. 8-21 Data Requirements Extended Read Cycles 8-21 Address Size State Extended Transfers. 8-22 Clock Default Modes Clock Configuration Modes Dedicated Pins SCCR Field Descriptions. SCMR Field Descriptions. Number PSDVAL Assertions Needed Assertion 10-12 Memory Controller Registers 10-13 Field Descriptions. 10-14 Field Descriptions (SDRAM Mode) 10-16 Mode Field Descriptions. 10-18 Option Register Mode. 10-20 PSDMR Field Descriptions 10-21 LSDMR Field Descriptions 10-24 Machine Mode Registers (MxMR). 10-27 Field Descriptions. 10-29 Field Description 10-30
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Table Number 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13-6 13-7 Title Page Number Bus-Assigned Refresh Timer (PURT) 10-30 Local Bus-Assigned Refresh Timer (LURT). 10-31 Bus-Assigned SDRAM Refresh Timer (PSRT) 10-31 LSRT Field Descriptions 10-32 MPTPR Field Descriptions. 10-32 SDRAM Interface Signals 10-33 SDRAM Interface Commands. 10-35 SDRAM Address Multiplexing 10-37 SDRAM Address Multiplexing 10-38 Address Partition 10-48 SDRAM Device Address Port during activate Command 10-49 SDRAM Device Address Port during read/write Command. 10-49 Register Settings (Page-Based Interleaving. 10-49 Address Partition 10-50 SDRAM Device Address Port during activate Command 10-50 SDRAM Device Address Port during read/write Command. 10-50 Register Settings (Bank-Based Interleaving). 10-51 GPCM Interfaces Signals 10-51 GPCM Strobe Signal Behavior. 10-52 TRLX EHTR Combinations 10-58 Boot Bank Field Values after Reset. 10-62 Interfaces Signals 10-62 Routines Start Addresses 10-65 Word Settings 10-71 MxMR Loop Field Usage. 10-76 Address Multiplexing. 10-77 Address Partition 10-80 DRAM Device Address Port during activate command. 10-80 Register Settings 10-80 UPMs Attributes Example. 10-82 UPMs Attributes Example. 10-90 Connection Field Value Example. 10-92 Signals 12-2 Boundary Scan Definition 12-6 Instruction Decoding 12-29 Acronyms Abbreviated Terms IV-v Possible MPC8260 Applications 13-3 Peripheral Prioritization. 13-6 RISC Controller Configuration Register Field Descriptions. 13-8 RTSCR Field Descriptions 13-10 RISC Microcode Revision Number. 13-10 Command Register Field Descriptions 13-11 Command Opcodes. 13-13
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Table Number 13-8 13-9 13-10 13-11 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 16-1 16-2 16-3 17-1 17-2 17-3 17-4 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 Title Page Number Command Descriptions 13-14 Buffer Descriptor Format 13-17 Parameter 13-18 RISC Timer Table Parameter 13-20 Entry (MCC 14-11 Entry (MCC 14-13 Entry Descriptions. 14-14 SIxGMR Field Descriptions 14-17 SIxMR Field Descriptions 14-18 SIxRSR Field Descriptions. 14-24 SIxCMDR Field Description 14-25 SIxSTR Field Descriptions 14-25 Signal Descriptions 14-27 Entries Interface 14-30 Signals. 14-31 Entries Interface (SCIT Mode) 14-34 Clock Source Options 15-6 CMXUAR Field Descriptions 15-7 CMXSI1CR Field Descriptions. 15-11 CMXSI2CR Field Descriptions. 15-12 CMXFCR Field Descriptions 15-13 CMXSCR Field Descriptions 15-15 CMXSMR Field Descriptions 15-18 BRGCx Field Descriptions 16-3 External Clock Source Options 16-4 Typical Baud Rates Asynchronous Communication 16-5 TGCR1 Field Descriptions 17-4 TGCR2 Field Descriptions 17-5 Field Descriptions 17-6 Field Descriptions 17-9 SDSR Field Descriptions. 18-3 PDTEM LDTEM Field Descriptions. 18-4 IDMA Transfer Parameters 18-7 IDMAx Parameter 18-16 Field Descriptions. 18-18 IDMA Channel Data Transfer Operation 18-20 Valid Memory-to-Memory STS/DTS Values 18-21 Valid STS/DTS Values Peripherals 18-21 IDSR/IDMR Field Descriptions 18-23 IDMA Field Descriptions. 18-24 IDMA Exceptions. 18-27 Parallel Register 18-28 Parallel Register 18-28
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Table Number 18-14 18-15 18-16 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 22-1 22-2 22-3 22-4 22-5 22-6 22-7 Title Page Number Parallel Register 18-29 Example: Peripheral-to-Memory 18-29 Example: Memory-to-Peripheral Fly-By Mode 18-30 GSMR_H Field Descriptions. 19-4 GSMR_L Field Descriptions 19-6 TODR Field Descriptions 19-10 Parameter Protocols 19-13 Parameter Base Addresses 19-15 RFCRx /TFCRx Field Descriptions. 19-16 SCCx Event, Mask, Status Registers 19-16 Preamble Requirements 19-24 DPLL Codings 19-25 UART-Specific Parameter Memory 20-4 Transmit Commands. 20-6 Receive Commands 20-7 Control Character Table, RCCM, RCCR Descriptions 20-9 TOSEQ Field Descriptions 20-10 Fields Descriptions. 20-12 Transmission Errors. 20-12 Reception Errors 20-13 PSMR UART Field Descriptions 20-14 UART RxBD Status Control Field Descriptions 20-17 UART TxBD Status Control Field Descriptions. 20-18 SCCE/SCCM Field Descriptions UART Mode. 20-21 UART SCCS Field Descriptions 20-22 UART Control Characters S-Records Example. 20-24 HDLC-Specific Parameter Memory 21-4 Transmit Commands. 21-5 Receive Commands 21-6 Transmit Errors 21-6 Receive Errors 21-6 PSMR HDLC Field Descriptions 21-7 HDLC RxBD Status Control Field Descriptions 21-9 HDLC TxBD Status Control Field Descriptions. 21-11 SCCE/SCCM Field Descriptions. 21-12 HDLC SCCS Field Descriptions 21-14 BISYNC Parameter Memory Map. 22-4 Transmit Commands. 22-5 Receive Commands 22-5 Control Character Table RCCM Field Descriptions. 22-7 BSYNC Field Descriptions. 22-8 BDLE Field Descriptions 22-9 Receiver SYNC Pattern Lengths 22-9
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Table Number 22-8 22-9 22-10 22-11 22-12 22-13 22-14 22-15 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 26-15 26-16 Title Page Number Transmit Errors 22-10 Receive Errors 22-10 PSMR Field Descriptions 22-11 BISYNC RxBD Status Control Field Descriptions. 22-12 BISYNC TxBD Status Control Field Descriptions. 22-14 SCCE/SCCM Field Descriptions. 22-16 SCCS Field Descriptions 22-17 Control Characters 22-18 Receiver SYNC Pattern Lengths 23-3 Transparent Parameter Memory 23-7 Transmit Commands. 23-7 Receive Commands 23-8 Transmit Errors 23-8 Receive Errors 23-8 Transparent RxBD Status Control Field Descriptions 23-9 Transparent TxBD Status Control Field Descriptions 23-11 SCCE/SCCM Field Descriptions. 23-12 SCCS Field Descriptions 23-13 Ethernet Parameter Memory Map. 24-8 Transmit Commands. 24-10 Receive Commands 24-11 Transmission Errors. 24-14 Reception Errors 24-15 PSMR Field Descriptions 24-16 Ethernet Receive RxBD Status Control Field Descriptions 24-17 Ethernet Transmit TxBD Status Control Field Descriptions. 24-20 SCCE/SCCM Field Descriptions. 24-21 SMCMR1/SMCMR2 Field Descriptions 26-4 UART Transparent Parameter Memory Map. 26-6 RFCR/TFCR Field Descriptions. 26-8 Transmit Commands. 26-12 Receive Commands 26-13 UART Errors 26-13 UART RxBD Field Descriptions 26-14 UART TxBD Field Descriptions. 26-17 SMCE/SMCM Field Descriptions. 26-18 Transparent Transmit Commands 26-25 Transparent Receive Commands. 26-25 Transparent Error Conditions. 26-25 Transparent RxBD Field Descriptions 26-26 Transparent TxBD. 26-27 Transparent TxBD Field Descriptions 26-27 SMCE/SMCM Field Descriptions. 26-28
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Table Number 26-17 26-18 26-19 26-20 26-21 26-22 26-23 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 28-1 28-2 28-3 28-4 28-5 28-6 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 Title Page Number Parameter Memory Map. 26-30 Commands. 26-32 Monitor Channel RxBD Field Descriptions. 26-32 Monitor Channel TxBD Field Descriptions 26-33 Channel RxBD Field Descriptions. 26-33 Channel TxBD Field Descriptions 26-34 SMCE/SMCM Field Descriptions. 26-34 Global Multiple-Channel Parameters 27-3 Channel Extra Parameters. 27-5 Channel-Specific Parameters HDLC 27-8 TSTATE High-Byte Field Descriptions 27-9 CHAMR Field Descriptions 27-10 RSTATE High-Byte Field Descriptions. 27-12 Channel-Specific Parameters Transparent Operation 27-12 CHAMR Field Mode. 27-14 MCCF Field Descriptions. 27-15 Group Channel Assignments 27-16 Transmit Commands. 27-16 Receive Commands 27-17 MCCE/MCCM Register Field Descriptions. 27-19 Interrupt Circular Table Entry Field Descriptions. 27-20 RxBD Field Descriptions. 27-21 TxBD Field Descriptions. 27-23 GFMR Register Field Descriptions 28-4 Data Synchronization Register (FDSR) 28-7 Transmit-on-Demand Register (TODR) 28-8 TODR Field Descriptions 28-8 Parameter Common Protocols 28-11 FCRx Field Descriptions 28-13 AService Types. 29-9 External Input Output Field Descriptions 29-15 Field Descriptions Address Compression 29-16 VCOFFSET Calculation Examples Contiguous VCLTs 29-17 VP-Level Table Entry Address Calculation Example 29-17 VC-Level Table Entry Address Calculation Example. 29-18 Fields their Positions Cells 29-26 Pre-Assigned Header Values 29-27 Pre-Assigned Header Values 29-28 Performance Monitoring Cell Fields 29-30 AParameter Map. 29-38 UEAD_OFFSETs Extended Addresses Extra Header 29-40 Filtering Enable Field Descriptions 29-40 GMODE Field Descriptions 29-41
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TABLES
Table Number 29-15 29-16 29-17 29-18 29-19 29-20 29-21 29-22 29-23 29-24 29-25 29-26 29-27 29-28 29-29 29-30 29-31 29-32 29-33 29-34 29-35 29-36 29-37 29-38 29-39 29-40 29-41 29-42 29-43 29-44 29-45 29-46 29-47 29-48 29-49 29-50 30-1 30-2 30-3 30-4 30-5 30-6 30-7 Title Page Number Receive Transmit Connection Table Sizes 29-42 Field Descriptions 29-45 Settings (AAL5 Protocol-Specific). 29-47 Protocol-Specific Field Descriptions 29-48 AAL1 Protocol-Specific Field Descriptions 29-49 AAL0-Specific Field Descriptions 29-50 Field Descriptions 29-52 AAL5-Specific Field Descriptions. 29-54 AAL1-Specific Field Descriptions. 29-55 AAL0-Specific Field Descriptions. 29-56 VBR-Specific TCTE Field Descriptions 29-56 UBR+ Protocol-Specific TCTE Field Descriptions 29-57 ABR-Specific TCTE Field Descriptions 29-58 Monitoring Table Field Descriptions. 29-61 Parameter Table 29-62 Priority Table Entry 29-63 Control Slot Field Description. 29-64 Free Buffer Pool Entry Field Descriptions 29-68 Free Buffer Pool Parameter Table 29-68 Receive Transmit Buffers 29-69 AAL5 RxBD Field Descriptions 29-70 AAL1 RxBD Field Descriptions 29-72 AAL0 RxBD Field Descriptions 29-73 AAL5 TxBD Field Descriptions. 29-75 AAL1 TxBD Field Descriptions. 29-76 AAL0 TxBD Field Descriptions. 29-77 Statistics Table. 29-79 Interrupt Queue Entry Field Description 29-81 Interrupt Queue Parameter Table. 29-81 UTOPIA Master Mode Signal Descriptions. 29-82 UTOPIA Slave Mode Signals. 29-84 UTOPIA Loop-Back Modes. 29-85 AMode Register (FPSMR). 29-86 FCCE/FCCM Field Descriptions. 29-88 FTIRRx Field Descriptions. 29-89 COMM_INFO Field Descriptions. 29-90 Flow Control Frame Structure 30-8 Ethernet-Specific Parameter 30-9 Transmit Commands. 30-12 Receive Commands 30-13 RMON Statistics Counters. 30-14 Transmission Errors. 30-19 Reception Errors 30-19
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Table Number 30-8 30-9 30-10 30-11 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 31-10 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 34-1 34-2 34-3 34-4 34-5 34-6 34-7 34-8 34-9 34-10 35-1 35-2 35-3 35-4 35-5 35-6 35-7 35-8 Title Page Number FPSMR Ethernet Field Descriptions 30-20 FCCE/FCCM Field Descriptions. 30-22 RxBD Field Descriptions. 30-24 Ethernet TxBD Field Definitions. 30-27 HDLC-Specific Parameter Memory 31-4 Transmit Commands. 31-5 Receive Commands 31-6 HDLC Transmission Errors 31-6 HDLC Reception Errors 31-7 FPSMR Field Descriptions 31-8 RxBD field Descriptions. 31-11 HDLC TxBD Field Descriptions 31-13 FCCE/FCCM Field Descriptions. 31-15 FCCS Register Field Descriptions. 31-17 SPMODE Field Descriptions. 33-6 Example Conventions. 33-8 SPIE/SPIM Field Descriptions 33-9 SPCOM Field Descriptions 33-10 Parameter Memory 33-10 RFCR/TFCR Field Descriptions. 33-12 Commands 33-12 RxBD Status Control Field Descriptions 33-14 TxBD Status Control Field Descriptions 33-15 I2MOD Field Descriptions 34-6 I2ADD Field Descriptions. 34-7 I2BRG Field Descriptions 34-8 I2CER/I2CMR Field Descriptions 34-8 I2COM Field Descriptions 34-9 Parameter Memory 34-9 RFCR/TFCR Field Descriptions. 34-11 Transmit/Receive Commands. 34-11 RxBD Status Control Bits. 34-13 TxBD Status Control Bits 34-14 PODRx Field Descriptions 35-2 PDIR Field Descriptions. 35-3 PPAR Field Descriptions. 35-4 PSORx Field Descriptions. 35-5 Port Assignment (PPARA 35-8 Port Dedicated Assignment (PPARB 35-12 Port Dedicated Assignment (PPARC 35-14 Port Dedicated Assignment (PPARD 35-17 User-Level PowerPC Registers (Non-SPRs). User-Level PowerPC SPRs.
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TABLES
Table Number Title Page Number Supervisor-Level PowerPC Registers (Non-SPR). Supervisor-Level PowerPC SPRs. MPC8260-Specific Supervisor-Level SPRs
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About This Book
primary objective this manual help communications system designers build systems using Motorola MPC8260 help software designers provide operating systems user-level applications take fullest advantage MPC8260. Although this book describes aspects regarding architecture that critical understanding MPC8260 core, does contain complete description architecture. Where additional information might help reader, references made PowerPC Microprocessor Family: Programming Environments. Ordering information this book provided section, information this book subject change without notice, described disclaimers title page this book. with technical documentation, responsibility sure they using most recent version documentation. more information, contact your sales representative.
Before Using this Note
Before using this manual, determine whether latest revision there errata addenda. locate published errata updates this document, refer worldwide
Audience
This manual intended software hardware developers application programmers want develop products MPC8260. assumed that reader basic understanding computer networking, layers, RISC architecture. addition, assumed that reader basic understanding communications protocols described here. Where considered useful, additional sources provided that provide in-depth discussions such topics.
MOTOROLA
About This Book
Organization
Following summary brief description chapters this manual: Part provides high-level description MPC8260, describing general operation listing basic features. Chapter provides high-level description MPC8260 functions features. roughly follows structure this book, summarizing relevant features providing references reader needs additional information. Chapter Processor provides overview MPC8260 core, summarizing topics described further detail subsequent chapters. Chapter presents table showing where MPC8260 registers mapped memory. includes cross references that indicate where registers described detail. Part describes start-up behavior MPC8260 Chapter Interface Unit describes system protection functions which provide various monitors timers, Chapter describes behavior MPC8260 reset start-up. Part III, Hardware describes external signals, clocking, memory control, power management MPC8260. Chapter shows functional pinout MPC8260 describes MPC8260 signals. Chapter describes signals bus. Chapter describes operation used PowerPC processors. Chapter Power describes clocking architecture MPC8260. Chapter describes memory controller, which controlling maximum eight memory banks shared between generalpurpose chip-select machine (GPCM) three user-programmable machines (UPMs). Chapter (L2) Cache provides information about implementation level-2 cache. Chapter 1149.1 Test Access describes dedicated useraccessible test access port (TAP), which fully compatible with IEEE 1149.1 Standard Test Access Port Boundary Scan Architecture. Part Processor describes clocking, operation various communications protocols supported MPC8260.
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Chapter Processor Module provides brief overview MPC8260 CPM. Chapter Interface with Time-Slot describes SIU, which controls system start-up, initialization operation, protection, well external system bus. Chapter describes multiplexing logic (CMX) which connects physical MII, modem lines, Chapter Generators describes eight independent, identical baud-rate generators (BRGs) that used with FCCs, SCCs, SMCs. Chapter describes MPC8260 timer implementation, which four identical 16-bit 32-bit general-purpose timers. Chapter Channels IDMA describes physical serial (SDMA) channels MPC8260. Chapter Communications Controllers describes four serial communications controllers (SCC), which independently implement different protocols bridging functions, routers, gateways, interface with wide variety standard WANs, LANs, proprietary networks. Chapter UART describes MPC8260 implementation universal asynchronous receiver transmitter (UART) protocol that used sending low-speed data between devices. Chapter HDLC describes MPC8260 implementation HDLC protocol. Chapter BISYNC describes MPC8260 implementation byte-oriented BISYNC protocol developed networking products. Chapter Transparent describes MPC8260 implementation transparent mode (also called totally transparent mode), which provides clear channel which send receive serial data without bit-level manipulation. Chapter Ethernet describes MPC8260 implementation Ethernet protocol. Chapter AppleTalk describes MPC8260 implementation AppleTalk. Chapter Management Controllers describes serial management controllers, full-duplex ports that independently support three transparent, general-circuit interface (GCI).
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About This Book
lvii
Chapter Controllers describes multi-channel controller (MCC), which handles serial, full-duplex data channels. Chapter Communications Controllers describes fast communications controllers (FCCs), which SCCs optimized synchronous high-rate protocols. Chapter describes MPC8260 Acontroller, which provides Aand layers Aprotocol. Acontroller performs segmentation reassembly (SAR) functions AAL5, AAL1, AAL0, most common parts convergence sublayer (CP-CS) these protocols. Chapter Ethernet describes implementation Ethernet IEEE 802.3 protocol. Chapter HDLC describes implementation HDLC protocol. Chapter Transparent describes implementation transparent protocol. Chapter Peripheral Interface describes serial peripheral interface, which allows MPC8260 exchange data between other MPC8260 chips, MC68360, MC68302, M68HC11, M68HC05 microcontroller families, peripheral devices such EEPROMs, real-time clocks, converters, ISDN devices. Chapter describes MPC8260 implementation inter-integrated circuit controller, which allows data exchanged with other devices, such microcontrollers, EEPROMs, real-time clock devices, converters. Chapter describes four general-purpose ports Each signal ports general-purpose signal signal dedicated supporting communications devices, such SMCs, SCCs. MCCs, FCCs. Appendix Quick Reference provides quick reference registers incorporated PowerPC core. This book also includes index glossary.
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Suggested Reading
This section lists additional reading that provides background information this manual well general information about PowerPC architecture.
MPC8xx Documentation
Supporting documentation MPC8260 accessed through world-wide http://www.mot.com/netcomm. This documentation includes technical reference materials, detailed applications notes.
PowerPC Documentation
PowerPC documentation organized following types documents: books provide details about individual PowerPC implementations intended used conjunction with Programming Environments Manual. These include following: PowerPC EC603e RISC Microprocessor Manual (Motorola order MPC603EUM/AD, Rev. PowerPC RISC Microprocessor Manual (Motorola order MPC604UM/AD) Programming environments books provide information about resources PowerPC architecture that common PowerPC processors. There versions, that describes functionality combined 64-bit architecture models that describes only 32-bit model. PowerPC Microprocessor Family: Programming Environments, (Motorola order MPCFPE/AD) PowerPC Microprocessor Family: Programming Environments 32-Bit Microprocessors, Rev. (Motorola order MPCFPE32B/AD) PowerPC Microprocessor Family: Interface 32-Bit Microprocessors (Motorola order MPCBUSIF/AD) provides detailed functional description interface, implemented PowerPC MPC603e, MPC604, MPC750 family PowerPC microprocessors. This document intended help system chip developers providing centralized reference source identify interface presented family PowerPC microprocessors. PowerPC Microprocessor Family: Reference Guide (Motorola order MPCPRG/D) concise reference that includes register summary, memory control model, exception vectors, PowerPC instruction set. PowerPC Microprocessor Family: Pocket Reference Guide (Motorola order MPCPRGREF/D). This feedlot card provides overview PowerPC registers, instructions, exceptions 32-bit implementations.
MOTOROLA
About This Book
Application short documents contain useful information about design issues useful programmers engineers working with PowerPC processors. current list PowerPC documentation, refer world-wide http://www.mot.com/PowerPC.
Conventions
This document uses following notational conventions:
Bold
mnemonics italics REG[FIELD]
Bold entries tables showing registers parameter should initialized user. Instruction mnemonics shown lowercase bold. Italics indicate variable command parameters, example, bcctrx. Book titles text italics. denote hexadecimal number denote binary number Instruction syntax used identify source Instruction syntax used identify destination Abbreviations acronyms registers buffer descriptors shown uppercase text. bits, numerical ranges appear brackets. example, MSR[LE] refers little-endian mode enable machine state register. certain contexts, such signal encoding indicates care. Used express numerical value logical operator logical operator logical operator
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Acronyms Abbreviations
Table contains acronyms abbreviations used this document. Note that meanings some acronyms (such SDR1 DSISR) historical, words which acronym stands intuitively obvious.
Table Acronyms Abbreviated Terms
Term BIST BUID CEPT DABR DPLL DRAM DSISR DTLB EEST EPROM FPSCR Analog-to-digital Arithmetic logic unit Asynchronous transfer mode Buffer descriptor Built-in self test Branch processing unit Basic rate interface. unit Content-addressable memory Conference administrations Europeanes Postes Telecommunications (European Conference Postal Telecommunications Administrations). multiplexing logic Communication processor module Condition register Cyclic redundancy check Count register Data address breakpoint register Data address register Decrementer register Direct memory access Digital phase-locked loop Dynamic random access memory Register used determining source exception Data translation lookaside buffer Effective address Enhanced Ethernet serial transceiver Erasable programmable read-only memory Floating-point register Floating-point status control register Meaning
MOTOROLA
About This Book
Table Acronyms Abbreviated Terms (Continued)
Term GPCM HDLC IEEE IrDA ISDN ITLB JTAG LIFO MESI NMSI No-op Floating-point unit General circuit interface General-purpose chip-select machine General-purpose register Graphical user interface High-level data link control Inter-integrated circuit Inter-chip digital link Institute Electrical Electronics Engineers Infrared Data Association Integrated services digital network Instruction translation lookaside buffer Integer unit Joint Test Action Group Link register Least recently used byte Load/store unit Multiply accumulate coherency protocol Memory management unit byte Machine state register number Next instruction address Nonmultiplexed serial interface operation Operating environment architecture Open systems interconnection Meaning
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Table Acronyms Abbreviated Terms (Continued)
Term PCMCIA RISC RTOS RWIRx SDLC SDMA SIMM SPRGn SRAM SRR0 SRR1 UART UIMM Peripheral component interconnect Personal Computer Memory Card International Association Processor register Primary rate interface Processor version register Reduced instruction computing Real-time operating system Read with intent modify Receive Serial communication controller Serial control port Synchronous Data Link Control Serial Serial interface Signed immediate value System interface unit Serial management controller Systems network architecture Serial peripheral interface Special-purpose register Registers available general purposes Static random access memory Machine status save/restore register Machine status save/restore register Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit Universal asynchronous receiver/transmitter Unsigned immediate value Meaning
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lxiii
Table Acronyms Abbreviated Terms (Continued)
Term UISA USART User instruction architecture User-programmable machine Universal synchronous/asynchronous receiver/transmitter Universal serial Virtual address Virtual environment architecture Register used primarily indicating conditions such carries integer operations Meaning
PowerPC Architecture Terminology Conventions
Table lists certain terms used this manual that differ from architecture terminology conventions.
Table Terminology Conventions
Architecture Data storage interrupt (DSI) Extended mnemonics Instruction storage interrupt (ISI) Interrupt Privileged mode privileged state) Problem mode problem state) Real address Relocation Storage (locations) Storage (the exception mnemonics exception Exception Supervisor-level privilege User-level privilege Physical address Translation Memory Access This Manual
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Table describes instruction notation conventions used this manual.
Table iii. Instruction Field Conventions
Architecture Equivalent crbA, crbB, crbD (respectively) crfD, crfS (respectively) (respectively) SIMM UIMM (shaded)
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About This Book
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Part Overview
Intended Audience
Part intended readers need high-level understanding MPC8260.
Contents
Part provides high-level description MPC8260, describing general operation listing basic features. Chapter provides high-level description MPC8260 functions features. roughly follows structure this book, summarizing relevant features providing references reader needs additional information. Chapter Processor provides overview MPC8260 core. Chapter presents table showing where MPC8260 registers mapped memory. includes cross references that indicate where registers described detail.
Conventions
Part uses following notational conventions: mnemonics italics Instruction mnemonics shown lowercase bold. Italics indicate variable command parameters, example, bcctrx. Book titles text italics. denote hexadecimal number denote binary number Instruction syntax used identify source Instruction syntax used identify destination
MOTOROLA
Part Overview
Part I-lxvii
Part Overview
REG[FIELD]
Abbreviations acronyms registers buffer descriptors shown uppercase text. bits, numerical ranges appear brackets. example, MSR[LE] refers little-endian mode enable machine state register. certain contexts, such signal encoding indicates care. Indicates numerical value
Acronyms Abbreviations
Table contains acronyms abbreviations that used this document.
Table Acronyms Abbreviated Terms
Term DABR DPLL DRAM DTLB GPCM HDLC IEEE Asynchronous Mode Buffer descriptor Branch processing unit Common on-chip processor Communications processor Communications processor module Cyclic redundancy check Count register Data address breakpoint register Data address register Decrementer register Direct memory access Digital phase-locked loop Dynamic random access memory Data translation lookaside buffer Effective address Fast communications controller Floating-point register General-purpose chip-select machine General-purpose register High-level data link control Inter-integrated circuit Institute Electrical Electronics Engineers Meaning
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Part Overview
Table Acronyms Abbreviated Terms (Continued)
Term ISDN ITLB JTAG NMSI RISC RTOS SDLC SDMA SRAM Integrated services digital network Instruction translation lookaside buffer Integer unit Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Multi-channel controller Media-independent interface Memory management unit Machine state register Nonmultiplexed serial interface Operating environment architecture Open systems interconnection Peripheral component interconnect Reduced instruction computing Real-time clock Real-time operating system Receive Serial communications controller Synchronous data link control Serial Serial interface System interface unit Serial management controller Serial peripheral interface Special-purpose register Static random access memory Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Meaning
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Part Overview
Part I-lxix
Part Overview
Table Acronyms Abbreviated Terms (Continued)
Term UART UISA Transmit Universal asynchronous receiver/transmitter User instruction architecture User-programmable machine Virtual environment architecture Meaning
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Chapter Overview
MPC8260 PowerQUICC versatile communications processor that integrates chip high-performance RISC microprocessor, very system integration unit, many communications peripheral controllers that used variety applications, particularly communications networking systems. core embedded variant PowerPC microprocessor with Kbytes instruction cache Kbytes data cache unit (FPU). system interface unit (SIU) consists memory controller that interfaces almost memory system, many other peripherals making this device complete system chip. communications processor module (CPM) includes peripherals found MPC860, with addition three high-performance communication channels that support emerging protocols (for example, 155-Mbps Aand Fast Ethernet). MPC8260 dedicated hardware that handle full-duplex, time-divisionmultiplexed logical channels This document describes functional operation MPC8260, with emphasis peripheral functions. Chapter Processor overview PowerPC microprocessor core; detailed information about core found MPC603e EC603e RISC Microprocessors Manual (order number: MPC603EUM/AD).
Features
following overview MPC8260 feature set: PowerPC dual-issue integer core core version MPC603e microprocessor System core microprocessor supporting frequencies Separate 16-Kbyte data instruction caches: Four-way associative Physically addressed replacement algorithm
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Chapter Overview
Part Overview
PowerPC architecture-compliant memory management unit (MMU) Common on-chip processor (COP) test interface Supports snooping cache coherency unit (FPU). Floating-point arithmetic supported. Support loads stores. Support cache locking. Low-power (less than when fully operational MHz, internal 3.3-V I/O) Separate power supply internal logic (3.3 Separate PLLs PowerPC core PowerPC core different frequencies power/performance optimization Internal PowerPC core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, ratios Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, ratios 64-bit data 32-bit address supports multiple master designs Supports single transfers burst transfers 64-, 32-, 16-, 8-bit port sizes controlled on-chip memory controller Supports data parity address parity 32-bit data 18-bit address local Single-master bus, supports external slaves Eight-beat burst transfers 32-, 16-, 8-bit port sizes controlled on-chip memory controller System interface unit (SIU) Clock synthesizer Reset controller Real-time clock (RTC) register Periodic interrupt timer Hardware monitor software watchdog timer IEEE 1149.1 JTAG test access port Twelve-bank memory controller Glueless interface SRAM, page mode SDRAM, DRAM, EPROM, Flash other peripherals
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Part Overview
Byte write enables selectable parity generation 32-bit address decodes with programmable bank size Three user programmable machines, general-purpose chip-select machine, page mode pipeline SDRAM machine Byte selects 64-bit width (60x) 32-bit width (local) Dedicated interface logic SDRAM Disable mode Communications processor module (CPM) Embedded 32-bit communications processor (CP) uses RISC architecture support communications peripherals Interfaces PowerPC core through on-chip 24-Kbyte dual-port controller Serial channels receive transmit serial channels Parallel registers with open-drain interrupt capability Virtual functionality executing memory memory memory transfers Three fast communication controllers (FCCs) supporting following protocols 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) Mbps, UTOPIA interface, AAL5, AAL1, AAL0 protocols, CBR, VBR, UBR, types, external connections Transparent rates (clear channel) multichannel controllers (MCCs) serial full-duplex data channels (for total Kbps channels). Each split into four subgroups channels each. Almost combination subgroups multiplexed single multiple interfaces Four serial communications controllers (SCCs) identical those MPC860, supporting digital portions following protocols: Ethernet/IEEE 802.3 CDMA/CS HDLC/SDLC HDLC Universal asynchronous receiver transmitter (UART) Synchronous UART Binary synchronous (BiSync) communications Transparent
MOTOROLA Chapter Overview
Part Overview
serial management controllers (SMCs), identical those MPC860 Provide management devices general-circuit interface (GCI) controllers time- division-multiplexed (TDM) channels Transparent UART (low-speed operation) serial peripheral interface identical MPC860 controller (identical MPC860 controller) Microwire compatible Multiple-master, single-master, slave modes eight interfaces Supports groups four channels total eight TDMs 2,048 bytes byte resolution Independent transmit receive routing, frame synchronization. Supports CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), serial interfaces Eight independent baud rate generators input clock pins supplying clocks FCC, SCC, serial channels Four independent 16-bit timers that interconnected 32-bit timers
Architecture Overview
MPC8260 external buses accommodate bandwidth requirements from high-speed system core very fast communications channels. shown Figure 1-1, MPC8260 three major functional blocks: 64-bit PowerPC core derived from MPC603e with MMUs cache system interface unit (SIU) communications processor module (CPM)
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Part Overview
16-Kbyte Instruction Cache IMMU MPC603e PowerPC Core
16-Kbyte Data Cache DMMU -to-Local Bridge Memory Controller Interface Unit Local
Timers Parallel Baud Rate Gen.
Interrupt Controller
24-Kbyte Dual Port
Serial DMAs Clock Counter Virtual IDMAs System Functions
32-Bit RISC Communications Processor (CP) Program
Time Slot Assigner Serial Interface TDMs UTOPIA MIIs Non-Multiplexed
Figure 1-1. MPC8260 Block Diagram
Both system core have internal PLL, which allows independent optimization frequencies which they run. system core both connected bus.
1.2.1 MPC603e Core
MPC603e core derived from PowerPC MPC603e microprocessor without unit with power management core highperformance low-power implementation PowerPC family reduced instruction computer (RISC) microprocessors. MPC603e core implements 32-bit portion PowerPC architecture, which provides 32-bit effective addresses, integer data types bits. MPC603e cache provides snooping ensure data coherency with other masters. This helps ensure coherency between system core. core includes Kbytes instruction cache Kbytes data cache. 64bit split-transaction external data bus, which connected directly external MPC8260 pins.
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Chapter Overview
Part Overview
MPC603e core internal common on-chip (COP) debug processor. This processor allows access internal scan chains debugging purposes. also used serial connection core emulator support. MPC603e core performance SPEC benchmark integer operations ranges between MHz. Dhrystone MIPS, MPC603e MIPS (compared MIPS MPC860 MHz). MPC603e core disabled. this mode, MPC8260 functions slave peripheral external core another MPC8260 device with core enabled.
1.2.2 System Interface Unit (SIU)
consists following: 60x-compatible parallel system 64-bit data width. MPC8260 supports 64-, 32-, 16-, 8-bit port sizes. MPC8260 internal arbiter arbitrates between internal components that access (system core, CPM, external master). This arbiter disabled, external arbiter used necessary. local (32-bit data, 32-bit internal 18-bit external address) bus. This used enhance operation very high-speed communication controllers. Without requiring extensive manipulation core, used store connection tables buffer descriptors (BDs) communication channels data that transmitted between channels. local synchronous runs same frequency. Memory controller supporting memory banks that allocated either system local bus. memory controller enhanced version MPC860 memory controller. supports three user-programmable machines. Besides MPC860 features, memory controller also supports SDRAM with page mode address data pipeline. Supports JTAG controller IEEE 1149.1 test access port (TAP). monitor that prevents lock-ups, real-time clock, periodic interrupt timer, other system functions useful embedded applications. Glueless interface cache (MPC2605) 4-/16-K-entry (MCM69C232/ MCM69C432).
1.2.3 Communications Processor Module (CPM)
contains features that allow MPC8260 excel variety applications targeted mainly networking telecommunication markets. superset MPC860 PowerQUICC CPM, with enhancements performance additional hardware microcode routines that support high rate protocols like A(up Mbps full-duplex) Fast Ethernet (100-Mbps fullduplex).
MPC8260 PowerQUICC Manual MOTOROLA
Part Overview
following list summarizes major features CPM: embedded 32-bit RISC controller residing separate (CPM local bus) from (used system core). With this separate bus, does affect performance PowerPC core. handles lower layer tasks control activities, leaving PowerPC core free handle higher layer activities. instruction optimized communications, also used general-purpose applications, relieving system core small often repeated tasks. serial (SDMA) that simultaneous transfers, optimized burst transfers local bus. Three full-duplex, serial fast communications controllers (FCCs) supporting A(155 Mbps) protocol through UTOPIA2 interface (there UTOPIA interfaces MPC8260), IEEE 802.3 Fast Ethernet protocols, HDLC rates Mbps) totally transparent operation. Each transmit fully transparent receive HDLC vice-versa. multichannel controllers (MCCs) that handle aggregate Kbps HDLC transparent channels, multiplexed eight interfaces. also supports super-channels rates higher than Kbps subchanneling 64-Kbps channels. Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/ Ethernet, high- level synchronous data link control, HDLC, local talk, UART, synchronous UART, BISYNC, transparent. full-duplex serial management controllers (SMC) supporting GCI, UART, transparent operations Serial peripheral interface (SPI) controllers Time-slot assigner (TSA) that supports multiplexing data from four SCCs, three FCCs, SMCs.
Software Compatibility Issues
much possible, MPC8260 features were made similar those previous devices (MPC860). code ports easily from previous devices MPC8260, except protocols supported MPC8260. Although many registers new, most registers retain status event bits, understanding programming models MC68360, MPC860, MPC85015 helpful. Note that MPC8260 initialization code requires changes from MPC860 initialization code (Motorola provides reference code).
1.3.1 Signals
Figure shows MPC8260 signals grouped function. Note that many these signals multiplexed this does indicate these signals multiplexed.
MOTOROLA
Chapter Overview
Part Overview
NOTE over signal name indicates that signal active example, (bus busy). Active-low signals referred asserted (active) when they negated when they high. Signals that active low, such (transfer size signals) referred asserted when they high negated when they low.
PAR/L_A14 SMI/FRAME/L_A15 TRDY/L_A16 CKSTOP_OUT/IRDY/L_A17 STOP/L_A18 DEVSEL/L_A19 IDSEL/L_A20 PERR/L_A21
REQ1/L_A24 GNT0/L_A25 GNT1/L_A26 CLK/L_A27 CORE_SRESET/RST/L_A28 INTA/L_A29 LOCK/L_A30 L_A31 LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS/LOE LGPL3/LSDCAS LPBS/LGPL4/LUPWAIT/LGTA LGPL5
SERR/L_A22 REQ0/L_A23
TBST GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR ABB/I
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