Introduction Development Board Features This data sheet describes

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Nios Embedded Processor Development Board
Introduction Development Board Features
This data sheet describes features functionality NiosCPU development board that included ExcaliburDevelopment Kit, featuring Nios embedded processor.
APEX20K200E device MByte (512 16-bit) flash memory pre-configured with 32-bit Nios reference design software KBytes SRAM 16-bit chips) On-board logic configuring APEX device from flash memory 3.3-V expansion/prototype headers (access user I/Os) 5-V-tolerant expansion/prototype headers (access user I/Os) SODIMM) socket, compatible with standard SDRAM modules IEEE-1386 peripheral component interconnect (PCI) mezzanine connectors RS-232 serial port user-definable 8-bit dual in-line package (DIP) switch block Four user-definable push-button switches Dual 7-segment display user-definable LEDs Joint Test Action Group (JTAG) connector ByteBlasterMVand MasterBlasterprogrammers Oscillator zero-skew clock distribution circuitry Power-on reset circuitry Power-supply circuitry (Input: unregulated, center-negative)
Functional Overview
Nios development board provides hardware platform immediately start developing embedded systems based Altera APEXdevices. Nios development board pre-loaded with 32-bit Nios embedded processor system reference design. QuartusII project directory containing reference design example installed with Nios hardware development (HDK). reference design software pre-loaded flash memory, boot power-up. reference design software includes monitor that used download debug programs.
Altera Corporation
A-MNL-NIOS-01
Nios Embedded Processor Development Board
Nios Development Board Components
This section contains brief overview several important components Nios development board. more complete list components appears Table page complete schematics, physical layout database, GERBER files Nios development board installed documentation Nios HDK.
Altera Corporation
Nios Embedded Processor Development Board
Figure Nios Development Board
Table page complete list Nios development board components.
Altera Corporation
Nios Embedded Processor Development Board
APEX 20K200EFC484 Device
APEX 20K200E device 484-pin fineline ball-grid array (BGA) package. useful Nios system module (CPU peripherals) typically occupies between logic this device. Table .APEX20K200E Device Features
Maximum system gates Typical gates ESBs Maximum bits Maximum macrocells Maximum user pins 526,000 211,000 8,320 106,496
development board provides separate methods configuring APEX device: JTAG connection (JP3) that used with Quartus software ByteBlaster MasterBlaster programming cable. configuration controller (U4) that configures APEX device power-up from hexout files stored flash memory (U3). "Configuration Controller" page more information.
Flash Memory Chip
(U3) advanced micro-devices (AMD) AM29LV800BB 1Mbyte flash memory chip. connected APEX device that used purposes simultaneously: Nios processor implemented APEX device flash general-purpose readable, writable non-volatile memory. flash memory hold APEX device configuration file that used configuration controller load APEX device power-up. "Configuration Controller" page more information.
hexout configuration file that implements 32-bit Nios reference design pre-loaded this flash memory. 32-bit reference design, once loaded, identify flash address space, includes monitor software that download files (either APEX device configurations, Nios software, both) into flash memory. Nios includes subroutines writing erasing this specific type flash memory.
Altera Corporation
Nios Embedded Processor Development Board
Dual SRAM Chips
Kbyte (64K 16-bit) asynchronous SRAM chips. They connected APEX device that they used Nios processor general-purpose zero-wait-state memory. 16-bit devices used parallel implement 32-bit wide memory subsystem. pre-loaded Nios reference design identifies these SRAM chips address space contiguous Kbyte, 32-bit-wide, zero-wait-state main memory. 144-pin SODIMM socket that compatible with standard single-data-rate, 64-bit-wide SDRAM modules. connected APEX device that user logic access SDRAM. pre-loaded reference design does make this connector.
SODIMM Connector
Altera Corporation
Nios Embedded Processor Development Board
Figure SODIMM Connector
Altera Corporation
Nios Embedded Processor Development Board
Expansion Prototype Connector Header: 3.3-V
Headers JP8, JP9, JP10 collectively form standard-footprint, mechanically-stable connection that used (for example) interface special-function daughter card. Contact your Altera sales representative list expansion daughter cards that used with Nios board. 3.3-V expansion prototype connector interface includes:
APEX device general-purpose signals. buffered, zero-skew copy on-board output (from U5). buffered, zero-skew copy APEX's PLL-output (from U5). APEX device clock-input (for daughter cards that drive clock programmable logic device (PLD). logic-negative power-on-reset signal. regulated 3.3-V power-supply pins (500 total load). Unregulated power-supply (connects directly power-input plug). Numerous ground connections. pre-loaded Nios reference design does 3.3-V expansion prototype connector.
Figure 3.3-V Expansion Prototype Connector
Altera Corporation
Nios Embedded Processor Development Board
Figure 3.3-V Expansion Prototype Connector
Figure 3.3-V Expansion Prototype Connector
Expansion Prototype Connector Header: Vtolerant.
Headers JP11, JP12, JP13 collectively form standard-footprint, mechanically-stable connection that used (for example) interface special-function daughter card. pre-loaded Nios reference design uses JP12 interface two-line character display included with Nios kit. 5-V-tolerant expansion connector similar 3.3-V expansion connector, except indicated herein below:
JP11 (pin used global card-enable signal. connections pass through analog switches (U8, U11, U12) protect APEX device from logic levels. These analog switches globally enabled (switched-on) APEX device (logic-0 enables switches).
Altera Corporation
Nios Embedded Processor Development Board
low-current power supply load) presented JP12 (the corresponding 3.3-V expansion connector connected). RC-filtered connection APEX device This circuit suitable producing high-impedance, low-precision analog output driven with duty-cycle-modulated waveform user-logic. corresponding 3.3-V expansion connector connected. Vref-voltage analog switches (3.3-V plus diode-drop) presented JP13. corresponding 3.3-V expansion connector connected.
pre-loaded Nios reference design uses JP12 interface twoline character display included with Nios Development Kit, featuring Nios embedded processor. Figure Expansion Prototype Connector JP11
Altera Corporation
Nios Embedded Processor Development Board
Figure Expansion Prototype Connector JP12
Figure Expansion Prototype Connector JP13
Mezzanine Connectors (PMC)
PMCJN1 PMCJN2 IEEE1386-compliant connectors. User logic APEX device access daughter cards through these connectors. pre-loaded Nios reference design does mezzanine connector (PMC) connectors.
Altera Corporation
Nios Embedded Processor Development Board
Figure Mezzanine Connectors (PMC)
Altera Corporation
Nios Embedded Processor Development Board
Serial Port Connector
standard DB-9 serial connector. This connector typically used host communication with desktop workstation using standard 9-pin serial cable connected (for example) COM-port. transmit (TXD) receive (RXD) clear send (CTS), ready send (RTS) signals standard high-voltage RS-232 logic levels. level-shifting buffer that presents accepts 3.3-V versions these signals from APEX device. Figure Serial Port Connector
JTAG Connector
10-pin JTAG interface connector compatible with Altera ByteBlaster MasterBlaster programming cables. JTAG connection used three purposes: Quartus software configure APEX device (U1) with bitstream (e.g., .sof) file MasterBlaster ByteBlaster programming cable. Quartus MAX+PLUS software re-program EPM7064 device (U4) with .pof file MasterBlaster ByteBlaster programming cable. User-provided host software conduct JTAG serial communication with card plugged-in connectors (PMCJN1 andPMCJN2) card makes JTAG signals that part IEEE-1386 standard.
JTAG chain Nios development board include all, some, none following three devices, order: (SW8) APEX device (U1) (SW9) EPM7064 configuration controller (U4) (SW10) card plugged-in connectors PMCJN1 PMCJN2, present.
Altera Corporation
Nios Embedded Processor Development Board
Figure JTAG Chain
Refer development board schematic precise complete connections information.
each device indicated two-position connect/bypass switch determines whether device included JTAG chain (connect) excluded (bypass). Figure Two-Position Switches
JTAG connection most commonly used download user configuration (e.g., .sof) files APEX device chip during logic development debugging. this case, usually most convenient leave connect position, both SW10 bypass position. EPM7064 device (U4) comes factory-programmed configuration controller. Factory User Configurations page PLUS+ projects that include design, implementation, programming files configuration-controller logic included with Nios HDK. Most users will never need re-program configuration controller(U4).
Altera Corporation
Nios Embedded Processor Development Board
Re-programming result inoperable development board. Altera recommends that users leave SW10 bypass.
Configuration Controller
configuration controller (U4), Altera EPM7064 PLD. comes factory-programmed with logic that configures APEX device (U1) from data stored flash (U3) power-up. power-up when reset switch pressed), configuration controller begins reading data flash memory. flash memory, APEX device, configuration controller connected that data from flash configures APEX device passive-parallel mode.
Configuration Data
Quartus software (optionally) produce hexout configuration files, that directly suitable download storage flash memory configuration data. hexout configuration file APEX20K200E device (U1) little less than 256Kbytes, thus occupies about flash memory (U3). exult-files stored flash memory (U3) software running Nios processor. preloaded 32-bit Nios reference design includes GERMS monitor program, that supports downloading exult files from host (e.g., desktop workstation) into flash memory. Nios Embedded Processor Software Development User Guide detailed description GERMS monitor program.
Factory User Configurations
configuration controller manage separate APEX device configurations stored flash memory. These configurations (hexoutfiles) conventionally referred user configuration factory configuration. Upon reset when reset switch (SW2) pressed) configuration controller will attempt load APEX device with user configuration data. this process fails (either because userconfiguration invalid present) configuration controller will then load APEX device with factory configuration data. configuration controller expects user-configuration factoryconfiguration files stored fixed locations (offsets) flash memory. Table page shows configuration controller expects flash memory contents arranged
Altera Corporation
Nios Embedded Processor Development Board
Table 2.Flash Memory Allocation
0x100000 0x17FFFF 0x180000 0x1BFFFF 0x1C0000 0x1FFFFF Kbytes Kbytes Kbytes Nios instruction nonvolatile data space. User-defined APEX device configuration data. Factory-default APEX device configuration. "Configuration Controller" page
32-bit Nios reference design pre-loaded into factoryconfiguration region flash memory. Altera recommends that users avoid overwriting factory configuration data. jumper (JP2) changes behavior configuration controller. shorting block present JP2, configuration controller will ignore user-configuration always configure APEX device from factory configuration. shorting JP2, "escape" from situation where valid-but-nonfunctional user configuration present flash memory. pre-loaded Nios reference design, flash memory mapped base-address 0x100000. Thus, user hexout-files should downloaded address 0x180000 flash-base-address userconfiguration offset). Refer Software Reference Manual detailed information about downloading relocating files using GERMS monitor. connected APEX device that each segment individually controlled general-purpose pin. Figure Dual-Digit Display
Two-Digit 7-segment display (D1)
pre-loaded Nios reference design includes parallel input/output (PIO) registers logic driving this display.
Altera Corporation
Nios Embedded Processor Development Board
Switches, Buttons, LEDs
8-DIP-switch block with each switch connected APEX general-purpose pull-up resistor. APEX device will logic-1 when each switch open, logic-0 when each switch closed. Figure Eight Switch Block
SW4, SW5, SW6, momentary-contact push-button switches, each connected APEX device general-purpose pull-up resistor. APEX device will logic-0 when each switch pressed. Discrete LEDs LED1 LED2 each controlled APEX device general-purpose I/O. Each will light-up when APEX device drives logic-1 controlling output. Figure Switches LEDs
Nios development board uses dedicated switches following fixed functions:
Altera Corporation
Nios Embedded Processor Development Board
SW2: Reset
When pressed, logic-0 value driven power-on reset controller. Pressing equivalent power-on reset. When pressed when board power-cycled), configuration controller will load APEX device from flash memory. "Configuration Controller" page more information. When development board delivered from factory, APEX device will configured with 32-bit reference design power-up when pressed). reference design will then begin executing GERMS monitor, serial debug/download utility.
SW3: Clear
When pressed, logic-0 driven onto APEX devices' DEV_CLRn (and user F12). result pressing depends APEX device currently configured. pre-loaded Nios reference design treats CPU-reset pin: reference Nios will reset start executing code from boot-address when pressed.
Power-supply circuitry
Nios development board runs from 9-V, unregulated, centernegative input. On-board circuitry generates 5-V, 3.3-V, 1.8-V regulated power levels.
1.8-V supply used only APEX device core power source available connector header. 3.3-V supply used power source APEX device pins. 3.3-V supply also available daughter cards other devices plugged-in expansion connectors, including connectors SDRAM SODIMM socket. total load from externally-connected 3.3-V devices exceed supply presented Pin2 JP12 devices plugged-in 5-V-tolerant expansion connectors. total load exceed
Clock Circuitry
Nios development board includes 33.333MHz free-running oscillator zero-skew, point-to-point clock distribution network that drives both APEX device pins expansion connectors, connectors, SODIMM connector. zero-skew buffer distributes both free-running 33MHz clock clock-output from APEX's device internal PLLs (CLKLK_OUT1).
Altera Corporation
Nios Embedded Processor Development Board
Figure Clock Circuitry
Notes:
Table .Nios Development Board Components (Sheet
PMCJN1 PMCJN2 JP10 JP11 JP12 JP13 JP14 LED1 LED2 LED3 Dual-digit 7-segment Power supply connector SDRAM SODIMM socket Serial port connector connector connector Jumper header configuration controller JTAG header 40-pin header volt daughter card 14-pin header volt daughter card 20-pin header volt daughter card 40-pin header volt daughter card 14-pin header volt daughter card 20-pin header volt daughter card 6-pin header serial debug JTAG header User-defined User-defined Flash-byte Power indication 8-bit switch block Resets board-clears APEX device reloads from configuration controller Clears
Altera Corporation
Nios Embedded Processor Development Board
Table .Nios Development Board Components (Sheet
Notes:
SW10
User-defined push-button User-defined push-button User-defined push-button User-defined push-button APEX device JTAG chain switch Configuration controller JTAG chain switch JTAG chain switch Ground point providing ground plane reference Ground point providing ground plane reference Ground point providing ground plane reference Ground point providing ground plane reference APEX EP20K200E device Flash memory device APEX device configuration controller Clock distribution chip Monitor reset RS-232 level-shifter SRAM SRAM Programmable High-Frequency Oscillator
Altera Corporation
Nios Embedded Processor Development Board
Altera Corporation

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