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OMAP5910 Dual-Core Processor

Literature Number: SPRS197D August 2002 - Revised August 2004

OMAP5910 Dual-Core Processor
Data Manual
Literature Number: SPRS197D August 2002 - Revised August 2004
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS197C device-specific data sheet to make it an SPRS197D revision. Scope: This document has been reviewed for technical accuracy the technical content is up-to-date as of the specified release date and includes the following changes.
PAGE(S) NO. All
Selectable UART / autobauding modes (autobauding on UART1 and UART2) Auto bauding between 1200bits / s and 115.2K bits / s Selectable UART / autobauding modes (autobauding on UART1 and UART2) with autobauding between 1200 bits / s and 115.2K bits / s
To read as follows:
Revised Section 3.11 to removed bulleted list and replace with the following: "The EMIFF Interface provides access to 16-bit-wide access to standard SDRAM memories and the IMIF provides access to the 192K bytes of on-chip SRAM."
August 2002 - Revised August 2004
SPRS197D
Revision History
PAGE(S) NO.
ADDITIONS / CHANGES / DELETIONS In Section 3.13, removed the following bulleted items:
Quantization / Dequantization (useful for JPEG, MPEG, H.26x Encoding / Decoding) Flexible 1D / 2D Wavelet Processing (useful for JPEG2000, MPEG4, and other compression standards) Boundary and Perimeter Computation (useful for Machine Vision applications) Image Threshold and Histogram Computations (useful for various Image Analysis applications)
SPRS197D
August 2002 - Revised August 2004
Contents
August 2002 - Revised August 2004
SPRS197D
Contents
Page 63 63 64 64 65 66 66 67 67 67 68 68 68 68 68 68 68 70 71 72 79 88 95 95 101 106 108 113 117 118 119 120 121 121 122 123 124 124 125 125 126 127 128 128 129
SPRS197D
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Contents
Page 130 130 137 141 141 145 149 151 152 154 156 157 158 159 161 164
August 2002 - Revised August 2004
SPRS197D
Contents
SPRS197D
August 2002 - Revised August 2004
Figures
List of Figures
August 2002 - Revised August 2004
SPRS197D
Figures
SPRS197D
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Tables
List of Tables
August 2002 - Revised August 2004
SPRS197D
Tables
Page 91 91 92 92 93 93 93 94 94 94 96 99 99 99 99 99 100 101 102 104 105 106 106 106 107 107 109 110 111 112 112 113 115 116 117 118 124 125 126 127 127 128 128 129 129
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Tables
Page 130 131 137 137 141 143 145 145 146 146 147 147 148 148 149 149 151 152 154 154 156 157 158 158 159 159
August 2002 - Revised August 2004
SPRS197D
Tables
SPRS197D
August 2002 - Revised August 2004
Features
OMAP5910 Features
D Low-Power, High-Performance CMOS
Technology - 0.13-µm Technology - 1.6-V Core Voltage TI925T (MPU) ARM9TDMI Core - Support 32-Bit and 16-Bit (Thumb Mode) Instruction Sets - 16K-Byte Instruction Cache - 8K-Byte Data Cache - Data and Program Memory Management Units (MMUs) - Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs - 17-Word Write Buffer TMS320C55x (C55x) DSP Core - One / Two Instructions Executed per Cycle - Dual Multipliers (Two MultiplyAccumulates per Cycle) - Two Arithmetic / Logic Units - One Internal Program Bus - Five Internal Data / Operand Buses (3 Read Buses and 2 Write Buses) - 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes) - 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes) - 16K x 16-Bit On-Chip ROM (32K Bytes) - Instruction Cache (24K Bytes) - Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression 192K Bytes of Shared Internal SRAM Memory Traffic Controller (TC) - 16-Bit EMIFS External Memory Interface to Access up to 128M Bytes of Flash, ROM, or ASRAM - 16-Bit EMIFF External Memory Interface to Access up to 64M Bytes of SDRAM 9-Channel System DMA Controller DSP Memory Management Unit Endianism Conversion Logic Digital Phase-Locked Loop (DPLL) for MPU / DSP / TC Clocking Control
D DSP Peripherals
TMS320C55x and C55x are trademarks of Texas Instruments. ARM9TDMI is a trademark of ARM Limited. Thumb is a registered trademark of ARM Limited. MICROWIRE is a trademark of National Semiconductor Corporation. 1-Wire is a registered trademark of Dallas Semiconductor Corporation. IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture. August 2002 - Revised August 2004
Three 32-Bit Timers and Watchdog Timer Level1 / Level2 Interrupt Handlers Six-Channel DMA Controller Two Multichannel Buffered Serial Ports (McBSP) - Two Multichannel Serial Interfaces (MCSI) TI925T Peripherals - Three 32-Bit Timers and Watchdog Timer - 32-kHz Timer - Level1 / Level2 Interrupt Handlers - USB (Full / Low Speed) Host Interface With up to 3 Ports - USB (Full Speed) Function Interface - One Integrated USB Transceiver for Either Host or Function - Multichannel Buffered Serial Port - Inter-Integrated Circuit (I2C) Master and Slave Interface - MICROWIRE Serial Interface - Multimedia Card (MMC) and Secure Digital (SD) Interface - HDQ / 1-Wire Interface - Camera Interface for CMOS Sensors - ETM9 Trace Module for TI925T Debug - Keyboard Matrix Interface (6 x 5 or 8 x 8) - Up to Ten MPU General-Purpose I / Os - Pulse-Width Tone (PWT) Interface - Pulse-Width Light (PWL) Interface - Two LED Pulse Generators (LPGs) - Real-Time Clock (RTC) - LCD Controller With Dedicated System DMA Channel Shared Peripherals - Three Universal Asynchronous Receiver / Transmitters (UARTs) (One Supporting SIR Mode for IrDA) - Four Interprocessor Mailboxes - Up to 14 Shared General-Purpose I / Os Individual Power-Saving Modes for MPU / DSP / TC On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Two 289-Ball Ball Grid Array Package Options (GZG and GDY Suffixes)
SPRS197D
Introduction
This section describes the main features of the OMAP5910 device, lists the terminal assignments, and describes the function of each terminal. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
Description
The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T ARM core. The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP / BIOS software kernel foundation, and is available in a 289-ball MicroStar BGA package. The OMAP5910 is targeted at the following applications: · · Applications processing devices Mobile communications - - - - - · · · · · · 802.11 Bluetooth wireless technology GSM (including GPRS and EDGE) CDMA Proprietary government and other
Video and image processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced speech applications (text-to-speech, speech recognition) Audio processing (MPEG-1 Audio Layer3 MP3, AMR, WMA, AAC, and other GSM speech codecs) Graphics and video acceleration Generalized web access Data processing (fax, encryption / decryption, authentication, signature verification and watermarking)
2.1.1 TMS320C55x DSP Core
The DSP core of the OMAP5910 device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
OMAP, DSP / BIOS, and MicroStar BGA are trademarks of Texas Instruments. Bluetooth is a trademark owned by Bluetooth SIG, Inc. Windows is a registered trademark of Microsoft Corporation. Other trademarks are the property of their respective owners. 16 SPRS197D August 2002 - Revised August 2004
Introduction
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic / logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The OMAP5910 DSP core also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.
DSP Tools Support
DSP Software Support
Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR / IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image / Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.
2.1.2 TI-Enhanced TI925T RISC Processor
The MPU core is a TI925T reduced instruction set computer (RISC) processor. The TI925T is a 32-bit processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The MPU core incorporates: · · · · A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. A separate 16K-byte instruction cache and 8K-byte data cache. Both are two-way associative with virtual index virtual tag (VIVT). A 17-word write buffer (WB)
The OMAP5910 device uses the TI925T core in little endian mode only. To reduce effective memory access time, the TI925T has an instruction cache, a data cache, and a write buffer. In general, these are transparent to program execution.
eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments. August 2002 - Revised August 2004 SPRS197D 17
Introduction
Terminal Assignments
Figure 2-1 illustrates the ball locations for the 289-ball GZG ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. GZG BGA ball numbers in Table 2-1 are read from left-to-right, top-to-bottom.
Figure 2-1. OMAP5910 GZG MicroStar BGA Package (Bottom View) In Table 2-1, signals with multiplexed functions are separated with forward slashes as follows: · signal1 / signal2 / signal3 (for example, GPIO11 / HDQ)
Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name as follows: ·
GZG BGA BALL # A1 A7 A15 A21 B4 B8 B13 B17 B21 C4 C8 C12
peripheral1.signal1 (for example, MCBSP1.DR) Table 2-1. GZG BGA Terminal Assignments
SIGNAL DVDD4 DVDD4 DVDD1 VSS SDRAM.D13 SDRAM.D4 CVDD3 LCD.P11 LCD.P1 SDRAM.D14 SDRAM.D2 SDRAM.A7 GZG BGA BALL # A2 A9 A17 B1 B5 B9 B14 B18 C1 C5 C9 C13 SIGNAL SDRAM.RAS CVDD LCD.P13 VSS VSS SDRAM.D0 SDRAM.A0 VSS FLASH.A3 SDRAM.D11 SDRAM.CLK SDRAM.A4 GZG BGA BALL # A3 A11 A19 B2 B6 B10 B15 B19 C2 C6 C10 C14 SIGNAL CVDD1 VSS DVDD1 VSS SDRAM.D8 DVDD4 LCD.AC LCD.P6 DVDD5 SDRAM.D9 SDRAM.BA0 SDRAM.A1 GZG BGA BALL # A5 A13 A20 B3 B7 B12 B16 B20 C3 C7 C11 C15 SIGNAL DVDD4 VSS LCD.P5 SDRAM.DQML VSS DVDD4 VSS CVDD3 SDRAM.WE SDRAM.D6 SDRAM.A10 LCD.PCLK
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
MicroStar BGA is a trademark of Texas Instruments. 18 SPRS197D August 2002 - Revised August 2004
Introduction
Table 2-1. GZG BGA Terminal Assignments (Continued)
L19 M4 M15 N1 N7 N18 P2
L21 M7 M18 N2 N8 N19 P3
M2 M8 M19 N3 N14 N20 P4
M3 M14 M20 N4 N15 N21 P7
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-1. GZG BGA Terminal Assignments (Continued)
P18 R2 R9 R13 R20 T4 U1 U18 V2 V6 V10 V14 V18 W2 W6 W10 W14
P19 R3 R10 R14 R21 T18 U2 U19 V3 V7 V11 V15 V19 W3 W7 W11 W15
P20 R4 R11 R18 T2 T19 U3 U20 V4 V8 V12 V16 V20 W4 W8 W12 W16
R1 R8 R12 R19 T3 T20 U4 U21 V5 V9 V13 V17 W1 W5 W9 W13 W17
W18 Y1 Y5
W19 Y2 Y6
W20 Y3 Y7
W21 Y4 Y8
Y9 Y14
Y10 Y15
Y12 Y16
Y13 Y17
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-1. GZG BGA Terminal Assignments (Continued)
GZG BGA BALL # Y18 AA1 AA7 AA15 AA21
SIGNAL TRST VSS VSS UART1.RTS VSS
GZG BGA BALL # Y19 AA2 AA9 AA17
GZG BGA BALL # Y20 AA3 AA11 AA19
SIGNAL CVDD CVDD2 DVDD1 TDO
GZG BGA BALL # Y21 AA5 AA13 AA20
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
Figure 2-2 illustrates the ball locations for the 289-ball GDY ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. GDY BGA ball numbers in Figure 2-2 are read from left-to-right, top-to-bottom.
Bottom View
Figure 2-2. OMAP5910 GDY Package (Bottom View) In Table 2-2, signals with multiplexed functions are separated with forward slashes as follows: · signal1 / signal2 / signal3 (for example, GPIO11 / HDQ)
Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name as follows: · peripheral1.signal1 (for example, MCBSP1.DR)
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-2. GDY BGA Terminal Assignments
G15 H2 H6 H10 H14 J1 J5
MCBSP1.CLKX FLASH.A20 FLASH.A22 VSS CAM.D1 / ETM.D1 / UART3.RTS FLASH.BE1 FLASH.BE0
G16 H3 H7 H11 H15 J2 J6
G17 H4 H8 H12 H16 J3 J7
H1 H5 H9 H13 H17 J4 J8
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-2. GDY BGA Terminal Assignments (Continued)
L11 L15 M2 M6 M10 M14 N1 N5
VSS GPIO12 / MCBSP3.FSX FLASH.D5 VSS UART1.CTS MPUIO1 FLASH.D9 VSS
L12 L16 M3 M7 M11 M15 N2 N6
L13 L17 M4 M8 M12 M16 N3 N7
L14 M1 M5 M9 M13 M17 N4 N8
N13 N17 P4 P8 P12
N14 P1 P5 P9 P13
N15 P2 P6 P10 P14
N16 P3 P7 P11 P15
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-2. GDY BGA Terminal Assignments (Continued)
FLASH.D12 MCBSP2.DX / MCBSP2.DR MMC.DAT3 / MPUIO6 TMS EMU0 UART2.BCLK MCSI2.CLK / USB2.SUSP DVDD1 CONF DVDD2 MCLK MCSI1.CLK / USB1.VM TRST
R3 R7 R11 R15 T2 T6 T10 T14 U1 U5 U9 U13 U17
R4 R8 R12 R16 T3 T7 T11 T15 U2 U6 U10 U14
R5 R9 R13 R17 T4 T8 T12 T16 U3 U7 U11 U15
R6 R10 R14 T1 T5 T9 T13 T17 U4 U8 U12 U16
See Section 5.6.1 and Section 5.6.2 for special VSS considerations with ocillator circuits.
Terminal Characteristics and Multiplexing
Table 2-3 describes terminal characteristics and the signals multiplexed on each ball. The table column headers are explained below: · · · SIGNAL NAME: The names of all the signals that are multiplexed on each ball. TYPE: The terminal type when a particular signal is multiplexed on the terminal. MUX CTRL SETTING: The register field that controls multiplexing on the terminal and the proper register field setting necessary to select the signal to be multiplexed on the terminal. The reset values of these register fields are indicated in bold type. DESELECTED INPUT STATE: The logic level internally driven to the signal when it is not selected to be multiplexed on the corresponding terminal. PULLUP / PULLDN: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled via software. BUFFER STRENGTH: Drive strength of the associated output buffer.
SPRS197D
August 2002 - Revised August 2004
Introduction
GZG BALL C3 A2 D4 B3 D5 C4 B4 D6 C5 H8 C6 B6 D7 C7 D8 B8 G8 C8 G9 B9 D9 C9 H9 D10 C10
GDY BALL A1 C4 A2 B2 D4 C5 G8 B4 B5 C6 A3 E6 D6 A4 B6 F7 C7 B7 E7 A6 D7 A7 F8 C9 B8
SIGNAL NAME SDRAM.WE SDRAM.RAS SDRAM.DQMU SDRAM.DQML SDRAM.D15:0
MUX CTRL SETTING NA NA NA NA NA
DESELECTED INPUT STATE NA NA NA NA NA
BUFFER STRENGTH 4 mA 4 mA 4 mA 4 mA 4 mA
RESET STATE# 1 1 1 1 0
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
SDRAM.CKE SDRAM.CLK SDRAM.CAS SDRAM.BA1:0
DVDD4 DVDD4 DVDD4 DVDD4
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
GZG BALL G10 H10 C11 D11 G11 C12 D12 H11 C13 D13 G12 C14 B14 D14 H12 B15 C15 D15 C16 A17 G13 B17 C17 D16 D17 C18 B19 A20 H13 G14 C19 B21 D18 C20 C21 E18 D19 D20 F18 E19 E20 H14 F19 G18 G19 G20 G21 H15 5
GDY BALL C8 B9 E9 A8 C10 F9 D9 A9 D10 C11 B10 A10 B11 D11 E11 A11 A12 D12 C13 B12 F11 B13 E12 A13 C14 B14 A15 C15 B15 A16 D15 C16 B16 A17 D16 B17 E15 E16 C17 D17 E17 F15 D14 D13 F14 F13 G15 F17
SIGNAL NAME SDRAM.A12:0
MUX CTRL SETTING NA
DESELECTED INPUT STATE NA
BUFFER STRENGTH 4 mA
RESET STATE# 0
SUPPLY DVDD4
LCD.VS LCD.HS LCD.AC LCD.PCLK LCD.P15:0
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
KB.C5:0
DVDD1
KB.R4:0
input
DVDD1
input input Z Z
DVDD1 DVDD1 DVDD1 DVDD1
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
GZG BALL H18 8 H20 H19 9 GDY BALL F16 6 G16 G 3 G13 SIGNAL NAME MCBSP1.DX MCBSP1.FSX MCBSP1.DR CAM.EXCLK ETM.SYNC UWIRE.SDO J 5 J15 H15 5 CAM.LCLK ETM.CLK UWIRE.SCLK J 8 J18 G G14 CAM.D7 ETM.D7 UWIRE.CS0 J 9 J19 G G12 CAM.D6 ETM.D6 UWIRE.CS3 J J14 H16 6 CAM.D5 ETM.D5 UWIRE.SDI K18 8 J 5 J15 CAM.D4 ETM.D4 UART3.TX K19 9 G G17 CAM.D3 ETM.D3 UART3.RX K15 5 H17 CAM.D2 ETM.D2 UART3.CTS K14 H14 CAM.D1 ETM.D1 UART3.RTS L19 9 J 6 J16 CAM.D0 ETM.D0 MPUIO12 L18 8 L15 5 J J17 K15 5 CAM.VS ETM.PSTAT2 CAM.HS ETM.PSTAT1 UART2.CTS
DESELECTED INPUT STATE NA 0 NA NA NA NA 0 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
BUFFER STRENGTH 4 mA
RESET STATE# 0 input 0
SUPPLY DVDD1 DVDD1 DVDD1
PD20 8 mA
input p
DVDD1
input p
DVDD1
input p
DVDD1
input p
DVDD1
input p
DVDD8
8 mA PD20 8 mA PD20 8 mA
input p
DVDD1
input p
DVDD1
input p
DVDD1
input p
DVDD1
input p input p
DVDD1 DVDD1
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
DESELECTED INPUT STATE NA NA NA NA NA NA NA NA 1 NA NA NA NA 1 NA 1 NA 1 NA 0 NA NA NA 1 NA NA NA NA NA NA NA NA NA NA NA NA
BUFFER STRENGTH 8 mA
RESET STATE# 0
SUPPLY DVDD1
DVDD1
input p
DVDD1
input
DVDD1
input p
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
input p
PD20 PD20 PD20 PD20 PD20
input p
PD20 PD20 PD20 PD20 PD20 PD20
input p
DVDD1
input p
DVDD1
GPIO2 SPI.CLK
input p
DVDD1
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
DESELECTED INPUT STATE NA NA NA NA 0 NA NA NA NA NA NA NA NA NA NA NA 1 1 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
BUFFER STRENGTH 4 mA 4 mA
RESET STATE# input p input p
SUPPLY DVDD1 DVDD1
input p input p
DVDD1 DVDD1
input p input Z Z input p
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PD20 PD20 PD20 PD20
DVDD1
DVDD1 DVDD1
DVDD1
R14 T15 T16 U17 U16 R13
input input input input 0 input
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
DESELECTED INPUT STATE NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 1 NA NA NA 0 NA
BUFFER STRENGTH
RESET STATE# input input Z Z input input p
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
DVDD1
PD20 PD20
DVDD1
input 0 0 input input 0 0
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PD20 PD20 PD20 4 mA
input p
DVDD1
MCSI1.SYNC USB1.VP
PD20 PD20
input p
DVDD1
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
DESELECTED INPUT STATE 0 0 0 NA 0 0 NA NA NA NA NA NA 1 NA NA NA NA 1 NA NA 1 NA NA NA 0 NA NA 0 NA NA 0 NA NA 0 NA NA NA
BUFFER STRENGTH 2 mA
RESET STATE# input p
SUPPLY DVDD1
input p
DVDD1
J, B F F PU20 PU20 4 mA PU20 PU20 PU20 PU20 PU20 PU10 0 PD20 PD20 PD20 4 mA PD20 PD20 4 mA PD20 PD20 PD20 4 mA 4 mA 4 mA J, A, G1 J, E J, E, G3 J, E, G3 4 mA J, A, G , G2 J, E 4 mA 4 mA J, B, G1 J, E J, B 4 mA J, B, G , G1 4 mA 4 mA J, A, G1 J, B, G1 J, B, G , G1 4 mA J, B, J B G1
input NA NA input p
DVDD1 NA NA DVDD1
0 input input p
DVDD1 DVDD1 DVDD1
input p
DVDD1
MMC.CMD / SPI.DO MCSI2.CLK USB2.SUSP MCSI2.DIN USB2.VP MCSI2.DOUT USB2.TXEN MCSI2.SYNC GPIO7 MCLK MCLKREQ
input input p input p 0 input p 0 input p input input
DVDD1 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3
GPIO9 GPIO8
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
GZG BALL V8 P10 0 W7 V7 Y6 W6 6 AA5 5 R9 9 Y5 5 GDY BALL P7 R6 6 T6 T5 5 U5 P6 6 R5 5 M7 N6 6 SIGNAL NAME MPUIO3 MCBSP2.DR MCBSP2.DX MCBSP2.FSX MCBSP2.CLKR GPIO11 MCBSP2.CLKX MCBSP2.FSR GPIO12 MCBSP2.DX MCBSP2.DR UART2.RX USB2.VM UART2.CTS USB2.RCV GPIO7 W5 5 U U4 pin forced to drive low UART2.RTS USB2.SE0 MPUIO5 V6 6 R4 pin forced to drive low UART2.TX USB2.TXD Y4 W4 P9 R8 Y2 W3 V4 W2 W1 U4
DESELECTED INPUT STATE NA NA NA 0 0 NA NA 0 NA NA NA 1 0 1 0 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
BUFFER STRENGTH 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA
RESET STATE# input input p input Z input Z 0 input p input p
SUPPLY DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3 DVDD3
PD20 PD20 PD20 PD20 PD20 PD20 4 mA 4 mA 4 mA
DVDD3
4 mA 8 mA 18.3 mA 18.3 mA
DVDD3 DVDD2 DVDD2 DVDD2 NA NA DVDD5 DVDD5 DVDD5 DVDD5
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-3. Terminal Characteristics and Multiplexing (Continued)
GZG BALL V3 T4 U3 U1 P8 T3 T2 R4 R3 R2 P7 P4 P2 N7 N2 N4 N3 N8 M4 M3 M7 M8 L3 L4 L7 K3 K4 L8 J1 J3 J4 J2 K7 H3 H4 K8 G2 G3 G4 F3 J7 E3 F4 D2 E4 C1 D3 J8 H7 E5
GDY BALL U2 T1 N2 R1 M3 P1 N1 N4 M5 M4 M2 M1 L6 L4 K3 L5 K4 L1 K5 5 K1 J2 J1 J5 H1 J3 J4 H6 H5 H2 H4 H3 G2 G1 G5 G3 G4 E1 F2 F4 F3 F5 D2 E4 E3 C2 C1 G6 B1 C3 N11
SIGNAL NAME FLASH.D15:0
MUX CTRL SETTING NA
DESELECTED INPUT STATE NA
BUFFER STRENGTH 4 mA
RESET STATE# 0
SUPPLY DVDD5
FLASH.CLK FLASH.CS3 FLASH.CS2 FLASH.BAA FLASH.CS1 FLASH.CS0 FLASH.BE1:0 FLASH.ADV FLASH.A24:1
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
FLASH.RDY RSVD
input NA
DVDD5 NA
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
August 2002 - Revised August 2004
SPRS197D
Introduction
Signal Description
Table 2-4 provides a description of the signals on OMAP5910. Many signals are available on multiple pins depending upon the software configuration of the pin multiplexing options. Ball numbers which are italicized indicate the default pin muxings at reset. Ball numbers for busses are listed from MSB to LSB (left to right, top to bottom). Table 2-4. Signal Description
SIGNAL GZG BALL C3 A2 D4 GDY BALL A1 C4 A2 DESCRIPTION TYPE
EMIFF SDRAM Interface SDRAM.WE SDRAM.RAS SDRAM.DQMU SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS commands to SDRAM memory. SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB, REFR, and MRS commands to SDRAM memory. SDRAM upper data mask. Active-low data mask for the upper byte of the SDRAM data bus (SDRAM.D15:8). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memories. SDRAM lower data mask. Active-low data mask for the lower byte of the SDRAM data bus (SDRAM.D7:0). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memories. SDRAM data bus. SDRAM.D15:0 provides data exchange between the Traffic Controller and SDRAM memory. O / Z O / Z O / Z
SDRAM.DQML
SDRAM.D15:0
D5, C4, B4, D6, C5, H8, C6, B6, D7, C7, D8, B8, G8, C8, G9, B9 D9
D4, C5, G8, B4, B5, C6, A3, E6, D6, A4, B6, F7, C7, B7, D7, A6 D7
SDRAM.CKE
SDRAM clock enable. Active-high output which enables the SDRAM clock during normal operation SDRAM.CKE is driven inactive to put the memory into low-power mode. SDRAM clock. Clock for synchronization SDRAM memory commands / accesses. To minimize voltage undershoot and overshoot effects, it is recommended to place a series resistor (typically ~33 ) close to the SDRAM.CLK driver pin. SDRAM.CLK can also be configured as an input to monitor skew control. SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes, and the REFR and MRS commands to SDRAM memory. SDRAM bank address bus. Provides the bank address to SDRAM memories.
SDRAM.CLK
SDRAM.CAS SDRAM.BA1:0
H9 D10, C10
F8 C9, B8
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL GZG BALL G10, H10, C11, D11, G11, C12, D12, H11, C13, D13, G12, C14, B14 GDY BALL C8, B9, E9, A8, C10, F9, D9, A9, D10, C11, B10, A10, B11 DESCRIPTION TYPE
EMIFF SDRAM Interface (Continued) SDRAM.A12:0 SDRAM address bus. Provides row and column address information to the SDRAM memory as well as MRS command data. SDRAM.A10 also serves as a control signal to define specific commands to SDRAM memory. O / Z
EMIFS FLASH and Asynchronous Memory Interface FLASH.WP FLASH.WE FLASH.RP FLASH.OE FLASH.D15:0 V4 W2 W1 U4 V3, T4, U3, U1, P8, T3, T2, R4, R3, R2, P7, P4, P2, N7, N2, N4 N3 N8 M4 M3 M7 M8, L3 L4 M4 R3 P2 T2 N3 U2, T1, N2, R1, M3, P1, N1, N4, M5, M4, M2, M1, L6, L4, K3, L5 K4 L1 K5 K1 J2 J1, J5 H1 K5 EMIFS byte enables. Active-low byte enable signals used to perform byte-wide accesses to memories or devices that support byte enables. EMIFS address valid. Active-low control signal used to indicate a valid address is present on the FLASH.A24:1 bus. EMIFS burst advance acknowledge. Active-low control signal used with Advanced Micro Devices burst Flash. FLASH.BAA is multiplexed with FLASH.CS2. O / Z O / Z O / Z EMIFS write protect. Active-low output for hardware write protection feature on standard memory devices. EMIFS write enable. Active-low write enable output for Flash or SRAM memories or asynchronous devices. EMIFS power down or reset output (Intel flash devices) EMIFS output enable. Active-low output enable output for Flash or SRAM memories or asynchronous devices. EMIFS data bus. Bidirectional 16-bit data bus used to transfer read and write data during EMIFS accesses. O / Z O / Z O / Z O / Z I / O / Z
FLASH.CLK FLASH.CS3 FLASH.CS2 FLASH.CS1 FLASH.CS0 FLASH.BE1:0 FLASH.ADV FLASH.BAA
EMIFS clock. Clock output that is active during synchronous modes of EMIFS operation for synchronous burst Flash memories. EMIFS chip selects. Active-low chip-select outputs that become active when the p p p appropriate address i d i dd is decoded i d d internal to the device. Each chip select decodes a l h d i E h hi l d d 32M-byte region of memory space space.
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL GZG BALL L7, K3, K4, L8, J1, J3, J4, J2, K7, H3, H4, K8, G2, G3, G4, F3, J7, E3, F4, D2, E4, C1, D3, J8 H7 GDY BALL J3, J4, H6, H5, H2, H4, H3, G2, G1, G5, G3, G4, E1, F2, F4, F3, F5, D2, E4, E3, C2, C1, G6, B1 C3 DESCRIPTION TYPE
EMIFS FLASH and Asynchronous Memory Interface (Continued) FLASH.A24:1 EMIFS address bus. Address output bus for all EMIFS accesses. FLASH.A24:1 provides the upper 24 bits of a 25-bit byte address. The byte enables must be used to implement 8-bit accesses. O / Z
FLASH.RDY
EMIFS ready. Active-high ready input used to suspend the EMIFS interface when the external memory or asynchronous device is not ready to continue the current cycle. It is recommended that this pin should be pulled high externally and unused. See the OMAP5910 Dual-Core Processor Silicon Errata (literature number SPRZ016) for more details. LCD vertical sync output. LCD.VS is the frame clock which signals the start of a new frame of pixels to the LCD panel. In TFT mode, LCD.VS is the vertical synchronization signal. LCD horizontal sync. LCD.HS is the line clock which signals the end of a line of pixels to the LCD panel. In TFT mode, LCD.HS is the horizontal synchronization signal. LCD AC-bias. LCD.AC is used to signal the LCD to switch the polarity of the row and column power supplies to counteract charge buildup causing DC offset. In TFT mode, LCD.AC is used as the output enable to latch LCD pixel data using the pixel clock. LCD pixel clock output. Clock output provided to synchronize pixel data to the LCD panel. In passive mode, LCD.PCLK only transitions when LCD.P15:0 is valid. In active mode, LCD.PCLK transitions continuously and LCD.AC is used as the output enable when LCD.P15:0 is valid.
LCD Interface LCD.VS D14 D11 O
LCD.HS
LCD.AC
LCD.PCLK
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL LCD Interface (Continued) LCD.P15:0 D15, C16, A17, G13, B17, C17, D16, D17, C18, B19, A20, H13, G14, C19, B21, D18 V19, P15, C20, C21, E18, D19, D20, F18 M20, N21, N19, E19, E20, H14, F19, G18 G20 G21 Y6 W16, N14 H15, H18 W7 N18, P18, P19, P20 D12, C13, B12, F11, B13, E12, A13, C14, B14, A15, C15, B15, A16, D15, C16, B16 M13, L12, A17, D16, B17, E15, E16, C17 K16, K17, K14, D17, E17, F15, D14, D13 F13 G15 U5 P14, R16 F17, F16 T6 L15, K12, K13, L14 LCD pixel data bus. Pixel data is transferred on this output bus to LCD panel. O GZG BALL GDY BALL DESCRIPTION TYPE
Keyboard Matrix Interface KB.C7:0 Keyboard matrix column outputs. KB.Cx column outputs are used in conjunction with the KB.Rx row inputs to implement a 6x5 or 8x8 keyboard matrix. O
KB.R7:0
Keyboard matrix row inputs. KB.Rx row inputs are used in conjunction with the KB.Cx column outputs to implement a 6x5 or 8x8 keyboard matrix.
Multichannel Buffered Serial Ports (McBSPs) MCBSP1.CLKS MCBSP1.CLKX MCBSP2.CLKX MCBSP3.CLKX MCBSP1.FSX MCBSP2.FSX MCBSP3.FSX McBSP1 clock source. Provides external clock reference for use with transmitter or reciever. CLKS is only present on McBSP1. McBSP transmit clock. Serial shift clock reference for the transmitter. CLKX is present on all McBSPs. In the case of McBSP1 and McBSP3, the clock input to ll M BSP I h f M BSP1 d M BSP3 h l k i the McBSP receiver may also be provided on this terminal via an internal loop-back connection between the transmitter and receiver clocks. McBSP transmit frame sync. Frame synchronization for transmitter. FSX is p present on all McBSPs. In the case of McBSP1 and McBSP3, the frame sync , y input to the McBSP receiver may also be provided on this terminal via an internal i t t th M BSP i l b id d thi t i l i i t l loop-back connection between the transmitter and receiver frame syncs syncs. I I / O / Z / /
August 2002 - Revised August 2004
SPRS197D
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL GZG BALL H18, H15 AA5, P10 P14, W21 V7 W6 H20 P10, AA5 AA17, U18 GDY BALL F16, F17 R5, R6 U13, P16 T5 P6 G16 R6, R5 R12, P17 McBSP2 receive clock. Serial shift clock reference for the receiver. CLKR is only present on McBSP2. McBSP2 receive frame sync. Frame synchronization for the receiver. FSR is only present on McBSP2. McBSP receive data. Serial receive data input. DR is present on all McBSPs. p p I / O / Z I / O / Z I DESCRIPTION TYPE
Multichannel Buffered Serial Ports (McBSPs) (Continued) MCBSP1.DX MCBSP2.DX MCBSP3.DX MCBSP2.CLKR MCBSP2.FSR MCBSP1.DR MCBSP2.DR MCBSP3.DR Camera Interface CAM.EXCLK CAM.LCLK CAM.VS CAM.HS CAM.D7:0 H19 J15 L18 L15 J18, J19, J14, K18, K19, K15, K14, L19 M19 G13 H15 J17 K15 G14, G12, H16, J15, G17, H17, H14, J16 J14 Camera interface external clock. Output clock used to provide a timing reference to a camera sensor. Camera interface line clock. Input clock to provide external timing reference from camera sensor logic. Camera interface vertical sync. Vertical synchronization input from external camera sensor. Camera interface horizontal sync. Horizontal synchronization input from external camera sensor. Camera interface data. Data input bus to receive image data from an external camera sensor. O I I I I McBSP transmit data. Serial transmit data output. DX is present on all McBSPs. O
CAM.RSTZ ETM9 Trace Macro Interface ETM.CLK ETM.SYNC ETM.D7:0
Camera interface reset. Reset output used to reset or Initialize external camera sensor logic.
J15 H19 J18, J19, J14, K18, K19, K15, K14, L19
H15 G13 G14, G12, H16, J15, G17, H17, H14, J16
ETM9 Trace Clock. Clock output for standard ETM9 test / debug equipment. ETM9 Trace Synchronization. Trace Sync output for standard ETM9 test / debug equipment. ETM9 Trace Packet data. Trace Packet outputs for standard ETM9 test / debug equipment.
SPRS197D
August 2002 - Revised August 2004
Introduction
Table 2-4. Signal Description (Continued)
SIGNAL GZG BALL L18, L15, M19 V19, J15 W21, H19 U18, J14 N14, J18 P15, J19 N20 GDY BALL J17, K15, J14 M13, H15 P16, G13 P17, H16 R16, G14 L12, G12 L16 DESCRIPTION TYPE
ETM9 Trace Macro Interface (Continued) ETM.PSTAT2:0 ETM9 Trace Pipe State 2-0. Pipeline status outputs for standard ETM9 test / debug equipment. O
MICROWIRE Interface UWIRE.SCLK UWIRE.SDO UWIRE.SDI UWIRE.CS0 UWIRE.CS3 HDQ / 1-Wire Interface HDQ HDQ / 1-wire interface. HDQ optionally implements one of two serial protocols: HDQ or 1-Wire. Shared General-Purpose I / O. Each GPIO pin can be used by either the DSP core p / p y or the MPU core. Control of each GPIO pin between the two cores is selected by h C l f h i b h i l db the MPU via control registers Each GPIO pin may also be configured to cause an registers. interrupt to its respective core processor. GPIO5 and GPIO10 are not available on the OMAP5910 device. device I / O MICROWIRE serial clock. This pin drives a clock to a MICROWIRE device. The active edge is software configurable. MICROWIRE serial data out. Write data is transferred to a MICROWIRE device on this pin. MICROWIRE serial data in. Read data is transferred from a MICROWIRE device on this pin. MICROWIRE chip select 0. The CS0 output selects a single MICROWIRE device (configurable as active high or active low). MICROWIRE chip select 3. The CS3 output selects a single MICROWIRE device (configurable as active high or active low). O O I O O
General-Purpose I / O (GPIO) and MPU I / O (MPUIO) GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO9 GPIO8 GPIO7 M20 N21 N19 N18, W6 N20, V7 W8 Y8 M15, Y5, V9 P19 P20 P18 M14 R19 R18 K16 K17 K14 L15, P6 L16, T5 M8 U6 L17, N6, R7 K13 L14 K12 M15 M17 M16 I / O / Z / /
GPIO6 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
August 2002 - Revi