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DragonBall Operation

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DragonBall Operation
Date: 11 / 12 / 98
Preliminary
Application Note 16bit SRAM Interface
INTRODUCTION
This note describes the method of interfacing a 16bit SRAM to DragonBall-EZ (MC68EZ328). The interface is simply constructed by discrete logic gates. In this note, the EZ68328ADS was used as a development platform and the TOSHIBA TC554161FTL-85 16bit Static Ram was used as an example. The TC554161FTL is 4, 194, 304 bits static random access memory organized as 262, 144 words by 16 bits.
HARDWARE
Figure 1 shows a functional block diagram of the 16 bit SRAM interface.
A1..17 D0..15
A1..A17 I / O 1..16
DragonBall -EZ
UWE LWE
LOGIC GATES
16 bit SRAM
OE CSC0
Figure 1. Block Diagram of the 16 bit SRAM interface
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
The logic implemented between the DragonBall -EZ and 16 bit SRAM is shown as following tables:
Write word Write Upper Byte Write Lower Byte Read
0 Table 1. Logic table for UDS LDS 0 1 0 0
Write word Write Upper Byte Write Lower Byte Read
Table 2. Logic table for LDS
Table 3. Logic table for R / W 4 AND gates and 4 NOT gates are used to implement the above logic. The following schematic shows how to use one 74HC04 and one 74HC08 to implement the logic.
2 DragonBall MC68EZ328 Application Notes MOTOROLA
74HC04 U3B 74HC08
5 4 3 2 54 53 52 51 33 32 31 30 29 27 26 25 24 23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
74HC08 U2D 74HC04 U2C U3D
TC55416FTL
74HC04
74HC08 74HC04 74HC08
MOTOROLA SEMICONDUCTORS LTD HK. 2 DAI KING ST, TAIPO, NT, HONG KONG.
Title 16 bit SRAM Interface Size Document Number Custom 16bitsram.SCH Date:
Rev 0.1 Friday, November 06, 1998
Sheet
Note:
Form the schematics and block diagram, we can see that A0 from the SRAM is connected to A18 from the DragonBallEZ. This connection is because of word addressing in 16 bit SRAM. D15...D8 D7.....D0 D15.......D0 0...00 0....01 0....02 0....03 0....04
abcd .. .. .. ..
DragonBall-EZ
16 bit SRAM
As shown in the above, the addressing in DragonBall-EZ and 16 bit SRAM is different. Connecting A0 to A18 can solve this problem. By connecting A0 to A18, the address is always even in 16 bit SRAM. Upper Byte Write and Lower Byte Write only depends on the UDS and LDS. When write to lower Byte, LDS asserts while UDS asserts when writing upper byte. For the read operation, UDS and LDS always assert since reading Lower Byte or Upper Byte depends on DragonBallEZ only. DragonBall can select to read D0-D7 or D8-D15 itself. Let us consider the following example, after connecting A0 to A18, the addressing in SRAM becomes: D15.......D0 0....00 0....02 0....04 0....06 .....
abcd .. .. .. ..
16 bit SRAM
As shown in the above table, there is no odd address, therefore the address line A0-A17 in SRAM is the same when accessing upper byte (0xab)and lower byte(0xcd). But the difference is when write to upper byte UDS asserts while LDS asserts when write to lower byte.
4 DragonBall MC68EZ328 Application Notes MOTOROLA
INITIALIZATION
Finally here is the source code for initialization.
SOURCE CODE
MOTOROLA
DragonBall MC68EZ328 Application Notes