DragonBall Operation Date: 11/12/98 Application Note 16bit S

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DragonBall Operation Date: 11/12/98 Application Note 16bit S

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DragonBall Operation
Date: 11/12/98
Application Note 16bit SRAM Interface
INTRODUCTION
This note describes method interfacing 16bit SRAM DragonBall-EZ (MC68EZ328). interface simply constructed discrete logic gates. this note, EZ68328ADS used development platform TOSHIBA TC554161FTL-85 16bit Static used example. TC554161FTL 4,194,304 bits static random access memory organized 262,144 words bits.
HARDWARE
Figure shows functional block diagram SRAM interface.
A1.17 D0.15
A1.A17 1.16
DragonBall
*UWE *LWE
LOGIC GATES
*UDS *LDS R/*W
SRAM
*CSC0
Figure Block Diagram SRAM interface
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
1996 Motorola, Inc. Rights Reserved.
logic implemented between DragonBall SRAM shown following tables:
*UWE *LWE
*UDS
Write word Write Upper Byte Write Lower Byte Read
Table Logic table *UDS *LDS
*UWE
*LWE
Write word Write Upper Byte Write Lower Byte Read
Table Logic table *LDS
*UWE *LWE
R/*W
Table Logic table R/*W gates gates used implement above logic. following schematic shows 74HC04 74HC08 implement logic.
DragonBallMC68EZ328 Application Notes MOTOROLA
74HC04 74HC08
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16
*UWE
*UDS *LDS R/*W
*LWE
*CSC0
74HC08 74HC04
TC55416FTL
74HC04
74HC08 74HC04 74HC08
MOTOROLA SEMICONDUCTORS KING TAIPO, HONG KONG.
Title SRAM Interface Size Document Number Custom 16bitsram.SCH Date:
Friday, November 1998
Sheet
Note:
Form schematics block diagram, that from SRAM connected from DragonBallEZ. This connection because word addressing SRAM. D15.D8 D7.D0 D15.D0 0.00 0.01 0.02 0.03 0.04
abcd
DragonBall-EZ
SRAM
shown above, addressing DragonBall-EZ SRAM different. Connecting solve this problem. connecting A18, address always even SRAM. Upper Byte Write Lower Byte Write only depends *UDS *LDS. When write lower Byte, *LDS asserts while *UDS asserts when writing upper byte. read operation, *UDS *LDS always assert since reading Lower Byte Upper Byte depends DragonBallEZ only. DragonBall select read D0-D7 D8-D15 itself. consider following example, after connecting A18, addressing SRAM becomes: D15.D0 0.00 0.02 0.04 0.06
abcd
SRAM
shown above table, there address, therefore address line A0-A17 SRAM same when accessing upper byte (0xab)and lower byte(0xcd). difference when write upper byte *UDS asserts while *LDS asserts when write lower byte.
DragonBallMC68EZ328 Application Notes MOTOROLA
INITIALIZATION
Finally here source code initialization.
SOURCE CODE
*This program initialize SRAM M328_GRPBASEC M328_CSC M328_CSD M328_PCSEL M328_DRAMCONT M328_EXTWE SECTION code START: MOVE.W MOVE.W MOVE.W ANDI.B ANDI.B ANDI.B #$400,M328_GRPBASEC #$89,M328_CSC #$9d,M328_CSD #$7f,M328_DRAMCONT #$fb,M328_PCSEL #$7f,M328_EXTWE ;Set Group Base Address ;Set Chip Select Register ;Disable DRAM ;Disable DRAM controller ;Enable Chip Select CSC0 ;Extend *LWE *UWE $fff104 $fff114 $fff116 $fff40B $fffc02 $fff150
MOTOROLA
DragonBallMC68EZ328 Application Notes

DragonBall Operation Date: 11/12/98 Application Note 16bit S

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