DTACK GENERATOR DTACK Generator state machine. delays memory acce
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PCMCIA RELEASE INTERFACE BOARD DRAGONBALL UPDATE
DTACK GENERATOR
DTACK Generator state machine. delays memory access cycle Card when card asserts *WAIT signal. state diagram shown Figure *CSD3=1
*CSD3=0 *CSD3=1
*CSD3=0
*WAIT=0 Figure 0-1. DTACK Generator State Diagram
state transitions take place rising edge system clock. state machine implemented following circuit.
MOTOROLA
PCMCIA RELEASE INTERFACE BOARD DRAGONBALL
74LS00 74LS00 74HC74 74LS00 74HC74 74LS00
*WAIT
*WAIT
*CSD3
*CSD3
74HC04
*WAIT 74HC04 74HC240 *DTACK *DTACK
MOTOROLA HIGH PERFORMANCE EMBEDDED SYSTEMS KING TAIPO TAIPO Title DTACK GENERATOR Size Document Number CustomHE95002 Date:
Tuesday, November 1998
Sheet
Design Document
State stands time when both *CSD3 negated. There card access activities. When *CSD3 asserted, state machine transits state Then after clock transits state After Card asserted *WAIT signal, state machine holds state Beginning from *DTACK generated from inverted *WAIT signal which implemented follows.
*WAIT
*DTACK
When state machine asserts enables inverter. Therefore when *WAIT asserts, *DTACK negated when *WAIT negates, *DTACK asserted. *CSD3 *WAIT
*DTACK
When there *WAIT asserting cycle, *DTACK will assert after until
*CSD3 *WAIT
*DTACK
After *WAIT signal negated, state machine transits When *CSD3 negates, returns negates disables invertor that *DTACK returns high impedance state.
PCMCIA RELEASE INTERFACE BOARD DRAGONBALL
MOTOROLA
Design Document
DECODER
implemented PAL22V10. decodes DragonBall control signals generates PCMCIA control signals. this application, space memory space inclucding attribute memory common memory card selected *CSD3. DragonBall assert *REG(PM2 while accessing attribute memory space. access common memory, DragonBall negate *REG(PM2=1). access I/O, DragonBall assert IOEN (PJ4) *REG. following updated equation with only chip select used.
TITLE AUTHOR COMPANY DATE REVISION PATTERN CHIP ;PIN PCMCIA 2.01 DECODER JACKY MOTOROLA INC. 23/11/98
PAL22V10 IOEN /CSD3 /UDS /LDS
/LWE
/UWE
/BUFF
;PIN
/BOE /BWE /IOW /IOR
/CE2 /CE1 GLOBAL
EQUATIONS CSD3 CSD3 CE1.TRST BUFF CSD3 CE2.TRST BUFF CSD3 IOEN IOR.TRST BUFF CSD3 IOEN CSD3 IOEN IOW.TRST BUFF /IOEN CSD3 BWE.TRST BUFF CSD3 BUFF /IOEN CSD3 BOE.TRST BUFF
MOTOROLA
PCMCIA RELEASE INTERFACE BOARD DRAGONBALL
Design Document
from equation, signals generated simple logic, therefore logic gates used instead implement this decoder.
MEMORY
PCMCIA interface memory shown 0-2.
0x800000 Common Memory *REG
Attribute Memory (IOEN=0) Space (IOEN=1) 0XBFFFFF
*REG
Figure 0-2. PCMCIA Interface Memory
INITIALIZATION CODE
Init_CS, port. (write 0xfff43b=0x1F) CSD3 selects address range 0x800000 0xBFFFFF external DTACK used.
*************BEFORE INSERTING CARD ************ Init_CS write 0xfff43b 0x1F write 0xfff14c 0x80013ff7 Buffer_Off write 0xfff441 0xFE AttrMem_Off write 0xfff44b 0x06 write 0xfff449 0xff write 0xfff448 0x00
*************AFTER INSERTING CARD ************
PCMCIA RELEASE INTERFACE BOARD DRAGONBALL
MOTOROLA
Design Document Vcc_On write 0xfff44b 0x1E write 0xfff449 0xE7 write 0xfff448 0x1C Buffer_On write 0xfff443 0x3C write 0xfff441 0xEE write 0xfff440 0x10 C_Reset write 0xfff44b 0x1E write 0xfff448 0x1C write 0xfff449 0xE7 AttrMem_On write 0xfff44b 0x1E write 0xfff449 0xE3 write 0xfff448 0x1C read attribute memory, type read 0x8000000 read space, type write 0x810000 0x41 write 0xfff438 0x10f5 Note: Port output port assert IOEN.
PCMCIA RELEASE INTERFACE BOARD DRAGONBALL
MOTOROLA
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