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PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL UPDATE

DTACK GENERATOR

PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL UPDATE
DATE : 24 NOV 98
DTACK GENERATOR
All the state transitions take place at rising edge of the system clock. The state machine can be implemented by following circuit.
MOTOROLA
PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL
CLK 4 U1B U3A 5 4 3 U1A CL Q1 1 3 74LS00 2 U1D 12 11 Q1 13 10 Q0 11 74LS00 CL Q 8 74HC74 Q1 CLK 9 PR 8 D Q D1 12 9 Q1 10 74LS00 U3B U1C VCC 1 2 74HC74 Q 6 Q0 74LS00 CLK PR 6 D Q D0 2 5
74HC04
U4A WAIT U2B D1 3 74HC04 4 2 4 6 8 1 A1 A2 A3 A4 G 74HC240 Y1 Y2 Y3 Y4 18 16 14 12 DTACK DTACK
MOTOROLA HIGH PERFORMANCE EMBEDDED SYSTEMS 2 DAI KING ST, TAIPO IND EST TAIPO NT HK Title DTACK GENERATOR Size Document Number CustomHE95002 Date:
Rev 0.1 Tuesday, November 24, 1998
Sheet
Design Document
State S0 stands for the time when both CSD3 is negated. There is no card access activities. When CSD3 is asserted, the state machine transits to state S1. Then after a clock , it transits to state S2. After the PC Card has asserted the WAIT signal, the state machine holds in state S2. Beginning from S2, DTACK is generated from inverted WAIT signal which is implemented as follows. D1
DTACK
When state machine is in S2 or S3, D1 asserts and enables the inverter. Therefore when WAIT asserts, DTACK is negated and when WAIT negates, DTACK is asserted. S2 CSD3 WAIT
DTACK
When there is no WAIT asserting in the cycle, DTACK will assert after S2 until S0.
CSD3 WAIT
DTACK
After WAIT signal is negated, the state machine transits to S3. When the CSD3 negates, it returns to S0 and D1 negates and disables the invertor so that DTACK returns to high impedance state.
PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL
MOTOROLA
Design Document
DECODER
TITLE AUTHOR COMPANY DATE REVISION PATTERN CHIP PIN PCMCIA VER 2.01 DECODER JACKY LI MOTOROLA INC. 23 / 11 / 98
U1 PAL22V10 2 3 4 5 IOEN / CSD3 / UDS / LDS 16 / G
11 / BUFF
12 GND
21 22 23 24 / CE2 / CE1 VCC GLOBAL
MOTOROLA
PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL
Design Document
As you can see from the PAL equation, the signals are generated by simple logic, therefore logic gates can be used instead of PAL to implement this decoder.
0.1 MEMORY MAP
The PCMCIA interface memory map is shown in Fig 0-2.
Figure 0-2. PCMCIA Interface Memory Map
0.2 INITIALIZATION CODE
nop AFTER INSERTING CARD
PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL
MOTOROLA
PCMCIA RELEASE 2.0 INTERFACE BOARD FOR DRAGONBALL
MOTOROLA