Hi-Speed host controller Rev. February 2003 Product data ISP
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ISP1561
Hi-Speed host controller
Rev. February 2003 Product data
ISP1561 PCI-based, single-chip Universal Serial (USB) Host Controller. integrates Original Open Host Controller Interface (OHCI) cores, Hi-Speed Enhanced Host Controller Interface (EHCI) core four transceivers that compliant with Hi-Speed Original USB. functional parts ISP1561 fully compliant with Universal Serial Specification Rev. 2.0, Open Host Controller Interface Specifications Rev. 1.0a, Enhanced Host Controller Interface Specification Universal Serial Rev. 0.95, Local Specification Rev. Power Management Interface Specification Rev. 1.1. integrated high performance transceivers enable ISP1561 handle Hi-Speed transfer speed modes: high-speed (480 Mbit/s), full-speed Mbit/s) low-speed (1.5 Mbit/s). ISP1561 provides four downstream ports that enables simultaneous connections devices different speeds. ISP1561 provides three downstream port status indicators-GoodLinkalong with green amber LEDs-to allow user-rich messages Root downstream ports status, without requiring detailed port information reflected internal registers. ISP1561 fully compatible with various operating system drivers, such Microsoft® Windows® standard OHCI EHCI drivers that present Windows Second Edition (SE), Windows Millennium Edition (Me), Windows Windows 2000. ISP1561 directly interfaces 32-bit, bus. V-tolerant pins that source interface fully complies with Local Specification, Rev. 2.2. ISP1561 ideally suited Hi-Speed host-enabled motherboards, Hi-Speed host add-on card applications, mobile applications, embedded solutions. facilitate motherboard development, ISP1561 available clock signal reduce total cost solution. However, reduce electromagnetic interference (EMI), recommended that clock used add-on card designs.
Philips Semiconductors
ISP1561
host controller
Abbreviations
Device EHCI Enhanced Host Controller Interface electromagnetic interference Host Controller HCCA Host Controller Communication Area Host Controller Driver OHCI Open Host Controller Interface Power Management Capabilities Power Management Event PMCSR Power Management Control/Status Universal Serial Vendor
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Product data
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ISP1561
host controller
Features
Complies with Universal Serial Specification Rev. Supports data transfer high-speed (480 Mbit/s), full-speed Mbit/s) low-speed (1.5 Mbit/s) Original OHCI cores comply with Open Host Controller Interface Specification Rev. 1.0a Hi-Speed EHCI core complies with Enhanced Host Controller Interface Specification Universal Serial Rev. 0.95 Supports 32-bit, interface compliant with Local Specification Rev. with support D3cold standby wake-up modes; pins standard, V-tolerant Compliant with Power Management Interface Specification Rev. hosts (EHCI OHCI), supports power states: D3hot D3cold Four downstream ports with support three types downstream port indicator LEDs: GoodLinkTM, amber green LEDs CLKRUN support mobile applications, such internal notebook design Configurable subsystem subsystem Vendor through external EEPROM Configurable four port root Digital analog power separation Supports Plug Play remote wake-up peripherals Supports individual power switching individual overcurrent protection downstream ports Supports partial dynamic port-routing capability downstream ports that allows sharing same physical downstream ports between Original Host Controller Hi-Speed Host Controller Supports legacy PS/2 keyboards mice Uses crystal oscillator reduce system cost emissions Operates +3.3 power supply input Full industrial operating temperature range from Full-scan design with high fault coverage (93% 95%) ensures high quality LQFP128 package available.
Applications
motherboard Notebook add-on card Set-Top (STB) appliance.
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Product data
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Philips Semiconductors
ISP1561
host controller
Ordering information
Table Ordering information Package Name ISP1561BM LQFP128 Description plastic profile quad flat package; leads; body Version SOT420-1 Type number
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Product data Rev. February 2003
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SMI# SEL48M PME# GLOBAL CONTROL legacy keyboard mouse support CORE MASTER
Block diagram
Philips Semiconductors
ISP1561BM
IRQ1 IRQ12 KBIRQ1 MUIRQ12 A20OUT
AD[31:0] C/BE#[3:0] REQ# GNT# IDSEL INTA#
PCI-bus
FRAME# DEVSEL# IRDY# CLKRUN# PERR# SERR# TRDY# STOP#
SLAVE CONFIGURATION SPACE CONFIGURATION FUNCTION CONFIGURATION FUNCTION CONFIGURATION FUNCTION OHCI (FUNCTION OHCI (FUNCTION EHCI (FUNCTION SEL2PORTS AVAUX_PLL AVAUX VAUX RREF GND_RREF AGND DGND
RST#
CORERESET PORT ROUTER
VDD_DETECT XTAL1 XOSC XTAL2
ATX1
ATX3
ATX2
ATX4
ORIGINAL
Hi-SPEED
ORIGINAL
Hi-SPEED
ORIGINAL
Hi-SPEED
ORIGINAL
Hi-SPEED
AMB1 GRN1 PWE1
AMB3 GRN3 PWE3
AMB2 GRN2 PWE2
AMB4 GRN4 PWE4
004aaa156
host controller
ISP1561
Block diagram.
Philips Semiconductors
ISP1561
host controller
Pinning information
Pinning
AVAUX_PLL GRN2
AVAUX PWE4
AVAUX GRN3
AVAUX
DGND
AGND
AGND
AGND
AGND
PWE3
GRN4
AMB4
AMB3
RREF
SEL48M PME# VAUX DGND IRQ1 IRQ12 SEL2PORTS
PWE2
AMB2
GRN1 GND_RREF AVAUX AMB1 PWE1 XTAL2 XTAL1 DGND VAUX AD[0] DGND AD[1] AD[2] AD[3] AD[4] AD[5] DGND AD[6] AD[7] C/BE#[0] AD[8] AD[9] DGND AD[10] AD[11] AD[12]
C/BE#[3] IDSEL AD[23] DGND AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] DGND AD[16] C/BE#[2] FRAME# IRDY# TRDY# DEVSEL# DGND STOP# CLKRUN# PERR# SERR# C/BE#[1] DGND AD[15] AD[14] AD[13]
MBL340
A20OUT KBIRQ1 MUIRQ12 DGND SMI# INTA# RST# GNT# DGND REQ# AD[31] AD[30] AD[29] AD[28] AD[27] DGND AD[26] AD[25] AD[24]
ISP1561BM
configuration.
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Product data
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ISP1561
host controller
description
Table Symbol[1] SEL48M description Type Description selection between crystal oscillator; push-pull; with hysteresis; tolerant crystal used oscillator used PME# I2C-bus clock (open-drain)[2] I2C-bus data (open-drain)[2] Power Management Event; used device request change device system power state; push-pull, open-drain; slew rate control; CMOS; tolerant auxiliary voltage (3.3 digital ground system keyboard interrupt; push-pull, open-drain; slew rate control; CMOS; tolerant system mouse interrupt; push-pull, open-drain; slew rate control; CMOS; tolerant active downstream port selection; push-pull; with hysteresis; tolerant four ports active only port port active; port port inactive A20OUT KBIRQ1 MUIRQ12 DGND SMI# INTA# RST# supply voltage (3.3 legacy gate output; push-pull, open-drain; slew rate control; CMOS; tolerant legacy keyboard interrupt input; push-pull; with hysteresis; tolerant[3] legacy mouse interrupt input; push-pull; with hysteresis; tolerant[3] digital ground System Management Interrupt; push-pull, open-drain; slew rate control; CMOS; tolerant interrupt; push-pull, open-drain; slew rate control; CMOS; tolerant supply voltage (3.3 reset; used bring PCI-specific registers, sequencers signals consistent state; push-pull; with hysteresis; tolerant system clock MHz) grant; indicates agent that access been granted digital ground
VAUX DGND IRQ1 IRQ12 SEL2PORTS
GNT# DGND
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ISP1561
host controller
description.continued Type Description request; indicates arbitrator that agent wants multiplexed address data multiplexed address data supply voltage (3.3 multiplexed address data multiplexed address data multiplexed address data digital ground multiplexed address data multiplexed address data multiplexed address data supply voltage (3.3 byte multiplexed command byte enable initialization device select; used chip select during configuration read write transactions multiplexed address data digital ground multiplexed address data multiplexed address data multiplexed address data supply voltage (3.3 multiplexed address data multiplexed address data multiplexed address data digital ground multiplexed address data byte multiplexed command byte enable cycle frame; driven master indicate beginning duration access supply voltage (3.3 initiator ready; indicates ability initiating agent complete current data phase transaction target ready; indicates ability target agent complete current data phase transaction device select; indicates device been selected digital ground stop; indicates that current target requesting master stop current transaction CLKRUN signal; push-pull input; three-state output; slew rate control; with hysteresis; tolerant
Table Symbol[1] REQ# AD[31] AD[30] AD[29] AD[28] AD[27] DGND AD[26] AD[25] AD[24] C/BE#[3] IDSEL AD[23] DGND AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] DGND AD[16] C/BE#[2] FRAME# IRDY# TRDY# DEVSEL# DGND STOP# CLKRUN#
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ISP1561
host controller
description.continued Type Description parity error; used report data parity errors during transactions except Special Cycle supply voltage (3.3 system error; used report address parity errors, data parity errors Special Cycle command, other system error where result will catastrophic; push-pull, open-drain; slew rate control; CMOS; tolerant parity byte multiplexed command byte enable digital ground multiplexed address data multiplexed address data multiplexed address data supply voltage (3.3 multiplexed address data multiplexed address data multiplexed address data digital ground multiplexed address data multiplexed address data byte multiplexed command byte enable supply voltage (3.3 multiplexed address data multiplexed address data digital ground multiplexed address data multiplexed address data multiplexed address data supply voltage (3.3 multiplexed address data multiplexed address data digital ground multiplexed address data auxiliary voltage (3.3 digital ground crystal oscillator input; this also clock input crystal oscillator output MHz) overcurrent sense input downstream port (digital); push-pull; with hysteresis; tolerant
Table Symbol[1] PERR# SERR#
C/BE#[1] DGND AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] DGND AD[9] AD[8] C/BE#[0] AD[7] AD[6] DGND AD[5] AD[4] AD[3] AD[2] AD[1] DGND AD[0] VAUX DGND XTAL1 XTAL2
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ISP1561
host controller
description.continued Type Description power enable downstream port (open-drain). Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant GoodLink indicator output downstream port (open-drain); default, blinks upon traffic; bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant amber indicator output downstream port (open-drain); default; programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant analog auxiliary voltage (3.3 supply voltage reference ground; RREF resistor must connected this green indicator output downstream port (open-drain); default.The programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant overcurrent sense input downstream port (digital). Push-pull; with hysteresis; tolerant power enable downstream port (open-drain). Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant GoodLink indicator output downstream port (open-drain); default, blinks upon traffic. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant amber indicator output downstream port (open-drain); default; programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant green indicator output downstream port (open-drain); default; programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant analog auxiliary voltage (3.3 supply voltage analog connection downstream port analog connection downstream port analog ground overcurrent sense input downstream port (digital). Push-pull; with hysteresis; tolerant
Table Symbol[1] PWE1
AMB1
AVAUX GND_RREF GRN1
PWE2
AMB2
GRN2
AVAUX_PLL AGND
AI/O AI/O
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ISP1561
host controller
description.continued Type Description power enable downstream port (open-drain). Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant analog connection external resistor analog auxiliary voltage (3.3 supply voltage analog connection downstream port analog connection downstream port analog ground GoodLink indicator output downstream port (open-drain). default, blinks upon traffic. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant amber indicator output downstream port (open-drain). default; programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant green indicator output downstream port (open-drain); default; programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant analog auxiliary voltage (3.3 supply voltage analog connection downstream port analog connection downstream port analog ground overcurrent sense input downstream port (digital) push-pull; with hysteresis; tolerant power enable downstream port (open-drain). Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant analog auxiliary voltage (3.3 supply voltage analog connection downstream port analog connection downstream port analog ground GoodLink indicator output downstream port (open-drain). default, blinks upon traffic. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant
Table Symbol[1] PWE3
RREF AVAUX AGND
AI/O AI/O AI/O
AMB3
GRN3
AVAUX AGND PWE4
AI/O AI/O
AVAUX AGND
AI/O AI/O
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Product data
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ISP1561
host controller
description.continued Type Description amber indicator output downstream port (open-drain); this acts input only during power-up sequence thereafter, acts output. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant register; supports D3cold register; does support D3cold
Table Symbol[1] AMB4
GRN4
green indicator output downstream port (open-drain) default; programmed enable blink. Bi-directional pin; push-pull input; three-state output; slew rate control; TTL; tolerant digital ground
DGND
Symbol names ending with (for example, NAME#) represent active signals pins. Symbol names with overscore (for example, NAME) represent active signals pins. pull-up resistor should always present even EEPROM used. legacy support used, connect this ground.
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Product data
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ISP1561
host controller
Functional description
OHCI Host Controller
OHCI Host Controller transfers data devices Original defined rate Mbit/s Mbit/s.
EHCI Host Controller
EHCI Host Controller transfers data Hi-Speed compliant device Hi-Speed defined rate Mbit/s. When EHCI Host Controller ownership port, OHCI Host Controllers allowed modify port register. additional port definitions required Enhanced Host Controller visible OHCI Host Controller.
Dynamic port-routing logic
port-routing feature allows sharing same physical downstream ports between Original Host Controller Hi-Speed Host Controller. This requirement Enhanced Host Controller Interface Specification provides four downstream ports, these ports multiplexed with ports OHCIs. first third downstream ports always connected first OHCI, second fourth downstream ports always connected second OHCI. EHCI responsible port-routing switching mechanism. register bits used ownership switching. During power-on system reset, default ownership downstream ports OHCIs. Enhanced Host Controller driver controls ownership during normal functionality.
Hi-Speed analog transceivers
Hi-Speed analog transceivers interface directly cables integrated termination resistors. These transceivers transmit receive serial data data rates: high-speed (480 Mbit/s), full-speed Mbit/s) low-speed (1.5 Mbit/s).
indicators downstream ports
Indication good connection provided through GoodLink technology (open-drain, maximum current mA). During enumeration, indicators blink momentarily corresponding enumeration traffic ISP1561 downstream ports. also blinks whenever there valid traffic downstream port. suspend mode, OFF. GoodLink feature provides user-friendly indication status traffic between host downstream hubs devices. useful diagnostics tool isolate faulty equipment helps reduce field support hotline costs. system designer also program optional port indicators- green amber LED-to indicate status Host Controller. These port indicators implemented specification.
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ISP1561
host controller
indicators open-drain output.
Power management
ISP1561 provides advanced power management capabilities interface that compliant with Power Management Interface Specification, Rev. 1.1. Power controlled managed interaction between drivers registers. Section detailed description power management.
Legacy support
ISP1561 provides legacy support keyboard mouse. This means that keyboard mouse should able work even before boot-up, with necessary support system's BIOS. Section 11.2 provides detailed description legacy support ISP1561.
Phase-Locked Loop (PLL)
clock multiplier integrated on-chip. This allows low-cost crystal, which also minimizes EMI. external components required operate.
interface
interface three functions. first function (#0) second function (#1) OHCI Host Controllers, third function (#2) EHCI Host Controller. functions supports both master target accesses share same interrupt signal INTA#. These functions provide memory-mapped, addressable operational registers required Open Host Controller Interface Specifications Rev. 1.0a Enhanced Host Controller Specification Universal Serial Rev. 0.95. Additionally, function provides legacy keyboard mouse support comply with Open Host Controller Interface Specification Rev. 1.0a. Each function configuration space, enumerator should allocate memory address space each these functions. Power management implemented each function power states provided. This allows system achieve power consumption switching functions which required. 8.1.1 configuration space
Local Specification Rev. requires that each three functions ISP1561 provides configuration registers, which vary size. addition basic configuration header registers, these functions implement capability registers support power management.
registers each these functions accessed respective driver. detailed description various configuration registers given Section 8.2.
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ISP1561
host controller
8.1.2
Initiator/Target initiator initiates transactions bus; target responds transactions slave. case ISP1561, Open Host Controllers Enhanced Host Controller function both initiators targets transactions issued host CPU. Host Controllers have their operational registers, which accessed system driver software. Drivers these registers configure Host Controller hardware system, issue commands and/or monitor status current hardware operation. Host Controller plays role target. operational registers Host Controllers transaction targets CPU. Normal transfers require Host Controller access system memory fields, which allocated Host Controller Drivers (HCDs) drivers. Host Controller hardware interacts with accessing these buffers. Host Controller works initiator this case, becomes master.
configuration registers
OHCI Host Controllers EHCI Host Controller contain sets software-accessible hardware registers: configuration registers memory-mapped Host Controller registers. configuration registers implemented each three functions ISP1561, Table Remark: addition normal header (from offset index 3FH), implementation-specific registers defined support power management function-specific features.
Table Address (Hex)
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configuration space registers OHCI1, OHCI2 EHCI[1] Bits Bits Bits Bits 1561 1131 0210 0000 0C0310 00000000 Reset Value Func0 OHCI1 Func1 OHCI2 Func2 EHCI DID[15:0] Status[15:0] Class Code[23:0] BIST[7:0] Header Type[7:0] LT[7:0] VID[15:0] Command[15:0] REVID[7:0] CLS[7:0] 1561 1131 0210 0000 0C0310 00000000 1562 1131 0210 0000 0C0320 00000000
0[31:0]
Base Address Register (Not configurable prevent setting driver)
00000000
00000000
00000000
Cardbus Pointer[31:0] SID[15:0] Reserved Reserved SVID[15:0] CP[7:0] Expansion Base Address[31:0]
00000000 1561 1131 00000000 000000 00000000
00000000 1561 1131 00000000 000000 00000000
00000000 1562 1131 00000000 000000 00000000
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ISP1561
host controller
Table Address (Hex)
configuration space registers OHCI1, OHCI2 EHCI[1].continued Bits Max_Lat[7:0] Bits Min_Gnt[7:0] Bits Interrupt Pin[7:0] Retry Time-out FLADJ[7:0] Next_Item_Ptr [7:0] Bits IL[7:0] TRDY Time-out SBRN[7:0] Cap_ID[7:0] 0000 Reset Value Func0 OHCI1 Func1 OHCI2 Func2 EHCI 0000 0000
Reserved
Enhanced Host Controller-specific registers PORTWAKECAP[15:0] PMC[15:0] DATA[7:0] PMCSR_BSE [7:0] 5202 0000 5202 0000 XX1F 20[2] FF02 XX00[2] Power management registers
PMCSR[15:0]
Reset values that highlighted (for example, indicate read/write access, reset values that highlighted (for example, indicate read-only. four ports ports.
Host Controller Driver (HCD) does usually interact with configuration space. configuration space used only enumerator identify Host Controller assign appropriate system resources reading Vendor (VID) Device (DID). 8.2.1 configuration header registers Enhanced Host Controller implements normal header register values, except values memory-mapping base address register, serial number Device Vendor register (address: 00H): This read-only register identifies manufacturer device. Special Interest Group (PCI-SIG) assigns valid vendor identifiers ensure uniqueness identifier. description shown Table
Table Vendor register: description Symbol VID[15:0] Access Value 1131H Description Vendor This read-only register value assigned Philips Semiconductors PCI-SIG 1131H.
Device register (address: 02H): Device two-byte read-only register that identifies particular device. This identifier allocated Philips Semiconductors. Table shows description register.
Table Device register: description Symbol DID[15:0] Access Value 156XH[1] Description Device This register value defined Philips Semiconductors identify Host Controller product.
OHCI1 OHCI2 EHCI.
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Command register (address: 04H): This two-byte register that provides coarse control over ability device generate respond cycles. allocation Command register given Table When logic written this register, device logically disconnected from accesses except configuration accesses. devices required support this base level functionality. Individual bits Command register support this base level functionality.
Table Symbol Reset Access Symbol Reset Access SCTRL Table VGAPS Command register: allocation reserved MWIE FBBE SERRE
Command register: description Symbol FBBE Description reserved Fast Back-to-Back Enable: This controls whether master fast back-to-back transactions different devices. initialization software needs this targets fast back-to-back capable. fast back-to-back transactions only allowed same agent (value after RST#) master allowed generate fast back-to-back transactions different agents
SERRE
SERR# Enable: This enable SERR# driver. devices that have SERR# must implement this bit. Address parity errors reported only this logic disable SERR# driver enable SERR# driver
SCTRL
Stepping Control: This used control whether device does address data stepping. Devices that never stepping must clear this bit. Devices that always stepping must this bit. Devices that either, must make this read/write have initialize logic after RST#. Parity Error Response: This controls response device parity errors. When set, device must take normal action when parity error detected. When logic device sets Detected Parity Error status (bit Status register) when error detected, does assert PERR# continues normal operation. state this after RST# logic Devices that check parity must implement this bit. Devices required generate parity even parity checking disabled.
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Command register: description.continued Symbol VGAPS Description Palette Snoop: This controls compatible graphics devices handle accesses palette registers. When this logic palette snooping enabled (that device does respond palette register writes snoops data). When logic device should treat palette write accesses like other accesses. compatible devices should implement this bit. Memory Write Invalidate Enable: This enable using Memory Write Invalidate command. When this logic masters generate command. When logic Memory Writes must used instead. State after RST# logic This must implemented master devices that generate Memory Write Invalidate command. Special Cycles: Controls action device Special Cycle operations. value logic causes device ignore Special Cycle operations. value logic allows device monitor Special Cycle operations. State after RST# logic Master: Controls ability device master bus. value logic disables device from generating accesses. value logic allows device behave master. State after RST# logic Memory Space: Controls response device Memory Space accesses. value logic disables device response. value logic allows device respond Memory Space accesses. State after RST# logic Space: Controls response device Space accesses. value logic disables device response. value logic allows device respond Space accesses. State after RST# logic
Table
MWIE
Status register (address: 06H): Status register two-byte read-only register used record status information bus-related events (bit allocation: Table
Table Symbol Reset Access Symbol Reset Access Status register: allocation FBBC reserved 66MC reserved MDPE DEVSELT[1:0]
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Status register: description Symbol Description Detected Parity Error: This must device whenever detects parity error, even parity error handling disabled. Signaled System Error: This must whenever device asserts SERR#. Devices that never assert SERR# need implement this bit. Received Master Abort: This must master device whenever transaction (except Special Cycle) terminated with Master-Abort. master devices must implement this bit. Received Target Abort: This must master device whenever transaction terminated with Target-Abort. master devices must implement this bit. Signaled Target Abort: This must target device whenever terminates transaction with Target-Abort. Devices that never signal Target-Abort need implement this bit. DEVSEL Timing: These bits encode timing DEVSEL#. There three allowable timings assertion DEVSEL#: fast medium slow reserved These bits read-only must indicate slowest time that device asserts DEVSEL# command except Configuration Read Configuration Write.
Table
DEVSELT[1:0]
MDPE
Master Data Parity Error: This implemented masters. when following three conditions met:
FBBC
agent asserted PERR# itself read) observed PERR# asserted write). agent setting acted master operation which error occurred. Parity Error Response Command register) set.
Fast Back-to-Back Capable: This read-only indicates whether target capable accepting fast back-to-back transactions when transactions same agent. This logic device accept these transactions must logic otherwise. reserved
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Status register: description.continued Symbol 66MC Description Capable: This read-only indicates whether this device capable running MHz. value logic indicates MHz, value logic indicates MHz. Capabilities List: This read-only indicates whether this device implements pointer Capabilities linked list offset 34H. value logic indicates that Capabilities linked list available. value logic indicates that value read offset pointer Configuration Space linked list capabilities. reserved
Table
Revision register (address: 08H): This one-byte read-only register indicates device specific revision identifier. value chosen vendor. This field vendor defined extension Device Revision register description given Table
Table Revision register: description Symbol REVID[7:0] Access Value Description Revision This byte specifies design revision number functions.
Class Code register (address: 09H): Class Code 24-bit read-only register used identify generic function device, some cases, specific register-level programming interface. Table shows allocation register. Class Code register divided into three byte-size fields. upper byte base class code that broadly classifies type function device performs. middle byte sub-class code that identifies more specifically function device. lower byte identifies specific register-level programming interface, any, that device independent software interact with device.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access
OHCI1 OHCI2; EHCI.
Class Code register: allocation BCC[7:0] SCC[7:0] RLPI[7:0] X0H[1]
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Class Code register: description Symbol BCC[7:0] SCC[7:0] RLPI[7:0] Description Base Class Code: base class code assigned this byte, implies serial controller. Sub-Class Code: sub-class code assigned this byte, implies Host Controller. Register-Level Programming Interface: programming interface code assigned OHCI, which specification compliant. programming interface code assigned EHCI, which specification compliant.
Table
CacheLine Size register (address: 0CH): CacheLine Size register read/write single byte register that specifies system cacheline size units DWords. This register must implemented master devices that generate Memory Write Invalidate command. value this register also used master devices determine whether Read, Read Line, Read Multiple commands accessing memory. Slave devices that want allow memory bursting using cacheline-wrap addressing mode must implement this register know when burst sequence wraps beginning cacheline. This field must initialized logic activation RST#. Table shows description CacheLine Size register.
Table CacheLine Size register: description Symbol CLS[7:0] Access Value Description CacheLine Size: This byte identifies system cacheline size.
Latency Timer register (address: 0DH): This one-byte register specifies, units clocks, value Latency Timer master. Latency Time register description given Table This register must implemented writable master that burst more than data phases. This register implemented read-only devices that burst fewer data phases, fixed value must limited less. register must initialized logic RST#, programmable.
Table Latency Timer register: description Symbol LT[7:0] Access Value Description Latency Timer: This byte identifies latency timer.
Header Type register (address: 0EH): Header Type register identifies layout second part predefined header (beginning byte Configuration Space). also identifies whether device contains multiple functions (bit allocation: Table 15).
Table Symbol Reset Access
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Header Type register: allocation HT[6:0]
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Header Type register: description Symbol Description Multi-Function Device: This identifies multi-function device. logic then device single function. logic then device multiple functions. Header Type: These bits identify layout part predefined header beginning byte Configuration Space.
Table
HT[6:0]
BIST register (address: 0FH): This register used control status Built Self Test (BIST). Devices that support BIST must always return value logic (that treat reserved register). device whose BIST invoked must prevent normal operation bus. BIST register used ISP1561. Therefore, logic value returned always zero. Base Address registers: Power-up software needs build consistent address before booting machine operating system. This means determine much memory system, much address space controllers system require. After determining this information, power-up software controllers into reasonable locations proceed with system boot. this mapping device independent manner, base registers this mapping placed predefined header portion Configuration Space. Base Address registers read-only used determine whether register maps into Memory Space. Base Address registers that Memory Space must return logic Base Address registers that Space must return logic description register given Table Base Address register (BAR (address: 10H)
Table register: description Symbol 0[31:0] Access Value 0000 0000H Description Base Address Memory-Mapped Host Controller Register Space: memory size required OHCI EHCI bytes, respectively. Therefore, 0[31:12] assigned OHCI ports, 0[31:8] assigned EHCI port.
Base Address register (BAR (address: 14H, 18H, 1CH, 24H): register spaces used ISP1561. CardBus Pointer register (address: 28H): This four-byte register used devices that want share silicon between CardBus PCI. CardBus Pointer register used point Card Information Structure (CIS) CardBus card. This register implemented ISP1561. Subsystem Vendor register (address: 2CH): Subsystem Vendor register used uniquely identify expansion board subsystem where device resides. This register allows expansion board vendors further distinguish their boards, even though boards have same Vendor Device Subsystem Vendor assigned PCI-SIG maintain uniqueness. description Subsystem Vendor register given Table
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Table
Subsystem Vendor register: description Symbol SVID[15:0] Access Value 1131H Description Subsystem Vendor 1131H subsystem Vendor assigned Philips Semiconductors.
Subsystem register (address: 2EH): Subsystem values vendor specific. description Subsystem register given Table
Table Subsystem register: description Symbol SID[15:0] Access Value 156XH[1] Description Subsystem ISP1561, Philips Semiconductors defined OHCI functions 1561H, EHCI function 1562H.
OHCI1 OHCI2; EHCI.
Expansion Base Address register (address: 30H): Some devices, especially those intended expansion boards architecture, require local EPROMs expansion ROM. This four-byte register offset type predefined header defined handle base address size information this expansion ROM. ISP1561 does support expansion EPROM. Capabilities Pointer register (address: 34H): Capabilities Pointer register used point linked list capabilities implemented device. This register only valid Status register set. implemented, reserved should 00B. Software should mask these bits before using this register pointer Configuration Space first entry linked list capabilities. description register given Table
Table Capabilities Pointer register: description Symbol CP[7:0] Access Value Description Capabilities Pointer: EHCI manages power efficiently using this register. This Power Management register allocated offset DCH. Only Host Controller needed manage power ISP1561.
Interrupt Line register (address: 3CH): Interrupt Line register one-byte read/write register used communicate interrupt line routing information. This register must implemented device device function) that uses interrupt pin. interrupt allocation done BIOS. POST software needs write routing information into this register initializes configures system. description Interrupt Line register given Table value this register tells which input system interrupt controller(s) interrupt device connected device itself does this value, rather used device drivers operating systems. Device drivers operating systems this information determine priority vector information. Values this register system architecture specific.
Table Interrupt Line register: description Symbol IL[7:0] Access Value Description Interrupt Line: Indicates which used reporting interrupt from ISP1561.
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Interrupt register (address: 3DH): This one-byte register specify which interrupt device device function) uses. description given Table value corresponds INTA#. value corresponds INTB#. value corresponds INTC#. value corresponds INTD#. Devices functions that interrupt must logic this register.
Table Interrupt register: description Symbol IP[7:0] Access Value Description Interrupt Pin: INTA# default interrupt used ISP1561.
Minimum Grant Maximum Latency registers (address: 3FH): Min_Gnt Max_Lat registers used specify desired settings device Latency Timer values. both registers, value specifies period time units Values indicates that device major requirements settings Latency Timers.The Min_Gnt register description given Table
Table Min_Gnt register: description Symbol Access Value 0XH[1] Description Min_Gnt: used specify long burst period device needs assuming clock rate MHz. Min_Gnt[7:0]
OHCI1 OHCI2; EHCI.
Max_Lat register description given Table
Table Max_Lat register: description Symbol Access Value XXH[1] Description Max_Lat: used specify often device needs gain access bus. Max_Lat[7:0]
OHCI1 OHCI2; EHCI.
8.2.2
Enhanced Host Controller-specific registers addition configuration header registers, EHCI needs some additional configuration space registers indicate serial release number, downstream port wake-up event capability adjust frame length Start-of-Frame (SOF). EHCI-specific registers given Table
Table Offset 62-63H EHCI-specific registers Register Serial Release Number (SBRN) Frame Length Adjustment (FLADJ) Port Wake Capability (PORTWAKECAP)
SBRN register (address: 60H): SBRN register one-byte register, description given Table This register contains release number specification with which this Host Controller module complaint.
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Table
SBRN register: description Symbol Access Value Description Serial Specification Release Number: This register value identify Serial Specification Release 2.0. other combinations reserved. SBRN[7:0]
FLADJ register (address: 61H): This feature used adjust offset from clock source that generates clock that drives counter. When value written these bits, length frame adjusted. allocation register given Table
Table Symbol Reset Access FLADJ register: allocation reserved Table FLADJ[5:0]
FLADJ register: description Symbol Description reserved
FLADJ[5:0] Frame Length Timing Value: Each decimal value change this register corresponds high-speed times. cycle time (number counter clock periods generate microframe length) equal 59488 value this field. default value decimal (20H), which gives cycle time 60000. FLADJ Value (00H) (01H) (02H) 31(1FH) (20H) (3EH) (3FH) cycle time (480 MHz) 59488 59504 59520 59984 60000 60480 60496
PORTWAKECAP register (address: 62H): PORTWAKECAP register two-byte register, description given Table This register used establish policy about which ports used wake events. positions mask correspond physical port implemented current EHCI controller. logic position indicates that device connected below port enabled wake-up device port enabled disconnect/connect overcurrent events wake-up events. This information only mask register. bits this register affect actual operation
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EHCI Host Controller. system-specific policy established BIOS initializing this register system-specific value. System software uses information this register when enabling devices ports remote wake-up.
Table PORTWAKECAP register: description Symbol PORTWAKECAP[15:0] Access Value Description 001FH Port Wake Capability Mask: EHCI does implement this feature.
8.2.3
Power management registers
Table Offset value read from address value read from address value read from address value read from address value read from address value read from address Power Management registers Register Capability Identifier (Cap_ID) Next Item Pointer (Next_Item_Ptr) Power Management Capabilities (PMC) Power Management Control/Status (PMCSR) Power Management Control/Status (PMCSR_BSE) Data
Cap_ID register (address: value read from address 0H): Capability Identifier (Cap_ID) register, when read system software indicates that data structure currently being pointed Power Management data structure. Each function device have only item capability list with Cap_ID 01H. description register given Table
Table Cap_ID register: description Symbol Cap_ID[7:0] Access Value Description This field when identifies linked list item being Power Management registers.
Next_Item_Ptr register (address: value read from address 1H): Next Item Pointer (Next_Item_Ptr) register (see Table describes location next item function's capability list. value given offset into function's Configuration Space. function does implement other capabilities defined PCI-SIG inclusion capabilities list, power management last item list, then this register must 00H.
Table Next_Item_Ptr register: description Symbol Next_Item_Ptr[7:0] Access Value Description Next Item Pointer: This field provides offset into function's Configuration Space pointing location next item function's capability list. there additional items Capabilities List, this register 00H.
register (address: value read from address 2H): Power Management Capabilities (PMC) register two-byte register, allocation given Table This read-only register provides information capabilities function related power management.
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Table Symbol Reset Access Symbol Reset Access
register: allocation X[1] AUX_C[2:0] PME_S[4:0] X[2] reserved X[2] D2_S X[2] D1_S VER[2:0] AUX_C[2:0] X[2]
OHCI1, OHCI2 EHCI EHCI OHCI1 OHCI2; EHCI.
Table
register: description Symbol PME_S[4:0] Description PME_Support: This 5-bit field indicates power states which function assert PME#. value indicates that function capable asserting PME# signal while that power state. PME_S[0] PME# asserted from PME_S[1] PME# asserted from PME_S[2] PME# asserted from PME_S[3] PME# asserted from D3hot PME_S[4] PME# asserted from D3cold
D2_S
D2_Support: this logic this function supports Power Management State. Functions that support must always return value logic this bit. D1_Support: this logic this function supports Power Management State. Functions that support must always return value logic this bit.
D1_S
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register: description.continued Symbol AUX_C[2:0] Description Aux_Current: This three-bit field reports VAUX auxiliary current requirements function. Data register been implemented this function:
Table
read from this field needs return value 000B. Data register takes precedence over this field VAUX current requirement reporting.
PME# generation from D3cold supported function (PMC(15) this field must return value 000B when read. functions that support PME# from D3cold implement Data register, assignments correspond maximum current required VAUX are: (self powered) Device Specific Initialization: This indicates whether special initialization this function required, beyond standard configuration header, before generic class device driver able Remark: This used some operating systems. example, Microsoft Windows Windows this determine whether Instead, they capabilities driver determine this. Logic indicates that function requires device specific initialization sequence following transition un-initialized state. reserved Clock: When this logic indicates that function relies presence clock PME# operation. When this logic indicates that clock required function generate PME#. Functions that support PME# generation state must return logic this field. Version: value 010B indicates that this function complies with Power Management Interface Specification Rev. 1.1.
VER[2:0]
logic level AMB4 power-on determines default value registers. this connected pull-up, then ISP1561 supports D3cold case notebook design). this left open pulled down, then ISP1561 does support D3cold case add-on card design).
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PMCSR register (address: value read from address 4H): Power Management Control/Status (PMCSR) register two-byte register used manage power management state function well enable monitor Power Management Events (PMEs). allocation register given Table
Table Symbol Reset Access Symbol Reset Access
PMCSR register: allocation PMES X[1] DS[1:0] reserved D_S[3:0] PS[1:0] PMEE X[1]
Sticky bit, function supports PME# from D3cold then indeterminate time initial operating system boot; function does support PME# from D3cold.
Table
PMCSR register: description Symbol PMES Description Status: This when function would normally assert PME# signal independent state PME_EN bit. Writing logic this clears causes function stop asserting PME# enabled). Writing logic effect. This defaults logic function does support PME# generation from D3cold. function supports PME# generation from D3cold, then this sticky must explicitly cleared operating system each time operating system initially loaded. Data Scale: This two-bit read-only field indicates scaling factor used when interpreting value Data register. value meaning this field vary depending which data value been selected field. This field required component Data register (offset must implemented Data register implemented. Data register been implemented, this field must return when PMCSR read. Data_Select: This four-bit field used select which data reported through Data register field. This field required component Data register (offset must implemented Data register implemented. Data register been implemented, this field must return when PMCSR read.
DS[1:0]
D_S[3:0]
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PMCSR register: description.continued Symbol PMEE Description Enabled: Logic enables function assert PME#. When logic PME# assertion disabled. This defaults logic function does support PME# generation from D3cold. function supports PME# from D3cold, then this sticky must explicitly cleared operating system each time operating system initially loaded. Functions that support PME# generation from D-state (that PMC[15:11] 00000B), hardwire this read-only always returning logic when read system software. reserved Power State: This two-bit field used determine current power state EHCI function function into power state. definition field values given D3hot software attempts write unsupported, optional state this field, write operation must complete normally bus; however, data discarded status change occurs.
Table
PS[1:0]
PMCSR_BSE register (address: value read from address 6H): PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports bridge specific functionality required PCI-to-PCI bridges. allocation this register given Table
Table Symbol Reset Access
PMCSR_BSE register: allocation BPCC_En 0[1] B2_B3# 0[1] reserved
Internally hardwired.
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PMCSR_BSE register: description Symbol BPCC_En Description Power/Clock Control Enable Indicates that power/clock control mechanism defined Table enabled. Indicates that bus/power control policies defined Table have been disabled. When Power/Clock Control mechanism disabled, bridge's PMCSR (Power State) field cannot used system software control power clock bridge's secondary bus.
Table
B2_B3#
B2/B3 support D3hot: state this determines action that occur direct result programming function D3hot. Indicates that when bridge function programmed D3hot, secondary bus's clock will stopped (B2). Indicates that when bridge function programmed D3hot, secondary will have power removed (B3). This only meaningful (BPCC_En) logic
Table
reserved
power clock control Secondary state Resultant actions bridge (either direct indirect) none none clock stopped secondary clock stopped removed from secondary only). definition B2_B3#, Table none
Originating device's bridge state D3hot
D3cold
Data register (address: value read from address 7H): Data register optional, 1-byte register that provides mechanism function report state dependent operating data, such power consumed heat dissipation. Table shows description register.
Table Data register: description Symbol DATA[7:0] Access Value Description DATA: This register used report state dependent data requested (Data_Select) field. value this register scaled value reported (Data_Scale) field.
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I2C-bus interface
simple I2C-bus interface provided ISP1561 read customized vendor product some other configuration bits from external EEPROM. I2C-bus interface intended bidirectional communication between serial wires, (data) (clock). Both lines driven open-drain circuits must connected positive supply voltage pull-up resistors.
Protocol
I2C-bus protocol defines following conditions:
free: both HIGH START: HIGH-to-LOW transition SDA, while HIGH STOP: LOW-to-HIGH transition SDA, while HIGH Data valid: after START condition, data stable during HIGH period SCL; data only change while LOW.
Each device I2C-bus unique slave address, which master uses select device access. master starts data transfer using START condition ends generating STOP condition. Transfers only initiated when free. receiver must acknowledge each byte means level during ninth clock pulse SCL. detailed information please consult I2C-bus it., order number 9398 40011.
Hardware connections
I2C-bus interface ISP1561 connected external EEPROM. hardware connections shown Figure
I2C-bus
24C01 ISP1561
HOST EEPROM equivalent
004aaa163
EEPROM connection diagram.
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slave address which ISP1561 uses access EEPROM 1010000B. Page mode addressing supported, pins EEPROM must connected ground (logic
Information loading from EEPROM
Figure shows content EEPROM memory. EEPROM present, default values Device (DID), Vendor (VID), subsystem subsystem assigned Philips Semiconductors PCI-SIG will loaded. Table these default value. instructions programming EEPROM, refer Designing Host Adapter Using ISP1561 Application Note ISP1561 Evaluation Board User's Guide.
Address
Subsystem Vendor Subsystem Vendor
Subsystem Device OHCI
Subsystem Device OHCI
Subsystem Device EHCI
Subsystem Device EHCI
Reserved Loads Subsystem Vendor Device Loads default values defined Philips Semiconductors
004aaa124
Signature
LOW; HIGH.
Information loading from EEPROM.
Power management
10.1 power states
characterized four power management states- state (PCI clock MHz, power This corresponds being fully operational. state (PCI clock intermittent clock operation mode, power When still applied devices bus. However, transactions allowed take place bus. state indicates perpetual idle state bus. state (PCI clock Stop, power still applied bus, clock stopped held state.
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state (PCI clock Stop, power OFF) been removed from devices segment.
10.2 states
Reset state When reset state, system stopped. Operational state When active state, system operating normally. Suspend state When suspend state, system stopped. Resume state When resume state, system operating normally.
Host Controller registers
Each Host Controller contains on-chip operational registers that mapped into non-cache memory system addressable space. This memory space must begin DWord (32-bit) boundary. size allocated space defined initial value register. Host Controller drivers need interact with these registers implement legacy support functionality. After enumeration driver finishes device configuration, base address these memory-mapped operational registers defined Host Controller Driver (HCD) access these registers using address base address value offset. Table contains list Host Controller registers.
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Table Address (Hex) FF-60
Host Controller registers OHCI Register Func0 OHCI1 (2P) HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] Reserved Reserved HceControl 00000110 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00002EDF 00000000 00000000 00000000 00000628 FF000902 00000000 00000000 00000000 00000000 00000000 Func0 OHCI1 (1P) 00000110 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00002EDF 00000000 00000000 00000000 00000628 FF000901 00000000 00000000 00000000 00000000 Reset Value[1] Func1 OHCI2 (2P) 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00002EDF 00000000 00000000 00000000 00000628 FF000902 00000000 00000000 00000000 00000000 00000000 Func1 OHCI2 (1P) 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00002EDF 00000000 00000000 00000000 00000628 FF000901 00000000 00000000 00000000 00000000 Func2 EHCI (4P) 0095000C 00002214 00000012 00080000 00001000 00000000 00000000 00000000 00000000 00000000 00000000 00002000 00002000 00002000 00002000 Func2 EHCI (2P) 0095000C 00002214 00000012 00080000 00001000 00000000 00000000 00000000 00000000 00000000 00000000 00002000 00002000 CAPLENGTH/ HCIVERSION HCSPARAMS HCCPARAMS USBCMD USBSTS USBINTR FRINDEX CTRLDSSEGMENT PERIODICLISTBASE ASYNCLISTADDR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CONFIGFLAG PORTSC1 EHCI Register
host controller
PORTSC2 PORTSC3 PORTSC4
ISP1561
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Table Address (Hex)
Host Controller registers.continued OHCI Register Func0 OHCI1 (2P) HceInput HceOutput HceStatus 00000000 00000000 00000000 Func0 OHCI1 (1P) 00000000 00000000 00000000 Reset Value[1] Func1 OHCI2 (2P) 00000000 00000000 00000000 Func1 OHCI2 (1P) 00000000 00000000 00000000 Func2 EHCI (4P) Func2 EHCI (2P) EHCI Register
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Reset values that highlighted (for example, ISP1561 implementation specific reset values, reset values that highlighted (for example, complaint with OHCI EHCI specification.
host controller
ISP1561
Philips Semiconductors
ISP1561
host controller
OHCI Host Controller, these registers divided into types: operational registers operation legacy support registers legacy keyboard mouse operation. Enhanced Host Controller, there types registers: read-only capability registers read/write operational registers.
11.1 OHCI Host Controller operational registers
OHCI Host Controller Drivers (HCDs) need communicate with these registers implement data transfers. Based their functions, these registers classified into four partitions:
11.1.1
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
Control Status Memory Pointer Frame Counter Root Hub.
HcRevision register (address: value read from func0 func1 address 00H)
HcRevision register: allocation reserved reserved reserved REV[7:0] X[1]
OHCI1 (2P) OHCI1 (1P); OHCI2 (2P) OHCI2 (1P).
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HcRevision register: description Symbol Description reserved Legacy: does support legacy devices supports legacy keyboard mouse
Table
REV[7:0]
Revision: This read-only field contains representation version specification that implemented this Host Controller. example, value corresponds version 1.1. Host Controller implementations that compliant with this specification need have value 10H.
11.1.2
HcControl register (address: value read from func0 func1 address 04H) HcControl register defines operating modes Host Controller. fields this register, except HostControllerFunctionalState (HCFS) RemoteWakeupConnected (RWC), modified only HCD. allocation given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcControl register: allocation HCFS[1:0] reserved reserved reserved CBSR[1:0]
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HcControl register: description Symbol Description reserved RemoteWakeupEnable: This used enable disable remote wake-up feature upon detection upstream resume signaling. When this HcInterruptStatus set, remote wake-up signaled host system. Setting this impact generation hardware interrupt. RemoteWakeupConnected: This indicates whether Host Controller supports remote wake-up signaling. remote wake-up supported used system, responsibility system firmware this during POST. Host Controller clears upon hardware reset does alter upon software reset. Remote wake-up signaling host system host-bus-specific described this specification. InterruptRouting: This determines routing interrupts generated events registered HcInterruptStatus. clear, interrupts routed normal host interrupt mechanism. set, interrupts routed System Management Interrupt. clears this upon hardware reset, does alter this upon software reset. uses this indicate ownership Host Controller.
Table
HCFS[1:0] HostControllerFunctionalState USB: USBRESET USBRESUME USBOPERATIONAL USBSUSPEND transition USBOPERATIONAL from another state causes generation begin later. determine whether Host Controller begun sending SOFs reading field HcInterruptStatus. This field changed Host Controller only when USBSUSPEND state. Host Controller move from USBSUSPEND state USBRESUME state after detecting resume signaling from downstream port. Host Controller enters USBSUSPEND after software reset; enters USBRESET after hardware reset. latter also resets Root asserts subsequent reset signaling downstream ports.
BulkListEnable: This enable processing Bulk list next Frame. cleared HCD, processing Bulk list does occur after next SOF. Host Controller checks this whenever wants process list. When disabled, modify list. HcBulkCurrentED pointing Endpoint Descriptor (ED) removed, must advance pointer updating HcBulkCurrentED before re-enabling processing list.
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HcControl register: description.continued Symbol Description ControlListEnable: This enable processing Control list next Frame. cleared HCD, processing Control list does occur after next SOF. Host Controller must check this whenever wants process list. When disabled, modify list. HcControlCurrentED pointing removed, must advance pointer updating HcControlCurrentED before re-enabling processing list. IsochronousEnable: This used enable disable processing isochronous EDs. While processing periodic list frame, Host Controller checks status this when finds Isochronous (enabled), Host Controller continues processing EDs. cleared (disabled), Host Controller halts processing periodic list (which contains only isochronous EDs) begins processing Bulk/Control lists. Setting this guaranteed take effect next Frame (not current Frame). PeriodicListEnable: This enable processing periodic list next Frame. cleared HCD, processing periodic list does occur after next SOF. Host Controller must check this before starts processing list.
Table
CBSR[1:0] ControlBulkServiceRatio: This specifies service ratio Control over Bulk EDs. Before processing non-periodic lists, Host Controller must compare ratio specified with internal count many non-empty Control have been processed, determining whether continue serving another Control switching Bulk EDs. internal count needs retained when crossing frame boundary. After reset, responsible restoring this value.
11.1.3
HcCommandStatus register (address: value read from func0 func1 address 08H) HcCommandStatus register used Host Controller receive commands issued HCD, also reflects current status Host Controller. HCD, appears "write set" register. Host Controller must ensure that bits written logic become register while bits written logic remain unchanged register. issue multiple distinct commands Host Controller without concern corrupting previously issued commands. normal read access bits. SOC[1:0] (SchedulingOverrunCount) field indicates number frames with which Host Controller detected scheduling overrun error. This occurs when Periodic list does complete before EOF. When scheduling overrun
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error detected, Host Controller increments counter sets (SchedulingOverrun) field HcInterruptStatus register. Table shows allocation HcCommandStatus register.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access Table reserved reserved reserved HcCommandStatus register: allocation reserved SOC[1:0]
HcCommandStatus register: description Symbol SOC[1:0] Description reserved SchedulingOverrunCount: incremented each scheduling overrun error. initialized wraps around 11B. needs incremented when scheduling overrun detected even HcInterruptStatus already been set. This used monitor persistent scheduling problems. reserved OwnershipChangeRequest: This request change control Host Controller. When set, Host Controller needs (OwnershipChange) field HcInterruptStatus. After changeover, this cleared remains until next request from HCD.
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HcCommandStatus register: description.continued Symbol Description BulkListFilled: This used indicate whether there Transfer Descriptors (TDs) Bulk list. whenever adds Bulk list. When Host Controller begins process head Bulk list, checks bulk-filled (BF). (BulkListFilled) logic Host Controller does need process Bulk list. logic Host Controller needs start processing Bulk list logic Host Controller finds list, then Host Controller needs logic causing Bulk list processing continue. found Bulk list, does BLF, then still logic when Host Controller completes processing Bulk list Bulk list processing stops. ControlListFilled: This used indicate whether there Control list. whenever adds Control list. When Host Controller begins process head Control list, checks ControlListFilled (CLF). logic Host Controller does need process Control list. control-filled (CF) logic Host Controller needs start processing Control list logic Host Controller finds list, then Host Controller needs logic causing Control list processing continue. found Control list, does CLF, then still logic when Host Controller completes processing Control list Control list processing stops.
Table
HostControllerReset: This initiate software reset Host Controller. Regardless functional state Host Controller, moves USBSUSPEND state which most operational registers reset except those stated otherwise; example, (InterruptRouting) field HcControl, Host accesses allowed. This cleared Host Controller upon completion reset operation. reset operation must completed within This bit, when set, should cause reset Root subsequent reset signaling should asserted downstream ports.
11.1.4
HcInterruptStatus register (address: value read from func0 func1 address 0CH) This register four-byte register that provides status events that cause hardware interrupts. allocation register given Table When event occurs, Host Controller sets corresponding this register. When becomes set, hardware interrupt generated interrupt enabled HcInterruptEnable register (see Table (MasterInterruptEnable) set. clear specific bits this register writing logic positions cleared. these bits. Host Controller does clear bit.
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Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcInterruptStatus register: allocation reserved reserved RHSC Table reserved reserved reserved
HcInterruptStatus register: description Symbol Description reserved OwnershipChange: This Host Controller when sets (OwnershipChangeRequest) field HcCommandStatus. This event, when unmasked, will always generate System Management Interrupt (SMI) immediately. This forced when SMI# implemented. reserved RootHubStatusChange: This when content HcRhStatus content changed. FrameNumberOverflow: This when HcFmNumber (bit changes value, after HccaFrameNumber been updated. UnrecoverableError: This when Host Controller detects system error related USB. Host Controller should proceed with processing signaling before system error been corrected. clears this after Host Controller been reset. ResumeDetected: This when Host Controller detects that device asserting resume signaling. transition from resume signaling resume signaling causing this set. This when sets USBRESUME state.
RHSC
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HcInterruptStatus register: description.continued Symbol Description StartOfFrame: start each frame, this Host Controller token generated same time. WritebackDoneHead: This immediately after Host Controller written HcDoneHead HccaDoneHead. Further, updates HccaDoneHead occur only after this been cleared. should only clear this after saved content HccaDoneHead. SchedulingOverrun: This when schedules current Frame overruns after update HccaFrameNumber. scheduling overrun causes (SchedulingOverrunCount) HcCommandStatus incremented.
Table
11.1.5
HcInterruptEnable register (address: value read from func0 func1 address 10H) Each enable HcInterruptEnable register corresponds associated interrupt HcInterruptStatus register. HcInterruptEnable register used control which events generate hardware interrupt. following conditions occur:
HcInterruptStatus register. corresponding HcInterruptEnable register set. (MasterInterruptEnable) set.
Then, hardware interrupt requested host bus. Writing logic this register sets corresponding bit, whereas writing logic this register leaves corresponding unchanged. read, current value this register returned. allocation given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access reserved HcInterruptEnable register: allocation reserved reserved
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Symbol Reset Access
reserved
RHSC Table
HcInterruptEnable register: description Symbol Description MasterInterruptEnable: Logic ignored Host Controller. Logic enables interrupt generation events specified other bits this register. ignore enable interrupt generation Ownership Change reserved ignore enable interrupt generation Root Status Change ignore enable interrupt generation Frame Number Overflow ignore enable interrupt generation Unrecoverable Error ignore enable interrupt generation Resume Detect ignore enable interrupt generation Start-of-Frame ignore enable interrupt generation HcDoneHead Writeback ignore enable interrupt generation Scheduling Overrun
RHSC
11.1.6
HcInterruptDisable register (address: value read from func0 func1 address 14H) Each disable HcInterruptDisable register corresponds associated interrupt HcInterruptStatus register. HcInterruptDisable register coupled with HcInterruptEnable register. Therefore, writing logic this register clears corresponding HcInterruptEnable register, whereas writing logic this register leaves corresponding HcInterruptEnable register unchanged. read, current value HcInterruptEnable register returned. register contains four bytes, allocation given Table
Table Symbol Reset Access
HcInterruptDisable register: allocation reserved
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reserved reserved
Symbol Reset Access Symbol Reset Access Symbol Reset Access
reserved
RHSC Table
HcInterruptDisable register: description Symbol Description MasterInterruptEnable: Logic ignored Host Controller. Logic disables interrupt generation events specified other bits this register. This field after hardware software reset. (Interrupts disabled). ignore disable interrupt generation Ownership Change reserved ignore disable interrupt generation Root Status Change ignore disable interrupt generation Frame Number Overflow ignore disable interrupt generation Unrecoverable Error ignore disable interrupt generation Resume Detect ignore disable interrupt generation Start-of-Frame ignore disable interrupt generation HcDoneHead Writeback ignore disable interrupt generation Scheduling Overrun
RHSC
11.1.7
HcHCCA register (address: value read from func0 func1 address 18H) HcHCCA register contains physical address Host Controller Communication Area (HCCA). allocation given Table determines alignment restrictions writing HcHCCA reading content HcHCCA. alignment evaluated examining number zeroes
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lower order bits. minimum alignment bytes; therefore, bits through will always return logic when read. This area used hold control structures Interrupt table that accessed both Host Controller HCD.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access Table reserved HCCA[7:0] HcHCCA register: allocation HCCA[23:16]
HCCA[15:8]
HcHCCA register: description Symbol HCCA[23:0] Description Host Controller Communication Area Base Address: This base address HCCA. reserved
11.1.8
HcPeriodCurrentED register (address: value read from func0 func1 address 1CH) HcPeriodCurrentED register contains physical address current Isochronous Interrupt Table gives allocation register.
Table Symbol Reset Access Symbol Reset Access
HcPeriodicCurrentED register: allocation PCED[27:20]
PCED[19:12]
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PCED[3:0] reserved
Symbol Reset Access Symbol Reset Access
Table
PCED[11:4]
HcPeriodCurrentED register: description Symbol Description PCED[27:0] PeriodCurrentED: This used Host Controller point head Periodic lists that needs processed current Frame. content this register updated Host Controller after periodic been processed. read content determining which currently being processed time reading. reserved
11.1.9
HcControlHeadED register (address: value read from func0 func1 address 20H) HcControlHeadED register contains physical address first Control list. allocation given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcControlHeadED register: allocation CHED[3:0] CHED[11:4] reserved CHED[27:20]
CHED[19:12]
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HcControlHeadED register: description Symbol CHED[27:0] Description ControlHeadED: Host Controller traverses Control list starting with HcControlHeadED pointer. content loaded from HCCA during initialization Host Controller. reserved
Table
11.1.10
HcControlCurrentED register (address: value read from func0 func1 address 24H) HcControlCurrentED register contains physical address current Control list. allocation given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcControlCurrentED register: allocation CCED[3:0] Table CCED[11:4] reserved CCED[27:20]
CCED[19:12]
HcControlCurrentED register: description Symbol CCED[27:0] Description ControlCurrentED: This pointer advanced next after serving present one. Host Controller needs continue processing list from where left last frame. When reaches Control list, Host Controller checks (ControlListFilled) HcCommandStatus. set, copies content HcControlHeadED HcControlCurrentED clears bit. set, does nothing. allowed modify this register only when (ControlListEnable) HcControl cleared. When set, only reads instantaneous value this register. Initially, this logic indicate Control list. reserved
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11.1.11
HcBulkHeadED register (address: value read from func0 func1 address 28H) This four-byte register, allocation given Table register contains physical address first Bulk list.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcBulkHeadED register: allocation BHED[3:0] Table reserved BHED[27:20]
BHED[19:12]
BHED[11:4]
HcBulkHeadED register: description Symbol BHED[27:0] Description BulkHeadED: Host Controller traverses Bulk list starting with HcBulkHeadED pointer. content loaded from HCCA during initialization Host Controller. reserved
11.1.12
HcBulkCurrentED register (address: value read from func0 func1 address 2CH) This register contains physical address current endpoint Bulk list. Bulk list needs served round-robin fashion, endpoints ordered according their insertion list. allocation given Table
Table Symbol Reset Access Symbol Reset Access
HcBulkCurrentED register: allocation BCED[27:20]
BCED[19:12]
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BCED[3:0] reserved
Symbol Reset Access Symbol Reset Access
Table
BCED[11:4]
HcBulkCurrentED register: description Symbol BCED[27:0] Description BulkCurrentED: This advanced next after Host Controller served present one. Host Controller continues processing list from where left last frame. When reaches Bulk list, Host Controller checks (ControlListFilled) HcControl. set, nothing done. set, copies content HcBulkHeadED HcBulkCurrentED clears bit. only modify this register when (BulkListEnable) HcControl cleared. When HcControl set, reads instantaneous value this register. This initially indicate Bulk list. reserved
11.1.13
HcDoneHead register (address: value read from func0 func1 address 30H) HcDoneHead register contains physical address last completed that added Done queue. normal operation, does need read this register content periodically written HCCA. Table contains allocation register.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcDoneHead register: allocation DH[27:20] DH[19:12] DH[11:4]
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DH[3:0] reserved
Symbol Reset Access
Table
HcDoneHead register: description Symbol DH[27:0] Description DoneHead: When completed, Host Controller writes content HcDoneHead NextTD field Host Controller then overwrites content HcDoneHead with address this This logic whenever Host Controller writes content this register HCCA. reserved
11.1.14
HcFmInterval register (address: value read from func0 func1 address 34H) HcFmInterval register contains 14-bit value that indicates time interval frame, (that between consecutive SOFs) 15-bit value indicating full-speed maximum packet size that Host Controller transmit receive without causing scheduling overrun. carry minor adjustment (FrameInterval) writing value over present each SOF. This provides possibility Host Controller synchronize with external clocking resource adjust unknown local clock offset. allocation register given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcFmInterval register: allocation reserved FI[7:0] FSMPS[14:8] FI[13:8]
FSMPS[7:0]
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HcFmInterval register: description Symbol FSMPS[14:0] Description FrameIntervalToggle: toggles this whenever loads value FrameInterval. FSLargestDataPacket: This field specifies value that loaded into Largest Data Packet Counter beginning each frame. counter value represents largest amount data bits that sent received Host Controller single transaction given time without causing scheduling overrun. field value calculated HCD. reserved FrameInterval: This specifies interval between consecutive SOFs times. nominal value 11,999. should store current value this field before resetting Host Controller because this causes field reset nominal value. then restore stored value upon completion reset sequence.
Table
FI[13:0]
11.1.15
HcFmRemaining register (address: value read from func0 func1 address 38H) HcFmRemaining register 14-bit down counter showing time remaining current Frame. Table contains allocation this four-byte register.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcFmRemaining register: allocation reserved FR[7:0] reserved FR[13:8] reserved
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HcFmRemaining register: description Symbol Description FrameRemainingToggle: This loaded from (FrameIntervalToggle) field HcFmInterval whenever (FrameRemaining) reaches This used synchronization between (FrameInterval) reserved FrameRemaining: This counter decremented each time. When reaches reset loading value specified HcFmInterval next time boundary. When entering USBOPERATIONAL state, Host Controller re-loads content with HcFmInterval uses updated value from next SOF.
Table
FR[13:0]
11.1.16
HcFmNumber register (address: value read from func0 func1 address 3CH) This register 16-bit counter, allocation given Table provides timing reference among events happening Host Controller HCD. 16-bit value specified this register generate 32-bit frame number without requiring frequent access register.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcFmNumber register: allocation reserved FN[7:0] reserved reserved FN[13:8]
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HcFmNumber register: description Symbol FN[13:0] Description reserved FrameNumber: This incremented when HcFmRemaining re-loaded. needs rolled over after FFFFH. When entering USBOPERATIONAL state, this incremented automatically. content written HCCA after Host Controller incremented FrameNumber each frame boundary sent before Host Controller reads first that frame. After writing HCCA, Host Controller sets (StartofFrame) HcInterruptStatus.
Table
11.1.17
HcPeriodicStart register (address: value read from func0 func1 address 40H) HcPeriodicStart register 14-bit programmable value that determines when earliest time Host Controller should start processing periodic list. allocation given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcPeriodicStart register: allocation reserved Table P_S[7:0] reserved reserved P_S[13:8]
HcPeriodicStart register: description Symbol P_S[13:0] Description reserved PeriodicStart: After hardware reset, this field cleared. This then during Host Controller initialization. value calculated roughly HcFmInterval. typical value 3E67H. When HcFmRemaining reaches value specified, processing periodic lists have priority over Control/Bulk processing. Host Controller, therefore, starts processing Interrupt list after completing current Control Bulk transaction that progress.
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11.1.18
HcLSThreshold register (address: value read from func0 func1 address 44H) This register contains 11-bit value used Host Controller determine whether commit transfer maximum 8-byte packet before EOF. Neither Host Controller allowed change this value. allocation HcLSThreshold register given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcLSThreshold register: allocation reserved Table LST[7:0] reserved reserved LST[11:8]
HcLSThreshold register: description Symbol LST[11:0] Description reserved LSThreshold: This field contains value that compared (FrameRemaining) field prior initiating low-speed transaction. transaction started only this field. value calculated with consideration transmission setup overhead.
11.1.19
HcRhDescriptorA register (address: value read from func0 func1 address 48H) HcRhDescriptorA register first registers describing characteristics Root Hub. Reset values implementation-specific. descriptor length (11), descriptor type (TBD) controller current fields Class Descriptor emulated HCD. other fields located HcRhDescriptorA HcRhDescriptorB registers. Table contains allocation HcRhDescriptorA register.
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Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcRhDescriptorA register: allocation reserved reserved NOCP NDP[7:0] X[1] X[2] OCPM POTPGT[7:0]
OHCI1 (2P) OHCI2 (2P); OHCI1 (1P) OHCI2 (1P). OHCI1 (2P) OHCI2 (2P); OHCI1 (1P) OHCI2 (1P).
Table
HcRhDescriptorA register: description Symbol POTPGT[7:0] Description PowerOnToPowerGoodTime: This byte specifies duration wait before accessing powered-on port Root Hub. implementation-specific. unit time duration calculated POTPGT reserved NoOverCurrentProtection: This describes overcurrent status Root ports reported. When this cleared, OCPM (OverCurrentProtectionMode) field specifies global per-port reporting. overcurrent status reported collectively downstream ports overcurrent protection supported
NOCP
OCPM
OverCurrentProtectionMode: This describes overcurrent status Root ports reported. reset, this fields reflects same mode PowerSwitchingMode. This field valid only NOCP field cleared. overcurrent status reported collectively downstream ports overcurrent status reported per-port basis
DeviceType: This specifies that Root compound device. Root permitted compound device. This field should always read
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HcRhDescriptorA register: description.continued Symbol Description NoPowerSwitching: This used specify whether power switching supported ports always powered. implementation-specific. When this cleared, (PowerSwitchingMode) field specifies global per-port switching. ports power switched ports always powered when Host Controller powered
Table
PowerSwitchingMode: This used specify power switching Root ports controlled. implementation-specific. This field only valid field cleared. ports powered same time. each port powered individually. This mode allows port power controlled either global switch per-port switching. PPCM (PortPowerControlMask) set, port responds only port power commands (Set/ClearPortPower). port mask cleared, then port controlled only global power switch (Set/ClearGlobalPower).
NDP[7:0]
NumberDownstreamPorts: These bits specify number downstream ports supported Root Hub. implementation-specific. minimum number ports maximum number ports supported OHCI
11.1.20
HcRhDescriptorB register (address: value read from func0 func1 address 4CH) HcRhDescriptorB register second registers describing characteristics Root Hub. allocation given Table These fields written during initialization correspond with system implementation. Reset values implementation-specific.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcRhDescriptorB register: allocation PPCM[7:0] DR[15:8] PPCM[15:0]
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DR[7:0]
Symbol Reset Access
Table
HcRhDescriptorB register: description Symbol PPCM[15:0] Description PortPowerControlMask: Each indicates whether port affected global power control command when PowerSwitchingMode set. When set, power state port only affected per-port power control (Set/ClearPortPower). When cleared, port controlled global power switch (Set/ClearGlobalPower). device configured global switching mode (PowerSwitchingMode this field valid. reserved Ganged-power mask Port Ganged-power mask Port
DR[15:0]
DeviceRemovable: Each dedicated port Root Hub. When cleared, attached device removable. When set, attached device removable. reserved Device attached Port Device attached Port
11.1.21
HcRhStatus register (address: value read from func0 func1 address 50H) HcRhStatus register divided into parts. lower word DWord represents Status field upper word represents Status Change field. Reserved bits should always written logic Table contains allocation register.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcRhStatus register: allocation CRWE DRWE reserved reserved reserved CCIC LPSC
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reserved
Symbol Reset Access
Table
HcRhStatus register: description Symbol CRWE Description write-ClearRemoteWakeupEnable: Writing logic clears DRWE (DeviceRemoteWakeupEnable). Writing logic effect. reserved OverCurrentIndicatorChange: This hardware when change occurred (OverCurrentIndicator) field this register. clears this writing logic Writing logic effect. read-LocalPowerStatusChange: Root does support local power status feature. Therefore, this always logic write-SetGlobalPower: global power mode (PowerSwitchingMode this written logic1 turn power ports (clear PortPowerStatus). per-port power mode, sets PortPowerStatus only ports whose PortPowerControlMask set. Writing logic effect.
CCIC
LPSC
DRWE
read-DeviceRemoteWakeupEnable: This enables ConnectStatusChange resume event, causing state transition USBSUSPEND USBRESUME setting ResumeDetected interrupt. ConnectStatusChange remote wake-up event ConnectStatusChange remote wake-up event write-SetRemoteWakeupEnable: Writing logic sets DRWE (DeviceRemoteWakeupEnable). Writing logic effect.
reserved OverCurrentIndicator: This reports overcurrent conditions when global reporting implemented. When set, overcurrent condition exists. When clear, power operations normal. per-port overcurrent protection implemented, this always logic read-LocalPowerStatus: Root does support local power status feature. Therefore, this always read logic write-ClearGlobalPower: global power mode (PowerSwitchingMode this written logic turn power ports (clear PortPowerStatus). per-port power mode, clears PortPowerStatus only ports whose PortPowerControlMask set. Writing logic effect.
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11.1.22
HcRhPortStatus[1:4] register (address: value read from func0 func1 address 54H) HcRhPortStatus[1:4] register used control report port events per-port basis. NumberDownstreamPorts represents number HcRhPortStatus registers that implemented hardware. lower word used reflect port status, whereas upper word reflects status change bits. Some status bits implemented with special write behavior. transaction (token through handshake) progress when write change port status occurs, resulting port status change postponed until transaction completes. Reserved bits should always written logic allocation register given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HcRhPortStatus[1:4] register: allocation reserved reserved Table reserved POCI reserved PRSC OCIC PSSC PESC LSDA
HCRhPortStatus[1:4] register: description Symbol PRSC Description reserved PortResetStatusChange: This port reset signal. write logic clear this bit. Writing logic effect. port reset complete port reset complete
OCIC
PortOverCurrentIndicatorChange: This valid only overcurrent conditions reported per-port basis. This when Root changes POCI (PortOverCurrentIndicator) bit. write logic clear this bit. Writing logic effect. change PortOverCurrentIndicator POCI changed
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HCRhPortStatus[1:4] register: description.continued Symbol PSSC Description PortSuspendStatusChange: This when full resume sequence been completed. This sequence includes resume pulse, re-synchronization delay. write logic clear this bit. Writing logic effect. This also cleared when ResetStatusChange set. resume completed resume completed
Table
PESC
PortEnableStatusChange: This when hardware events cause (PortEnableStatus) cleared. Changes from writes this bit. write logic clear this bit. Writing logic effect. change change
ConnectStatusChange: This whenever connect disconnect event occurs. write logic clear this bit. Writing logic effect. (CurrentConnectStatus) cleared when SetPortReset, SetPortEnable SetPortSuspend write occurs, this force driver re-evaluate connection status because these writes should occur port disconnected. change change Remark: DeviceRemovable[NDP] set, this only after Root reset inform system that device attached.
LSDA
reserved read-LowSpeedDeviceAttached: This indicates speed device attached this port. When set, low-speed device attached this port. When clear, full-speed device attached this port. This field valid only when set. port suspended port suspended write-ClearPortPower: clear (PortPowerStatus) writing logic this bit. Writing logic effect.
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HCRhPortStatus[1:4] register: description.continued Symbol Description read-PortPowerStatus: This reflects port power status, regardless type power switching implemented. This cleared overcurrent condition detected. this writing SetPortPower SetGlobalPower. clear this writing ClearPortPower ClearGlobalPower. PowerSwitchingMode PortPowerControlMask[NDP] determine which power control switches enabled. global switching mode (PowerSwitchingMode only Set/ClearGlobalPower controls this bit. per-port power switching (PowerSwitchingMode PortPowerControlMask[NDP] port set, only Set/ClearPortPower commands enabled. mask set, only Set/ClearGlobalPower commands enabled. When port power disabled, (CurrentConnectStatus), (PortEnableStatus), (PortSuspendStatus) (PortResetStatus) should reset. port power port power write-SetPortPower: write logic (PortPowerStatus) bit. Writing logic effect. Remark: This always reads logic1 power switching supported.
Table
reserved read-PortResetStatus: When this write SetPortReset, port reset signaling asserted. When reset completed PRSC (PortResetStatusChange) set, this cleared. port reset signal active port reset signal active write-SetPortReset: port reset signaling writing this bit. Writing effect. cleared, this write does (PortResetStatus) instead sets CCS. This informs driver that attempted reset disconnected port.
POCI
read-PortOverCurrentIndicator: This valid only when Root configured show overcurrent conditions reported per-port basis. per-port overcurrent reporting supported, this logic cleared, power operations normal this port. set, overcurrent condition exists this port. overcurrent condition overcurrent condition detected write-ClearSuspendStatus: write logic initiate resume. Writing logic effect. resume initiated only (PortSuspendStatus) set.
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HCRhPortStatus[1:4] register: description.continued Symbol Description read-PortSuspendStatus: This indicates whether port suspended resume sequence. SetSuspendState write cleared when PSSC (PortSuspendStatusChange) resume interval. This (CurrentConnectStatus) cleared. This also cleared when PRSC (PortResetStatusChange) port reset when Host Controller placed USBRESUME state. upstream resume progress, will propagate Host Controller. port suspended port suspended write-SetPortSuspend: (PortSuspendStatus) writing logic this bit. Writing logic effect. cleared, this write does PSS; instead sets CSS. This informs driver that attempted suspend disconnected port.
Table
read-PortEnableStatus: This indicates whether port enabled disabled. Root clear this when overcurrent condition, disconnect event, switched-off power operational error detected. This change also causes PortEnabledStatusChange set. this writing SetPortEnable clear writing ClearPortEnable. This cannot when (CurrentConnectStatus) cleared. This also completion port reset when ResetStatusChange completion port suspend when SuspendStatusChange set. port disable port enabled write-SetPortEnable: (PortEnableStatus) writing logic Writing logic effect. cleared, this write does PES, instead sets (ConnectStatusChange). This informs driver that attempted enable disconnected port.
read-CurrentConnectStatus: This reflects current state downstream port. device connected device connected write-ClearPortEnable: write logic this clear (PortEnableStatus) bit. Writing logic effect. (CurrentConnectStatus) bit, read, affected write ClearPortEnable. Remark: This always reads logic when attached device nonremovable (DeviceRemoveable[NDP]).
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11.2 legacy support registers
ISP1561 supports legacy keyboards mice. Four operational registers used provide legacy support. Each these registers located 32-bit boundary. offset these registers relative base address Host Controller operational registers with HceControl located offset 100H.
Table Offset 100H 104H 108H 10CH Table Legacy support registers Register HceControl HceInput HceOutput HceStatus Emulated registers Cycle Type Register Contents Accessed/Modified HceOutput HceInput HceStatus HceInput Side Effects from port sets OutputFull HceStatus port sets InputFull CmdData HceStatus from port returns current value HceStatus with other side effect port sets InputFull CmdData HceStatus Description Used enable control emulation hardware report various status information Emulation legacy Input Buffer register Emulation legacy Output Buffer register where keyboard mouse data written software Emulation legacy Status register
Address
11.2.1
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access IRQ12A
HceControl register (address: value read from func0 func1 address 100H)
HceControl register: allocation IRQ1A GA20S reserved reserved reserved EIRQEn IRQEn A20S
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HceControl register: description Symbol A20S Description reserved A20State: This indicates current state Gate keyboard controller. used compare against value written when GA20S (GateA20Sequence) active. IRQ12Active: This indicates that positive transition IRQ12 from keyboard controller occurred. Writing logic sets IRQ12 logic (inactive). Writing logic this effect. IRQ1Active: This indicates that positive transition IRQ1 from keyboard controller occurred. Writing logic sets IRQ1 logic (inactive). Writing logic this effect. GateA20Sequence: This Host Controller when data value written port cleared, write port value other than D1H. ExternalIRQEn: When this logic IRQ1 IRQ12 from keyboard controller cause emulation interrupt. This independent setting (EmulationEnable) this register. IRQEn: When this set, Host Controller generates IRQ1 IRQ12 long OUT_FULL (OutputFull) HceStatus logic AUX_OUT_FULL (AuxOutputFull) HceStatus logic then IRQ1 generated; logic then IRQ12 generated. CharacterPending: When this set, emulation interrupt generated when OUT_FULL (OutputFull) HceStatus register logic EmulationInterrupt: This shows emulation interrupt condition. logic legacy emulation enabled logic legacy emulation disabled
Table
IRQ12A
IRQ1A
GA20S
EIRQEn
IRQEn
EmulationEnable: When this logic Host Controller enabled legacy emulation. Host Controller decodes accesses registers enables interrupts IRQ1 and/or IRQ12. Host Controller also generates emulation interrupt appropriate times invoke emulation software.
11.2.2
HceInput register (address: value read from func0 func1 address 104H) HceInput register four-byte register, allocation given Table data that written ports captured this register when emulation enabled. This register read written directly accessing Host Controller's operational register space. When accessed directly memory cycle, reads writes this register have side effects.
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Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HceInput register: allocation Table reserved reserved reserved
IN_DATA[7:0]
HceInput register: description Symbol IN_DATA[7:0] Description reserved InputData: This register holds data that written ports 64H.
11.2.3
HceOutput register (address: value read from func0 func1 address 108H) Data placed this register emulation software returned when port read emulation enabled. read this location, OUT_FULL (OutputFull) HceStatus logic allocation given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access
HceOutput register: allocation reserved reserved reserved
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Symbol Reset Access
Table
OUT_DATA[7:0]
HceOutput register: description Symbol Description reserved
OUT_DATA[7:0] OutputData: This register holds data that returned when read port requested application software.
11.2.4
HceStatus register (address: value read from func0 func1 address 10CH) contents HceStatus register returned read port when emulation enabled. Reads writes port writes port cause changes this register. Emulation software directly access this register through memory address Host Controller's operational register space. Accessing this register through memory address produces side effects. Table contains allocation.
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
HceStatus register: allocation PARITY TIMEOUT Table AUX_OUT _FULL reserved reserved reserved INH_SW CMD_DATA FLAG IN_FULL OUT_FULL
HceStatus register: description Symbol PARITY TIMEOUT Description reserved Parity: This indicates parity error keyboard mouse data. Timeout: This indicates timeout.
9397 10015
Koninklijke Philips Electronics N.V. 2003. rights reserved.
Product data
Rev. February 2003
Philips Semiconductors
ISP1561
host controller
HceStatus register: description.continued Symbol AUX_OUT_ FULL INH_SW CMD_DATA FLAG IN_FULL Description AuxOutputFull: IRQ12 asserted whenever this logic OUT_FULL (OutputFull) logic IRQEn set. Inhibit Switch: This reflects state keyboard inhibit switch. set, keyboard active. CmdData: Host Controller sets this logic write port logic write port 64H. Flag: Nominally used system flag software indicate warm cold boot. InputFull: Except case Gate sequence, this logic write address 64H. While this logic emulation enabled, emulation interrupt condition exists. OutputFull: Host Controller sets this logic read port 60H. IRQEn set, AUX_OUT_FULL (AuxOutputFull) determines which activated. While this logic CharacterPending HceControl logic emulation interrupt condition exists.
Table
OUT_FULL
11.3 EHCI controller capability registers
Other than OHCI Host Controller, there some registers EHCI that define capability EHCI. address range these registers located before operational registers. 11.3.1 CAPLENGTH/HCIVERSION register (address: value read from func2 address 00H) allocation this four-byte register given Table
Table Symbol Reset Access Symbol Reset Access Symbol Reset Access Symbol Reset Access
9397 10015
CAPLENGTH/HCIVERSION register: allocation reserved
HCIVERSION[15:8]
HCIVERSION[7:0]
CAPLENGTH[7:0]
Koninklijke Philips Electronics N.V. 2003. rights reserved.
Product data
Rev. February 2003
Philips Semiconductors
ISP1561
host controller
CAPLENGTH/HCIVERSION register: description Symbol Description reserved
Table
HCIVERSION Host Controller Interface Version Number: contains [15:0] encoding version number interface which Host Controller interface conforms standard. CAPLENGTH Capability Registe
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