100V, 0.180 Ohm, N-Channel Power MOSFET 2N6796 N-Channel enhancem
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2N6796
100V, 0.180 Ohm, N-Channel Power MOSFET
2N6796 N-Channel enhancement mode silicon gate power field effect transistor designed applications such switching regulators, switching converters, motor drivers, relay drivers, drivers high power bipolar switching transistors requiring high speed gate drive power. This type operated directly from integrated circuits.
Features
100V rDS(ON) 0.180 Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Majority Carrier Device
Ordering Information
PART NUMBER 2N6796 PACKAGE TO-205AF BRAND 2N6796
Related Literature TB334 "Guidelines Soldering Surface Mount Components Boards"
NOTE: When ordering, entire part number.
Symbol
Packaging
JEDEC TO-205AF
DRAIN (CASE)
SOURCE
GATE
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
2N6796
Absolute Maximum Ratings
25oC, Unless Otherwise Specified 2N6796 0.20 UNITS W/oC
Drain Source Breakdown Voltage (Note Drain Gate Voltage (RGS 20k) (Note VDGR Continuous Drain Current (Note 100oC Pulsed Drain Current (Note Gate Source Voltage (Note Continuous Source Current (Body Diode) Pulse Source Current (Body Diode). Maximum Power Dissipation (Figure Linear Derating Factor (Figure Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief .Tpkg
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: 25oC 125oC.
Electrical Specifications
PARAMETER
25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS VDS(ON) IGSS rDS(ON) td(ON) td(OFF) CISS COSS CRSS Free Operation 80V, 310mA 3.12V, 25V, 1MHz, (Figure TEST CONDITIONS 0.25mA, VDS, 0.5mA 100V, 80V, 125oC ±20V 10V, 125oC 25oC, 30V, (Figure MOSFET Switching Times Essentially Independent Operating Temperature 0.75 0.14 1000 1.56 ±100 0.180 0.350 UNITS
oC/W oC/W
Drain Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note Gate Source Leakage Current Drain Source Resistance (Note
Diode Forward Voltage (Note Forward Transconductance (Note Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction Case Thermal Resistance Junction Ambient Safe Operating Area
Source Drain Diode Specifications
PARAMETER Reverse Recovery Time Reverse Recovered Charge NOTES: Pulse test: pulse width 300µs, duty cycle Repetitive rating: pulse width limited maximum junction temperature. Transient Thermal Impedance curve (Figure SYMBOL TEST CONDITIONS 150oC, dISD/dt 100A/µs 150oC, dISD/dt 100A/µs UNITS
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
2N6796 Typical Performance Curves
POWER DISSIPATION MULTIPLIER DRAIN CURRENT
Unless Otherwise Specified
CASE TEMPERATURE (oC)
CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
ZJC, NORMALIZED THERMAL IMPEDANCE 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 NOTES: DUTY FACTOR: t1/t2 PEAK
RECTANGULAR PULSE DURATION
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
OPERATION THIS AREA LIMITED rDS(ON) DRAIN CURRENT 10µs 100µs DRAIN CURRENT
1000 PULSE DURATION 80µs
25oC RATED SINGLE PULSE
10ms 100ms
-0.1
VDS, DRAIN SOURCE VOLTAGE
VDS, DRAIN SOURCE VOLTAGE
FIGURE FORWARD BIAS SAFE OPERATING AREA
FIGURE OUTPUT CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
2N6796 Typical Performance Curves
DRAIN CURRENT VDS, DRAIN SOURCE VOLTAGE
Unless Otherwise Specified (Continued)
PULSE DURATION 80µs DRAIN CURRENT
80µs PULSE TEST 125oC 25oC -55oC
VGS, GATE SOURCE VOLTAGE
FIGURE SATURATION CHARACTERISTICS
rDS(ON), ON-STATE RESISTANCE NORMALIZED ON-RESISTANCE 2.00 1.75 1.50 1.25 1.00 0.75 0.50
FIGURE TRANSFER CHARACTERISTICS
DRAIN CURRENT
0.25
JUNCTION TEMPERATURE (oC)
NOTE: Heating effect pulse minimal. FIGURE DRAIN SOURCE RESISTANCE GATE VOLTAGE DRAIN CURRENT FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
1.15 NORMALIZED ON-RESISTANCE 1.10
2000 1MHz CISS CRSS COSS
1600 1.05 1.00 0.95 0.90 0.85 0.80 JUNCTION TEMPERATURE (oC) CAPACITANCE (pF)
1200
CISS
COSS CRSS
VDS, DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
2N6796 Typical Performance Curves
gfs, TRANSCONDUCTANCE
Unless Otherwise Specified (Continued)
ISD, SOURCE DRAIN CURRENT
80µs PULSE TEST
-55oC 25oC 125oC
150oC
25oC
DRAIN CURRENT
VSD, SOURCE DRAIN VOLTAGE
FIGURE TRANSCONDUCTANCE DRAIN CURRENT
FIGURE SOURCE DRAIN DIODE VOLTAGE
VGS, GATE SOURCE
TOTAL GATE CHARGE (nC)
FIGURE GATE SOURCE VOLTAGE GATE CHARGE
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
2N6796 Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
(ISOLATED SUPPLY) SAME TYPE Qg(TOT)
BATTERY
0.2µF
0.3µF
IG(REF) CURRENT SAMPLING RESISTOR
CURRENT SAMPLING RESISTOR IG(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORMS
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
2N6796 TO-205AF
LEAD JEDEC TO-205AF HERMETIC METAL PACKAGE
INCHES SYMBOL 0.160 0.016 0.350 0.315 0.095 0.190 0.095 0.010 0.028 0.029 0.500 0.075 0.180 0.021 0.370 0.335 0.105 0.210 0.105 0.020 0.034 0.045 0.560
MILLIMETERS 4.07 0.41 8.89 8.01 2.42 4.83 2.42 0.26 0.72 0.74 12.70 1.91 4.57 0.53 9.39 8.50 2.66 5.33 2.66 0.50 0.86 1.14 14.22 NOTES
SEATING PLANE
NOTES: These dimensions within allowable dimensions Rev. JEDEC TO-205AF outline dated 11-82. Lead dimension (without solder). Solder coating vary along lead length, typically 0.002 inches (0.05mm) solder coating. Position lead measured 0.100 inches (2.54mm) from bottom seating plane. This zone controlled automatic handling. variation actual diameter within this zone shall exceed 0.010 inches (0.254mm). Lead butt welded stem base. Controlling dimension: Inch. Revision dated 6-94.
©2001 Fairchild Semiconductor Corporation
2N6796 Rev.
TRADEMARKS
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LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices critical component component life support device system whose failure perform systems which, intended surgical implant into reasonably expected cause failure life body, support sustain life, whose support device system, affect safety failure perform when properly used accordance with instructions provided labeling, effectiveness. reasonably expected result significant injury user. PRODUCT STATUS DEFINITIONS Definition Terms Datasheet Identification Advance Information Product Status Formative Design Definition This datasheet contains design specifications product development. Specifications change manner without notice. This datasheet contains preliminary data, supplementary data will published later date. Fairchild Semiconductor reserves right make changes time without notice order improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves right make changes time without notice order improve design.
Preliminary
First Production
Identification Needed
Full Production
Obsolete
Production
This datasheet contains specifications product that been discontinued Fairchild semiconductor. datasheet printed reference information only.
Rev.
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