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FLASH MEMORY CMOS MBM29F016A-70/-90/-12 FEATURES S


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DS05-20844-4E
FLASH MEMORY
CMOS
MBM29F016A-70/-90/-12
FEATURES
Single read, write, erase Minimizes system level power requirements Compatible with JEDEC-standard commands Pinout software compatible with single-power supply Flash Superior inadvertent write protection 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) Minimum 100,000 write/erase cycles High performance maximum access time Sector erase architecture Uniform sectors bytes each combination sectors erased. Also supports full chip erase. Embedded EraseAlgorithms Automatically pre-programs erases chip sector Embedded ProgramAlgorithms Automatically programs verifies data specified address Data Polling Toggle feature detection program erase cycle completion Ready/Busy output (RY/BY) Hardware method detection program erase cycle completion write inhibit Hardware RESET Resets internal state machine read mode Erase Suspend/Resume Supports reading programming data sector being erased Sector group protection Hardware method that disables combination sector groups from write erase operation sector group consists adjacent sectors bytes each) Temporary sector groups unprotection Temporary sector unprotection RESET
Embedded EraseTM, Embedded Programand ExpressFlashare trademarks Advanced Micro Devices, Inc.
MBM29F016A-70/-90/-12
PACKAGE
48-pin Plastic TSOP(I) Marking Side 48-pin Plastic TSOP(I)
Marking Side (FPT-48P-M19) (FPT-48P-M20)
MBM29F016A-70/-90/-12
GENERAL DESCRIPTION
MBM29F016A M-bit, V-Only Flash memory organized bytes bits each. bytes data divided into sectors bytes flexible erase capability. data will appear DQ7. MBM29F016A offered 48-pin TSOP(I) package. This device designed programmed in-system with standard system supply. 12.0 required program erase operations. device also reprogrammed standard EPROM programmers. standard MBM29F016A offers access times between allowing operation high-speed microprocessors without wait states. eliminate contention device separate chip enable (CE), write enable (WE), output enable (OE) controls. MBM29F016A command compatible with JEDEC standard E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from 12.0 Flash EPROM devices. MBM29F016A programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Each sector programmed verified less than seconds. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. This device also features sector erase architecture. sector erase mode allows sectors memory erased reprogrammed without affecting other sectors. sector typically erased verified within second already completely preprogrammed). MBM29F016A erased when shipped from factory. MBM29F016A device also features hardware sector group protection. This feature will disable both program erase operations combination eight sector groups memory. sector group consists four adjacent sectors grouped following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, 28-31. Fujitsu implemented Erase Suspend feature that enables user erase hold period time read data from program data non-busy sector. Thus, true background erase achieved. device features single power supply operation both read program functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations during power transitions. program erase detected Data Polling DQ7, Toggle feature RY/BY output pin. Once program erase cycle been completed, device automatically resets read mode. MBM29F016A also hardware RESET pin. When this driven low, execution Embedded Program Embedded Erase operations will terminated. internal state machine will then reset into read mode. RESET tied system reset circuity. Therefore, system reset occurs during Embedded Program Embedded Erase operation, device will automatically reset read mode. This will enable system microprocessor read boot-up firmware from Flash memory. Fujitsu's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability, cost effectiveness. MBM29F016A memory electrically erases bits within sector simultaneously Fowler-Nordheim tunneling. bytes programmed byte time using EPROM programming mechanism electron injection.
MBM29F016A-70/-90/-12
FLEXIBLE SECTOR-ERASE ARCHITECTURE
Thirty byte sectors sector groups each which consists adjacent sectors following pattern; sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, 28-31 Individual-sector multiple-sector erase capability Sector group protection user-definable 1FFFFFH byte SA31 1EFFFFH byte SA30 Sector 1DFFFFH Group byte SA29 1CFFFFH byte SA28 1BFFFFH 1AFFFFH 19FFFFH 18FFFFH 17FFFFH 16FFFFH 15FFFFH 14FFFFH 13FFFFH 12FFFFH 11FFFFH 10FFFFH Sectors Total 0FFFFFH 0EFFFFH 0DFFFFH 0CFFFFH 0BFFFFH 0AFFFFH 09FFFFH 08FFFFH 07FFFFH 06FFFFH 05FFFFH 04FFFFH byte byte byte byte 03FFFFH 02FFFFH 01FFFFH 00FFFFH 000000H Sector Group
MBM29F016A-70/-90/-12
PRODUCT LINE
Part Ordering Part ±10% Max. Address Access Time (ns) Max. Access Time (ns) Max. Access Time (ns) MBM29F016A
BLOCK DIAGRAM
RY/BY Buffer
RY/BY Erase Voltage Generator Input/Output Buffers
State Control
RESET Command Register Program Voltage Generator
Chip Enable Output Enable Logic
Data Latch
Y-Decoder
Y-Gating
Detector
Timer Program/Erase
Address Latch
X-Decoder
Cell Matrix
MBM29F016A-70/-90/-12
CONNECTION DIAGRAMS
TSOP(I) N.C. N.C. N.C. RESET N.C. N.C. N.C. N.C. N.C. RY/BY N.C. N.C.
(Marking Side)
MBM29F016A Standard Pinout
FPT-48P-M19
N.C. N.C. RESET N.C. N.C. N.C.
(Marking Side)
MBM29F016A Reverse Pinout
N.C. N.C. RY/BY N.C. N.C. N.C.
FPT-48P-M20
MBM29F016A-70/-90/-12
LOGIC SYMBOL
Table
MBM29F016A Configuration Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Sector Protection Unlock Internal Connection Device Ground Device Power Supply
RESET RY/BY
RY/BY RESET N.C. Table
MBM29F016A User Operations RESET Code Code DOUT HIGH-Z HIGH-Z Code HIGH-Z
Operation Auto-Select Manufacturer Code Auto-Select Device Code Read Standby Output Disable Write (Program/Erase) Enable Sector Group Protection Verify Sector Group Protection Temporary Sector Group Unprotection Reset (Hardware) Legend: VIL, VIH, VIH,
Pulse Input. Characteristics voltage levels.
Notes: Manufacturer device codes also accessed command register write sequence. Refer Table Refer section Sector Group Protection. VIL, initiates write operations.
MBM29F016A-70/-90/-12
ORDERING INFORMATION Standard Products
Fujitsu standard products available several packages. order number formed combination
MBM29F016
PFTN
PACKAGE TYPE PFTN 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout
SPEED OPTION Product Selector Guide Device Revision
DEVICE NUMBER/DESCRIPTION MBM29F016 Mega-bit 8-Bit) CMOS Flash Memory V-only Read, Write, Erase Byte Sectors)
MBM29F016A-70/-90/-12
FUNCTIONAL DESCRIPTION Read Mode
MBM29F016A control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins (assuming addresses have been stable least tACC-tOE time).
Standby Mode
There ways implement standby mode MBM29F016A device, using both RESET pins; other RESET only. When using both pins, CMOS standby mode achieved with RESET inputs both held ±0.3 Under this condition current consumed less than standby mode achieved with RESET pins held VIH. Under this condition current reduced approximately During Embedded Algorithm operation, Active current (ICC2) required even VIH. device read with standard access time (tCE) from either these standby modes. When using RESET only, CMOS standby mode achieved with RESET input held ±0.3 "L"). Under this condition current consumed less than standby mode achieved with RESET held "L"). Under this condition current required reduced approximately Once RESET taken high, device requires wake time before outputs valid read access. standby mode outputs high impedance state, independent input.
Output Disable
With input logic high level (VIH), output from device disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from device will identify manufacturer type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, programming equipment must force (11.5 12.5 address identifier bytes then sequenced from device outputs toggling address from VIH. addresses don't cares except (See Table manufacturer device codes also read command register, instances when MBM29F016A erased programmed system without access high voltage pin. command sequence illustrated Table (Refer Autoselect Command section.) Byte VIL) represents manufacturer's code (Fujitsu 04H) byte VIH) represents device identifier code MBM29F016A ADH. These bytes given table identifiers manufactures device will exhibit parity with defined parity bit. order read proper device codes when executing Autoselect, must VIL. (See Table Autoselect mode also facilitates determination sector group protection system. performing read operation address location XX02H with higher order address bits A18, desired sector group address, device will return protected sector group non-protected sector group.
MBM29F016A-70/-90/-12
Table Type Manufacture's Code Device Code Sector Group Protection MBM29F016A Sector Protection Verify Autoselect Codes Code (HEX) 01H*
Sector Group Addresses
Outputs protected sector addresses outputs unprotected sector addresses. Table SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 Sector Address Table Address Range 000000H 00FFFFH 010000H 01FFFFH 020000H 02FFFFH 030000H 03FFFFH 040000H 04FFFFH 050000H 05FFFFH 060000H 06FFFFH 070000H 07FFFFH 080000H 08FFFFH 090000H 09FFFFH 0A0000H 0AFFFFH 0B0000H 0BFFFFH 0C0000H 0CFFFFH 0D0000H 0DFFFFH 0E0000H 0EFFFFH 0F0000H 0FFFFFH 100000H 10FFFFH 110000H 11FFFFH 120000H 12FFFFH 130000H 13FFFFH 140000H 14FFFFH 150000H 15FFFFH 160000H 16FFFFH 170000H 17FFFFH 180000H 18FFFFH 190000H 19FFFFH 1A0000H 1AFFFFH 1B0000H 1BFFFFH 1C0000H 1CFFFFH 1D0000H 1DFFFFH 1E0000H 1EFFFFH 1F0000H 1FFFFFH
MBM29F016A-70/-90/-12
Table SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 Sector Group Addresses Sectors SA11 SA12 SA15 SA16 SA19 SA20 SA23 SA24 SA27 SA28 SA31
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Group Protection
MBM29F016A features hardware sector group protection. This feature will disable both program erase operations combination eight sector groups memory. Each sector group consists four adjacent sectors grouped following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, 28-31 (see Table sector group protection feature enabled using programming equipment user's site. device shipped with sector groups unprotected. activate this mode, programming equipment must force address control (suggest 11.5 VIL. sector addresses (A20, A19, A18) should sector protected. Tables define sector address each thirty (32) individual sectors, sector group address each eight individual group sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector addresses must held constant during pulse. figures sector protection waveforms algorithm. verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector addresses (A20, A19, A18) while (A6, will produce logical code device output protected sector. Otherwise device will produce unprotected sector. this mode, lower order addresses, except DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. also possible determine sector group protected system writing Autoselect command. Performing read operation address location XX02H, where higher order addresses (A20, A19, A18) desired sector group address will produce logical protected sector group. Table Autoselect codes.
MBM29F016A-70/-90/-12
Temporary Sector Group Unprotection
This feature allows temporary unprotection previously protected sector groups MBM29F016A device order change data. Sector Group Unprotection mode activated setting RESET high voltage During this mode, formerly protected sector groups programmed erased selecting sector group addresses. Once taken away from RESET pin, previously protected sector groups will protected again. Refer Figures Table
Write Cycles Req'd
MBM29F016A Command Definitions
Command Sequence
Fifth Sixth First Second Third Fourth Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset* Reset/Read* Autoselect Byte Program Chip Erase Sector Erase
XXXH 555H 555H 555H 555H 555H
2AAH 2AAH 2AAH 2AAH 2AAH
555H 555H 555H 555H 555H
2AAH 2AAH
555H
555H 555H
Sector Erase Suspend Sector Erase Resume
Erase suspended during sector erase with Addr ("H" "L"), Data (B0H) Erase resumed after suspend with Addr ("H" "L"), Data (30H)
Notes: Address bits address commands except Program Address (PA) Sector Address (SA). operations defined Table Address memory location read. Address memory location programmed. Addresses latched falling edge pulse. Address sector erased. combination A20, A19, A18, A17, will uniquely select sector. Data read from location during read operation. Data programmed location Data latched rising edge Read Byte program functions non-erasing sectors allowed Erase Suspend mode. system should generate following address pattens: 555H 2AAH addresses A10. Either reset commands will reset device.
Command Definitions
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset device read mode. Table defines valid register command sequences. Note that Erase Suspend (B0H) Erase Resume (30H) commands valid only while Sector Erase operation progress. Moreover, both Read/Reset commands functionally equivalent, resetting device read mode.
MBM29F016A-70/-90/-12
Read/Reset Command
read reset operation initiated writing read/reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until command register contents altered. device will automatically power-up read/reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desirable system design practice. device contains autoselect command operation supplement traditional PROM programming methodology. operation initiated writing autoselect command sequence into command register. Following command write, read cycle from address XX00H retrieves manufacture code 04H. read cycle from address XX01H returns device code ADH. (See Table manufacturer device codes will exhibit parity with defined parity bit. Sector state (protection unprotection) will informed address XX02H. Scanning sector group addresses (A18, A19, A20) while (A6, will produce logical device output protected sector group. terminate operation, necessary write read/reset command sequence into register also write Autoselect command during operation, execute after writing Read/Reset command sequence.
Byte Programming
device programmed byte-by-byte basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. This automatic programming operation completed when data equivalent data written this which time device returns read mode addresses longer latched. (See Table Hardware Sequence Flags.) Therefore, device requires that valid address device supplied system this particular instance time. Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. hardware reset occurs during programming operation, impossible guarantee data being written. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting either hang device result apparent success according data polling algorithm read from reset/read mode will show that data still "0". Only erase operations convert "0"s "1"s. Figure illustrates Embedded ProgrammingAlgorithm using typical command strings operations.
MBM29F016A-70/-90/-12
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence device will automatically program verify entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. automatic erase begins rising edge last pulse command sequence terminates when data (see Write Operation Status section) which time device returns read mode. Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed Sector Erase command. sector address (any address location within desired sector) latched falling edge while command (Data 30H) latched rising edge After time-out from rising edge last sector erase command, sector erase operation will begin. Multiple sectors erased concurrently writing cycle operations Table This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted erasure will start. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last will initiate execution Sector Erase command(s). another falling edge occurs within time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset device read mode, ignoring previous command string. Resetting device once execution begun will corrupt data that sector. that case, restart erase those sectors allow them complete. (Refer Write Operation Status section DQ3, Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors 31). Sector erase does require user program device prior erase. device automatically programs memory locations sector(s) erased prior electrical erase. When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. automatic sector erase begins after time from rising edge pulse last sector erase command pulse terminates when data (see Write Operation Status section) which time device returns read mode. Data polling must performed address within sectors being erased. Figure illustrates Embedded EraseAlgorithm using typical command strings operations.
Erase Suspend
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from programs sector being erased. This command applicable ONLY during Sector Erase operation which includes time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writing Erase Suspend command during
MBM29F016A-70/-90/-12
Sector Erase time-out results immediate termination time-out period suspension erase operation. other command written during Erase Suspend mode will ignored except Erase Resume command. Writing Erase Resume command resumes erase operation. addresses DON'T CARES when writing Erase Suspend Erase Resume command. When Erase Suspend command written during Sector Erase operation, device will take maximum suspend erase operation. When device entered erase-suspended mode, RY/BY output will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, device defaults erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-read mode will cause toggle. (See section DQ2.) After entering erase-suspend-read mode, user program device writing appropriate command sequence Byte Program. This program mode known erase-suspend-program mode. Again, programming this mode same programming regular Byte Program mode except that data must programmed sectors that erase-suspended. Successively reading from erasesuspended sector while device erase-suspend-program mode will cause toggle. erase-suspended program operation detected RY/BY output pin, Data polling DQ7, Toggle (DQ6) which same regular Byte Program operation. Note that must read from Byte Program address while read from address. resume operation Sector Erase, Resume command (30H) should written. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
MBM29F016A-70/-90/-12
Write Operation Status
Table Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Time Limits Embedded Erase Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) Hardware Sequence Flags Data Toggle Toggle Data Toggle (Note Toggle Toggle Toggle Data Data Toggle Toggle (Note Data (Note
Progress
Notes: Performing successive read operations from erase-suspended sector will cause toggle. Performing successive read operations from address will cause toggle. Reading byte address being programmed while erase-suspend program mode will indicate logic bit. However, successive reads from erase-suspended sector will cause toggle.
Data Polling MBM29F016A device features Data Polling method indicate host that embedded algorithms progress completed. During Embedded Program Algorithm, attempt read device will produce complement data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded EraseAlgorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown Figure Data polling will also flag entry into Erase Suspend. will switch start Erase Suspend mode. Please note that address erasing sector must applied order observe Erase Suspend Mode. During Program Erase Suspend, Data polling will perform same regular program execution outside suspend mode. chip erase, Data Polling valid after rising edge sixth pulse write pulse sequence. sector erase, Data Polling valid after last rising edge sector erase pulse. Data Polling must performed sector address within sectors being erased sector that within protected sector group. Otherwise, status valid. Just prior completion Embedded Algorithm operation change asynchronously while output enable (OE) asserted low. This means that device driving status information instant time then that byte's valid data next instant time. Depending when system samples
MBM29F016A-70/-90/-12
output, read status valid data. Even device completed Embedded Algorithm operations valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, erase-suspend-program mode, sector erase time-out. (See Table Figure Data Polling timing specifications diagrams.
Toggle MBM29F016A also features "Toggle method indicate host system that embedded algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from device address will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth pulse four write pulse sequence. chip erase, sector erase Toggle valid after rising edge sixth pulse write pulse sequence. Sector Erase, Toggle valid after last rising edge sector erase pulse. Toggle active during sector erase time out. programming, sector being written protected, Toggle will toggle about then stop toggling without data having changed. erase, device will erase selected sectors except ones that protected. selected sectors protected, chip will toggle Toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle. Figure Toggle timing specifications diagrams.
Exceeded Timing Limits will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling DQ7, only operating function device under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described Table failure condition also appear user tries program location that previously programmed this case device locks never completes Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once device exceeded timing limits, will indicate "1." Please note that this device failure condition since device incorrectly used. this occurs, reset device.
Sector Erase Timer After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled
MBM29F016A-70/-90/-12
erase cycle begun; attempts write subsequent commands (other than Erase Suspend) device will ignored until erase operation completed indicated Data Polling Toggle ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted. Refer Table Hardware Sequence Flags.
Toggle This toggle along with DQ6, used determine whether device Embedded EraseAlgorithm Erase Suspend. Successive reads from erasing sector will cause toggle during Embedded EraseAlgorithm. device erase-suspended-read mode, successive reads from erase-suspended sector will cause toggle. When device erase-suspended-program mode, successive reads from byte address non-erase suspended sector will indicate logic bit. Mode Program Erase Erase Suspend Read (Erase-Suspended Sector) Erase Suspend Program toggles toggles toggles toggles toggles
Notes: These status flags apply when outputs read from sector that been erase-suspended. These status flags apply when outputs read from byte address non-erase suspended sector. different from that toggles only when standard program Erase, Erase Suspend Program operation progress. behavior these status bits, along with that DQ7, summarized follows: example, used together determine erase-suspend-read mode (DQ2 toggles while does not). also Table Figure Furthermore, also used determine which sector being erased. When device erase mode, toggles this read from erasing sector.
RY/BY
Ready/Busy MBM29F016A provides RY/BY open-drain output indicate host system that Embedded Algorithms either progress been completed. output low, device busy with either program erase operation. output high, device ready accept read/write erase operation. When RY/BY low, device will accept additional program erase commands with exception Erase Suspend command. MBM29F016A placed Erase Suspend mode, RY/BY output will high, means connecting with pull-up resistor VCC. During programming, RY/BY driven after rising edge fourth pulse. During erase operation, RY/BY driven after rising edge sixth pulse. RY/BY will indicate busy condition during RESET pulse. Refer Figure detailed timing diagram. RY/BY pulled high standby mode.
MBM29F016A-70/-90/-12
Since this open-drain output, several RY/BY pins tied together parallel with pull-up resistor VCC.
RESET
Hardware Reset MBM29F016A device reset driving RESET VIL. RESET must kept (VIL) least operation progress will terminated internal state machine will reset read mode after RESET driven low. hardware reset occurs during program operation, data that particular location will indeterminate. When RESET internal reset complete, device goes standby mode cannot accessed. Also, note that data output pins tri-stated duration RESET pulse. Once RESET taken high, device requires wake time until outputs valid read access. RESET tied system reset input. Therefore, system reset occurs during Embedded Program Erase Algorithm, device will automatically reset read mode this will enable system's microprocessor read boot-up firmware from Flash memory.
Data Protection
MBM29F016A designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power device automatically resets internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completions specific multi-bus cycle command sequences. device also incorporates several features prevent inadvertent write cycles resulting from power-up power-down transitions system noise.
Write Inhibit
avoid initiation write cycle during power-up power-down, write cycle locked less than (typically VLKO, command register disabled internal program/erase circuits disabled. Under this condition device will reset read mode. Subsequent writes will ignored until level greater than VLKO. users responsibility ensure that control pins logically correct prevent unintentional writes when above
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL, VIH. initiate write cycle must logical zero while logical one.
Power-Up Write Inhibit
Power-up device with will accept commands rising edge internal state machine automatically reset read mode power-up.
MBM29F016A-70/-90/-12
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .-55°C +125°C Ambient Temperature with Power Applied .-40°C +85°C Voltage with Respect Ground pins except RESET (Note 1).-2.0 +7.0 (Note .-2.0 +7.0 RESET (Note .-2.0 +13.5 Notes: Minimum voltage input pins -0.5 During voltage transitions, inputs negative overshoot -2.0 periods Maximum voltage output pins +0.5 During voltage transitions, outputs positive overshoot +2.0 periods Minimum input voltage RESET pins -0.5 During voltage transitions, RESET pins negative overshoot -2.0 periods Maximum input voltage RESET +13.0 which overshoot 14.0 periods Voltage difference between input voltage power supply. (VIN VCC) exceed WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING RANGES
Ambient Temperature (TA) -40°C +85°C Supply Voltages MBM29F016A-70. +4.75 +5.25 MBM29F016A-90/-12. +4.50 +5.50 Operating ranges define those limits between which functionality device guaranteed. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MBM29F016A-70/-90/-12
MAXIMUM OVERSHOOT
+0.8 -0.5 -2.0
Figure
Maximum Negative Overshoot Waveform
+2.0 +0.5 +2.0
Figure
Maximum Positive Overshoot Waveform
+14.0 +13.0 +0.5
This waveform applied RESET.
Figure
Maximum Positive Overshoot Waveform
MBM29F016A-70/-90/-12
CHARACTERISTICS
Parameter Symbol ILIT ICC1 ICC2 Parameter Description Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Active Current (Note Active Current (Note Test Conditions VCC, Max. VOUT VCC, Max. Max. RESET 12.5 VIL, VIL, Max., RESET ICC3 Current (Standby) Max., ±0.3 RESET ±0.3 Max. RESET ICC4 Current (Standby, Reset) Max. RESET ±0.3 VOH1 Output High Voltage Level VOH2 VLKO Lock-Out Voltage Input Level Input High Level Voltage Autoselect Sector Protection (A9, RESET) (Note Output Voltage Level 12.0 Min. -2.5 Min. -100 -0.5 11.5 VCC-0.4 VCC+0.5 12.5 0.45 Min. Max. ±1.0 ±1.0 Unit
Notes: current listed includes both operating current frequency dependent component MHz). frequency component typically mA/MHz, with VIH. active while Embedded Algorithm (program erase) progress. Applicable sector protection function. (VID VCC) exceed
MBM29F016A-70/-90/-12
CHARACTERISTICS
Read Only Operations Characteristics Parameter Symbols JEDEC Standard tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tACC tREADY Read Cycle Time Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output HIGH-Z Output Enable Output HIGH-Z Output Hold Time From Addresses, whichever occurs first RESET Read Mode Min. Max. Max. Max. Max. Max. Min. Max. (Note1) (Note2) (Note2) Unit
Description
Test Setup
Note: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:
Note: Test Conditions: Output Load: gate Input rise fall times: Input pulse levels: 0.45 Timing measurement reference level Input: Output:
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Note: including capacitance including capacitance Figure Test Conditions
MBM29F016A-70/-90/-12
Write/Erase/Program Operations Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tOES tOEH tGHWL tGHEL tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tWPP tOESP tCSP Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read Enable Hold Toggle Data Polling Time Read Recover Time Before Write Read Recover Time Before Write Setup Time Setup Time Hold Time Hold Time Write Pulse Width Write Pulse Width Write Pulse Width High Write Pulse Width High Byte Programming Operation Sector Erase Operation (Note Setup Time Voltage Transition Time (Note Write Pulse Width (Note Setup Time Active (Note Setup Time Active (Note Recover Time from RY/BY Description Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. Max. Min. Min. Min. Min. Min. Min. MBM29F016A Unit
(Continued)
MBM29F016A-70/-90/-12
(Continued)
Parameter Symbols JEDEC Standard tBUSY tEOE RESET Pulse Width RESET Hold Time Before Read Program/Erase Valid RY/BY Delay Description Min. Min. Max. Max. MBM29F016A Unit
Notes: This does include preprogramming time. This timing Sector Protection operation.
MBM29F016A-70/-90/-12
SWITCHING WAVEFORMS
Switching Waveforms
WAVEFORM INPUTS Must Steady Change from Change from Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
Addresses
tACC
Addresses Stable
tOEH
Outputs
High-Z
Output Valid
High-Z
Figure
Waveforms Read Operations
MBM29F016A-70/-90/-12
Cycle Addresses
555H
Data Polling
tGHWL
tWHWH1
tWPH DOUT DOUT
Data
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Waveforms Alternate Controlled Program Operations
MBM29F016A-70/-90/-12
Cycle
Data Polling
Addresses
555H
tGHEL
tWHWH1
tCPH
Data
DOUT
Notes: address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence.
Figure
Waveforms Alternate Controlled Program Operations
MBM29F016A-70/-90/-12
Addresses
555H
2AAH
555H
555H
2AAH
tGHWL
tWPH
Data
10H/30H
tVCS
sector address Sector Erase. Addresses 555H Chip Erase.
Figure
Waveforms Chip/Sector Erase Operations
MBM29F016A-70/-90/-12
tOEH
Data
Valid Data tEOE
High-Z
tWHWH1
Data
Output Flug
Valid Data
High-Z
Valid Data (The device completed Embedded operation.) Figure Waveforms Data Polling During Embedded Algorithm Operations
tOEH
tOES
Data
Toggle
Toggle
Stop Toggling
Valid
stops toggling (The device completed Embedded operation.) Figure Waveforms Toggle during Embedded Algorithm Operations
MBM29F016A-70/-90/-12
rising edge last signal
Entire programming erase operations
RY/BY
tBUSY
Figure
RY/BY Timing Diagram During Program/Erase Operations
RESET
tREADY
RY/BY
Figure
RESET, RY/BY Timing Diagram
MBM29F016A-70/-90/-12
SGAX
SGAY
tVLHT tWPP tOESP tCSP tVLHT tVLHT tVLHT
Data tVCS
SGAX Sector Group Address initial sector SGAY Sector Group Address next sector
Figure
Waveforms Sector Group Protection Timing Diagram
MBM29F016A-70/-90/-12
tVCS RESET
tVIDR tVLHT
tVLHT RY/BY
Program Erase Command Sequence
tVLHT
Unprotection period
Figure
Temporary Sector Group Unprotection Timing Diagram
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Toggle with
Note: read from erase-suspended sector. Figure
MBM29F016A-70/-90/-12
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See Below)
Data Polling Device
Increment Address
Last Address
Programming Completed
Program Command Sequence (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
Figure
Embedded ProgramAlgorithm
MBM29F016A-70/-90/-12
Start
Write Erase Command Sequece (See Below) Data Polling Toggle Successfully Completed
Erasure Completed
Chip Erase Command Sequence (Address/Command): 555H/AAH
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands optional.
Sector Address/30H
Note: insure command been accepted, system software should check status prior following each subsequent sector erase command. were high second status check, command have been accepted.
Figure
Embedded EraseAlgorithm
MBM29F016A-70/-90/-12
Start
Read Byte (DQ0 DQ7) Addr.
Data? Read Byte (DQ0 DQ7) Addr.
Address programming sector addresses within sector being erased during sector erase multiple erases operation. sector group addresses within sector being protected during sector erase multiple sector erases operation.
Data? Fail
Pass
Note: rechecked even because change simultaneously with DQ5.
Figure
Data Polling Algorithm
MBM29F016A-70/-90/-12
Start
Read Byte (DQ0 DQ7) Addr. Toggle Read Byte (DQ0 DQ7) Addr.
Toggle Fail
Pass
Note: rechecked even because stop toggling same time changing "1".
Figure
Toggle Algorithm
MBM29F016A-70/-90/-12
Start
Setup Sector Group Addr. (A20, A19, A18)
PLSCNT
VID, VID, VIL, RESET
Increment PLSCNT
Activate Pulse
Time
VIH, VIL, should remain VID)
Read from Sector Group Addr. (A20, A19, A18) PLSCNT Remove from Write Reset Command Data 01H? Protect Another Sector Group? Device Failed Remove from Write Reset Command
Sector Protection Completed
Figure
Sector Group Protection Algorithm
MBM29F016A-70/-90/-12
Start
RESET (Note
Perform Erase Program Operations
RESET
Temporary Sector Group Unprotection Completed (Note
Notes: Protected sector groups unprotected. previously protected sector groups protected once again. Figure Temporary Sector Group Unprotection Algorithm
MBM29F016A-70/-90/-12
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle 100,000 Typ. 16.8 Max. cycles Excludes programming prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
TSOP(I) CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance Test Setup VOUT Typ. Max. Unit
Note: Test conditions 25°C,
MBM29F016A-70/-90/-12
PACKAGE DIMENSIONS
48-pin plastic TSOP(I) (FPT-48P-M19)
Resin Protrusion. (Each Side:0.15(.006)MAX)
LEAD
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008)
12.00±0.20 (.472±.008) 11.50REF (.460)
(Mounting height)
1.10 -0.05 +.004 .043 -.002
+0.10
0.10(.004)
0.50(.0197) 0.15±0.05 (.006±.002) 0.20±0.10 (.008±.004)
0.05(0.02)MIN STAND 0.10(.004)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004)
1996 FUJITSU LIMITED F48029S-2C-2
Dimensions mm(inches)
(Continued)
MBM29F016A-70/-90/-12
(Continued)
48-pin plastic TSOP(I) (FPT-48P-M20)
Resin Protrusion. (Each Side:0.15(.006)MAX)
LEAD
INDEX
Details part 0.15(.006)
0.15(.006)
0.35(.014) 0.25(.010)
19.00±0.20 (.748±.008)
0.50±0.10 (.020±.004) 0.15±0.10 (.006±.002) 0.20±0.10 (.008±.004) 0.10(.004)
0.10(.004)
0.50(.0197)
0.05(0.02)MIN STAND
18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008)
11.50(.460)REF 12.00±0.20(.472±.008)
1.10 -0.05 +.004 .043 -.002
(Mounting height)
+0.10
1996 FUJITSU LIMITED F48030S-2C-2
Dimensions mm(inches)
MBM29F016A-70/-90/-12
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inhereut chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9903 FUJITSU LIMITED Printed Japan

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