HCPL-3700 HCPL-3700 voltage/current threshold detection optocoupl

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HCPL-3700 HCPL-3700 voltage/current threshold detection optocoupl

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AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
HCPL-3700 voltage/current threshold detection optocoupler consists AlGaAs connected threshold sensing input buffer which optically coupled high gain darlington output. input buffer chip capable controlling threshold levels over wide range input voltages with single resistor. output CMOS compatible.
FEATURES
input Programmable sense voltage Logic level compatibility Threshold guaranteed over temperature (0°C 70°C) Optoplanarconstruction high common mode immunity recognized (file E90700) TRUTH TABLE (Positive Logic) Input Output
APPLICATIONS
voltage detection AC/DC voltage sensing Relay contact monitor Current sensing Microprocessor Interface Industrial controls
bypass capacitor must connected between pins
AC/DC POWER
HCPL-3700 LOGIC
DCAC
ABSOLUTE MAXIMUM RATINGS derating required 70°C)
Parameter Storage Temperature Operating Temperature Lead Solder Temperature EMITTER Input Current Average Surge Transient Input Voltage (Pins 2-3) Input Power Dissipation Total Package Power Dissipation DETECTOR Output Current Supply Voltage Output Voltage (Average) (Pins 8-5) (Pins 6-5) (Note (Note (MAX) -0.5 -0.5 (MAX) (Note (Note Pulse Rate Pulse Rate Symbol TSTG TOPR TSOL Value +125 (MAX) (MAX) (MAX) -0.5 (MIN) (MAX) (MAX) Units
Output Power Dissipation
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
ELECTRICAL CHARACTERISTICS 70°C Unless otherwise specified)
Parameter Input Threshold Current Test Conditions (VIN VTH+, (Note (VIN Pins Open) (VCC (Note (VIN Pins Open) (VCC (Note |VIN (Pins Open) (VCC (Note |VIN (Pins Open) (VCC (Note (IHYS ITH+ ITH-) (VHYS VTH+ VTH-) (VIHC1 GND) (IIN Pins Connected (VIHC2 V4|) (|IIN| (Pins Open) (VIHC3 GND) (IIN Pins Open) (VILC GND) (IIN Input Current Bridge Diode Forward Voltage Logic Output Voltage Logic High Output Current Logic Supply Current Logic High Supply Current Input Capacitance (VIN (Pins Open) (IIN (IIN (VCC (Note (Note (VOH Open) (VCC (VCC Open) MHz; (Pins Pins Open) Symbol ITH+ ITHVTH+ 1.96 1.00 3.35 3.11 1.62 4.05 Unit
(Pins 2,3)
VTH-
2.01
2.86
Input Threshold Voltage (Pins 1,4)
VTH+
4.23
5.50
VTHIHYS VHYS VIHC1
2.87
4.20
Hysteresis
Input Clamp Voltage
VIHC2 VIHC3 VILC VD1,2 VD3,4 ICCL ICCH
12.5 -0.75 0.65 0.65 0.04
13.4
0.01
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Operating Temperature Operating Frequency Symbol Units
SWITCHING CHARACTERISTICS 25°C, Unless otherwise specified)
Characteristics Propagation Delay Time Output Level) Propagation Delay Time Output High Level) Output Rise Time (10-90%) Output Fall Time (90-10%) Common Mode Transient Immunity Output High Level) Common Mode Transient Immunity Output Level) Test Conditions (Note (Note (IIN 1400 (Notes 7,8) 3.11 mA,RL (Notes 7,8) Symbol TPHL TPLH |CMH| 25.0 4000 Unit V/µs
|CML|
V/µs
PACKAGE CHARACTERISTICS 70°C Unless otherwise specified)
Characteristics Withstand Insulation Voltage Resistance (input output) Capacitance (input output) Test Conditions (Relative humidity 50%) 25°C, min) (Notes 9,10) (Note (VIO Vdc) MHz, Vdc) Symbol VISO RI-O CI-O 2500 1012 Unit VRMS
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
NOTES
Derate linearly above 70°C free-air temperature rate mW/°C. Derate linearly above 70°C free-air temperature rate mW/°C. Derate linearly above 70°C free-air temperature rate mA/°C. Derate linearly above 70°C free-air temperature rate mW/°C. Logic output level occurs when VINVTH+ when VIN>VTH- once exceeds VTH+. Logic high output level occurs when VINVTH- when VIN<VTH+ once decreases below VTH-. TPHL propagation delay measured from level leading edge input pulse rise time) level leading edge output pulse. TPLH propagation delay measured trailing edges input output pulse. (Refer Fig. Common mode transient immunity logic high level maximum tolerable (positive) dVcm/dt leading edge common mode pulse signal VCM, assure that output will remain logic high state (i.e., VO>2.0 Common mode transient immunity logic level maximum tolerable (negative) dVcm/dt trailing edge common mode pulse signal, VCM, assure that output will remain logic state (i.e., VO<0.8 (Refer Fig.10) applications where dVcm/dt exceed 50,000 V/µs (Such static discharge), series resistor, RCC, should included protect detector chip from destructive surge currents. recommended value volt allowable drop (between VCC) with minimum value Device considered terminal device: Pins shorted together Pins shorted together. 2500 VRMS/1 min. capability validated kVRMS/1 sec. dielectric voltage withstand test. voltage instantaneous voltage VTH+ VTH-. typicals 25°C, unless otherwise specified.
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
TYPICAL PERFORMANCE CURVES
Fig. Logic Supply Current Operating Supply Voltage
ICCL LOGIC SUPPLY CURRENT (mA)
(Pins shorted together pins shorted together)
Fig. Input Current Input Voltage
INPUT CURRENT (mA)
(Pins Open)
(pins Open)
OPERATING SUPPLY VOLTAGE
INPUT VOLTAGE
Fig. Input Current/Low Level Output Voltage Temperature
Fig. Current Threshold/Voltage Threshold Temperature
VTH(DC) VOLTAGE THRESHOLD
(PINS
ITHVTHITH+ VTH+
Input Current, (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
Fig. Propagation Delay Temperature
Fig. Rise Fall Time Temperature
PROPAGATION DELAY (µs)
RISE TIME (µs)
TPLH TPHL
TEMPERATURE (°C)
TEMPERATURE (°C)
2003 Fairchild Semiconductor Corporation
Page
11/8/04
FALL TIME (µs)
ITH(DC) CURRENT THRESHOLD (mA)
(mV)
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
Fig. Logic High Supply Current Temperature
1000
Fig. External Threshold Characteristics V+/V-
V+/V- -EXTERNAL THRESHOLD VOLTAGE
(AC) (AC)
ICCH LOGIC HIGH SUPPLY CURRENT (nA)
OPEN
(DC)
(DC)
TEMPERATURE (°C)
EXTERNAL SERIES RESISTOR
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
Pulse Generator .1uf bypass Output Output Input (VIN) 2.5V
Pulse Amplitude Pulse Width 90%)
Fig. Switching Test Circuit
DCVO .1uf bypass
Output CL**
Switching Pos. (Min)
NOTE
Pulse (Max)
WHICH INCLUDES PROBE STRAY WIRING CAPACITANCE
Switching Pos. 3.11
Fig. Test Circuit Common Mode Transient Immunity Typical Waveforms
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
Package Dimensions (Through Hole) Package Dimensions (Surface Mount)
0.390 (9.91) 0.370 (9.40)
0.270 (6.86) 0.250 (6.35)
0.270 (6.86) 0.250 (6.35)
0.390 (9.91) 0.370 (9.40)
SEATING PLANE
0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.020 (0.51)
0.070 (1.78) 0.045 (1.14) 0.020 (0.51)
0.300 (7.62) 0.016 (0.41) 0.008 (0.20)
0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) 0.016 (0.40) 0.008 (0.20) 0.300 (7.62)
0.022 (0.56) 0.016 (0.41) 0.100 (2.54) Lead Coplanarity 0.004 (0.10)
0.045 [1.14] 0.315 (8.00) 0.405 (10.30)
Package Dimensions (0.4"Lead Spacing)
NOTE dimensions inches (millimeters)
0.270 (6.86) 0.250 (6.35)
0.390 (9.91) 0.370 (9.40)
SEATING PLANE
0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.004 (0.10)
0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) 0.016 (0.40) 0.008 (0.20) 0.400 (10.16)
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
ORDERING INFORMATION
Order Entry Identifier
Option
Description Surface Mount Lead Bend Surface Mount; Tape reel 0.4" Lead Spacing
MARKING INFORMATION
3700
Definitions
Fairchild logo Device number mark (Note: Only appears parts ordered with option order entry table) digit year code, e.g., `03' digit work week ranging from `01' `53' Assembly package code
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
Carrier Tape Specifications ("D" Taping Orientation)
12.0 ±0.1 ±0.1 ±0.1 ±0.05 1.75 ±0.10
4.90 ±0.20
0.30 ±0.05
±0.1 13.2 ±0.2 16.0 ±0.3 10.30 ±0.20
10.30 ±0.20
±0.1
User Direction Feed
Reflow Profile
Temperature (°C) peak
10-30
Time above 183C, 60-150 Ramp 3C/sec
Time (Minute) Peak reflow temperature: 225C (package surface temperature) Time temperature higher than 183C 60-150 seconds time soldering reflow recommended
2003 Fairchild Semiconductor Corporation
Page
11/8/04
AC/DC LOGIC INTERFACE OPTOCOUPLER
HCPL-3700
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
2003 Fairchild Semiconductor Corporation
Page
11/8/04

HCPL-3700 HCPL-3700 voltage/current threshold detection optocoupl

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