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9080 Data Sheet
Version 1.02 July 1997
Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408-774-9060 FAX: 408-774-2169
9080
TABLE CONTENTS
TABLE CONTENTS
GENERAL DESCRIPTION
1.1.1 1.1.2
APPLICATIONS 9080
Adapter Cards. Embedded Systems.
1.3.1 1.3.2
MAJOR FEATURES.3 COMPATIBILITY 9080 WITH 9060, 9060ES, 9060SD.4
Compatibility Register Compatibility
COMPARISON 9060, 9060ES, 9060SD, 9080.5
OPERATION.6
2.1.1 2.1.2 2.1.2.1 2.1.2.2 2.1.3
CYCLES.6
Target Command Codes. Master Command Codes Master Command Codes Direct Local Command Codes Arbitration
2.2.1 2.2.2 2.2.3
LOCAL CYCLES.7
Local Arbitration. Local Direct Master. Local Direct Slave. Ready/Wait State Control Wait State-Local Side. Wait State-PCI Side
2.2.3.1
2.2.3.1.1 2.2.3.1.2 2.2.3.2
Burst Mode Continuous Burst Mode (Bterm "Burst Terminate" Mode). Burst Mode Continuous Burst Mode (Bterm "Burst Terminate" Mode). Partial Lword Accesses
2.2.3.2.1 2.2.3.2.2 2.2.3.2.3 2.2.3.3 2.2.3.4 2.2.3.5 2.2.3.6 2.2.3.7 2.2.3.8
Recovery States Local Read Accesses Local Write Accesses Direct Slave Write Accesses-8- 16-Bit Buses. Local Data Parity Local Little/Big Endian Local Bus-Big Endian Mode Local Bus-Big Endian Mode Local Bus-Big Endian Mode
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2.2.3.8.1 2.2.3.8.2 2.2.3.8.3
©PLX Technology, Inc., 1997
9080
TABLE CONTENTS
FUNCTIONAL DESCRIPTION.12
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5
RESET
Input RST# Software Reset LRESETo# Local Input LRESETi# Local Output LRESETo# Software Reset
3.2.1 3.2.2
9080 INITIALIZATION.12
Serial EEPROM Initialization Local Initialization
3.3.1 3.3.2 3.3.3 3.3.4 3.3.5
SERIAL EEPROM
Short Serial EEPROM Load. Long Serial EEPROM Load Extra Long Serial EEPROM Load. Recommended Serial EEPROMs Programming Serial EEPROM.
3.4.1 3.4.2
INTERNAL REGISTER ACCESS
Access Internal Registers Local Access Internal Registers
3.6.1
RESPONSE FIFO FULL/EMPTY.18 DIRECT DATA TRANSFER MODES.18
Direct Master Operation (Local Master Target). Decode FIFOs. Memory Access IO/CFG Access. (PCI Configuration Type Type Cycles). Direct Master Lock. Master/Target Abort. Write Invalidate Write Invalidate Direct Master Write Invalidate. 3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.1.5 3.6.1.6 3.6.1.7 3.6.1.8 3.6.1.9
3.6.1.9.1 3.6.1.9.2 3.6.2 3.6.2.1 3.6.2.2
Direct Slave Operation (PCI Master Local Access) Mode. Local Address Mapping Byte Enables Local Initialization Software Initialization Software.
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3.6.2.2.1 3.6.2.2.2 3.6.2.2.3
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9080
3.6.2.3 3.6.2.3.1 3.6.2.3.2 3.6.2.3.3 3.6.2.4 3.6.3
TABLE CONTENTS
Deadlock BREQo. Backoff. Software/Hardware Solution Systems without Backoff Capability Software Solutions Deadlock
Direct Slave Lock. Direct Slave Priority
3.7.1 3.7.2 3.7.3
OPERATION
Non-Chaining Mode Chaining Mode DMA. Data Transfers Local Transfer. Local Transfer. Unaligned Transfers Demand Mode Priority. Arbitration Transfer (EOT0# EOT1#) Input Abort Local Latency Pause Timers.
3.7.3.1 3.7.3.2 3.7.3.3 3.7.4 3.7.5 3.7.6 3.7.6.1 3.7.6.2 3.7.6.3
3.10 3.11 3.12
VENDOR DEVICE REGISTERS DOORBELL REGISTERS MAILBOX REGISTERS.34 USER INPUT OUTPUT INTERRUPTS
Interrupts (INTA#) Local Interrupt Input. Master/Target Abort Interrupt. 3.12.1.1 3.12.1.2
3.12.1
3.12.2
Local Interrupts (LINTo#) Local Doorbell Interrupt. Local Doorbell Interrupt. Built-In Self Test Interrupt (BIST). Channel Interrupts
3.12.2.1 3.12.2.2 3.12.2.3 3.12.2.4 3.12.3 3.12.4
SERR# (PCI NMI) Local LSERR# (Local NMI).
3.13
COMPATIBLE MESSAGE UNIT
Inbound Messages Outbound Messages. Pointer Management Inbound Free List FIFO.
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3.13.1 3.13.2 3.13.3 3.13.4
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9080
3.13.5 3.13.6 3.13.7 3.13.8 3.13.9 3.13.10
TABLE CONTENTS
Inbound Post List FIFO Outbound Post List FIFO Outbound Post Queue Inbound Free Queue. Outbound Free List FIFO Enable Sequence
REGISTERS
4.1.1
REGISTER DEFINITIONS SUMMARY
Register Differences between 9080 9060, 9060ES, 9060SD.
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5
REGISTER ADDRESS MAPPING.50
Configuration Registers Local Configuration Registers. Runtime Registers Registers. Messaging Queue Registers.
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9
CONFIGURATION REGISTERS
(PCIIDR; PCI:00h, LOC:00h) Configuration Register (PCICR; PCI:04h, LOC:04h) Command Register (PCISR; PCI:06h, LOC:06h) Status Register. (PCIREV; PCI:08h, LOC:08h) Revision Register (PCICCR; PCI:09-0Bh, LOC:09-0Bh) Class Code Register. (PCICLSR; PCI:0Ch, LOC:0Ch) Cache Line Size Register (PCILTR; PCI:0Dh, LOC:0Dh) Latency Timer Register (PCIHTR; PCI:0Eh, LOC:0Eh) Header Type Register (PCIBISTR; PCI:0Fh, LOC:0Fh) Built-In Self Test (BIST) Register (PCIBAR0; PCI:10h, LOC:10h) Base Address Register Memory Accesses Local, Runtime, Registers. (PCIBAR1; PCI:14h, LOC:14h) Base Address Register Accesses Local, Runtime, Registers. (PCIBAR2; PCI:18h, LOC:18h) Base Address Register Memory Accesses Local Address Space (PCIBAR3; PCI:1Ch, LOC:1Ch) Base Address Register Memory Accesses Local Address Space (PCIBAR4; PCI:20h, LOC:20h) Base Address Register (PCIBAR5; PCI:24h, LOC:24h) Base Address Register (PCICIS; PCI:28h, LOC:28h) Cardbus Pointer Register (PCISVID; PCI:2Ch, LOC:2Ch) Subsystem Vendor Register. (PCISID; PCI:2Eh, LOC:2Eh) Subsystem Register (PCIERBAR; PCI:30h, LOC:30h) Expansion Base Register (PCIILR; PCI:3Ch, LOC:3Ch) Interrupt Line Register (PCIIPR; PCI:3Dh, LOC:3Dh) Interrupt Register (PCIMGR; PCI:3Eh, LOC:3Eh) Min_Gnt Register
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4.3.10 4.3.11 4.3.12 4.3.13 4.3.14 4.3.15 4.3.16 4.3.17 4.3.18 4.3.19 4.3.20 4.3.21 4.3.22
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9080
4.3.23
TABLE CONTENTS
(PCIMLR; PCI:3Fh, LOC:3Fh) Max_Lat Register
4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9
LOCAL CONFIGURATION REGISTERS
(LAS0RR; PCI:00h, LOC:80h) Local Address Space Range Register Local (LAS0BA; PCI:04h, LOC:84h) Local Address Space Local Base Address (Remap) Register (MARBR; PCI:08h ACh, LOC:88h 12Ch) Mode/Arbitration Register. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register. (EROMRR; PCI:10h, LOC:90h) Expansion Range Register (EROMBA; PCI:14h, LOC:94h) Expansion Local Base Address (Remap) Register BREQo Control (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion Region Descriptor Register. (DMRR; PCI:1Ch, LOC:9Ch) Local Range Register Direct Master PCI. (DMLBAM; PCI:20h, LOC:A0h) Local Base Address Register Direct Master Memory (DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register Direct Master IO/CFG. (DMPBAM; PCI:28h, LOC:A8h) Base Address (Remap) Register Direct Master Memory (DMCFGA; PCI:2Ch, LOC:ACh) Configuration Address Register Direct Master IO/CFG. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space Range Register Local Bus. (LAS1BA; PCI:F4h, LOC:174h) Local Address Space Local Base Address (Remap) Register. (LBRD1; PCI:F8h, LOC:178h) Local Address Space Region Descriptor Register.
4.4.10 4.4.11 4.4.12 4.4.13 4.4.14 4.4.15
4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9
RUNTIME REGISTERS
(MBOX0; PCI:40h 78h, LOC:C0h) Mailbox Register (MBOX1; PCI:44h 7Ch, LOC:C4h) Mailbox Register (MBOX2; PCI:48h, LOC:C8h) Mailbox Register (MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register (MBOX4; PCI:50h, LOC:D0h) Mailbox Register (MBOX5; PCI:54h, LOC:D4h) Mailbox Register (MBOX6; PCI:58h, LOC:D8h) Mailbox Register (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register (P2LDBELL; PCI:60h, LOC:E0h) Local Doorbell Register (L2PDBELL; PCI:64h, LOC:E4h) Local Doorbell Register (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register (CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, Command Codes, User Control, Init Control Register (PCIHIDR; PCI:70h, LOC:F0h) Permanent Configuration Register. (PCIHREV; PCI:74h, LOC:F4h) Permanent Revision Register
4.5.10 4.5.11 4.5.12 4.5.13 4.5.14
4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6
REGISTERS.78
(DMAMODE0; PCI:80h, LOC:100h) Channel Mode Register (DMAPADR0; PCI:84h, LOC:104h) Channel Address Register. (DMALADR0; PCI:88h, LOC:108h) Channel Local Address Register. (DMASIZ0; PCI:8Ch, LOC:10Ch) Channel Transfer Size (Bytes) Register (DMADPR0; PCI:90h, LOC:110h) Channel Descriptor Pointer Register. (DMAMODE1; PCI:94h, LOC:114h) Channel Mode Register
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4.6.7 4.6.8 4.6.9 4.6.10 4.6.11 4.6.12 4.6.13 4.6.14
TABLE CONTENTS
(DMAPADR1; PCI:98h, LOC:118h) Channel Address Register. (DMALADR1; PCI:9Ch, LOC:11Ch) Channel Local Address Register (DMASIZ1; PCI:A0h, LOC:120h) Channel Transfer Size (Bytes) Register (DMADPR1; PCI:A4h, LOC:124h) Channel Descriptor Pointer Register (DMACSR0; PCI:A8h, LOC:128h) Channel Command/Status Register (DMACSR1; PCI:A9h, LOC:129h) Channel Command/Status Register (DMAARB; PCI:ACh, LOC:12Ch) Arbitration Register. (DMATHR; PCI:B0h, LOC:130h) Threshold Register
4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9
MESSAGING QUEUE REGISTERS.84
(OPLFIS; PCI:30h, LOC:B0) Outbound Post List FIFO Interrupt Status Register. (OPLFIM; PCI:34h, LOC:B4) Outbound Post List FIFO Interrupt Mask Register. (IQP; PCI:40h) Inbound Queue Port Register. (OQP; PCI:44h) Outbound Queue Port Register (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register (IFHPR; PCI:C8h, LOC:148h) Inbound Free Head Pointer Register (IFTPR; PCI:CCh, LOC:14Ch) Inbound Free Tail Pointer Register (IPHPR; PCI:D0h, LOC:150h) Inbound Post Head Pointer Register (IPTPR; PCI:D4h, LOC:154h) Inbound Post Tail Pointer Register. (OFHPR; PCI:D8h, LOC:158h) Outbound Free Head Pointer Register. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer Register. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer Register (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer Register (QSR; PCI:E8h, LOC:168h) Queue Status/Control Register
4.7.10 4.7.11 4.7.12 4.7.13 4.7.14 4.7.15
DESCRIPTION SUMMARY COMMON MODES.90 MODE MODE OUT.96 MODE
ELECTRICAL SPECIFICATIONS.100 PACKAGE, SIGNAL, SPECS.103 PACKAGE MECHANICAL DIMENSIONS .103 TYPICAL MASTER ADAPTER.104 9080 MODES).105
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TABLE CONTENTS
TIMING DIAGRAMS.106 LIST TIMING DIAGRAMS.106 INITIALIZATION .109 MODE .112
8.3.1 Direct Slave 8.3.2 Direct Master 8.3.3 DMA.
MODE.167
8.4.1 Direct Slave 8.4.2 Direct Master 8.4.3 DMA.
MODE .181
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REVISION HISTORY
REVISION HISTORY
Date 7/3/97 Revision 7/10/97 1.01 7/24/97 1.02 Initial release. Release timing diagrams. Corrected typos matched spec. Changed Changed LARBR (Local/Arbitration Register) MARBR (Mode/Arbitration Register). hold output timings Change mechanical package dimension. Complete electrical tables Section Correct timing diagrams. Matched spec. Changed title Section Added READYo# value Table 6-6. Removed signals from Timing Diagram 8-20. Corrected titles Timing Diagrams 8-20 8-68. Corrected titles Sections 8.3.3 8.4.3. Comment
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9080
ACCELERATOR
JULY 1997 VERSION 1.02
COMPATIBLE MASTER INTERFACE CHIP ADAPTERS EMBEDDED SYSTEMS
FEATURES
Version compliant Master Interface chip adapters embedded systems Compatible Messaging Unit Volt signaling, volt core, low-power CMOS 208-pin PQFP independent channels local memory to/from host data transfers Eight programmable FIFOs zero wait state burst operation Local data transfers MB/sec Programmable local supports nonmultiplexed 32-bit address/data, multiplexed bit, slave accesses local devices Local runs asynchronously Eight mailbox doorbell registers Performs Endian/Little Endian conversion Upward compatibility with 9060/9060ES/9060SD
GENERAL DESCRIPTION
9080 provides compact, high performance master interface adapter boards embedded systems. programmable local chip configured directly connect wide variety processors, controllers memory subsystems. 9080 contains Intelligent (I2O) messaging unit that allows high performance compatible software implementations protocol specification. Users 9060, 9060ES 9060SD chips upgrade their products support I2O, Volts other features with little change existing hardware software. 9080 provides eight programmable FIFOs. Each operating mode-slave, direct, master, channel-have dedicated, independent read write FIFOs. 9080 also allows local processor configure other devices system.
Figure 1-1. Typical Adapter Block Diagram
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9080
GENERAL DESCRIPTION
Figure 1-2. 9080 Internal Block Diagram
APPLICATIONS 9080
1.1.1 Adapter Cards
Major adapter card applications 9080 include high performance communications, networking, disk control, multimedia, video adapters. 9080 moves data between host adapter local several ways. First, local host processor program controller 9080 move data between adapter memory host bus. Second, 9080 perform "Direct Master Transfers," whereby local controller accesses directly through master transfer. 9080 also supports slave transfers which another device master. Finally, 9080 contains complete messaging unit with mailbox registers, doorbell registers, queue management
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pointers that used message passing under protocol custom protocol.
1.1.2 Embedded Systems
Another application 9080 embedded systems, such network hubs routers, printer engines, industrial equipment. this configuration, four above-mentioned data transfer modes used. addition, 9080 supports Type Type configuration cycles, which allows embedded embedded system host configure other devices system.
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9080
GENERAL DESCRIPTION
Volt Volt Operation. 9080 core requires VCC. 9080 provides volt signaling bus. local operates signaling level. Serial EEPROM Interface. 9080 contains optional serial EEPROM interface that used load configuration information. This useful loading information that unique particular adapter (such Network Vendor ID). Mailbox Registers. 9080 contains eight mailbox registers that accessed from local bus. Doorbell Registers. 9080 includes doorbell registers. generates interrupts from local bus. other generates interrupts from local bus. Unaligned Transfer Support. 9080 transfer data byte boundary. Big/Little Endian Conversion. 9080 supports dynamic switching between Endian Little Endian operations Direct Slave, Direct Master, DMA, internal register accesses local side. 9080 supports on-the-fly Endian conversion Space Space expansion space. local Big/Little Endian using BIGEND# input programmable internal register configuration. When BIGEND# asserted, overwrites internal register configuration.
MAJOR FEATURES
Compliant. 9080 compliant with aspects specification v2.1. Messaging Unit. 9080 incorporates messaging unit. This enables adapter embedded system communicate with other I2O-supported devices. messaging unit fully compatible with extension specification v1.5. Dual Independent Programmable Controllers with Programmable FIFOs. 9080 provides independently programmable controllers with programmable FIFOs each channel. Each channel supports nonchaining chaining modes, demand mode DMA, Transfer (EOT) mode. Direct Master. 9080 supports memory-mapped bursts, transfer accesses, I/O-mapped singletransfer accesses from Local Master. 9080 also supports interlock (LOCK#) cycles. Read write FIFOs enable highperformance bursting. Host Capability. direct master mode, 9080 generate Type Type configuration cycles. Direct Slave. 9080 supports burst memory mapped single I/O-mapped accesses local bus. Read write FIFOs enable high-performance bursting. Programmable Local Modes. 9080 master interface chip that connects three local types, selected through mode pins. 9080 connected local with similar design with little glue logic. Table lists three modes. Table 1-1. Programmable Local Modes
Mode Description 32-bit address/32-bit data, nonmultiplexed 32-bit address/32-bit data, multiplexed 32-bit address/16-bit data, multiplexed
Note:
always Little Endian.
Read Ahead Mode. 9080 supports read ahead mode, where prefetched data read from 9080 internal FIFO instead local side. Address must subsequent previous address 32-bit aligned (next address current address Programmable Wait States. 9080 programmed keep generating wait state(s), de-asserting TRDY#, write FIFO becomes full. 9080 also programmed keep local bus. LHOLD asserted, Direct Slave Write FIFO becomes empty Direct Slave Read FIFO becomes full. local dropped either case when Local Latency Timer enabled expires.
Interrupt Generator. 9080 generate local interrupts from several sources. Clock. 9080 local interface runs from local clock generates necessary internal clocks. This clock runs asynchronously clock. There buffered clock (BPCLKo) local side use. BPCLKo connected LCLK.
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9080
GENERAL DESCRIPTION 1.3.2 Register Compatibility
registers implemented 9060/ES/SD implemented 9080. There limited number definitions several registers. Refer Section 4.1, "New Register Definitions Summary."
COMPATIBILITY 9080 WITH 9060, 9060ES, 9060SD
9080 upward compatible with 9060, 9060ES 9060SD, except noted Table Section 4.1, "New Register Definitions Summary."
1.3.1 Compatibility
When upgrading from 9060, 9060ES 9060SD, observe following definitions listed Table 1-2. Table 1-2. Compatibility
9060/ES/SD Name CLKSEL Description Serial EEPROM Clock Select Optional Serial EEPROM Clock Source Name 9080 Description
EE1MC
EESEL
Serial EEPROM Select 1=93CS46 bit) 0=93CS56 bit)
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GENERAL DESCRIPTION
COMPARISON 9060, 9060ES, 9060SD, 9080
Table 1-3. Comparison 9060, 9060ES, 9060SD, 9080
Feature Number Channel(s) Local Address Spaces Direct Master Mode Mailbox Registers Doorbell Registers FIFOs FIFO Depth-Direct Slave Write, Direct Master Write, Read Write FIFO Depth -Direct Slave Read, Direct Master Read, Read Write LLOCKo# Lock Cycles WAITI# Wait State Generation BPCLKo Pin; Buffered Clock DREQ# DACK# Pins Demand Mode Support Register Addresses 9060 Eight Lwords bytes) Lwords bytes) 9060ES Four Lwords bytes) Lwords bytes) Identical except 9060ES registers Tables were added Signals deleted: DREQ0# (pin DACK0# (pin Input signals added: WAITI# (pin BIGEND# (pin Output signals added: BPCLKo (pin 168) LLOCKo# (pin 9060SD Four Lwords bytes) Lwords bytes) (Channel only) Identical, except 9060SD register Tables 4-29 4-30 were added Signals deleted: BREQ (pin DMPAF# (pin DREQ0# (pin DACK0# (pin BTERMo# (pin Input signals added: WAITI# (pin BIGEND# (pin EOT0# (pin mode, modes) Output signals added: BPCLKo (pin 168) LLOCKo# (pin Big/Little Endian Conversion Spec. Deferred Reads Programmable Prefetch Counter Write Invalidate Cycle Additional Device Vendor Register Messaging Unit Signaling 9080 Eight Lwords (128 bytes) Lwords bytes) Identical except 9080 additional related registers 30h, 34h, 40h, were remapped Input signal added: EOT1# (pin 163) Signal changed: EESEL (pin 175)
9080 includes changes made Note: 9060, 9060ES, 9060SD.
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9080
OPERATION
Note: cannot perform configuration accesses.
OPERATION
CYCLES
9080 compliant with Specification v2.1. Refer spec specific features bus.
2.1.2.1 Master Command Codes
controllers 9080 generate memory cycles listed Table 2-2. Table 2-2. Master Command Codes
Command Type Memory Read Memory Write Memory Read Multiple Memory Read Line Memory Write Invalidate Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh) 1111 (Fh)
2.1.1 Target Command Codes
target, 9080 allows access 9080 internal registers local bus, using commands listed Table 2-1. Table 2-1. Target Command Codes
Command Type Read Write Memory Read Memory Write Memory Read Multiple Memory Read Line Memory Write Invalidate Configuration Read Configuration Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh) 1111 (Fh) 1010 (Ah) 1011 (Bh)
2.1.2.2 Direct Codes
Local
Command
direct local accesses, 9080 generates cycles listed Table through Table 2-5. Table 2-3. Local Memory Access
Command Type Memory Read Memory Write Memory Read Multiple Code (C/BE[3:0]#) 0110 (6h) 0111 (7h) 1100 (Ch) 1110 (Eh)
read write accesses 9080 byte, word, longword (Lword) accesses. memory commands aliased basic memory commands. accesses 9080 decoded Lword boundary. byte enables used determine which bytes read written. access with illegal byte enable combinations terminated with Target Abort.
Memory Read Line
Table 2-4. Local Access
Command Type Read Write Code (C/BE[3:0]#) 0010 (2h) 0011 (3h)
Table 2-5. Local Configuration Access
2.1.2 Master Command Codes
9080 access perform transfers Direct Master Local transfers. During Direct master transfer, command code assigned 9080 internal register location (PCI:6Ch)(LOC:ECh) bits [15:0] used command code (refer Table 4-59[15:0]). Table through Table list various Master Command codes.
Command Type Configuration Memory Read Configuration Memory Write
Code (C/BE[3:0]#) 1010 (Ah) 1011 (Bh)
2.1.3 Arbitration
9080 asserts output REQ# request bus. 9080 programmed using (PCI:08h PCI:ACh)(LOC:88h LOC:12Ch) (refer Table 435[23]) de-assert REQ# when asserts FRAME# during master cycle, keep REQ# asserted entire master cycle. 9080 always de-asserts
Note: Programmable internal registers determine command codes when 9080 master.
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9080
OPERATION
modes, local direct master accesses 9080 must nonpipelined bus. mode, local direct master accesses 9080 must nonpipelined bus.
REQ# minimum clocks between master ownership that includes target disconnect. Direct Master Write Delay bits (bits [15:14]) DMPBAM Register (PCI:28h)(LOC:A8h) programmed delay 9080's assertion REQ# signal during Direct Master write cycle. This register programmed wait clocks after 9080 received first write data from local master ready begin write transaction. This feature useful applications where local master bursting local clock slower than clock. This allows write data accumulate 9080's Direct Master Write FIFO, which provides better utilization.
2.2.3 Local Direct Slave
Master read/write local (PCI 9080 target local master).
2.2.3.1 Ready/Wait State Control
-"%!.
LOCAL CYCLES
9080 connects host several local processor types, listed Table 2-6. operates three modes, selected through mode pins corresponding three types-C, Table 2-6. Local Processor Types
Mode Reserved Type 32-bit nonmultiplexed 32-bit multiplexed 16-bit multiplexed
Figure 2-1. Wait States READYi# input disabled, external READYi# input effect wait states local access. Wait states between data cycles generated internally wait state counter. Wait state counter initialized with configuration register value start each data access. READYi# enabled, READYi# effect until wait state counter READYi# then controls number additional wait states. BTERM# input sampled until wait state counter BTERM# overrides READYi# when BTERM# asserted.
2.2.1 Local Arbitration
When 9080 owns local bus, both LHOLD output LHOLDA input asserted. When 9080 samples BREQ asserted during transfer Direct Slave write transfer, gives local within Lword transfers de-asserting LHOLD floating local outputs BREQ gated disabled, gating enabled Local Latency Timer expires. Local Arbiter grant local another local master. After 9080 samples that LHOLDA de-asserted local pause timer zero, re-asserts LHOLD request local bus. When 9080 receives LHOLDA, drives continues from where left off.
2.2.3.1.1 Wait State-Local Side
With Direct Master mode accessing 9080 registers (PCI 9080 local slave): 9080 generates wait states with READYo# Local processor generates wait states with WAITI#
2.2.2 Local Direct Master
Local cycles continuous single burst cycles (programmable 9080 internal registers). local target, 9080 allows access 9080 internal registers bus.
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9080
OPERATION
Note: Bterm disabled, 9080 performs following: local bus-Burst four Lwords local bus-Burst Lwords local bus-Burst Lword
With Direct Slave modes (PCI 9080 local master): 9080 generates wait states with WAITO# Local processor generates wait states with READYi# Table 4-39[21:18, 5:2], Table 4-62[5:2], Table 4-67[5:2] program number wait states
every case, performs four transactions. Note: following sections, Bterm refers 9080 internal register bit. BTERM# refers 9080 external signal.
2.2.3.1.2 Wait State-PCI Side
When wait state occurs side, Master throttles IRDY# Slave throttles TRDY#.
2.2.3.2.1 Burst Mode
2.2.3.2 Burst Mode Continuous Burst Mode (Bterm "Burst Terminate" Mode)
Table 2-7. Burst Bterm Local Side
Mode Single Cycle Single Cycle Burst-4 Burst Forever Burst Bterm Result ADS# data (default) Still ADS# data ADS# four data (use this mode i960) ADS# BTERM#
bursting enabled BTERM# input enabled, bursting start boundary continue address boundary, described Table 2-8. After data boundary transferred, 9080 generates address cycle (ADS#). Table 2-8. Burst Mode
Mode Burst 32-bit bus-Four Lwords quad Lword boundary (LA3, 16-bit bus-Four words quad word boundary (LA2, 8-bit bus-Four bytes quad byte boundary (LA1, 16-bit bus-Eight words quad Lword boundary (LA3,
local side, BLAST# BTERM# perform following: burst enabled (Table 4-39[26,24] non-DMA, Table 4-62[8] Table 4-67[8] DMA), Bterm disabled (Table 4-39[7], Table 4-62[7] Table 4-67[7]), then 9080 bursts four Lwords. BLAST# generated fourth Lword (LA[3:2]=11), ADS# first Lword (LA[3:2]=00) next burst. BTERM# sampling enabled BTERM# low, 9080 forces ADS#, does generate BLAST#. BTERM# input only valid when 9080 Master local (Direct Slave modes). BTERM# generated external logic. input 9080 (and i960) used tell 9080 (and i960) break burst cycle. BTERM# used example signal memory access crossing page boundary.
2.2.3.2.2 Continuous Burst Mode (Bterm "Burst Terminate" Mode)
Bterm mode enables 9080 perform long bursts devices that accept longer than four Lword bursts. 9080 generates address cycle continues burst data. device requires address cycle after certain address boundary, assert BTERM# input cause 9080 generate address cycle. BTERM# input acknowledges current data transfer requests that address cycle generated (ADS#). address will next data transfer. Bterm mode enabled, 9080 asserts BLAST# only FIFOs become FULL/EMPTY transfer complete.
Note: BTERM# asserted, BLAST# does assert until previously described conditions met.
side, burst always enabled.
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2.2.3.2.3 Partial Lword Accesses
9080
OPERATION
each lane during local reads from 9080 during 9080 master writes local bus. Even data parity checked during local writes 9080 during 9080 reads from local bus. Parity checked each byte lane with asserted byte enable. PCHK# asserted clock cycle following data being checked parity error detected. Generation local data parity optional. signals data parity pins effect operation 9080. parity checking generation independent local parity checking generation.
Lword accesses which byte enables asserted broken into single address data cycles, listed Table 2-9. Table 2-9. Partial Lword Accesses
Register Value (PCI:18h)(LOC:98h) Burst Enable Bterm Enable Result (Number Transfers) Single Cycle (Default) Single Cycle Burst four Lwords time Continuous Burst Mode
2.2.3.8 Local Little/Big Endian
Little Endian (that data Lword aligned lowermost byte lane). Byte (address appears AD[7:0], Byte appears AD[15:8], Byte appears AD[23:16] Byte appears AD[31:24]. 9080 local programmed operate Little Endian mode, listed Table 2-10. Table 2-10. Little Endian Program Mode
BIGEND# Register 1=Big, 0=Little Endian Little
2.2.3.3 Recovery States
modes, 9080 inserts recovery state between last data transfer next address cycle. 9080 does support 80960J feature using READYi# input recovery states. additional recovery states added READYi# input remains asserted during last data cycle.
2.2.3.4 Local Read Accesses
single cycle local read accesses, 9080 reads only bytes corresponding byte enables requested initiator. burst cycle single cycle read accesses, 9080 reads only Lwords.
2.2.3.5 Local Write Accesses
local writes, only bytes specified master 9080 controller written. Access 16-bit results Lword being broken into multiple local transfers. each transfer, byte enables encoded 80960C provide local address bits LA[1:0]. Configuration cycles, refer Table 4-36[0]. Direct Master, Memory, cycles, refer Table 436[1]. Direct Slave cycles, refer Table 4-36[2], Space Table 4-36[3], expansion ROM. Endian mode, 9080 transposes data byte lanes. Data transferred listed Table 2-11 through Table 2-15.
2.2.3.6 Direct Slave Write Accesses-8- 16-Bit Buses
Direct access 16-bit results Lword being broken into multiple local transfers. each transfer, byte enables encoded 80960C provide local address bits LA[1:0].
2.2.3.8.1 Local Bus-Big Endian Mode
Data Lword aligned uppermost byte lane. Byte lanes burst orders listed Table 2-11 illustrated Figure 2-2.
2.2.3.7 Local Data Parity
There data parity each byte lane 9080 data (DP[3:0]). Even data parity generated
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Table 2-11. Upper Lword Lane Transfer
Burst Order First Transfer Byte Lane
9080
OPERATION
Byte appears Local Data [31:24] Byte appears Local Data [23:16] Byte appears Local Data [15:8] Byte appears Local Data [7:0]
Figure 2-3. Big/Little Endian-16 Local
2.2.3.8.3 Local Bus-Big Endian Mode
local bus, 9080 programmed upper lower byte lane. Byte lanes burst order listed Table 2-14 Table 2-15 illustrated Figure 2-4. Table 2-14. Upper Byte Lane Transfer
Figure 2-2. Big/Little Endian-32 Local
2.2.3.8.2 Local Bus-Big Endian Mode
local bus, 9080 programmed upper lower word lane. Byte lanes burst order listed Table 2-12 Table 2-13 illustrated Figure 2-3. Table 2-12. Upper Word Lane Transfer
Burst Order First Transfer Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [23:16] Second Transfer Byte appears Local Data [31:24] Byte appears Local Data [23:16]
Burst Order First transfer Second transfer Third transfer Fourth transfer
Byte Lane Byte appears Local Data [31:24] Byte appears Local Data [31:24] Byte appears Local Data [31:24] Byte appears Local Data [31:24]
Table 2-15. Lower Byte Lane Transfer
Burst Order First Transfer Second Transfer Third Transfer Fourth Transfer Byte Lane Byte appears Local Data [7:0] Byte appears Local Data [7:0] Byte appears Local Data [7:0] Byte appears Local Data [7:0]
Table 2-13. Lower Word Lane Transfer
Burst Order First Transfer Byte Lane Byte appears Local Data [15:8] Byte appears Local Data [7:0] Second Transfer Byte appears Local Data [15:8] Byte appears Local Data [7:0]
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9080
OPERATION
each following transfer types, 9080 local independently programmed operate Little Endian Endian mode: Local accesses 9080 configuration registers Direct Slave accesses Local Address Space Direct Slave accesses Local Address Space Direct Slave accesses expansion Channel accesses local Channel accesses local Direct Master Accesses
Figure 2-4. Big/Little Endian-8 Local
local configuration accesses, input used dynamically change Endian mode.
Notes: always Little Endian mode. Only byte lanes swapped, individual bits.
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9080
FUNCTIONAL DESCRIPTION 3.1.3 Local Input LRESETi#
FUNCTIONAL DESCRIPTION
Functional operation described changed modified, depending register configuration.
When asserted, LRESETi# input resets local portion 9080, clears local configuration registers causes LRESETo# output asserted.
RESET
3.1.1 Input RST#
RST# input host reset. causes outputs float, resets entire 9080 causes local reset output, LRESETo#, asserted. have host, Table 4-11[2:0] (Master Enable, Memory Space, Space) programmed host after initialization complete (Table 459[31]=1). (Refer Figure 3-1.)
3.1.4 Local Output LRESETo#
LRESETo# asserted when RST# input asserted, LRESETi# input asserted, software reset Init Control Register
3.1.5 Software Reset
host software reset Init Control Register reset 9080 assert LRESETo# output. local configuration registers reset. configuration registers reset. When software reset set, 9080 responds accesses, local accesses. 9080 remains this reset condition until host clears bit.
!"#$
Note: local side cannot clear this reset because local reset state.
9080 INITIALIZATION
9080 configuration registers programmed optional serial EEPROM and/or local processor, listed Table 3-1. serial EEPROM reloaded setting (LOC:ECh), Serial EEPROM Control Register (refer Table 4-59[29]). general, 9080 retries cycles until "Local Init Done bit" low.
Note: Internal configuration register also accessed host processor after power-on.
Figure 3-1. Reset Initialization Process
3.1.2 Software Reset LRESETo#
When asserted, LRESETo# Software Reset (Table 4-59[30]) resets 9080 Local Configuration Local Registers. However, does reset Configuration Shared Runtime Registers. When set, 9080 responds accesses, local accesses. 9080 remains this condition until host clears bit. serial EEPROM reloaded Table 4-59[29] set.
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9080
FUNCTIONAL DESCRIPTION
EEPROM programmed. first word bit) ones, blank serial EEPROM 9080 uses default values instead. serial EEPROM clock (EESK, 173) derived from clock. 9080 generates serial EEPROM clock internally dividing clock serial EEPROM read programmed from local bus. Bits [27:24] Serial EEPROM Control Register (refer Table 4-59[27:24]) controls 9080 pins that enable reading writing serial EEPROM data bits. (Refer manufacturer's data sheet particular serial EEPROM being used.) 9080 three serial EEPROM load options: Short Load Mode-SHORT# input pulled down 9080 loads five Lwords from serial EEPROM Long Load Mode-SHORT# input pulled Local Region Descriptor Register (LOC:98h) 9080 loads Lwords from serial EEPROM (refer Table 4-39) Extra Long Load Mode-SHORT# input pulled Local Region Descriptor Register (LOC:98h) during Long Load from serial EEPROM, 9080 loads Lwords from serial EEPROM (refer Table 4-39)
Table 3-1. Serial EEPROM Guidelines
Serial EEPROM Programmed Blank High System Boot Condition Boot with 9080 default values. Boot with serial EEPROM values. recommended (uses default values). Local processor programs 9080 registers, then sets Local Init Status (Table 4-59[31] done).
Some systems hang Direct Note: Slave reads writes take long (during initialization, host also performs Direct Slave accesses). Value Target Retry Delay Clocks (Table 4-39[31:28]) resolve this problem.
Programmed Blank Load serial EEPROM, local processor reprogram 9080. Load serial EEPROM (default values), local processor reprogram 9080. System boot.
Serial EEPROM Note: programmed through 9080 after system boots this condition.
3.2.1 Serial EEPROM Initialization
During serial EEPROM initialization, 9080 response target accesses RETRY. During serial EEPROM initialization, 9080 response local processor hold READYo#.
3.2.2 Local Initialization
9080 issues RETRY accesses until "Local Init Done bit" Init Control Register set. "Init Done bit" programmable through local configuration accesses. this going local processor, then input should tied low. Holding input externally forces Local Init Done 9080 default values used serial EEPROM present local Init Status holding input local processor.
3.3.1 Short Serial EEPROM Load
registers listed Table loaded from serial EEPROM after reset de-asserted SHORT# low. serial EEPROM organized words bit). 9080 first loads (Most Significant Word; bits [31:16]), starting from most significant (bit 31). 9080 then loads (Least Significant Word; bits [15:0]), starting again from most significant (bit 15). Therefore, 9080 loads Device Vendor class code, forth. five 32-bit words stored sequentially serial EEPROM.
SERIAL EEPROM
After reset, 9080 attempts read serial EEPROM determine presence. active start indicates serial EEPROM present (PCI 9080 supports 93CS46 (1K) 93CS56 (2K), selectable EESEL pin). (Refer manufacturer's data sheet particular serial EEPROM being used.) first word then checked verify serial
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9080
FUNCTIONAL DESCRIPTION 3.3.2 Long Serial EEPROM Load
registers listed Table 4-39 loaded from serial EEPROM after reset de-asserted SHORT# high. serial EEPROM organized words bit). 9080 first loads (Most Significant Word; bits [31:16]), starting from most significant (bit 31). 9080 then loads (Least Significant Word; bits [15:0]), starting again from most significant (bit 15). Therefore, 9080 will load Device Vendor class code, forth. serial EEPROM value entered into DATA programmer order shown below. values shown examples must modified each particular application. 16-bit words listed table stored sequentially serial EEPROM.
Table 3-2. Short Serial EEPROM Load Registers
Serial EEPROM Offset Description Sample Serial EEPROM Value 9080 10B5 0680 0002 0000 0100 xxxx xxxx xxxx xxxx
Device Vendor Class Code Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined)
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FUNCTIONAL DESCRIPTION
Table 3-3. Long Serial EEPROM Load Registers
Serial EEPROM Offset Description Device Vendor Class Code Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Range Local Address Space Range Local Address Space Local Base Address (Remap) Local Address Space Local Base Address (Remap) Local Address Space Local Arbitration Register Local Arbitration Register Local Big/Little Endian Descriptor Register Local Big/Little Endian Descriptor Register Range Local Expansion Range Local Expansion Local Base Address (Remap) Local Expansion Local Base Address (Remap) Local Expansion Region Descriptors Local Accesses Region Descriptors Local Accesses range Direct Master range Direct Master Local Base Address Direct Master Memory Local Base Address Direct Master Memory Local Address Direct Master IO/CFG Local Address Direct Master IO/CFG Base Address (Remap) Direct Master Base Address (Remap) Direct Master Configuration Address Register Direct Master IO/CFG Configuration Address Register Direct Master IO/CFG
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9080
FUNCTIONAL DESCRIPTION 3.3.5 Programming Serial EEPROM
3.3.3 Extra Long Serial EEPROM Load
Extra Long Load mode provided 9080 (refer Table 4-39) load additional five Lwords from serial EEPROM. Local Region Descriptor Register (LOC:98h) (refer Table 4-39), following five Lword registers loaded addition normal Long Load process (refer Section 3.3.2, "Long Serial EEPROM Load"). must during Long Load Process. (Refer Table 3-4.) Table 3-4. Registers
Serial EEPROM Offset
serial EEPROM written read, using bits [28:24] Serial EEPROM Control Register (refer Table 4-59[28:24]).
INTERNAL REGISTER ACCESS
9080 chip provides several internal registers, allowing maximum flexibility interface design performance. register types accessible from both local buses, including following: configuration registers Local configuration registers Mailbox registers Doorbell registers registers Messaging queue registers (I2O)
Extra
Description
Long
Serial
EEPROM
Load
Subsystem Subsystem Vendor Range Local Address Space Range Local Address Space Local Base Address (Remap) Local Address Space Local Base Address (Remap) Local Address Space Region Descriptors (Space local accesses Region Descriptors (Space local accesses Base Address local expansion Base Address local expansion
Figure illustrates these registers accessed.
3.3.4 Recommended Serial EEPROMs
(National NM93CS46 compatible) (National NM93CS56 compatible) device used. Table lists recommended serial EEPROM loads. Refer also Table Section "Pin Description." Table 3-5. Recommended Serial EEPROM Loads
Load Short Long Extra Long Unused Bytes CS46 (1K) Unused Bytes CS56 (2K)
Figure 3-2. 9080 Internal Register Access
Note: 9080 does support serial EEPROMs that support sequential read write (such NM93C46 NM93C56).
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9080
FUNCTIONAL DESCRIPTION
Notes: must decoded while ADS# low. ADMODE LA[31:29], specify local memory space allocated accessing internal registers.
local read write accesses 9080 registers byte, word, Lword accesses. local accesses 9080 registers burst nonburst. modes, accesses must nonpipelined bus. 9080 READYo# indicates data transfer complete. mode, accesses must nonpipelined bus. 9080 READYo# indicates data transfer complete.
3.4.1 Access Internal Registers
9080 "PCI configuration registers" accessed from with configuration Type cycle. 9080 internal registers accessed memory cycle, with address that matches base address specified Base Address Memory Mapped Configuration Register 9080. They also accessed cycle, with address matching base address specified Base Address Mapped Configuration Register 9080. read write accesses 9080 registers byte, word, Lword accesses. memory accesses 9080 registers burst nonburst. 9080 responds with Disconnect burst accesses 9080 registers.
3.4.2 Local Access Internal Registers
local processor access internal registers 9080 through either internal external address decode logic. 9080 provides Address Decode Mode (ADMODE) that selects whether internal address decode logic used whether designer will supply external chip select from external address decoder. Figure illustrates dual address decode logic works. Address Decode Mode internal 9080 address decode logic enabled. this mode, 9080 internal registers selected when local address bits LA[31:29] match input address select pins S[2:0]. Address Decode Mode 9080 responds local access when asserted through external chip select logic.
Figure 3-3. Dual Address Decode Mode
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9080
FUNCTIONAL DESCRIPTION
RESPONSE FIFO FULL/EMPTY
Table lists response 9080 full empty FIFOs. Table 3-6. Response FIFO Full/Empty
Mode Direct Master Write Direct Master Read Direct Slave Write Direction Local Local Local FIFO Full Empty Full Empty Full Empty Direct Slave Read Local Full Empty Local Local Full Empty Full Empty action De-assert REQ# (off bus) De-assert REQ# throttle IRDY# action Disconnect throttle TRDY# action action Throttle TRDY# action De-assert REQ# De-assert REQ# action Side action action De-assert READYo# action De-assert LHOLD, assert BLAST# (see Note) De-assert LHOLD, assert BLAST# (see Note) action De-assert LHOLD, assert BLAST# action action De-assert LHOLD, assert BLAST# Local Side De-assert READYo#
Note:
De-assert LHOLD depends MARBR[21].
(!%1
DIRECT DATA TRANSFER MODES
Figure Figure illustrate direct data transfer modes. Refer also Table responses full empty FIFOs.
(!%1 (!%1 (!%1 (!%1 (!%1 (!%1 (!%1 (!%1
Figure 3-5. Mailbox/Doorbell Message Passing
"#!$
3.6.1 Direct Master Operation (Local Master Target)
9080 supports direct access local processor intelligent controller. Master mode must enabled Command Register. Five registers used define local access: Range Local Base Address Direct Master Memory Register Local Base Address Direct Master IO/CFG Register
Figure 3-4. Direct Master, Direct Slave,
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9080
FUNCTIONAL DESCRIPTION
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Configuration Address Register Direct Master IO/CFG Base Address
3.6.1.1 Decode
Range register specifies local address bits decoding Local access. local processor perform only memory cycles. Therefore, Local Base Address Direct Master Memory Register used decode access memory space Local Base Address Direct Master IO/CFG Register used decode access space configuration cycle access.
3.6.1.2 FIFOs
Direct Master memory access bus, 9080 Lword (128 byte) write FIFO Lword byte) read FIFO. FIFOs enable local operate independently allows highperformance bursting local buses. Direct Master Write, local processor (Master) writes data (Slave). Direct Master Read, local processor (Master) reads data from (Slave). Figure Figure illustrate FIFOs during Direct Master Write Read.
Figure 3-7. Direct Master Read
3.6.1.3 Memory Access
local processor read write memory. 9080 converts local read/write access. Local Address space starts from Direct Master Local Base Address range. Remap (PCI Base Address) defines starting address. Writes-PCI 9080 continues accept writes return READYo# until write FIFO full. then holds READYo# until space becomes available write FIFO. programmable Direct Master FIFO "almost full" status output provided (DMPAF#). Reads-PCI 9080 holds READYo# while gathering Lword from bus. Programmable prefetch modes available prefetch enabled: prefetch, continuous until Direct Master cycle ends. read cycle terminated when local BLAST# input asserted. Unused read data flushed from FIFO. 9080 does prefetch read data single cycle Direct Master reads (local BLAST# input asserted during first data phase). this case, 9080 reads single Lword. Direct Master single cycle reads, 9080 asserts same byte enables asserted local bus. multiple cycle reads, 9080 reads entire Lwords (all byte enables asserted), regardless local byte enables. prefetch limit DMPBAM (PCI:28h)(LOC:A8h) (refer Table 4-43[11]) enabled, 9080 does prefetch past boundary. Also, local side must cross boundary during burst read.
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Figure 3-6. Direct Master Write
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9080
FUNCTIONAL DESCRIPTION
write command code output with address during address cycle (refer Table 4-44). writes, local data loaded into write FIFO READYo# returned. reads, 9080 holds READYo# while gathering Lword from bus. Example 1-To perform Type configuration cycle device AD[21]. 9080 must configured allow Direct Master access buses. 9080 must also respond space accesses. These bits must (LOC:04h): Field Space Field Master Enable
9080 never prefetches beyond region specified direct master accesses.
3.6.1.4 IO/CFG Access
When Local Direct Master access made, Configuration Address Register's Configuration Enable determines configuration access made bus. Local burst accesses broken into single address/data cycles. 9080 does prefetch read data reads. Direct Master Configuration cycles, 9080 asserts same byte enables asserted local bus.
3.6.1.5
Configuration Enable clear, single access made bus. local address, remapped decode address bits local byte enables encoded provide address output with read write command during address cycle. writes, data loaded into write FIFO READYo# returned Local bus. reads, 9080 holds READYo# while gathering Lword from bus. When remap select value these address bits [31:16] forced value (refer Table 4-43[13]).
Direct Master Range selected board designer. this example, range
000FFFFFh
Value program into range register inverse 000FFFFFh, which FFF00000h: (LOC:9Ch) FFF00000h
Local Base Address Direct Master IO/CFG determined board designer. this example, 40000000h: (LOC:A4h) 40000000h
Address (Remap) Direct Master Memory Register must enable Direct Master access. This must (LOC:A8h): Field Direct Master Access Enable
3.6.1.6 (PCI Configuration Type Type Cycles)
Configuration Enable set, access made bus. addition enabling configuration (bit (PCI:2Ch)(LOC:ACh) (refer Table 4-44[31]), user must provide register information. register number (bits [7:2]) device number (bits [15:11]) must modified read/write cycle must performed before other registers devices accessed. Configuration Address Register selects Type command, bits [10:0] from register copied address bits [10:0]. Bits [15:11] ("device number") translated into single being address bits [31:11]. address bits [31:11] used device select. Type command, bits [23:0] copied from register bits [23:0] address. address bits [31:24] configuration read
must know which device configuration register configuration cycle accessing. this example, access device AD[21]. Also access Base Address Memory Mapped Configuration Register (PCI:10h). (PCI:10h) fourth register, counting from (use Table 4-5, "PCI Configuration Registers," reference). These bits must (LOC:ACh): Fields Configuration Type Fields Register number fourth register, therefore must program into this field, beginning with 000100b Fields 10:8 Function Number 000b Fields 15:11 Device Number n-11, where value AD[n]=21-11 01010b Fields 23:16 Number 00000000b Field Configuration Enable
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FUNCTIONAL DESCRIPTION
3.6.1.9.1 Write Invalidate
Write Invalidate transfers enabled when write invalidate enable controller Mode Register Memory Write Invalidate enable Command Register. Write Invalidate mode, 9080 waits until number Lwords required specified cache line size have been read from local before starting access. This ensures that complete cache line write completed ownership. target disconnects before cache line completed, 9080 completes remainder that cache line using normal writes before resuming write invalidate transfers. write invalidate cycle progress, 9080 continues burst another cache line been read from local before cycle completes. Otherwise, 9080 terminates burst waits next cache line read from local bus. final transfer complete cache line, 9080 completes transfer using normal writes.
register number (bits [7:2]) device number (bits [15:11]) must modified read/write cycle must performed before other registers devices accessed.
3.6.1.7 Direct Master Lock
9080 supports direct local exclusive accesses (locked atomic operations). locked operation must start with local input LLOCK# being asserted during Direct Master read cycle. Refer timing Section "Timing Diagrams."
3.6.1.8 Master/Target Abort
9080 Master/Target abort logic enables local master perform Direct Master poll devices determine whether devices exist (typically when local performs configuration cycles bus). Master, Target Abort, Retry Time-out encountered during transfer, 9080 asserts LSERR# enabled (refer INTCSR[1:0], Table 4-58) (can used NMI). local master waiting READYo#, asserted along with BTERMo#. local master's interrupt handler take appropriate application specific action. then clear abort bits Status configuration register (refer Table 4-12) 9080 clear LSERR# interrupt re-enable Direct Master transfers. local master attempting burst read from nonresponding device (Master/Target abort), receives READYo# BTERMo# first cycle only. local processor cannot terminate burst cycle, cause local processor hang. local must then reset from local watchdog timer asserting RESETi#. local master cannot terminate cycle with BTERMo#, should perform burst cycles when attempting determine whether device exists.
3.6.1.9.2 Direct Master Write Invalidate
Direct Master Write Invalidate transfers enabled when invalidate enable Base Address (Remap) Register Direct Master Memory Memory Write Invalidate enable Command Register (refer Table 411). Write Invalidate mode, start address Direct Maser transfer cache line boundary, 9080 waits until number Lwords required specified cache line size have been written from local before starting Write Invalidate access. This ensures that complete cache line write completed ownership. start address cache line boundary, 9080 starts normal write access. 9080 terminates cycle cache line boundary performing normal write performing Write Invalidate cycle another cache line data available. entire cache line available time 9080 regains bus, 9080 resumes Write Invalidate cycles. Otherwise, continues with normal write. target disconnects before cache line completed, 9080 completes remainder that cache line using normal writes.
3.6.1.9 Write Invalidate
9080 programmed perform write invalidate cycles Direct Master transfers. 9080 supports Write Invalidate transfers cache line sizes Lwords. size specified Cache Line Size Register. size other than specified, 9080 performs write transfers rather than Write Invalidate transfers.
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FUNCTIONAL DESCRIPTION
Figure 3-8. Local Master Direct Master Access
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FUNCTIONAL DESCRIPTION
3.6.2 Direct Slave Operation (PCI Master Local Access)
9080 supports both burst memory mapped transfer accesses I/O-mapped, single-transfer accesses local from bus. Base Address registers provided location adapter memory space. addition, local mapping registers allow address translation from address space Local Address Space. There three spaces available: Space Space Expansion space
Figure 3-9. Specification v2.1 Delayed Reads addition delayed read, 9080 supports following specification v2.1 features. write while read pending (RETRY reads) Write flush pending read
Expansion space intended support bootable device host. Each local space programmed operate bit, bit, local width. 9080 internal wait state generator external wait state input (READYi#). READYi# disabled enabled with internal configuration register. local bus, independent bus, Burst long data available (Continuous Burst mode) Burst four Lwords time Perform continuous single cycle, with without wait state(s)
9080 also supports Read Ahead mode (refer Figure 3-10), where prefetched data read from 9080 internal FIFO instead from local side. address must subsequent previous address must 32-bit aligned (next address current address
single cycle Direct Slave reads, 9080 reads single local Lword partial Lword. 9080 disconnects after transfer Direct Slave accesses. highest data transfer rate, 9080 supports posted write programmed prefetch data during Burst Read. prefetch size, when enabled, Lwords, until stops requesting. 9080 will prefetch enabled drop local after prefetch counter reached. continuous prefetch mode, 9080 prefetches long FIFO space available terminates prefetch when terminates request. read prefetching disabled, 9080 disconnects after read transfer.
3.6.2.1 Mode
9080 programmed through Local Arbitration Mode Register perform delayed reads, specified specification v2.1.
Figure 3-10. 9080 Read Ahead Mode 9080 programmed keep generating wait state(s), de-asserting TRDY#, write FIFO becomes full. 9080 also programmed keep local bus, LHOLD asserted, Direct Slave Write FIFO becomes empty Direct Slave Read FIFO becomes full. local dropped either
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FUNCTIONAL DESCRIPTION 3.6.2.2 Local Address Mapping
Note: applicable mode.
Three local address spaces-Space Space expansion ROM-are accessible from bus. Each defined three registers: Local Address Range Local Base Address Base Address
case when Local Latency Timer enabled expires. (Refer Figure 3-11 Figure 3-12.)
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fourth register, Region Descriptor Register local accesses, defines local characteristics both regions. (Refer Figure 3-13.)
3.6.2.2.1 Byte Enables
LBE[3:0]# (pins 139-142) encoded based configured width, follows:
Figure 3-11. Direct Slave Write direct slave writes, (Master) writes data local (slave). Direct Slave "Command from host," which highest priority. Direct Slave Direct Master pre-empts DMA; however, Direct Slave does pre-empt Direct Master (refer Section 3.6.2.3.1, "Backoff").
32-Bit Bus-For 32-bit bus, four byte enables indicate which four bytes active during data cycle. BE3# Byte Enable 3-LD[31:24] BE2# Byte Enable 2-LD[23:16] BE1# Byte Enable 1-LD[15:8] BE0# Byte Enable 0-LD[7:0]
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16-Bit Bus-For 16-bit bus, BE3#, BE1# BE0# encoded provide BHE#, LA1, BLE#, respectively.
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BE3# Byte High Enable (BHE#)-LD[15:8] BE2# used BE1# Address (LA1) BE0# Byte Enable (BLE#)- LD[7:0]
8-Bit Bus-For 8-bit bus, BE1# BE0# encoded provide LA0, respectively. BE3# used BE2# used BE1# Address (LA1) BE0# Address (LA0)
Figure 3-12. Direct Slave Read direct slave reads, (Master) reads data from local (Slave). 9080 supports on-the-fly Endian conversion Space Space expansion space. local Big/Little Endian either using BIGEND# input programmable internal register configuration. When BIGEND# asserted, overwrites internal register configuration.
Each Local Address space defined part reset initialization described next section.
Note:
always Little Endian.
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9080
FUNCTIONAL DESCRIPTION
Local Region Descriptor-Specifies local characteristics.
3.6.2.2.2 Local Initialization Software
Range-Specifies which address bits decoding access local space. Each bits corresponds address bit. corresponds Address Write value bits that must included decode others. Remap Local Addresses into Local Address Space-Bits this register remap (replace) address bits used decode Local Address bits.
3.6.2.2.3 Initialization Software
reset software determines much address space required writing value ones Base Address register then reading back value. 9080 return zeroes "don't care" address bits, effectively specifying address space required. software then maps Local Address space into Address space programming Base Address register. (Refer Figure 3-13.)
Figure 3-13. Direct Slave Access Local
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FUNCTIONAL DESCRIPTION 3.6.2.3 Deadlock BREQo
deadlock situation occur when master wants access 9080 local same time master local 9080 wants access bus. types deadlock situations occur: Partial Deadlock-A master local performing direct master access device other than device that concurrently trying access local bus. Full Deadlock-A master local performing direct master access same device that concurrently trying access local bus.
Example Local Address Space 12300000h through 123FFFFFh accessible from addresses 78900000h through 789FFFFFh. Local initialization software sets Range Local Base Address Registers follows: Range-FFF00000h decode upper address bits) Local Base Address (remap)-123XXXXXh (Local Base Address local accesses) (bit Space Enable bit, must recognized host)
Initialization software writes ones Base Address, then reads back again. 9080 returns value FFF00000h. software then writes Base Address register Base Address-789XXXXXh (PCI Base Address access Local Address space)
This applies only direct ("pass through") master slave accesses through 9080. Deadlock will occur transfers through 9080 controller mailboxes. partial deadlock, access local times (the Target Retry Timer, which programmable through Local Region Descriptor Register local accesses) 9080 responds with RETRY. specification requires that master release request (de-asserts REQ#) minimum clocks after receiving RETRY. This allows arbiter grant 9080 that complete direct master access free local bus. Possible solutions described below cases which arbiter does function described (PCI architecture dependent), waiting time-out undesirable, full deadlock condition exists. full deadlock, only solution back local master.
direct access local bus, 9080 Lword (128 byte) write FIFO Lword byte) read FIFO. FIFOs enable local operate independently bus. 9080 programmed return RETRY response throttle TRDY# transaction attempting write 9080 local when FIFO full. read transactions from 9080 local bus, 9080 holds TRDY# while gathering local Lword returned. read accesses mapped memory space, 9080 prefetches Lwords (has continuous prefetch mode) from local bus. Unused read data flushed from FIFO. read accesses mapped space, 9080 does prefetch read data. Rather, breaks each read burst cycle into single address/data cycle local bus. period time 9080 holds TRDY# programmed, Target Retry Timer, Local Region Descriptor Register (refer Table 4-39). 9080 issues RETRY transaction master when programmed time period expires. This occurs when 9080 cannot gain control local return TRDY# within programmed time period.
3.6.2.3.1 Backoff
9080 contains (BREQo) that indicates possible deadlock condition exists. 9080 starts BREQo timer (programmable through registers) when detects following conditions: master trying access memory device local gaining access (for example, LHOLDA received). master local performing direct master read access master local performing direct master write access 9080's direct master write FIFO cannot accept another write cycle.
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3.6.2.3.3 Software Solutions Deadlock
host software local software combination mailbox registers, doorbell registers, interrupts, direct local accesses direct local accesses avoid deadlock.
timer expires 9080 received LHOLDA, 9080 asserts BREQo. External logic this signal perform backoff. backoff cycle device/bus architecture dependent. External logic (arbiter) assert necessary signals cause local master release local (backoff). After backing local master, grant 9080 asserting LHOLDA). Once BREQo asserted, READYo# current data cycle will never asserted (the local master must perform backoff). When 9080 detects LHOLDA, proceeds with master local access. When this access complete 9080 releases local bus, external logic release backoff local master resume cycle that interrupted backoff cycle. write FIFO 9080 retains data acknowledged (i.e. last data which READYo# asserted). After backoff condition ends, local master restarts last cycle with ADS#. writes, data following this ADS# should data that acknowledged 9080 prior backoff cycle (for instance, last data which there READYo# asserted). read cycle completed when local backed off, local master receives that data local master restarts same last cycle. (Data read twice). read performed, resumed local cycle same backed cycle.
3.6.2.4 Direct Slave Lock
9080 supports direct local exclusive accesses (locked atomic operations). locked operation local results entire address space space expansion space being locked until they released master. 9080 asserts LLOCKo# during first clock atomic operation (address cycle) de-asserts minimum clock, following last access atomic operation. LLOCKo# de-asserted after 9080 detects FRAME# LOCK# de-asserted same time. Refer timing diagrams Section "Timing Diagrams." Locked operations enabled disabled with Local Region Descriptor Register local accesses. responsibility external arbitration logic monitor LLOCKo# enforce meaning atomic operation. example, local master initiates locked operation, local arbiter choose grant local other masters until locked operation complete.
3.6.3 Direct Slave Priority
3.6.2.3.2 Software/Hardware Solution Systems without Backoff Capability
adapters that support backoff, possible deadlock solution follows. host software, external local hardware, general purpose output USERO general purpose input (USERI) used host software prevent deadlock. USERO request that external arbiter grant local master except 9080. status output from local arbiter connected general purpose input USERI indicate that local master owns local bus. input read host determine that local master currently owns local bus. host then perform direct slave access. When host done, clears USERO. devices that support preempt, USERO used preempt current master device. current local master device completes current cycle gives local (de-asserts LHOLD). Direct Slave accesses have higher priority than accesses. Direct Slave accesses preempt transfers. When 9080 controller owns local bus, LHOLD output LHOLDA input asserted LDSHOLD output de-asserted. When Direct Slave access occurs, 9080 gives local within Lword transfers de-asserting LHOLD floating local outputs. After 9080 samples LHOLDA input de-asserted, requests local Direct Slave transfer asserting LHOLD LDSHOLD. When 9080 receives LHOLDA, drives performs Direct Slave transfer. Upon completion Direct Slave transfer, 9080 gives local de-asserting both LHOLD LDSHOLD floating local outputs. After 9080 samples LHOLDA de-asserted local pause timer zero, requests local transfer re-asserting LHOLD. When receives LHOLDA, drives continues with transfer.
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direction. host local processor then sets control initiate transfer. 9080 will arbitrate local buses transfer data. Once transfer complete, 9080 sets "channel done" value generates interrupt local processor host (programmable). done internal register pooled indicate status transfer. registers accessible from local bus. (Refer Figure 3-14.)
OPERATION
9080 supports independent channels capable transferring data from local from local bus. Each channel consists controller programmable FIFO. Both channels support chaining non-chaining transfers, Demand Mode DMA, Transfer (EOT) pins. Master mode must enabled Command register.
3.7.1 Non-Chaining Mode
host processor local processor sets local address, address, transfer count transfer
""-'
Figure 3-14. Non-Chaining Initialization
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FUNCTIONAL DESCRIPTION
local processor requires DMA. 9080 master both local buses. Direct Slave Direct Master pre-empts DMA. 9080 releases following occurs (refer Figure 3-15):
Terminal count reached Latency Timer (PCI:0Dh)(LOC:0Dh) expires (refer Table 4-16[7:0])-normally programmed Host BIOS- GNT# de-asserts host asserts STOP Direct Master request pending
Figure 3-16. DMA, Local
3.7.2 Chaining Mode
Chaining mode DMA, Host Processor Local Processor sets descriptor blocks local host memory that composed address, local address, transfer count, transfer direction, address next descriptor block (refer Figure 3-18). Host Local Processor then sets address initial descriptor block descriptor pointer register 9080 initiates transfer setting control bit. 9080 loads first descriptor block initiates data transfer. 9080 continues load descriptor blocks transfer data until detects chain next descriptor pointer register. 9080 programmed interrupt local processor setting "Interrupt after Terminal Count" host upon completion each block transfer after block transfers complete (done) (refer Figure 3-17). chaining descriptors located local memory, controller programmed clear transfer size completion each DMA. (Refer Clear Count mode, Table 4-62[16] Table 4-67[16].)
Figure 3-15. DMA, Local 9080 releases local following occurs (refer Figure 3-16): FIFO empty Terminal count reached Local Latency Timer (PCI:08h PCI:ACh) (LOC:88h LOC:12Ch) expires (refer Table 4-35[7:0]) BREQ# input asserted Direct Slave request pending
Notes: Chaining mode DMA, descriptor includes address, local address, transfer size next descriptor pointer. (PCI:84h, location 104-PCI:90h, location 110D). descriptor pointer register contains chain bit, direction transfer, next descriptor address, next descriptor location. descriptor local memory memory, both (first descriptor local memory, second descriptor memory).
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FUNCTIONAL DESCRIPTION
""-'
""-'
Figure 3-17. Chaining Initialization
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FUNCTIONAL DESCRIPTION 3.7.3 Data Transfers
9080 controller programmed transfer data from local side side from side local side. Refer Figure 3-19 Figure 3-20 description operation.
Figure 3-18. Chaining Mode from Local
3.7.3.1 Local Transfer
/""+1
/""+1
,(%9
Figure 3-19. Local Data Transfer Operation
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3.7.3.2 Local Transfer
"#$/
Figure 3-20. Local Data Transfer Operation
3.7.3.3 Unaligned Transfers
unaligned local transfers, 9080 reads partial Lword from local bus. continues read Lwords from local bus. Lwords assembled, aligned address loaded into FIFO. local transfers, Lwords read from loaded into FIFO. local side, Lwords assembled from FIFO, aligned local address written local bus. both local buses, byte enables writes determine LA[1:0] start transfer. last transfer, byte enables specify bytes written. reads Lwords.
transferred after controllers DREQ[1:0]# input de-asserted. BLAST# output required last Lword transfer (bit controller releases data after receives external READYi# internal wait state counter decrements value current Lword. controller currently bursting data, which last data phase burst, BLAST# output will asserted. BLAST# output required last Lword transfer (bit controller transfers Lwords. DREQ[1:0]# de-asserted during address phase first transfer 9080 local ownership (ADS#, LHOLDA asserted), controller completes current Lword. DREQ[1:0]# de-asserted during phase other than address phase first transfer 9080 local ownership, controller completes current Lword, additional Lword (this allows BLAST# output asserted during final Lword). FIFO full/empty after data phase which
3.7.4 Demand Mode
Mode Register (BLAST mode demand mode DMA), determines number Lwords
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FUNCTIONAL DESCRIPTION
last data phase burst, BLAST# output will asserted. BLAST# output required last Lword transfer (bit controller transfers Lwords. EOT[1:0]# asserted, controller completes current Lword, additional Lword (this allows BLAST# output asserted during final Lword). FIFO full/empty after data phase which EOT[1:0]# asserted, second Lword transferred. controller terminates transfer Lword boundary after EOT[1:0]# asserted. 8-bit bus, 9080 terminates after last byte Lword transferred. 16-bit bus, 9080 terminates after last word Lword transferred.
DREQ[1:0]# de-asserted, second Lword transferred. DREQ[1:0]# controls only number Lword transfers. 8-bit bus, 9080 gives after last byte Lword transferred. 16-bit bus, 9080 gives after last word Lword transferred.
3.7.5 Priority
Channel priority, Channel priority, rotating priority specified Arbitration Register.
3.7.6 Arbitration
9080 controller releases control local (de-asserts LHOLD) when following occurs: FIFOs full local transfer FIFOs empty local transfer Local Latency Timer expires enabled) BREQ input asserted (BREQ enabled disabled, gated with latency timer before 9080 gives local bus) Direct Slave access pending input received enabled)
3.7.6.2 Abort
transfer aborted. abort process follows: Channel must enabled (Table 4-72[0]=1). Channel must started (Table 4-72[1]=1). Wait Channel Done zero (Table 4-72[4]=0). Disable Channel (Table 4-72[0] =0). Abort programming Channel Abort (Table 4-72[2]=1). Wait until Channel Done (Table 472[4]=1).
controller releases control when following occurs: FIFOs full empty Latency Timer expires loses grant signal Target Disconnect response received
Note: data transfers occur after abort set. Aborting when cycles progress causes next abort.
3.7.6.3 Local Latency Pause Timers
Local Latency Timer Local Pause Timer programmable with Arbitration Register. local latency timer expires, 9080 completes current Lword transfer releases LHOLD. After programmable Pause Timer expires, reasserts LHOLD. When receives LHOLDA, continues transfer. transfer continues until FIFO empty local transfer until full local transfer.
controller de-asserts request (REQ#) minimum clocks.
3.7.6.1 Transfer (EOT0# EOT1#) Input
Mode Register (BLAST mode EOT), determines number Lwords transferred after controller EOT[1:0]# input asserted. BLAST# output required last Lword transfer (bit controller releases data terminates after receives external READYi# internal wait state counter decrements value current Lword. controller currently bursting data, which
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VENDOR DEVICE REGISTERS
Three Vendor Device registers supported: (LOC:00h), which contains normal Device Vendor IDs. This register loaded from serial EEPROM from local processors. (LOC:2Ch), which contains Subsystem Subvendor IDs. This register loaded from serial EEPROM from local processors. (LOC:F0h), which contains hardcoded Vendor Device IDs.
3.10 MAILBOX REGISTERS
There eight mailbox registers 9080 that written read from both buses. These registers used pass command status information directly between local devices. local interrupt generated, enabled, when host writes first four mailbox registers.
3.11 USER INPUT OUTPUT
9080 supports user input output pins, USERI (pin USERO (pin 27), respectively. User output data logged writing (LOC:ECh). User input data read from (Refer Table 4-59.)
DOORBELL REGISTERS
There doorbell interrupt/status registers 9080. assigned interface other assigned local interface. local processor generate interrupt writing number other than zeroes Local Doorbell Register (refer Table 4-56). host generate local interrupt writing number other than zeroes Local Doorbell Register (refer Table 4-57).
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FUNCTIONAL DESCRIPTION
3.12 INTERRUPTS
Parity Error Master Abort Retrys Target Abort Messaging Queue
[12]
Done Terminal Count Doorbells
LSERR#
[17]
Mailboxes Done Terminal Count Doorbells Master Abort Retrys Target Abort LINTi#
[11] [12] [10]
[16]
LINTo#
BIST
[23]
Messaging Queue
Done Terminal Count
INTA#
represent register (LOC [E8h]) Bits [7:6] register (LOC [168h]) register (LOC [100h]) register (LOC [E110h]) register (LOC [E8h]) register (LOC [100h]) Bits [5:4] register (LOC [168h]) register (LOC [114h]) register (LOC [124h]) register (LOC [E8h]) register (LOC [114h]) register (LOC [B0h]) register (LOC [B4h])
Messaging Queue Done Terminal Count
17='0', then LINTo# generated 17='1', then INTA# generated.
Figure 3-21. Interrupt Error Sources
3.12.1 Interrupts (INTA#)
9080 Interrupt (INTA#) generated following: Local Doorbell Register Local interrupt input Master/target abort status condition 0/Ch Done 0/Ch Terminal Count reached Messaging Outbound Post Queue empty
3.12.1.1 Local Interrupt Input
Asserting local input LINTi# generate interrupt. host processor read 9080 Interrupt Control/Status Register determine that interrupt pending LINTi# being asserted. interrupt remains asserted long LINTi# asserted Local Interrupt input enabled. Adapter specific action taken host processor cause local release LINTi#.
INTA#, individual sources interrupt, enabled disabled with 9080 Interrupt Control/Status Register (refer Table 4-58). This register also provides interrupt status each interrupt source. 9080 interrupt level output. interrupt cleared disabling interrupt enable clearing cause(s) interrupt.
3.12.1.2 Master/Target Abort Interrupt
9080 sets master abort target abort status configuration register when detects master target abort. These status bits cause INTA# asserted interrupts enabled. interrupt remains asserted long master target abort bits remain Status configuration register (refer Table 4-12) master/target abort interrupt enabled. Type configuration access local access clear
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FUNCTIONAL DESCRIPTION 3.12.2.2 Local Doorbell Interrupt
master generate local interrupt writing Local Doorbell Register (refer Table 4-56). Local processor then read 9080 Interrupt Control/Status Register (refer Table 458) determine that doorbell interrupt pending. then read 9080 Local Doorbell Register. Each Local Doorbell Register individually controlled. Bits Doorbell Register only side. From side, writing position sets that writing position effect. Bits Local Doorbell Register only cleared from local side. From local side, writing position clears that writing position effect.
master abort target abort interrupt bits Status configuration register. Bits [26:24] Interrupt Control/Status Register (refer Table 4-58) latched time target abort interrupt master abort interrupt. They provide information master when abort occurred. 9080 updates these bits whenever abort occurs.
3.12.2 Local Interrupts (LINTo#)
9080 Local Interrupt (LINTo#) generated following: Local Doorbell/Mailboxes Register access BIST interrupt, done interrupt terminal count reached abort interrupt messaging outbound post queue empty
Note: local side cannot clear Doorbell Interrupt, Local Doorbell Register.
interrupt remains asserted long Local Doorbell Register bits Local Doorbell interrupt enabled. prevent race conditions when local accessing Doorbell Register configuration register), 9080 automatically issues RETRY bus.
LINTo#, individual sources interrupt, enabled disabled with 9080 Interrupt Control/Status Register (refer Table 4-58). Interrupt Control/Status Register also provides interrupt status each source interrupt. 9080 local interrupt level output. interrupt cleared disabling interrupt enable source clearing cause interrupt.
3.12.2.3 Built-In Self Test Interrupt (BIST) 3.12.2.1 Local Doorbell Interrupt
local master generate interrupt writing Local Doorbell Register (refer Table 4-57). host processor then read 9080 Interrupt Control/Status Register (refer Table 4-58) determine that doorbell interrupt pending. then read 9080 Local Doorbell Register. Each Local Doorbell Register individually controlled. Bits Doorbell Register only local side. From local side, writing position sets that writing position effect. Bits Local Doorbell Register only cleared from side. From side, writing position clears that writing position effect. interrupt remains asserted long Local Doorbell Register bits Doorbell interrupt enabled. prevent race conditions when accessing Doorbell Register configuration register), 9080 automatically de-asserts READYo# prevent local accesses. master generate local interrupt performing Type configuration write BIST Register. local processor then read 9080 Interrupt Control/Status Register (refer Table 4-58) determine that BIST interrupt pending. interrupt remains asserted long BIST interrupt enabled. local then resets when BIST complete. Host software fail device reset after seconds.
Note:
9080 does have internal BIST.
3.12.2.4 Channel Interrupts
channel generate local interrupt when done (transfer complete) after transfer complete descriptor chaining mode. mode register determines whether generate local interrupt. local processor then read 9080 Interrupt Control/Status Register (refer Table 4-58) determine whether channel interrupt pending.
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FUNCTIONAL DESCRIPTION
LSERR# abort parity error. LSERR# level output that remains asserted long Abort Parity Error Status bits set.
Done Status Control/Status Register used determine whether interrupt done interrupt result transfer descriptor chain that complete
3.13 COMPATIBLE MESSAGE UNIT
Messaging Unit supplies paths messages, inbound FIFOs receive messages from primary outbound FIFOs pass messages primary bus. Refer Architecture Specification v1.5 details. Figure 3-22 Figure 3-23 illustrate information about architecture.
Mode Register channel enables done interrupt. chaining mode, Next Descriptor Pointer Register channel (loaded from local memory) specifies whether generate interrupt transfer current descriptor. channel interrupt cleared writing Clear Interrupt Command/Status Register (refer Table 4-72[3] Table 4-73[3]).
3.12.3 SERR# (PCI NMI)
9080 generates SERR# pulse parity checking enabled Command Register detects address parity error Generate SERR# Interrupt Control/Status Register (refer Table 4-58) written. SERR# output enabled disabled with Command Register.
3.12.4 Local LSERR# (Local NMI)
LSERR# interrupt output asserted following occurs: Target Abort Master Abort status Status configuration register Parity error status Status configuration register Messaging outbound free queue overflows
Figure 3-22. System Architecture
parity error checking enabled Command Register, 9080 sets Master Detected Parity Error Status Status configuration register (refer Table 4-12) detects following: Parity error during 9080 master read signal PERR# being asserted during 9080 master write
9080 sets parity error Status configuration register (refer Table 4-12) detects following: Data parity error during 9080 master read Data parity error during slave write access 9080 Address parity error
Figure 3-23. Software Architecture
9080 Interrupt Control/Status Register (refer Table 4-58) used individually enable disable
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SECTION 3.13.1 Inbound Messages
9080
FUNCTIONAL DESCRIPTION
Table 3-7. Queue Starting Address
FIFO Inbound Free List Inbound Post List Outbound Post List Outbound Free List Starting Address QBAR QBAR FIFO Size) QBAR FIFO Size) QBAR FIFO Size)
Inbound messages reside pool message frames (minimum 64-byte frames) allocated shared local (IOP) memory. inbound message queue comprised pair rotating FIFOs implemented local memory. Inbound Free List FIFO holds message frame addresses (MFA) available message frames local memory. Inbound Post List FIFO holds currently-posted messages. inbound circular FIFOs accessed external agents through Inbound Queue Port location address space. Inbound Queue Port, when read external agent, returns Inbound Free List FIFO MFA. external agent places message frame into Inbound Post List FIFO writing inbound queue port location.
3.13.3 Pointer Management
FIFOs always reside shared local (IOP) memory allocated initialized IOP. Before enabling (Messaging Queue Configuration Register local processor must initialize Inbound Post Free Head Pointer Registers, Inbound Post Free Tail Pointer Registers, Outbound Post Free Head Pointer Registers, Outbound Post Free Tail Pointer Registers with initial offset according configured FIFO size. Messaging Unit automatically adds Queue Base Address offset each head tail pointer register. software then enable I2O. After initialization, local software should write pointers managed hardware. empty flags queues disabled (MQCR head tail pointers equal. This occurs independently head tail pointers set. empty flag cleared, signifying empty, only queues enabled pointers become equal. empty flag cleared queues enabled, empty flag will only tail pointer incremented head tail pointers become equal. Full flags always cleared when queues disabled head tail pointers equal. full flag when queues enabled, head pointer incremented, head tail pointers become equal. Each circular FIFO head pointer tail pointer, which offsets from Queue Base Address. Writes FIFO occur head FIFO reads occur from tail. head tail pointers incremented either local processor hardware. unit that writes FIFO also maintains pointer. pointers incremented after FIFO access. Both pointers wrap around first address circular FIFO when they reach FIFO size, that head tail pointers "chase" each other around around circular FIFO. wraps pointers automatically pointers that maintains. software must wrap pointers that maintains. Whenever they equal, FIFO empty. prevent overflow conditions,
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3.13.2 Outbound Messages
Outbound messages reside pool message frames (minimum 64-byte frames) allocated shared (Host System) memory. outbound message queue comprised pair rotating FIFOs implemented local memory. Outbound Free List FIFO holds message frame addresses (MFA) available message frames system memory. Outbound Post List FIFO holds currently posted messages. outbound circular FIFOs accessed external agents through Outbound Queue Port location address space. Outbound Queue Port, when read external agent, returns Outbound Post List FIFO MFA. external agent places free message frames into Outbound Free List FIFO writing free into Outbound Queue Port location. Memory circular FIFOs themselves must allocated local (IOP) memory. queues base address contained Queue Base Address Register (QBAR). Each FIFO entry data value. Each read write queue must single 32-bit access. circular FIFOs range size from entries entries. four FIFOs must same size contiguous. Therefore, total amount local memory needed circular FIFOs ranges from FIFO size specified Messaging Queue Configuration Register (MQCR) (refer Table 4-79). starting address each FIFO based Queue base Address FIFO Size, listed Table 3-7.
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FUNCTIONAL DESCRIPTION 3.13.4 Inbound Free List FIFO
local processor allocates inbound message frames shared memory place address free (available) message frame into Inbound Free List FIFO writing into FIFO location pointed Queue Base Register Inbound Free Head Pointer Register. local processor must then increment Inbound Free Head Pointer Register. master (Host another IOP) obtain free message frame reading Inbound Queue Port Address (40h first Memory Base Address Register). FIFO empty free inbound message frames currently available, head tail pointers equal), returns value (FFFFFFFFh). FIFO empty (head tail pointers equal), reads pointed Queue Base Register Inbound Free Tail Pointer Register, returns value increments Inbound Free Tail Pointer Register. Inbound Free Queue empty, queue prefetching enabled (QSR Register next entry FIFO read from local into prefetch register. prefetch register then provides data next read from this queue, thus reducing number wait states.
specifies that number message frames allocated should less than equal number entries FIFO. (Refer Figure 3-24 additional information.) Each inbound specified offset from start shared local (IOP) memory region start message frame. Each outbound specified offset from Host memory location 0x00000000h start message frame shared Host memory. Since actual address, message frames need contiguous. allocates initializes inbound message frames shared memory using suitable memory allocation technique. Host allocates initializes outbound message frames shared Host memory using suitable memory allocation technique. Message frames minimum bytes length. uses "push" (write preferred) memory model. That means that will write messages data shared Host memory, Host will write messages data shared memory. Software should make burst transfers whenever possible ensure efficient message passing. Additional information message passing implementation found Architecture Specification v1.5.
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High Address Local Memory
FUNCTIONAL DESCRIPTION
Write External Agent Read Outbound Queue Port Outbound Free List FIFO Incremented 9080 hardware Head Pointer Tail Pointer
Incremented local processor
Local Processor
Read
Outbound Queue
Write Outbound Post List FIFO Incremented local processor Head Pointer Tail Pointer
Incremented 9080 hardware
Write External Agent Read Inbound Queue Port Inbound Post List FIFO Incremented 9080 hardware Head Pointer Tail Pointer
Incremented local processor
Local Processor
Read
Inbound Queue
Write Inbound Free List FIFO Incremented local processor Head Pointer Tail Pointer
Incremented 9080 hardware Address Local Memory
Figure 3-24. Circular FIFO Operation
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SECTION 3.13.5 Inbound Post List FIFO
9080
FUNCTIONAL DESCRIPTION
returns value increments Outbound Post Tail Pointer Register. 9080 generates Interrupt when Outbound Post Head Pointer Register equal Outbound Post Tail Pointer Register. Outbound Post List FIFO Interrupt Outbound Post List FIFO Interrupt Status (OPLFIS) Register indicates interrupt status. When pointers become equal, both interrupt Outbound Post List FIFO interrupt automatically cleared. pointers become equal when master (Host another IOP) reads enough FIFO entries empty FIFO. interrupt masked Outbound Post List FIFO Interrupt Mask (OPLFIM) Register).
master (Host another IOP) write message into available message frame shared local (IOP) memory. then post that message writing message frame address (MFA) Inbound Queue Port Address (40h first Memory Base Address Register). When port written, writes Inbound Post List FIFO location pointed Queue Base Register FIFO Size Inbound Post Head Pointer Register. After writes Inbound Post List FIFO, increments Inbound Post Head Pointer Register. Inbound Post Tail Pointer Register points Inbound Post List FIFO location which holds oldest posted message. tail pointer maintained local processor. After local processor reads oldest MFA, remove from Inbound Post List FIFO incrementing Inbound Post Tail Pointer Register. 9080 generates local Interrupt when Inbound Post List FIFO empty. Inbound Post List FIFO Interrupt Queue Status/Control Register (QSR) indicates interrupt status. interrupt clears when Inbound Post List FIFO empty. interrupt masked Inbound Post List FIFO Interrupt Mask (refer Table 4-89[4]). prevent race conditions from time write transaction received until data written local memory Inbound Post Head Pointer Register incremented, direct slave access 9080 issued RETRY.
3.13.7 Outbound Post Queue
reduce read latency, prefetching from tail queue occurs whenever queue empty tail pointer incremented (queue been read from), when queue empty head pointer incremented (queue been written to). When host reads Outbound Post Queue, data immediately available.
3.13.8 Inbound Free Queue
reduce read latency, prefetching from tail queue occurs whenever queue empty tail pointer incremented (queue been read from), when queue empty head pointer incremented (queue been written to). When host reads Inbound Free Queue, data immediately available.
3.13.6 Outbound Post List FIFO
local master (IOP) write message into available message frame shared Host memory. then post that message writing message frame address (MFA) Outbound Post List FIFO location pointed Queue Base Register Outbound Post Head Pointer Register FIFO Size). local processor should then increment Outbound Post Head Pointer Register. master obtain oldest posted message reading Outbound Queue Port Address (44h first Memory Base Address Register). FIFO empty more outbound messages posted, head tail pointers equal), returns value (FFFFFFFFh). Outbound Post List FIFO empty (head tail pointers equal), reads pointed Queue Base Register FIFO Size) outbound Post Tail Pointer Register,
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3.13.9 Outbound Free List FIFO
master (Host another IOP) allocates outbound message frames shared memory place address free (available) message frame into Outbound Free List FIFO writing message frame address (MFA) Outbound Queue Port Address (44h first Memory Base Address Register). When port written, writes Outbound Free List FIFO location pointed Queue Base Register FIFO Size) Outbound Free Head Pointer Register. After writes Outbound Free List FIFO, increments Outbound Free Head Pointer Register. When needs free outbound message frame, must first check whether free frames available. Outbound Free List FIFO empty (outbound free head tail pointers equal), must wait Host place additional outbound free message frames
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FUNCTIONAL DESCRIPTION
FIFO. When head pointer incremented becomes equal tail pointer, Outbound Free List FIFO full, generates local LSERR (NMI) interrupt. interrupt recorded Queue Status Control (QSR) Register. From time that write transaction received until data written into local memory Outbound Free Head Pointer Register incremented, direct slave access 9080 issued RETRY.
Outbound Free List FIFO. Outbound Free List FIFO empty (head tail pointers equal), obtain oldest free outbound message frame reading location pointed Queue Base Register FIFO Size) Outbound Free Tail Pointer Register. After reads MFA, must increment Outbound Free Tail Pointer Register. prevent overflow conditions, specifies that number message frames allocated should less than equal number entries FIFO. also checks overflows Outbound Free List Table 3-8. Circular FIFO Summary
FIFO Name Inbound Free List FIFO Inbound Post List FIFO Outbound Post List FIFO Outbound Free List FIFO Port Inbound Queue Port (Host read) Inbound Queue Port (Host write) Outbound Queue Port (Host read) Outbound Queue Port (Host write) Generate Interrupt? Yes, when FIFO empty
Generate Local Interrupt Yes, when Port written Yes, (LSERR) when FIFO full
Head Pointer Maintained Local processor hardware Local processor hardware
Tail Pointer Maintained hardware Local processor hardware Local processor
3.13.10 Enable Sequence
enable I2O, local processor should perform following: Initialize Space address range Initialize FIFOs message frame memory class code Register (PCI:09h-0Bh) device with programming interface enable Local Init Done enable Queue Status Register (LOC: 168h; Table 4-89) causes remapping resources mode. When this set, memory mapped configuration registers (such queue ports 44h) Space share PCIBAR0 (PCI:10h, LOC:10h; Table 4-19). accesses offset 00h-FFh PCIBAR0 will result accesses internal configuration registers 9080. Accesses above offset PCIBAR0 will result local space accesses beginning offset 100h from Local Space Remap Register (LAS1BA, LOC:174h; Table 446). Therefore space located offset 00h-FFh from LAS1BA addressable PCIBAR0.
Note: must pulled 9080 issues retries accesses until Local Init Done register (LOC:ECh) (refer Table 4-59) local processor.
Programmer's Note: Because accesses offset 00h-FFh PCIBAR0 result internal configuration accesses, Inbound Free MFAs must greater than FFh.
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9080
REGISTERS
REGISTERS
REGISTER DEFINITIONS SUMMARY
Refer descriptions following sections full explanation. Table 4-1. Registers Definitions Summary
Offset Local Offset 12Ch Register MARBR Bits LBRD0 DMPBAM 15:14 OPLFIS OPLFIM INTCSR 31:28 100h DMAMODE0 114h DMAMODE1 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h 170h 174h 178h MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OPHPR OPTPR LAS1RR LAS1BA LBRD1 Description PCIREQMODE output. Read Ahead mode. Single read mode removed. Extend almost full flag five bits (fifth contiguous). CDMPFLIMIT output; prefetch past boundary Direct master read prefetch size control. Remap select. Direct master write delay. outbound post list FIFO Interrupt Status Register. outbound post list FIFO Interrupt Mask Register. inbound queue port register. outbound queue port register. Move DMA0INTSEL output DMAMODE0. Change reserved. Move DMA1INTSEL output DMAMODE1. Change reserved. Mailbox interrupt enable 9060. Mailbox interrupts 9060. Clear byte count chaining descriptor. C0_INTSEL output. 0=local int., 1=PCI int. Clear byte count chaining descriptor. C1_INTSEL output. 0=local int., 1=PCI int. messaging queue configuration register. queue base address register. inbound free head pointer. inbound free tail pointer. inbound post head pointer. inbound post tail pointer. outbound free head pointer. outbound free tail pointer. outbound post head pointer. outbound post tail pointer. queue status register. Local Address Space Range Register local. Local Address Space Local Base Address (Remap). Local Address Space Region Descriptor.
©PLX Technology, Inc., 1997
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REGISTERS
4.1.1 Register Differences between 9080 9060, 9060ES, 9060SD
Table 4-2. Register Differences between 9080 9060
Register PCIIDR PCICR PCISR PCICLSR PCIBAR0 PCIBAR1 PCIBAR3 PCISVID PCISID MARBR PCI/Local Offset 00/00 04/04 06/06 0C/0C 10/10 14/14 1C/1C 2C/2C 2E/2E AC/88, Bits 31:16 31:0 15:0 15:0 31:0 BIGEND EROMBA LBRD0 0C/8C 14/94 18/98 14:11 17:16 DMPBAM 28/A8 15:14 LAS1RR LAS1BA LBRD1 MBOX0 MBOX1 F0/170 F4/174 F8/178 78/C0 7C/C4 31:0 31:0 31:0 31:0 31:0 Description Default changed from 9060 9080 Memory Write Invalidate supported User definable added Cache line size used Memory Write Invalidate Register Bank size changed from Register Bank size changed from Base address register Local Address Space Subsystem Vendor Register Subsystem Register Mode/Arbitration Register accessible from Local Direct Slave Give Mode Direct Slave Lock Enable Request Mode Mode Read/No Write Mode Read with Write Flush Mode Local Latency Timer with BREQ Read/No Flush Mode Big/Little Endian Descriptor Register BREQo Timer Resolution control Local width programmable mode Read Prefetch Count Enable Read Prefetch Count Local width programmable mode Extra long serial EEPROM load Direct Master Read Prefetch Size Control Programmable Almost Full Flag increased bits Direct Master Prefetch Limit Remap select Direct Master Write Delay Local Address Space Range Register Local Address Space Local Base Address Register (Remap) Local Address Space Region Descriptor Register MBOX0 moved address when Messaging Queue enabled MBOX1 moved address when Messaging Queue enabled
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Table 4-2. Register Differences between 9080 9060 (continued)
Register INTCSR PCI/Local Offset 68/E8 Bits PCIHIDR PCIHREV DMAMODE0 70/F0 74/F4 80/100 31:0 DMADPR0 DMAMODE1 90/110 94/114 DMADPR1 DMACSR0 DMACSR1 DMATHR OPQIS OPQIM MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OFHPR OPTPR A4/124 A8/128 A9/129 B0/130 30/B0 34/B4 C0/140 C4/144 C8/148 CC/14C D0/150 D4/154 D8/158 DC/15C E0/160 E4/164 E8/168 15:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Mailbox Interrupt Enable Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Permanent Configuration Register Permanent Revision Register Write Invalidate Mode Channel transfers Write Invalidate Mode EOT[1:0]# (End Transfer) Input Enable Stop Data Transfer Mode Clear Count Mode Interrupt Select Descriptor Location Selector (PCI Local) Write Invalidate Mode EOT[1:0]# (End Transfer) Input Enable Stop Data Transfer Mode Clear Count Mode Interrupt Select Descriptor Location Selector (PCI Local) Channel Done Channel Done Changed thresholds accommodate word write FIFOs Outbound Post Queue Interrupt Status Register Outbound Post Queue Interrupt Mask Register Inbound Queue Port Outbound Queue Port Messaging Queue Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register Description
©PLX Technology, Inc., 1997
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REGISTERS
Table 4-3. Register Differences between 9080 9060ES
Register PCIIDR PCISR PCICLSR PCIBAR0 PCIBAR1 PCIBAR3 PCISVID PCISID MARBR PCI/Local Offset 00/00 06/06 0C/0C 10/10 14/14 1C/1C 2C/2C 2E/2E AC/88, Bits 31:16 31:0 15:0 15:0 20:19 BIGEND 0C/8C EROMBA LBRD0 14/94 18/98 17:16 DMPBAM 28/A8 15:14 LAS1RR LAS1BA LBRD1 MBOX0 MBOX1 MBOX4 MBOX5 MBOX6 MBOX7 P2LDBELL L2PDBELL INTCSR F0/170 F4/174 F8/178 78/C0 7C/C4 50/D0 54/D4 58/D8 5C/DC 60/E0 64/E4 68/E8 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:8 31:8 Description Default changed from 906E 9080 User definable added Cache line size used Memory Write Invalidate Register Bank size changed from Register Bank size changed from Base address register Local Address Space Subsystem Vendor Register Subsystem Register Channel Priority Request Mode Read/No Write Mode Read with Write Flush Mode Local Latency Timer with BREQ Read/No Flush Mode Direct Slave Endian Mode Channel Endian Mode Channel Endian Mode BREQo Timer Resolution control Local width programmable mode Single Read Access Mode removed Local width programmable mode Extra long serial EEPROM load Direct Master Read Prefetch Size Control Programmable Almost Full Flag increased Direct Master Prefetch Limit Remap select Direct Master Write Delay Local Address Space Range Register Local Address Space Local Base Address Register (Remap) Local Address Space Region Descriptor Register MBOX0 moved address when Messaging Queue enabled MBOX1 moved address when Messaging Queue enabled MBOX4 added MBOX5 added MBOX6 added MBOX7 added more doorbell bits added Local Doorbell Register more doorbell bits added Local Doorbell Register Mailbox Interrupt Enable
©PLX Technology, Inc., 1997
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REGISTERS
Table 4-3. Register Differences between 9080 9060ES (continued)
Register INTCSR PCI/Local Offset 68/E8 Bits CNTRL 6C/EC PCIHREV DMAMODE0 DMAPADR0 DMALADR0 DMASIZ0 DMADPR0 DMAMODE1 DMAPADR1 DMALADR1 DMASIZ1 DMADPR1 DMACSR0 DMACSR1 DMATHR OPQIS OPQIM MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OFHPR OPTPR 74/F4 80/100 84/104 88/108 8C/10C 90/110 94/114 98/108 9C/11C A0/120 A4/124 A8/128 A9/129 B0/130 30/B0 34/B4 C0/140 C4/144 C8/148 CC/14C D0/150 D4/154 D8/158 DC/15C E0/160 E4/164 E8/168 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Description Channel interrupt enable Channel interrupt enable Channel interrupt status Channel interrupt status Channel active during abort Channel active during abort Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Mailbox Interrupt Status Read command Write command Permanent Revision Register Channel Mode Register Channel Address Register Channel Local Address Register Channel Size Register Channel Descriptor Pointer Register Channel Mode Register Channel address Register Channel Local address Register Channel Size Register Channel Descriptor Pointer Register Channel Command/Status Channel Command/Status Threshold Register Outbound Post Queue Interrupt Status Register Outbound Post Queue Interrupt Mask Register Inbound Queue Port Outbound Queue Port Messaging Queue Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register
©PLX Technology, Inc., 1997
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REGISTERS
Table 4-4. Register Differences between 9080 9060SD
Register PCIIDR PCISR PCIBAR0 PCIBAR1 PCISVID PCISID MARBR PCI/Local Offset 00/00 06/06 10/10 14/14 2C/2C 2E/2E AC/88, Bits 31:16 15:0 15:0 31:0 BIGEND 0C/8C EROMBA 14/94 LBRD0 18/98 17:16 DMRR DMLBAM DMLBAI DMPBAM LAS1RR LAS1BA LBRD1 LBRD1 MBOX0 MBOX1 MBOX4 MBOX5 MBOX6 MBOX7 INTCSR 1C/9C 20/A0 24/A4 28/A8 F0/170 F4/174 F8/178 F8/178 40,78/C0 7C/C4 50/D0 54/D4 58/D8 5C/DC 68/E8 31:16 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 PCIHREV 74/F4 Description Default changed from 906D 9080 User definable added Register Bank size changed from Register Bank size changed from Subsystem Vendor Register Subsystem Register Mode/Arbitration Register accessible from Request Mode Read/No Flush Mode Direct Master Endian Mode Channel Endian Mode Direct Slave BREQo Delay Clocks Local BREQo Enable BREQo Timer Resolution control Local width programmable mode Single Read Access Mode removed Local width programmable mode Local Range Register Direct Master Local Base Address Register Direct Master Memory Local Base Address Register Direct Master IO/CFG Base Address (Remap) Register Direct Master Memory Local Address Space Range Register 30/B0 9060SD Local Address Space Local Base Address Register (Remap) 34/B4 9060SD Local Address Space Region Descriptor Register 38/B8 9060SD Single Read Access Mode removed MBOX0 moved address when Messaging Queue enabled MBOX1 moved address when Messaging Queue enabled MBOX4 added MBOX5 added MBOX6 added MBOX7 added Channel interrupt enable Channel interrupt active Direct Master active during abort Channel active during abort Permanent Revision Register
©PLX Technology, Inc., 1997
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REGISTERS
Table 4-4. Register Differences between 9080 9060SD (continued)
Register DMAMODE0 DMAPADR0 DMALADR0 DMASIZ0 DMADPR0 DMACSR0 DMATHR OPQIS OPQIM MQCR QBAR IFHPR IFTPR IPHPR IPTPR OFHPR OFTPR OFHPR OPTPR PCI/Local Offset 80/100 84/104 88/108 8C/10C 90/110 A8/128 B0/130 30/B0 34/B4 C0/140 C4/144 C8/148 CC/14C D0/150 D4/154 D8/158 DC/15C E0/160 E4/164 E8/168 Bits 31:0 31:0 31:0 31:0 31:0 15:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 Description Channel Mode Register Channel Address Register Channel Local Address Register Channel Transfer Size Register Channel Descriptor Pointer Register Channel Command/Status Register Channel Thresholds Outbound Post Queue Interrupt Status Register Outbound Post Queue Interrupt Mask Register Inbound Queue Port Outbound Queue Port Messaging Queue Configuration Register Queue Base Address Register Inbound Free Head Pointer Register Inbound Free Tail Pointer Register Inbound Post Head Pointer Register Inbound Post Tail Pointer Register Outbound Free Head Pointer Register Outbound Free Tail Pointer Register Outbound Post Head Pointer Register Outbound Post Tail Pointer Register Queue Status/Control Register
©PLX Technology, Inc., 1997
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REGISTERS
REGISTER ADDRESS MAPPING
4.2.1 Configuration Registers
Table 4-5. Configuration Registers
Register Address Local Access (Offset from Chip Select Address) Max_Lat Min_Gnt BIST ensure software compatibility with other versions 9080 family ensure compatibility with future enhancements, write zero unused bits. PCI/Local Writable Serial EEPROM Writable
Device Status Class Code Header Type
Vendor Command Revision Latency Timer Cache Line Size
Local Local [15:0], Local Local
Base Address Memory Mapped Configuration Registers (PCIBAR0) Base Address Mapped Configuration Registers (PCIBAR1) Base Address Local Address Space (PCIBAR2) Base Address Local Address Space (PCIBAR3) Unused Base Address (PCIBAR4) Unused Base Address (PCIBAR5) Cardbus Pointer (Not Supported) Subsystem Subsystem Vendor
Base Address Local Expansion Reserved Reserved Interrupt Interrupt Line
[7:0], Local
Note:
Refer spec definitions these registers.
©PLX Technology, Inc., 1997
Page
Version 1.02
SECTION
9080
REGISTERS
4.2.2 Local Configuration Registers
Table 4-6. Local Configuration Registers
(Offset from Base Address) Local Access (Offset fr
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