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CY7C346 128-Macrocell MAX® EPLD macrocells eight logic array


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ULTRA37000FOR DESIGNS
CY7C346
128-Macrocell MAX® EPLD
macrocells eight logic array blocks (LABs) dedicated inputs, bidirectional pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology Available 84-pin CLCC, PLCC, 100-pin PGA, PQFP macrocells CY7C346 divided into eight LABs, LAB. There expander product terms, LAB, used shared macrocells within each LAB. Each interconnected through programmable interconnect array, allowing signals routed throughout chip. speed density CY7C346 allow used wide range applications, from replacement large amounts 7400-series logic, complex controllers multifunction chips. With greater than times functionality 20-pin PLDs, CY7C346 allows replacement over devices. replacing large amounts logic, CY7C346 reduces board space, part count, increases system reliability.
Functional Description
CY7C346 Erasable Programmable Logic Device (EPLD) which CMOS EPROM cells used configure logic functions within device. MAX® architecture 100% user-configurable, allowing device accommodate variety independent logic functions.
Logic Block Diagram
(C7) [16] (A10) (B9) [10] (A9) [11] (A8) [14] (B7) [15] (A7) [17] (C6) [20] (A5) [21] (B5) [22] INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT SYSTEM CLOCK MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 121-128 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 105-112 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 86-96 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL [58] [57] [56] [55] [54] [53] [52] [51] (M4) (N3) (M3) (N2) (M2) (N1) (L2) (M1) INPUT [59] INPUT [60] INPUT [61] INPUT [64] INPUT [65] INPUT [66] INPUT [67] INPUT [70] INPUT [71] INPUT [72] (N4) (M5) (N5) (N6) (M7) (L7) (N7) (L8) (N9) (M9)
(B13) (C12) (A13) (B12) (A12) (11) (A11) (B10)
[100] (C13) [99] (D12) [98] (D13) [97] (E12) [96] (E13) [95] (F11) [92] (G13) [91] (G11)
MACROCELL 9-16 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
(A4) (B4) (A3) (A2) (B3) (A1) (B2) (B1)
[23] [24] [25] [26] [27] [28] [29] [30]
[90] [89] [86] [85] [84] [83] [82] [81]
(G12) (H13) (J13) (J12) (K13) (K12) (L13) (L12)
MACROCELL 25-32 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
(C2) [31] (C1) [32] (D2) [33] (D1) [34] (E2) [35] (E1) [36] (F1) [39] (G2) [40]
[80] [79] [78] [77] [76] [75] [74] [73]
(M13) (M12) (N13) (M11) (N12) (N11) (M10) (N10)
MACROCELL 41-48 (G3) [41] (G1) [42] (H3) [45] (J1) [46] (J2) [47] (K1) [48] (K2) [49] (L1) [50] MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
MACROCELL (A6,B6,F12,F13,H1,H2,M8,N8) (B8,C8,F2,F3,H11,H12,L6,M6) [18, [12,
MACROCELL PERTAIN 100-PIN PACKAGE -PERTAIN 100-PIN PQFP PACKAGE
Cypress Semiconductor Corporation Document 38-03005 Rev.
3901 North First Street
Jose, 95134
408-943-2600 Revised April 2004
ULTRA37000FOR DESIGNS
Selection Guide
7C346-25 Maximum Access Time Maximum Operating Current Commercial Military Industrial Maximum Standby Current Commercial Military Industrial 7C346-30 7C346-35
CY7C346
Unit
Configurations
PLCC/CLCC View
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
Bottom View
CY7C346
CY7C346
/CLK
INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
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ULTRA37000FOR DESIGNS
Configurations (continued)
PQFP View
CY7C346
INPUT INPUT INPUT INPUT INPUT INPUT/CLK INPUT INPUT INPUT INPUT
INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
CY7C346
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Logic Array Blocks
There eight logic array blocks CY7C346. Each consists macrocell array containing macrocells, expander product term array containing expanders, block. programmable interconnect array dedicated input bus. macrocell feedbacks macrocell array, expander array, programmable interconnect array. Expanders feed themselves macrocell array. feedbacks programmable interconnect array that they accessed macrocells other LABs well macrocells which they situated. Externally, CY7C346 provides dedicated inputs, which used system clock. There pins
CY7C346
that individually configured input, output, bidirectional data flow.
Programmable Interconnect Array
Programmable Interconnect Array (PIA) solves interconnect limitations routing only signals needed each logic array block. inputs outputs every macrocell within device feedback every device.
Timing Delays
Timing delays within CY7C346 easily determined using Warp®, Warp ProfessionalTM, Warp Enterprisesoftware. CY7C346 fixed internal delays, allowing user determine worst case timing delays design.
EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tCLR tLAC tPRE INPUT DELAY LOGIC ARRAY DELAY tLAD tRSU
REGISTER OUTPUT DELAY OUTPUT tCOMB tLATCH
INPUT
SYSTEM CLOCK DELAY tICS CLOCK DELAY FEEDBACK DELAY
DELAY tPIA
DELAY
Figure CY7C346 Internal Timing Model
Design Recommendations
Operation devices described herein with conditions above those listed under "Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure absolute maximum ratings conditions extended periods time affect device reliability. CY7C346 contains circuitry protect device pins from high static voltages electric fields, normal precautions should taken avoid application voltage higher than maximum rated voltages. proper operation, input output pins must constrained range (VIN VOUT) VCC. Unused inputs must always tied appropriate logic level Document 38-03005 Rev.
(either GND). Each pins must connected together directly device. Power supply decoupling capacitors least must connected between GND. most effective decoupling, each should separately decoupled directly device. Decoupling capacitors should have good frequency response, such monolithic ceramic types have.
Design Security
CY7C346 contains programmable design security feature that controls access data programmed into device. this programmable feature used, proprietary design implemented device cannot copied retrieved. This enables high level design control Page
ULTRA37000FOR DESIGNS
obtained since programmed data within EPROM cells invisible. that controls this function, along with other program data, reset simply erasing entire device. CY7C346 fully functionally tested guaranteed through complete testing each programmable EPROM internal logic elements thus ensuring 100% programming yield. erasable nature these devices allows test programs used erased during early stages production flow. devices also contain on-board logic test circuitry allow verification function specification once encapsulated non-windowed packages.
CY7C346
Timing Considerations
Unless otherwise stated, propagation delays include expanders. When using expanders, maximum expander delay tEXP overall delay. Similarly, there additional tPIA delay input from when compared signal from straight input pin. When calculating synchronous frequencies, inputs dedicated input pins. parameter should used data applied pin. greater than tCO1, 1/tS2 becomes limiting frequency data path mode unless 1/(tWH tWL) less than 1/tS2. When expander logic used data path, appropriate maximum expander delay, tEXP tS1. Determine which 1/(tWH tWL), 1/tCO1, 1/(tEXP tS1) lowest frequency. lowest these frequencies maximum data path frequency synchronous configuration. When calculating external asynchronous frequencies, tAS1 inputs dedicated input pins. data applied pin, tAS2 must used required set-up time. (tAS2 tAH) greater than tACO1, 1/(tAS2 tAH) becomes limiting frequency data path mode unless 1/(tAWH tAWL) less than 1/(tAS2 tAH). When expander logic used data path, appropriate maximum expander delay, tEXP tAS1. Determine which 1/(tAWH tAWL), 1/tACO1, 1/(tEXP tAS1) lowest frequency. lowest these frequencies maximum data path frequency asynchronous configuration.
Typical fMAX
ACTIVE (mA) Typ.
5.0V Room Temp.
MAXIMUM FREQUENCY
Output Drive Current
OUTPUT CURRENT (mA) TYPICAL
parameter indicates system compatibility this device when driving other synchronous logic with positive input hold times, which controlled same synchronous clock. greater than minimum required input hold time subsequent synchronous logic, then devices guaranteed function properly with common synchronous clock under worst-case environmental supply voltage conditions. parameter tAOH indicates system compatibility this device when driving subsequent registered logic with positive hold time using same asynchronous clock CY7C346. general, tAOH greater than minimum required input hold time subsequent logic (synchronous asynchronous) then devices guaranteed function properly under worst-case environmental supply voltage conditions, provided clock signal source same. This also applies expander logic used clock signal path driving device, driven device. This expander logic second device's clock signal path adding additional delay (tEXP) causing output data from preceding device change prior arrival clock signal following device's register.
5.0V Room Temp.
0.45
OUTPUT VOLTAGE
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C to+150°C Ambient Temperature with Power Applied. -55°C to+125°C Maximum Junction Temperature (under bias). 150°C Supply Voltage Ground Potential -2.0V +7.0V Maximum Power Dissipation.2500 Current .500
CY7C346
Output Current Input Voltage[1] .-3.0V +7.0V Program Voltage. 13.0V Static Discharge Voltage. 1100V (per MIL-STD-883, Method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature +70°C -40°C +85°C -55°C +125°C (Case)
Electrical Characteristics Over Operating Range[2]
Parameter Description Output HIGH Voltage ICC1 ICC2 Output Voltage Input HIGH Voltage Input Voltage Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current[5] Recommended Input Rise Time Recommended Input Fall Time Test Conditions Min., -4.0 Min., -0.3 Min. Max. 0.45 Unit
Max., VOUT 0.5V[3, Load) Commercial Military/Industrial Load) Commercial MHz[4] Military/Industrial
Capacitance[6]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions VOUT Max. Unit
Test Loads Waveforms[6]
OUTPUT INCLUDING SCOPE Equivalent OUTPUT INPUT PULSES 3.0V
INCLUDING SCOPE EQUIVALENT (Commercial/Military) OUTPUT 1.75V
Notes: Minimum input -0.3V. During transitions, inputs undershoot -3.0V periods less than Typical values 25°C more than output should tested time. Duration short circuit should more than second. VOUT 0.5V been chosen avoid test problems caused tester ground degradation. Guaranteed design 100% tested. This parameter measured with device programmed 16-bit counter each LAB. Part Test Load Waveforms used parameters except tXZ, which used part Test Load Waveforms. external timing parameters measured referenced external pins device.
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7C346-25 Min. Max. 34.5 55.5 62.5 62.5 27.7 43.4 7C346-30 Min. Max.
CY7C346
7C346-35 Min. Max.
Commercial Industrial External Synchronous Switching Characteristics[6] Over Operating Range
Parameter Description tPD1 Dedicated Input Combinatorial Output Delay[7] tPD2 Input Combinatorial Output Delay[10] tPD3 Dedicated Input Combinatorial Output Delay with Expander Delay[11] tPD4 Input Combinatorial Output Delay with Expander Delay[4, Input Output Enable Delay[4, Input Output Disable Delay[4, tCO1 Synchronous Clock Input Output Delay tCO2 Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[7, Input Set-Up Time Synchronous Clock Input[7] Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Asynchronous Clear Recovery Time[4, Asynchronous Clear Registered Output Delay[7] Asynchronous Preset Width[4, Asynchronous Preset Recovery Time[4, Asynchronous Preset Registered Output Delay[7] Synchronous Clock Local Feedback Input[4, External Synchronous Clock Period (1/(fMAX3)[4] fMAX1 External Feedback Maximum Frequency (1/(tCO1 tS1))[4, fMAX2 Internal Local Feedback Maximum Frequency, lesser (1/(tS1 tCF)) (1/tCO1)[4, fMAX3 Data Path Maximum Frequency, lesser (1/(tWL tWH)), (1/(tS1 tH)) (1/tCO1)[4, fMAX4 Maximum Register Toggle Frequency (1/(tWL tWH)[4, Output Data Stable Time from Synchronous Clock Input[4, Unit
12.5 12.5
22.2 32.2
Notes: This specification measure delay from input signal applied dedicated input (68-pin PLCC input combinatorial output output pin. This delay assumes expander terms used form logic function. When this note applied parameter specification indicates that signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) applied dedicated input only signal path (either clock data) employs expander logic. input signal applied additional delay equal tPIA should added comparable delay dedicated input. expanders used, maximum expander delay tEXP overall delay comparable delay without expanders. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function. This specification measure delay from input signal applied dedicated input (68-pin PLCC input combinatorial output output pin. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This specification measure delay from input signal applied macrocell output. This delay assumes expander terms used form logic function includes worst-case expander logic delay pass through expander logic. This parameter tested periodically sampling production material. This specification measure delay from synchronous register clock internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used, register synchronously clocked feedback within same LAB. This parameter tested periodically sampling production material. data applied input capture macrocell register, input set-up time minimums should observed. These parameters synchronous operation tAS2 asynchronous operation. This specification measure delay associated with internal register feedback path. This delay from synchronous clock logic array input. This delay plus register set-up time, tS1, minimum internal period internal synchronous state machine configuration. This delay feedback within same LAB. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency, synchronous mode, which state machine configuration with external feedback operate. assumed that data inputs external feedback signals applied dedicated inputs. This specification indicates guaranteed maximum frequency which state machine with internal-only feedback operate. register output states must also control external points, this frequency still observed long this frequency less than 1/tCO1. feedback assumed local originating within same LAB. This frequency indicates maximum frequency which device operate data path mode (dedicated input output pin). This assumes data input signals applied dedicated input pins expander logic used. data inputs pins, appropriate calculation. This specification indicates guaranteed maximum frequency, synchronous mode, which individual output buried register cycled clock signal applied dedicated clock input pin. This parameter indicates minimum time after synchronous register clock input that previous register output data maintained output pin.This specification measure delay from asynchronous register clock input internal feedback register output signal input logic array then combinatorial output. This delay assumes expanders used logic combinatorial output asynchronous clock input. clock signal applied dedicated clock input feedback within single LAB. This parameter tested periodically sampling production material.
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CY7C346
Commercial Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
7C346-25 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input Output Delay[7] Asynchronous Clock Input Local Feedback Combinatorial Output[20] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time Asynchronous Clock Input
7C346-30 Min. Max.
7C346-35 Min. Max. Unit 23.2 33.3 28.5 33.3
Min.
Max.
33.3
Time[7, Input[4,
Asynchronous Clock Local Feedback
27.7 33.3
External Asynchronous Clock Period (1/(fMAXA4))[4] External Feedback Maximum Frequency Asynchronous Mode (1/(tACO1 tAS1))[4, Maximum Internal Asynchronous Frequency[4, Data Path Maximum Frequency Asynchronous Mode[4, Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4, Output Data Stable Time from Asynchronous Clock Input[4,
Notes: This parameter measured with positive-edge triggered clock register. negative edge triggering, tAWH tAWL parameters must swapped. given input used clock multiple registers with both positive negative polarity, tAWH should used both tAWH tAWL. This specification measure delay associated with internal register feedback path asynchronous clock logic array input. This delay plus asynchronous register set-up time, tAS1, minimum internal period internal asynchronously clocked state machine configuration. This delay feedback within same LAB, assumes expander logic clock path, assumes that clock input signal applied dedicated input pin. This parameter tested periodically sampling production material. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine configuration with external feedback operate. assumed that data inputs, clock inputs, feedback signals applied dedicated inputs that expander logic employed clock signal path data path. This specification indicates guaranteed maximum frequency which asynchronously clocked state machine with internal-only feedback operate. This parameter determined lesser (1/(tACF tAS1)) (1/(tAWH tAWL)). register output states must also control external points, this frequency still observed long this frequency less than 1/tACO1. This specification assumes expander logic utilized, data inputs clock inputs applied dedicated inputs, state feedback within single LAB. This parameter tested periodically sampling production material. This frequency maximum frequency which device operate asynchronously clocked data path mode. This specification determined lesser 1/(tAWH tAWL), 1/(tAS1 tAH) 1/tACO1. assumes data clock input signals applied dedicated input pins expander logic used. This specification indicates guaranteed maximum frequency which individual output buried register cycled asynchronously clocked mode clock signal applied external dedicated input pin. This parameter indicates minimum time that previous register output data maintained output after asynchronous register clock input applied external dedicated input pin.
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Commercial Industrial Internal Switching Characteristics Over Operating Range
7C346-25 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB tICS tPRE tCLR tPCW tPCR tPIA Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay
[28]
CY7C346
7C346-30 Min. Max.
7C346-35 Min. Max. Unit 12.5 12.5
Min.
Max.
Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow Through Latch Delay Register Delay Transparent Mode Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset Clear Pulse Width Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Delay[29]
Notes: Sample tested only output change This specification guarantees maximum combinatorial delay associated with macrocell register bypass when macrocell configured combinatorial operation.
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Military External Synchronous Switching Characteristics[6] Over Operating Range
7C346-30 Parameter tPD1 tPD2 tPD3 tPD4 tCO1 tCO2 fMAX1 fMAX2 fMAX3 fMAX4 Description Dedicated Input Combinatorial Output Delay Input Combinatorial Output Delay[10] Dedicated Input Combinatorial Output Delay with Expander Delay[11] Input Combinatorial Output Delay with Expander Delay[4, Input Output Enable Delay[4, Input Output Disable Delay[4, Synchronous Clock Input Output Delay Synchronous Clock Local Feedback Combinatorial Output[4, Dedicated Input Feedback Set-Up Time Synchronous Clock Input[7, Input Set-Up Time Synchronous Clock Input[7] Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input Time Asynchronous Clear Width[4, Time[4, Asynchronous Clear Recovery Asynchronous Preset Time[4, 27.7 43.4 22.2 32.2
CY7C346
7C346-35 Min. Max. 12.5 12.5 Unit
Min.
Max.
Asynchronous Clear Registered Output Delay[7] Width[4, Asynchronous Preset Recovery
Asynchronous Preset Registered Output Delay[7] Synchronous Clock Local Feedback Input[4, External Synchronous Clock Period (1/(fMAX3 External Feedback Maximum Frequency (1/(tCO1 tS1))[4, Internal Local Feedback Maximum Frequency, lesser (1/(tS1 tCF)) (1/tCO1)[4, Data Path Maximum Frequency, lesser (1/(tWL tWH)), (1/(tS1 tH)) (1/tCO1)[4, Maximum Register Toggle Frequency (1/(tWL tWH))[4, Output Data Stable Time from Synchronous Clock Input[4, ))[4]
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Military External Asynchronous Switching Characteristics[6] Over Operating Range
7C346-30 Parameter tACO1 tACO2 tAS1 tAS2 tAWH tAWL tACF fMAXA1 fMAXA2 fMAXA3 fMAXA4 tAOH Description Asynchronous Clock Input Output Delay
CY7C346
7C346-35 Min. Max. Unit 23.2 33.3 28.5 33.3
Min.
Max.
Asynchronous Clock Input Local Feedback Combinatorial Output[20] Dedicated Input Feedback Set-Up Time Asynchronous Clock Input[7] Input Set-Up Time Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input Time[7, Input[4, ))[4] 27.7 33.3 Asynchronous Clock Local Feedback
External Asynchronous Clock Period (1/(fMAXA4 External Feedback Maximum Frequency Asynchronous Mode (1/(tACO1 tAS1))[4,
Maximum Internal Asynchronous Frequency[4, Data Path Maximum Frequency Asynchronous Mode[4, Maximum Asynchronous Register Toggle Frequency 1/(tAWH tAWL)[4, Output Data Stable Time from Asynchronous Clock Input[4,
Document 38-03005 Rev.
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ULTRA37000FOR DESIGNS
Military Typical Internal Switching Characteristics Over Operating Range
7C346-30 Parameter tEXP tLAD tLAC tRSU tLATCH tCOMB tICS tPRE tCLR tPCW tPCR tPIA Description Dedicated Input Buffer Delay Input Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer Delay Output Buffer Enable Delay
[28]
CY7C346
7C346-35 Min. Max. Unit 12.5 12.5
Min.
Max.
Output Buffer Disable Delay Register Set-Up Time Relative Clock Signal Register Register Hold Time Relative Clock Signal Register Flow Through Latch Delay Register Delay Transparent Mode Clock HIGH Time Clock Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Asynchronous Preset Clear Pulse Width Asynchronous Preset Clear Recovery Time Programmable Interconnect Array Delay Time Delay[29]
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ULTRA37000FOR DESIGNS
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ INPUT tPD1 COMBINATORIAL OUTPUT tER[7] COMBINATORIAL REGISTERED OUTPUT HIGH-IMPEDANCE THREE-STATE VALID OUTPUT
CY7C346
/tPD2
[10]
HIGH-IMPEDANCE THREE-STATE
External Synchronous
DEDICATED INPUTS REGISTERED FEEDBACK SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[7] tRO/tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK tRW/tPW tRR/tPR
External Asynchronous
DEDICATED INPUTS REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAWH tAWL
tACO1 tAOH
tRW/tPW
tRR/tPR
ASYNCHRONOUS CLEAR/PRESET
tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCHRONOUS REGISTERED FEEDBACK
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Switching Waveforms (continued)
Internal Combinatorial
INPUT tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
CY7C346
LOGIC ARRAY OUTPUT
Internal Asynchronous
tIOR CLOCK CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT LOCAL LOGIC ARRAY tPIA REGISTER OUTPUT ANOTHER tCLR,tPRE tAWH tAWL
Internal Synchronous
SYSTEM SYSTEM REGISTER tRSU DATA FROM LOGIC ARRAY tICS
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Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM LOGIC ARRAY
CY7C346
DATA FROM LOGIC ARRAY OUTPUT HIGH IMPEDANCE STATE
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MILITARY SPECIFICATIONS Group Subgroup Testing Characteristics
Parameter ICC1 Subgroups
CY7C346
Switching Characteristics
Parameter tPD1 tPD2 tPD3 tCO1 tACO1 tACO2 tAS1 tAWH tAWL Subgroups
Ordering Information
Speed (ns) Ordering Code CY7C346-25HC/HI CY7C346-25JC/JI CY7C346-25NC/NI CY7C346-25RC/RI CY7C346-30HC/HI CY7C346-30JC/JI CY7C346-30NC/NI CY7C346-30HMB CY7C346-30RMB Package Name N100 R100 N100 R100 Package Type 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Grid Array 84-pin Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 84-pin Windowed Leaded Chip Carrier 100-pin Windowed Ceramic Grid Array Operating Range Commercial/Industrial
Commercial/Industrial
Military
Document 38-03005 Rev.
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ULTRA37000FOR DESIGNS
Ordering Information (continued)
Speed (ns) Ordering Code CY7C346-35JC/JI CY7C346-35NC/NI CY7C346-35RC/RI CY7C346-35HMB CY7C346-35RMB Package Name N100 R100 R100 Package Type 84-lead Plastic Leaded Chip Carrier 100-lead Plastic Quad Flatpack 100-pin Windowed Ceramic Grid Array 84-pin Windowed Leaded Chip Carrier 100-pin Windowed Ceramic Grid Array
CY7C346
Operating Range Commercial/Industrial
Military
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier
51-80081-**
Document 38-03005 Rev.
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ULTRA37000FOR DESIGNS
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier
CY7C346
51-85006-*A
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ULTRA37000FOR DESIGNS
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
CY7C346
51-85052-*A
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ULTRA37000FOR DESIGNS
Package Diagrams (continued)
100-Pin Windowed Ceramic Grid Array R100
CY7C346
51-80010-*C
Warp registered trademarks Ultra37000, Warp Professional Warp Enterprise trademarks Cypress Semiconductor Corporation. product company names mentioned this document trademarks their respective holders.
Document 38-03005 Rev.
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Cypress Semiconductor Corporation, 2004. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
ULTRA37000FOR DESIGNS
Document History Page
Document Title: CY7C346 128-Macrocell MAX® EPLD Document Number: 38-03005 REV. 106270 113614 213375 Issue Date 04/23/01 04/11/02 Orig. Change Description Change Change from Spec number 38-00244 38-03005 package diagram dimensions updated
CY7C346
Added note title page: "Use Ultra37000 Designs"
Document 38-03005 Rev.
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KPHK-1608MGC - KPHK-1608MGC   KPHK-1608MGC Datasheet
F1030C - F1030C   F1030C Datasheet
F10200C - F10200C   F10200C Datasheet
B43867 - B43867   B43867 Datasheet

 

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