133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, DRCG S

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133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, DRCG S

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CY221
133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, DRCG Support
Features Mixed 2.5V 3.3V Operation Compliant Intel® CK133 (CY2210-3) CK133W (CY2210-2) synthesizer driver specification Multiple output clocks different frequencies Four clocks, Eight synchronous clocks, free-running CPU/2 clocks, one-half frequency Four clocks Three synchronous APIC clocks, 16.67 clock reference clocks 14.318 Spread Spectrum clocking 32.5-kHz modulation frequency 33.1-kHz modulation frequency CY2210-02/03 33.4-kHz modulation frequency CY2210-04 EPROM programmable percentage spreading. Default -0.6%, which recommended Intel Power-down features Three Select inputs Low-skew low-jitter outputs Test Mode support 56-pin SSOP package Benefits Usable with Pentium® Pentium® processors
Single-chip main motherboard clock generator Driven together, support CPUs chipset Support slots chipset Drives main memory clock generators, including DRCG (CPUCLK/2) Support multiple slots Support multiprocessing systems Supports frequencies chip Enables reduction some systems
Supports mobile systems Supports eight clock frequencies Meets tight system timing requirements high frequency Enables "bed nails" testing Widely available, standard package enables lower cost
Logic Block Diagram
Configuration
SSOP View REFCLK [0-1] (14.318 MHz)
VSSREF REFCLK0 REFCLK1 VDDREF VDDAPIC APICCLK2 APICCLK1 APICCLK0 VSSAPIC VDDCPU/2 CPUCLK/2 (DRCG) CPUCLK/2 (DRCG) VSSCPU/2 VDDCPU CPUCLK3 CPUCLK2 VSSCPU VDDCPU CPUCLK1 CPUCLK0 VSSCPU AVDD AVSS PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDDUSB USBCLK VSSUSB
CPUCLK [0-3] CPU_STOP XTALIN
XTALOUT
14.318 OSC.
XTALIN XTALOUT VSSPCI
PCICLK_F (33.33 MHz) PCICLK [1-7] (33.33 MHz) APICCLK [0-2] (16.67 MHz) AGPCLK [0-3] (66.67 MHz)
PCICLK2 PCICLK3 VSSPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 VSSPCI VSSAGP AGPCLK0 AGPCLK1 VDDAGP VSSAGP AGPCLK2 AGPCLK3 VDDAGP SEL133
SEL1 SEL0 SEL133 SPREAD PCI_STOP PWR_DWN
EPROM
USBCLK MHz)
Intel Pentium registered trademarks Intel Corporation.
Cypress Semiconductor Corporation Document 38-07204 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised December 2002
CY2210-2/-3/-4
Divider, EPROMProgDelay Stop Logic
CPUCLK/2 [0-1] (DRCG)
PCICLK_F PCICLK1 VDDPCI
CY221Pin Summary
Name VSSREF VDDREF VSSPCI VDDPCI VSSAGP VDDAGP VSSUSB VDDUSB VSSCPU VDDCPU VSSCPU/2 VDDCPU/2 VSSAPIC VDDAPIC AVSS AVDD XTALIN
Pins
Description 3.3V Reference ground 3.3V Reference voltage supply 3.3V ground 3.3V voltage supply 3.3V ground 3.3V voltage supply 3.3V ground 3.3V voltage supply 2.5V ground 2.5V voltage supply 2.5V CPU/2 ground 2.5V CPU/2 voltage supply 2.5V APIC ground 2.5V APIC voltage supply Analog ground Core Analog voltage supply Core Reference crystal input Reference crystal feedback clock outputs clock outputs, synchronously running 33.33 Free running clock CPU/2 clock outputs, drive memory clock generator clock outputs, running 66.66 APIC clock outputs, running 16.67 Reference clock outputs, 14.318 48-MHz clock output Active input, disables clocks when asserted Active input, disables clocks when asserted Active input, powers down part when asserted Active input, enables spread spectrum when asserted frequency select input (See Function Table) frequency select input (See Function Table) frequency select input (See Function Table)
XTALOUT[1] CPUCLK [0-3] PCICLK [1-7] PCICLK_F CPUCLK/2 AGPCLK [0-3] APICCLK [0-2] REFCLK [0-1] USBCLK CPU_STOP PCI_STOP PWR_DWN SPREAD SEL1 SEL0 SEL133
Note: best accuracy, parallel-resonant crystal, CLOAD crystals with different CLOAD, please refer application note, "Crystal Oscillator Topics."
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CY221Function Table[2]
SEL133 SEL1 SEL0 CPUCLK (MHz) Hi-Z 100.227 TCLK/2 133.33 133.33
CPUCLK/2 (MHz) Hi-Z 50.114 TCLK/4 66.67 66.67
AGPCLK (MHz) Hi-Z 66.818 66.67 66.67 TCLK/4 66.67 66.67
PCICLK (MHz) Hi-Z 33.409 33.33 33.33 TCLK/8 33.33 33.33
USBCLK (MHz) Hi-Z 48.008 TCLK/2
REFCLK (MHz) Hi-Z 14.318 14.318 14.318 TCLK 14.318 14.318
APICCLK (MHz) Hi-Z 16.705[3] 16.67 16.67 TCLK/16 16.67 16.67
Actual Clock Frequency Values
Target Frequency (MHz) 100.0 133.33 48.0 100.0 133.33 48.0 100.0 133.33 48.0 99.126 132.769 48.008 Actual Frequency (MHz) 99.126 132.769 48.008 100.227 132.769 48.008 -8740 -4208 -8740 -4208 +2714 -4208
Clock Output CPUCLK CPUCLK USBCLK
Clock Enable Configuration
CPU_STOP PWR_DWN PCI_STOP CPUCLK CPUCLK/2 PCI_F APIC OSC. VCOs
Clock Driver Impedances
Impedance Buffer Name CPU, CPU/2, APIC USB, PCI, Range 2.375-2.625 3.135-3.465 3.135-3.465 Buffer Type Type Type Type Minimum 13.5 Typical Maximum
Notes: TCLK test clock driven XTALIN input test mode. Only CY2210-2 supports this option. CY2210-3, this selection defined "N/A" "Reserved".
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CY221Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Supply Voltage .-0.5 +7.0V Input Voltage -0.5V VDD+0.5 Storage Temperature (Non-Condensing) -65°C +150°C Junction Temperature. +150°C Package Power Dissipation. Static Discharge Voltage (per MIL-STD-883, Method 3015) >2000V
Operating Conditions Over which Electrical Parameters Guaranteed
Parameter VDDREF, VDDPCI, AVDD, VDDAGP, VDDUSB VDDCPU, VDDCPU/2 VDDAPIC Description 3.3V Supply Voltages CPU/2 Supply Voltage APIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load CPUCLK, CPUCLK/2, USBCLK, REF, APIC PCICLK, Reference Frequency, Oscillator Nominal Value Power-up time VDD's reach minimum specified voltage (power ramps must monotonic) 14.318 0.05 Min. 3.135 2.375 2.375 Max. 3.465 2.625 2.625 14.318 Unit
f(REF)
Electrical Characteristics Over Operating Range
Parameter Description High-level Input Voltage Low-level Input Voltage Except Crystal Pads 2.0V 2.0V 2.4V 2.4V 0.4V 0.4V 0.4V 0.4V USB, REF, PCI, Low-level Output Voltage Input High Current Input Current High-level Output Current[4]
Test Conditions Except Crystal Pads. Threshold voltage crystal pads VDD/2
Min. Max. Unit
High-level Output Voltage[4] CPU, CPU/2, APIC CPU, CPU/2, APIC USB, REF, PCI, CPU, CPU/2 APIC USB, AGP,
Low-level Output
Current[4]
CPU, CPU/2 APIC USB, AGP,
IDD2 IDD3 IDDPD2 IDDPD3
Output Leakage Current
Three-state
2.5V Power Supply Current AVDD/VDD33 3.465V, VDD25 2.625V, FCPU 3.3V Power Supply Current AVDD/VDD33 3.465V, VDD25 2.625V, FCPU 2.5V Shutdown Current 3.3V Shutdown Current AVDD/VDD33 3.465V, VDD25 2.625V AVDD/VDDQ3 3.465V, VDD25 2.625V
Note: Parameter guaranteed design characterization. 100% tested production.
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CY221Switching Characteristics[4, Over Operating Range
Parameter CPU, CPU/2, APIC USB, PCI, CPU, CPU/2, APIC USB, PCI, CPU/2 APIC CPU, AGP, CPU, APIC CPU, CPU/2 APIC CPU, Output Description Output Duty Cycle[6] t1A/t1B Between 0.4V 2.0V Between 0.4V 2.4V Between 0.4V 2.4V Between 2.0V 0.4V Between 2.4V 0.4V Between 2.4V 0.4V Measured 1.25V Measured 1.25V Measured 1.25V Measured 1.5V Measured 1.5V leads. Measured 1.25V 2.5V clocks 1.5V 3.3V clocks leads. Measured 1.5V leads. Measured 1.25V leads. Measured 1.25V clocks 1.5V 3.3V clocks With outputs running (CY2210-2) With outputs running (CY2210-3/-4) With output turned (CY2210-3/-4) Rising Edge Rate Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Falling Edge Rate CPU-CPU Skew CPU/2-CPU/2 Skew APIC-APIC Skew AGP-AGP Skew PCI-PCI Skew CPU-AGP Clock Skew AGP-PCI Clock Skew CPU-APIC Clock Skew CPU-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time clock stabilization from power-up Test Conditions Min. Max. 1000 Unit V/ns V/ns V/ns V/ns V/ns V/ns
Notes: parameters specified with loaded outputs. Duty cycle measured 1.5V when 3.3V. When 2.5V, duty cycle measured 1.25V.
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CY221Switching Waveforms
Duty Cycle Timing
Outputs Rise/Fall Time
OUTPUT
CPU-CPU Clock Skew
CPUCLK
CPUCLK
CPU/2 CPU/2 Clock Skew
CPU/2
CPU/2
APIC-APIC Clock Skew
APIC
APIC
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CY221Switching Waveforms (continued)
AGP-AGP Clock Skew
PCI-PCI Clock Skew
CPU-AGP Clock Skew
Clock Skew
CPU-APIC Clock Skew
APIC
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CY221Switching Waveforms (continued)
CPU-PCI Clock Skew
CPU_STOP Timing
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPU, CPU/2, (External)
PCI_STOP
CPUCLK (Internal) PCICLK (Internal) PCICLK
(Free-Running)
PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) Crystal Shaded section Crystal waveforms indicates that crystal oscillator active, there valid clock.
Notes: CPUCLK CPUCLK latency CPUCLK cycles. CPU_STOP applied asynchronously. synchronized internally.
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CY221Test Circuit
VDDPCI, VDDAGP, VDDUSB, VDDREF, AVDD
CY221
VDDCPU, VDDCPU/2, VDDAPIC
OUTPUTS CLOAD
Note: Each supply must have individual decoupling capacitor. Note: capacitors must placed close pins physically possible.
Ordering Information
Ordering Code CY2210PVC-2/-3/-4 Package Name Package Type 56-Pin SSOP Operating Range Commercial
Package Diagram
56-Lead Shrunk Small Outline Package
51-85062-*C
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Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY221
Document Title: CY2210 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, DRCG Support Document Number: 38-07204 REV. 111724 121839 Issue Date 01/10/02 12/14/02 Orig. Change Description Change Change from Spec number: 38-00888 38-07204 Power requirements added Operating Conditions Information
Document 38-07204 Rev.
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133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, DRCG S

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