AK4588 2/8-Channel Audio CODEC with GENERAL DESCRIPTION AK45
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[AK4588]
AK4588
2/8-Channel Audio CODEC with
GENERAL DESCRIPTION AK4588 single chip CODEC that includes channels eight channels DAC. outputs 24bit data accepts 24bit input data. Enhanced Dual architecture with wide dynamic range. introduces developed Advanced Multi-Bit architecture, achieves wider dynamic range lower outband noise. AK4588 dynamic range 102dB ADC, 106dB well suited digital surround home theater audio. AK4588 also balance volume control corresponding Dolby Digital (AC-3) system. also digital audio receiver (DIR) transmitter (DIT) compatible with 192kHz, 24bits. 8-channel input selector automatically detect Non-PCM stream. AK4588 provides fully compatibility hardware software with AK4628 AK4114.
*AC-3 trademark Dolby Laboratories.
FEATURES ADC/DAC part 24bit Oversampling Sampling Rate 96kHz Linear Phase Digital Anti-Alias Filter Single-Ended Input S/(N+D): 92dB Dynamic Range, S/N: 102dB Digital offset cancellation Overflow flag 24bit 128x Oversampling Sampling Rate 192kHz 24bit times Digital Filter Single-Ended Outputs On-chip Switched-Capacitor Filter S/(N+D): 90dB Dynamic Range, S/N: 106dB Individual channel digital volume with levels 0.5dB step Soft mute Zero Detect Function High Jitter Tolerance Extenal Master Clock Input: 256fs, 384fs, 512fs (fs=32kHz 48kHz) 128fs, 192fs, 256fs (fs=64kHz 96kHz) 128fs (fs=120kHz 192kHz)
MS0287-E-01
2004/03
[AK4588]
DIR/DIT Part AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible jitter Analog Lock Range 32kHz 192kHz Clock Source: X'tal 8-channel Receiver input 2-channel Transmission output (Through output DIT) Auxiliary digital input De-emphasis 32kHz, 44.1kHz, 48kHz 96kHz Detection Functions Non-PCM Stream Detection DTS-CD Stream Detection Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) Unlock Parity Error Detection Validity Flag Detection 24bit Audio Data Format Audio I/F: Master Slave Mode 40-bit Channel Status Buffer Burst Preamble Buffer Non-PCM stream Q-subcode Buffer stream Serial Master Clock Outputs: 64fs/128fs/256fs/512fs Level Digital 4-wire Serial mode setting Operating Voltage: 5.5V with tolerance Power Supply output buffer: 5.5V 80pin LQFP Package (0.5mm pitch)
MS0287-E-01
2004/03
[AK4588]
Block Diagram
PVSS PVDD DAIF Decoder DAUX2 AVDD AVSS DVDD DVSS TVDD B,C,U, VOUT AC-3/MPEG Detect Error STATUS Detect Q-subcode buffer CCLK CDTO CDTI INT0 INT1 Audio Input Selector LRCK2 BICK2 SDTO2 Clock Recovery X'tal Oscillator Clock Generator MCKO1 MCKO2
DATT DATT DATT DATT DATT DATT DATT DATT
SDOUT Format Converter
Audio
LOUT1
MCLK LRCK BICK
MCLK LRCK1 BICK1 DAUX1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
SDTO1
LOUT4
SDIN1 SDIN2 SDIN3 SDIN4
SDTI1 SDTI2 SDTI3 SDTI4
ROUT4
MS0287-E-01
2004/03
[AK4588]
Ordering Guide
AK4588VQ AKD4588 +70°C 80pin LQFP(0.5mm pitch) Evaluation Board AK4588
Layout
INT0 MCLK DAUX2 CAD1 CAD0 TEST2 PVDD PVSS
MS0287-E-01
CCLK/SCL CDTI/SDA DAUX1 SDTI4 SDTI3 SDTI2 SDTI1 XTL1 XTL0 MASTER DZF2 DZF1 LOUT4 ROUT4 LOUT3
INT1 BOUT TVDD DVDD DVSS TEST3 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO
(Top View)
TEST1 AVSS AVDD VREFH VCOM ROUT1 LOUT1 ROUT2 LOUT2 ROUT3
2004/03
[AK4588]
Compatibility with AK4628 AK4114
Functions AK4628+ AK4114 AK4588 Parallel control mode TDM0, DFS0, DZFE, SDOS, Available available SMUTE pins Chip wire serial AK4628: CAD1/0 pins ADC/DAC part: CAD1/0 pins address(*) (I2C pin= "L") AK4114: Fixed "00" DIR/DIT part: Fixed "00" AK4628: CAD1/0 pins ADC/DAC part: CAD1/0 pins (I2C "H") AK4114: CAD1/0 pins DIR/DIT part: Fixed "00" AK4588 register maps including ADC/DAC part (compatible with AK4628) DIR/DIT part (compatible with AK4114). Each register selected Chip Address.
MS0287-E-01
2004/03
[AK4588]
PIN/FUNCTION
Name INT1 BOUT TVDD DVDD DVSS TEST3 MCKO2 MCKO1 COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1 CDTO CCLK CDTI DAUX1 SDTI4 SDTI3 SDTI2 SDTI1 XTL1 XTL0 Function Interrupt Block-Start Output Receiver Input during first flames. Output Buffer Power Supply Pin, 2.7V5.5V Digital Power Supply Pin, 4.5V5.5V Digital Ground X'tal clock Output X'tal External clock Input Test This should connected DVSS. Master Clock Output Master Clock Output C-bit Output Receiver Input U-bit Output Receiver Input V-bit Output Receiver Input Audio Serial Data Output (DIR/DIT part) Audio Serial Data Clock (DIR/DIT part) Channel Clock (DIR/DIT part) Audio Serial Data Output (ADC/DAC part) Audio Serial Data Clock (ADC/DAC part) Input Channel Clock Control Data Output Serial Mode, pin= "L". Control Data Clock Serial Mode, pin= Control Data Clock Serial Mode, pin= Control Data Input Serial Mode, pin= "L". Control Data Serial Mode, pin= "H". Chip Select Serial Mode, pin="L". This should connected DVSS, pin="H". Audio Serial Data Input (ADC/DAC part) DAC4 Audio Serial Data Input DAC3 Audio Serial Data Input DAC2 Audio Serial Data Input DAC1 Audio Serial Data Input X'tal Frequency Select X'tal Frequency Select
MS0287-E-01
2004/03
[AK4588]
Name MASTER
DZF2
DZF1 LOUT4 ROUT4 LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 VCOM VREFH
Function Power-Down Mode When "L", AK4588 powered-down, output goes "L", registers reset. When CAD1-0 pins changed, AK4588 should reset pin. Master Mode Select "H": Master mode, "L": Slave mode Zero Input Detect (Table When input data group follow total 8192 LRCK cycles with input data, this goes "H". When RSTN1 PWDAN "0", this goes "H". Analog Input Overflow Detect This goes analog input overflows. This becomes OVFE Zero Input Detect (Table When input data group follow total 8192 LRCK cycles with input data, this goes "H". When RSTN1 PWDAN "0", this goes "H". DAC4 Analog Output Connect internal bonding. This should opened. DAC4 Analog Output Connect internal bonding. This should opened. DAC3 Analog Output Connect internal bonding. This should opened. DAC3 Analog Output Connect internal bonding. This should opened. DAC2 Analog Output Connect internal bonding. This should opened. DAC2 Analog Output Connect internal bonding. This should opened. DAC1 Analog Output Connect internal bonding. This should opened. DAC1 Analog Output Connect internal bonding. This should opened. Analog Input Analog Input Common Voltage Output 2.2µF capacitor should connected AVSS externally. Positive Voltage Reference Input Pin, AVDD
MS0287-E-01
2004/03
[AK4588]
Function Analog Power Supply Pin, 4.5V5.5V Analog Ground Pin, Receiver Channel (Internal biased pin. Internally biased PVDD/2) Connect internal bonding. This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) Test TEST1 This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) Connect internal bonding. This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) PVSS Ground External Resistor +/-1% resistor should connected PVSS externally. PVDD Power supply Pin, 4.5V5.5V Receiver Channel (Internal biased pin. Internally biased PVDD/2) Test TEST2 This should connected PVSS. Receiver Channel (Internal biased pin. Internally biased PVDD/2) Chip Address (ADC/DAC part) CAD0 Receiver Channel (Internal biased pin. Internally biased PVDD/2) Chip Address (ADC/DAC part) CAD1 Receiver Channel (Internal biased pin. Internally biased PVDD/2) Control Mode Select Pin. "L": 4-wire Serial, "H": DAUX2 Auxiliary Audio Data Input (DIR/DIT part) V-bit Input Transmitter Output Master Clock Input MCLK Transmit Channel (Through Data) Output Transmit Channel Output1 When "0", Transmit Channel (Through Data) Output Pin. When "1", Transmit Channel (DAUX2 Data) Output (Default). INT0 Interrupt Note: input pins except internal biased pins internal pull-down should left floating.
PVDD 20k(typ) 20k(typ) PVSS VCOM
Name AVDD AVSS
Internal biased Circuit
MS0287-E-01
2004/03
[AK4588]
Handling Unused
unused pins should processed appropriately below. Classification Analog Digital Name RX7-0, LOUT4-1, ROUT4-1, LIN, INT1-0, BOUT, XTO, MCKO2-1, COUT, UOUT, VOUT, SDTO2-1, CDTO, DZF2-1, TX1-0 CSN, DAUX2-1, SDTI4-1, XTL1-0 TEST3-1 Setting These pins should open. These pins should open. These pins should connected DVSS. These pins should connected PVSS.
MS0287-E-01
2004/03
[AK4588]
ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, PVSS=0V; Note Parameter Symbol Power Supplies Analog AVDD -0.3 Digital DVDD -0.3 PVDD -0.3 Output buffer TVDD -0.3 |AVSS-DVSS| (Note GND1 |AVSS-PVSS| (Note GND2 Input Current (any pins except supplies) Analog Input Voltage (LIN, pins) VINA -0.3 Digital Input Voltage Except LRCK1-2, BICK1-2, RX0-7, CAD0-1, VIND1 -0.3 TEST1-2 pins LRCK1-2, BICK1-2 pins VIND2 -0.3 RX0-7, CAD0-1, TEST1-2 VIND3 -0.3 Ambient Temperature (power applied) Storage Temperature Tstg
Notes: voltages with respect ground. 2.AVSS, DVSS PVSS must connected same analog ground plane.
AVDD+0.3 DVDD+0.3 TVDD+0.3 PVDD+0.3
Units
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, PVSS=0V; Note Parameter Symbol Power Supplies Analog AVDD (Note Digital DVDD PVDD Output buffer TVDD
AVDD AVDD DVDD
Units
Notes: voltages with respect ground. power sequence between AVDD, DVDD, PVDD TVDD critical. save leak current power down mode, AVDD, DVDD, PVDD become same voltage much possible. WARNING: assumes responsibility usage beyond conditions this datasheet.
MS0287-E-01
2004/03
[AK4588]
ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz fs=48kHz, 20Hz~40kHz fs=96kHz; 20Hz~40kHz fs=192kHz, unless otherwise specified) Parameter Units Analog Input Characteristics Resolution Bits S/(N+D) (-0.5dBFS) fs=48kHz fs=96kHz (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted (Note fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted Interchannel Isolation Accuracy Interchannel Gain Mismatch Gain Drift ppm/°C Input Voltage AIN=0.62xVREFH 2.90 3.10 3.30 Input Resistance fs=48kHz fs=96kHz Power Supply Rejection (Note Analog Output Characteristics Resolution Bits S/(N+D) fs=48kHz fs=96kHz fs=192kHz (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted (Note fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted Interchannel Isolation Accuracy Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage AOUT=0.6xVREFH 2.75 3.25 Load Resistance Power Supply Rejection (Note Power Supplies Power Supply Current Normal Operation (PDN "H") (Note AVDD fs=48kHz,fs=96kHz fs=192kHz PVDD DVDD+TVDD fs=48kHz (Note fs=96kHz fs=192kHz Power-down mode (PDN "L") (Note
MS0287-E-01
2004/03
[AK4588]
Notes: measured CCIR-ARM 96dB(@fs=48kHz). applied AVDD, DVDD, PVDD TVDD with 1kHz, 50mVpp. VREFH held constant voltage. measured CCIR-ARM 102dB(@fs=48kHz). CL=20pF, X'tal=24.576MHz, CM1-0="10", CM1-0="10", OCKS1-0="10"@48kHz,"00"@96kHz, "11"@192kHz. TVDD=13mA(typ). power-down mode. inputs open digital input pins including clock pins (MCLK, BICK, LRCK) held DVSS.
FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.55.5V; TVDD=2.75.5V; fs=48kHz) Parameter Symbol Digital Filter (Decimation LPF): Passband ±0.1dB (Note -0.2dB -3.0dB Stopband 28.0 Passband Ripple Stopband Attenuation Group Delay (Note Group Delay Distortion Digital Filter (HPF): Frequency Response (Note -3dB -0.1dB Digital Filter: Passband (Note -0.1dB -6.0dB Stopband 26.2 Passband Ripple Stopband Attenuation Group Delay (Note Digital Filter Analog Filter: Frequency Response: 20.0kHz 40.0kHz (Note 80.0kHz (Note
18.9 ±0.04
Units 1/fs
20.0 23.0
21.8 ±0.02 19.2 ±0.2 ±0.3 ±1.0
24.0
1/fs
Notes: passband stopband frequencies scale with example, 21.8kHz -0.1dB 0.454 (DAC). reference frequency these responses 1kHz. calculating delay time which occurred digital filtering. This time from setting input analog signal setting 24bit data both channels output register ADC. DAC, this time from setting 20/24bit data both channels input register output analog signal. 40kHz@fs=96kHz, 80kHz@fs=192kHz
MS0287-E-01
2004/03
[AK4588]
CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.55.5V; TVDD=2.75.5V) Parameter Symbol High-Level Input Voltage (Except pin) (XTI pin) 70%DVDD Low-Level Input Voltage (Except pin) (XTI pin) Input Voltage Coupling (XTI pin) (Note 40%DVDD High-Level Output Voltage (Except TX0-1, pins Iout=-400µA) TVDD-0.4 (TX0-1 Iout=-400µA) DVDD-0.4 (DZF Iout=-400µA) AVDD-0.4 Low-Level Output Voltage (Iout=400µA) Input Leakage Current Notes: case connecting capacitance pin.
30%DVDD
Units
S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V; TVDD=2.7~5.5V) Parameter Symbol Input Resistance Input Voltage (internally biased PVDD/2) Input Hysteresis Input Sample Frequency PVDD 20k(typ) 20k(typ) PVSS VCOM
Units mVpp
Internal biased Circuit
MS0287-E-01
2004/03
[AK4588]
SWITCHING CHARACTERISTICS (ADC/DAC part) (Ta=25°C; AVDD, DVDD, PVDD=4.55.5V; TVDD=2.75.5V; CL=20pF) Parameter Symbol Master Clock Timing Master Clock 256fsn, 128fsd: fCLK 8.192 Pulse Width tCLKL Pulse Width High tCLKH 384fsn, 192fsd: fCLK 12.288 Pulse Width tCLKL Pulse Width High tCLKH 512fsn, 256fsd: fCLK 16.384 Pulse Width tCLKL Pulse Width High tCLKH
LRCK1 Timing (Slave Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle mode LRCK1 frequency time time mode LRCK1 frequency time time LRCK1 Timing (Master Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle mode LRCK1 frequency time (Note mode LRCK1 frequency time (Note Power-down Reset Timing Pulse Width (Note SDTO1 valid (Note
Units
12.288
18.432
24.576
Duty tLRH tLRL tLRH tLRL
1/256fs 1/256fs 1/128fs 1/128fs
Duty tLRH tLRH tPDV
1/8fs 1/4fs
1/fs
Notes: time format. AK4588 reset bringing upon power-up. These cycles number LRCK rising from rising.
MS0287-E-01
2004/03
[AK4588]
Parameter Audio Interface Timing (Slave Mode) Normal mode BICK1 Period BICK1 Pulse Width Pulse Width High LRCK1 Edge BICK1 (Note BICK1 LRCK1 Edge (Note LRCK1 SDTO1(MSB) BICK1 SDTO1 SDTI1-4,DAUX1 Hold Time SDTI1-4,DAUX1 Setup Time mode BICK1 Period BICK1 Pulse Width Pulse Width High LRCK1 Edge BICK1 (Note BICK1 LRCK1 Edge (Note BICK1 SDTO1 SDTI1 Hold Time SDTI1 Setup Time mode BICK1 Period BICK1 Pulse Width Pulse Width High LRCK1 Edge BICK1 (Note BICK1 LRCK1 Edge (Note BICK1 SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time Audio Interface Timing (Master Mode) Normal mode BICK1 Frequency BICK1 Duty BICK1 LRCK1 Edge BICK1"" SDTO1 SDTI1-4,DAUX1 Hold Time SDTI1-4,DAUX1 setup Time mode BICK1 Frequency BICK1 Duty (Note BICK1 LRCK1 Edge BICK1 SDTO1 SDTI1 Hold Time SDTI1 Setup Time mode BICK1 Frequency BICK1 Duty (Note BICK1 LRCK1 Edge BICK1 SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time
Symbol
Units
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS
fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
64fs 256fs 128fs
Notes: BICK1 rising edge must occur same time LRCK1 edge. When MCLK 512fs, dBCK guaranteed. When 384fs 256fs, dBCK guaranteed. When MCLK 256fs, dBCK guaranteed. When 128fs, dBCK guaranteed.
MS0287-E-01
2004/03
[AK4588]
Timing Diagram(ADC/DAC part)
1/fCLK tCLKH tCLKL
MCLK
1/fsn, 1/fsd, 1/fsq
LRCK1
tBCK tBCKH tBCKL
BICK1
Clock Timing (Normal mode)
1/fCLK tCLKH tCLKL
MCLK
1/fs tLRH tLRL
LRCK1
tBCK BICK1 tBCKH tBCKL
Clock Timing (TDM mode, mode)
MS0287-E-01
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[AK4588]
LRCK1 tBLR tLRB
BICK1
tLRS tBSD
SDTO1 tSDS
50%TVDD
tSDH
SDTI
Audio Interface Timing (Normal mode)
tBLR tLRB tBSD
LRCK1
BICK1
SDTO1 tSDS
50%TVDD
tSDH
SDTI
Audio Interface Timing (TDM mode, mode)
MS0287-E-01
2004/03
[AK4588]
LRCK1
50%TVDD
tMBLR BICK1 50%TVDD
tBSD
SDTO1 tDXS tDXH
50%TVDD
DAUX1
Audio Interface timing (Master Mode)
MS0287-E-01
2004/03
[AK4588]
SWITCHING CHARACTERISTICS (DIR/DIT part) (Ta=25°C; DVDD, AVDD4.5~5.5V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 External Clock Frequency fECLK 11.2896 Duty dECLK MCKO1 Output Frequency fMCK1 4.096 Duty dMCK1 MCKO2 Output Frequency fMCK2 2.048 Duty dMCK2 Clock Recover Frequency (RX0-7) fpll LRCK2 Frequency Duty Cycle dLCK Audio Interface Timing Slave Mode BICK2 Period tBCK tBCKL BICK2 Pulse Width Pulse Width High tBCKH tLRB LRCK2 Edge BICK2 (Note tBLR BICK2 LRCK2 Edge (Note tLRM LRCK2 SDTO2 (MSB) tBSD BICK2 SDTO2 tDXH DAUX2 Hold Time tDXS DAUX2 Setup Time Master Mode BICK2 Frequency fBCK 64fs BICK2 Duty dBCK tMBLR BICK2 LRCK2 tBSD BICK2 SDTO2 tDXH DAUX2 Hold Time tDXS DAUX2 Setup Time Notes; BICK2 rising edge must occur same time LRCK2 edge.
24.576 24.576 24.576 24.576
Units
MS0287-E-01
2004/03
[AK4588]
Timing Diagram(DIR/DIT part)
1/fECLK tECLKH tECLKL dECLK tECLKH fECLK tECLKL fECLK
1/fMCK1
MCKO1 tMCKH1 tMCKL1
50%TVDD dMCK1 tMCKH1 fMCK1 tMCKL1 fMCK1
1/fMCK2
MCKO2 tMCKH2 tMCKL2
50%TVDD dMCK2 tMCKH2 fMCK2 tMCKL2 fMCK2
1/fs tLRH tLRL dLCK tLRH tLRL
LRCK2
LRCK2 tBCK tBLR BICK2 tLRB tBCKL tBCKH
tLRM tBSD 50%TVDD
SDTO2 tDXS tDXH
DAUX2
Serial Interface Timing (Slave Mode)
MS0287-E-01
2004/03
[AK4588]
LRCK2
50%TVDD
tMBLR BICK2 50%TVDD
tBSD 50%TVDD
SDTO2 tDXS tDXH
DAUX2
Serial Interface Timing (Master Mode)
Power Down Reset Timing
MS0287-E-01
2004/03
[AK4588]
SWITCHING CHARACTERISTICS (ADC/DAC part DIR/DIT part) (Ta=25°C; AVDD, DVDD, PVDD=4.55.5V; TVDD=2.75.5V; CL=20pF) Parameter Symbol Control Interface Timing (4-wire serial mode) CCLK Period tCCK CCLK Pulse Width tCCKL Pulse Width High tCCKH CDTI Setup Time tCDS CDTI Hold Time tCDH Time tCSW tCSS CCLK tCSH CCLK tDCD CDTO Delay tCCZ CDTO Hi-Z Control Interface Timing mode) fSCL Clock Frequency tBUF Free Time Between Transmissions tHD:STA Start Condition Hold Time (prior first clock pulse) tLOW Clock Time tHIGH Clock High Time tSU:STA Setup Time Repeated Start Condition tHD:DAT Hold Time from Falling (Note 0.25 tSU:DAT Setup Time from Rising Rise Time Both Lines Fall Time Both Lines tSU:STO Setup Time Stop Condition Capacitive load Pulse Width Spike Noise Suppressed Input Filter
Notes: Data must held sufficient time bridge transition time SCL. registered trademark Philips Semiconductors.
Units
Purchase Asahi Kasei Microsystems Co., components conveys license under Philips patent components system, provided system conform specifications defined Philips.
MS0287-E-01
2004/03
[AK4588]
Timing Diagram (ADC/DAC part DIR/DIT part)
tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS
CDTI
CDTO
Hi-Z
WRITE/READ Command Input Timing 4-wire serial mode ADC/DAC part doesn't support READ command.
tCSW tCSH
CCLK
CDTI
CDTO
Hi-Z
WRITE Data Input Timing 4-wire serial mode
CCLK
CDTI
tDCD
CDTO
Hi-Z
50%TVDD
READ Data Output Timing 4-wire serial mode ADC/DAC part doesn't support READ command.
MS0287-E-01
2004/03
[AK4588]
tCSW tCSH CCLK
CDTI
tCCZ
CDTO
50%TVDD
READ Data Input Timing 4-wire serial mode ADC/DAC part doesn't support READ command.
tBUF tLOW tHIGH tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
mode Timing ADC/DAC part doesn't support READ command.
tPDV
SDTO
50%TVDD
Power-down Reset Timing
MS0287-E-01
2004/03
[AK4588]
OPERATION OVERVIEW (ADC/DAC part) System Clock
external clocks, which required operate AK4588, MCLK, LRCK1 BICK1. MCLK should synchronized with LRCK1 phase critical. There methods MCLK frequency. Manual Setting Mode (ACKS "0": Default), sampling speed DFS1-0 (Table frequency MCLK each sampling speed automatically. (Table Auto Setting Mode (ACKS "1"), MCLK frequency detected automatically (Table internal master clock becomes appropriate frequency (Table necessary DFS1-0 bits. Only MCLK necessary master mode. Master Clock Input Frequency should selected CKS1-0 bits (Table Sampling Speed should selected DFS1-0 bits (Table frequencies duties clocks (LRCK1, BICK1) stabile after setting CKS1-0 bits DFS1-0 bits External clocks (MCLK, BICK1, LRCK1) should always present whenever AK4588 normal operation mode (PDN "H"). these clocks provided, AK4588 draw excess current because device utilizes dynamic refreshed logic internally. external clocks present, AK4588 should power-down mode (PDN "L") reset mode (RSTN1 "0"). After exiting reset power-up etc., AK4588 power-down mode until MCLK LRCK input. Master mode, External clock(MCLK) should always supplied except power-down mode. power-down mode until MCLK will supplied, when Reset canceled Power-ON
DFS1
DFS0
Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 120kHz~192kHz
Default
Table Sampling Speed (Manual Setting Mode)
CKS1
CKS0
Normal 256fs 384fs 512fs 256fs
Double 128fs 192fs 256fs 256fs
Quad 128fs 128fs 128fs 128fs
Default
Table 2.Master clock input select (Master Mode) LRCK1 32.0kHz 44.1kHz 48.0kHz MCLK (MHz) 384fs 12.2880 16.9344 18.4320 BICK1 (MHz) 64fs 2.0480 2.8224 3.0720
256fs 8.1920 11.2896 12.2880
512fs 16.3840 22.5792 24.5760
Table System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK1 88.2kHz 96.0kHz
128fs 11.2896 12.2880
MCLK (MHz) 192fs 16.9344 18.4320
256fs 22.5792 24.5760
BICK1 (MHz) 64fs 5.6448 6.1440
Table System Clock Example (Double Speed Mode @Manual Setting Mode) (Note: Double speed mode (DFS1= "0", DFS0 "1"), 128fs 192fs available ADC.) MS0287-E-01 2004/03
[AK4588]
LRCK1 176.4kHz 192.0kHz
128fs 22.5792 24.5760
MCLK (MHz) 192fs
256fs
BICK1 (MHz) 64fs 11.2896 12.2880
Table System Clock Example (Quad Speed Mode @Manual Setting Mode) (Note: Quad speed mode (DFS1= "1", DFS0 "0") available ADC.)
MCLK 512fs 256fs 128fs
Sampling Speed Normal Double Quad
Table Sampling Speed (Auto Setting Mode)
LRCK1 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs 22.5792 24.5760
MCLK (MHz) 256fs 22.5792 24.5760
512fs 16.3840 22.5792 24.5760
Sampling Speed Normal Double Quad
Table System Clock Example (Auto Setting Mode)
De-emphasis Filter
AK4588 includes digital de-emphasis filter (tc=50/15µs) filter. De-emphasis filter available Double Speed Mode Quad Speed Mode. This filter corresponds three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis each individually register data DEMA1-C0 bits (DAC1: DEMA1-0 bits, DAC2: DEMB1-0 bits, DAC3: DEMC1-0 bits, DAC4: DEMD1-0 bits, "Register Definitions"). Mode Sampling Speed Normal Speed Normal Speed Normal Speed Normal Speed DEM1 DEM0 44.1kHz 48kHz 32kHz
Default
Table De-emphasis control
Digital High Pass Filter
digital high pass filter offset cancel. cut-off frequency 1.0Hz fs=48kHz scales with sampling rate (fs).
MS0287-E-01
2004/03
[AK4588]
Master mode Slave mode
Master Mode selected setting MASTER "H". LRCK1 BICK1 will outputs Master Mode. And, Slave Mode selected setting this "L". LRCK1 BICK1 will inputs Slave Mode. Operation LRCK1 BICK1 shown below Table
PWADN bit, PWDAN
MASTER LRCK1 Input output Input "00" output Input Except "00" Output Table Operation LRCK1 BICK1
BICK1 Input output Input output Input Output
Audio Serial Interface Format
When TDM1-0 "00", modes selected DIF1-0 bits shown Table modes serial data MSB-first, complement format. SDTO1 clocked falling edge BICK1 SDTI/DAUX1 latched rising edge BICK1. Figures shows timing SDOS "0". this case, SDTO1 outputs output data. When SDOS bits "1", data input DAUX1 converted SDTO1's format output from SDTO1. Mode SDTI input formats used 16-20bit data zeroing unused LSBs. Mode MASTER TDM0 DIF1 DIF0 SDTO1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, SDTI1-4, DAUX 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, LRCK1 BICK1 48fs 48fs 48fs 48fs 64fs 64fs 64fs 64fs Default
Table Audio data formats (Normal mode) audio serial interface format becomes mode TDM1-0 bits "01". Mode, serial data (eight channels) input SDTI1 pin. input data SDTI2-4 pins ignored. BICK1 should fixed 256fs. time time LRCK1 should 1/256fs least. Eight modes selected DIF1-0 bits shown Table modes serial data MSB-first, complement format. SDTO1 clocked falling edge BICK1 SDTI1 latched rising edge BICK1 pin. SDOS LOOP1-0 bits should mode. Mode TDM1-0 "10". this Mode, serial data (four channels; input SDTI1 pin. Other four data (L3, input SDTI2 pin.
MS0287-E-01
2004/03
[AK4588]
Mode
MASTER
TDM0
DIF1
DIF0
SDTO1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit,
SDTI1 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit,
LRCK1
BICK1 256fs 256fs 256fs 256fs 256fs 256fs 256fs 256fs
Table Audio data formats (TDM mode)
Mode
MASTER
DIF1
DIF0
SDTO1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit,
SDTI1, SDTI2 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit,
LRCK1
BICK1 128fs 128fs 128fs 128fs 128fs 128fs 128fs 128fs
Table Audio data formats (TDM mode)
MS0287-E-01
2004/03
[AK4588]
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Data
Data
Figure Mode Timing
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care 23:MSB, 0:LSB
Don't Care
Data
Data
Figure Mode Timing
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB
Data
Data
Figure 3.Mode Timing
LRCK1
BICK1(64fs) SDTO1(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB Data Data
Figure Mode Timing
MS0287-E-01
2004/03
[AK4588]
LRCK1 LRCK1 BICK1(256fs) SDTO1(o)
I1(i)
Figure Mode Timing
LRCK1 LRCK1 BICK1(256fs) SDTO1(o)
I1(i)
Figure Mode Timing
LRCK1 LRCK1 BICK1(256fs) SDTO1(o)
I1(i)
Figure Mode Timinig
LRCK1 LRCK1 BICK1(256fs) SDTO1(o)
I1(i)
Figure Mode Timing
MS0287-E-01
2004/03
[AK4588]
LRCK1 LRCK1 BICK1(128fs) SDTO1(o)
I1(i)
I2(i)
BICK
Figure Mode Timing
LRCK1 LRCK1 BICK1(128fs)
I1(i)
I2(i)
BICK
Figure Mode TIming
LRCK1 LRCK1 BICK1(128fs) SDTO1(o)
I1(i)
I2(i)
Figure Mode Timing
MS0287-E-01
2004/03
[AK4588]
LRCK1 LRCK1 BICK1(128fs) SDTO1(o)
I1(i)
I2(i)
BICK
Figure Mode Timing
MS0287-E-01
2004/03
[AK4588]
Overflow Detection
AK4588 overflow detect function analog input. Overflow detect function enable OVFE "1". goes analog input overflows (more than -0.3dBFS). output overflowed analog input same group delay 19.1/fs 398µs @fs=48kHz). 522/fs (=11.8ms @fs=48kHz) after then overflow detection enabled.
Zero Detection
AK4588 pins zero detect flag outputs. Channel grouping selected DZFM3-0 bits (Table 13). DZF1 corresponds group channels DZF2 corresponds group channels. However DZF2 becomes OVFE "1". Zero detection mode mode DZF1 eight channels DZF2 disabled ("L") mode Table shows relation OVFE DZF. When input data channels group 1(group continuously zeros 8192 LRCK1 cycles, DZF1 (DZF2) goes "H". DZF1 (DZF2) immediately goes input data channels group (group zero after going DZF1 (DZF2) "H". Mode DZFM AOUT DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 disable (DZF1=DZF2 "L") DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1
DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1
DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF1 DZF1
DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF1 DZF2
DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 Default DZF2 DZF2
disable (DZF1=DZF2 "L")
Table Zero detect control OVFE DZF1 DZF2/OVF Selectable (Table Selectable (Table Selectable (Table output Table DZF1-2 pins outputs
MS0287-E-01
2004/03
[AK4588]
Digital Attenuator
AK4588 channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level each channel each ATT7-0 bits (Table 15). ATT7-0 Attenuation Level -0.5dB -1.0dB -62.5dB -63dB MUTE MUTE MUTE
Default
Table Attenuation level digital attenuator Transition time between values ATT7-0 bits selected ATS1-0 bits (Table 16). Transition between values soft transition. Therefore, switching noise does occur transition. Mode ATS1 ATS0 speed 1792/fs 896/fs 256/fs 256/fs
Default
Table Transition time between values ATT7-0 bits transition between values soft transition 1792 levels mode takes 1792/fs (37.3ms@fs=48kHz) from 00H(0dB) 7FH(MUTE) mode goes "L", ATTs initialized 00H. ATTs when RSTN "0". When RSTN return "1", ATTs fade their current value.
MS0287-E-01
2004/03
[AK4588]
Soft mute operation
Soft mute operation performed digital domain. When SMUTE goes "1", output signal attenuated during transition time (Table from current level. When SMUTE returned "0", mute cancelled output attenuation gradually changes level during transition time. soft mute cancelled before attenuating after starting operation, attenuation discontinued returned level same cycle. soft mute effective changing signal source without stopping signal transmission.
SMUTE
Level Attenuation
AOUT 8192/fs
DZF1,2
Notes: transition time (Table 16). example, Normal Speed Mode, this time 1792LRCK1 cycles (1792/fs) ATT_DATA=00H. transition soft-mute from analog output corresponding digital input group delay, soft mute cancelled before attenuating after starting operation, attenuation discontinued returned level same cycle. When input data channels group continuously zeros 8192 LRCK1 cycles, each channel goes "H". immediately goes input data either channel group zero after going "H". Figure Soft mute zero detection
System Reset
AK4588 should reset once bringing upon power-up. AK4588 powered internal timing starts clocking LRCK1 after exiting reset power down state MCLK. AK4588 power-down mode until MCLK LRCK1 input.
MS0287-E-01
2004/03
[AK4588]
Power ON/OFF Sequence DACs AK4588 placed power-down mode bringing both digital filters reset same time. also reset control registers their default values. power-down mode, analog outputs VCOM voltage DZF1-2 pins "L". This reset should always done after power-up. case ADC, analog initialization cycle starts after exiting power-down mode. Therefore, output data, SDTO1 becomes available after cycles LRCK1 clock. case DAC, analog initialization cycle starts after exiting power-down mode. analog outputs VCOM voltage during initialization. Figure shows sequences power-down power-up.
DACs powered-down individually PWADN PWDAN bits. DAC1-4 power-down individually PD1-4 bits. this case, internal register values initialized. When PWADN "0", SDTO1 goes "L". When PWDAN PD1-4 bits "0", analog outputs VCOM voltage DZF1-2 pins "H". Because some click noise occurs, analog output should muted externally click noise influences system application.
Power
522/fs
Internal State Internal State (Analog) (Digital) (Digital)
"0"data
Init Cycle 516/fs
Normal Operation
Power-down
Normal Operation Power-down
Init Cycle
"0"data
"0"data
"0"data
(Analog) Clock
MCLK,LRCK,SCLK
Don't care
Don't care 1011/fs (10)
DZF1/DZF2
External Mute
Mute
Mute
Notes: analog part initialized after exiting power-down state. analog part initialized after exiting power-down state. Digital output corresponding analog input analog output corresponding digital input have group delay (GD). output data power-down state. Click noise occurs initialization analog part. Please mute digital output externally click noise influences system application. Click noise occurs falling edge 512/fs after rising edge PDN. When external clocks (MCLK, BICK1 LRCK1) stopped, AK4588 should power-down mode. DZF1-2 pins power-down mode (PDN "L"). Please mute analog output externally click noise influences system application. (10) DZF= 1011/fs after PDN= Figure Power-down/up sequence example MS0287-E-01 2004/03
[AK4588]
Reset Function
When RSTN1 "0", DACs powered-down internal register initialized. analog outputs VCOM voltage, DZF1-2 pins SDTO1 goes "L". Because some click noise occurs, analog output should muted externally click noise influences system application. Figure shows power-up sequence.
RSTN
4~5/fs 1~2/fs
Internal RSTN
516/fs
Internal State Internal State
Normal Operation
Digital Block Power-down
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
Normal Operation
(Analog) (Digital) (Digital)
"0"data
"0"data
(Analog) Clock
MCLK,LRCK,SCLK
Don't care
45/fs
DZF1/DZF2
Notes: analog part initialized after exiting reset state. Digital output corresponding analog input analog output corresponding digital input have group delay (GD). output data power-down state. Click noise occurs when internal RSTN becomes "1". Please mute digital output externally click noise influences system application. When RSTN1 "0", analog outputs VCOM voltage. Click noise occurs 45/fs after RSTN1 becomes "0", occurs 12/fs after RSTN1 becomes "1". This noise output even data input. external clocks (MCLK, BICK1 LRCK1) stopped reset mode. When exiting reset mode, should written RSTN1 after external clocks (MCLK, BICK1 LRCK1) fed. pins when RSTN1 becomes "0", 6~7/fs after RSTN1 becomes "1". There delay, 4~5/fs from RSTN1 internal RSTN "0". Figure Reset sequence example
MS0287-E-01
2004/03
[AK4588]
partial Power-Down Function
DACs AK4588 powered-down individually PD1-4 bits. analog part power-down PD1-4 bits ="1", however, digital part power-down Even DACs were power-down partial power-down bits, digital part continue function. analog output channel which power-down PD1-4 bits fixed voltage VCOM. though detection being done, result detection stops reflecting DZF1-2 pins. Because some click noise occurs both set-up release power-down, either analog output should muted externally PD1-4 bits should when PWDAN ="0" RSTN ="0", click noise influences system application. Figure shows sequence power-down power-up PD1-4 bits.
PD1-4 Power Down Channel Digital Internal State Analog Internal State (Digital)
Normal Operation Normal Operation
Power-down
Normal Operation
Power-down
Normal Operation Normal Operation
"0"data
8192/fs
(Analog) Detect Internal State Normal Operation Channel (Digital)
"0"data
(Analog)
8192/fs
Detect Internal State
Clock
MCLK,LRCK,SCLK
DZF1/DZF2
Notes: Digital output corresponding analog input analog output corresponding digital input have group delay (GD). Analog output powered down PD1-4 bits ="1" fixed voltage VCOM. Immediately after PD1-4 bits changed, some click noise occurs output channel changed bits. Though detection being done certain channel which PD1-4 bits ="1", result detection stops reflecting DZF1-2 pins. detection which power-down setting ignored, DZF1-2 pins become "H". When power-down function channel input signal, even partial power-down function DZF1-2 bits become "H". Figure partial power-down example
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2004/03
[AK4588]
Register
Addr Register Name Control Control LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control De-emphasis speed Power Down Control Zero detect LOUT4 Volume Control ROUT4 Volume Control CKS1 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 DEMD1 OVFE ATT7 ATT7 DFS1 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 DEMD0 DZFM3 ATT6 ATT6 TDM1 LOOP1 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 DEMA1 ATS1 DZFM2 ATT5 ATT5 TDM0 LOOP0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 DEMA0 ATS0 DZFM1 ATT4 ATT4 DIF1 SDOS ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 DEMB1 DZFM0 ATT3 ATT3 DIF0 DFS0 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DEMB0 PWVRN ATT2 ATT2 ACKS ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 DEMC1 PWADN ATT1 ATT1 SMUTE CKS0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 DEMC0 RSTN1 PWDAN ATT0 ATT0
Note: addresses from 1FH, data written. When goes "L", registers initialized their default values. When RSTN1 goes "0", internal timing reset DZF1-2 pins "H", registers initialized their default values.
Register Definitions
Addr Register Name Control Default TDM1 TDM0 DIF1 DIF0 SMUTE
SMUTE: Soft Mute Enable Normal operation outputs soft-muted DIF1-0: Audio Data Interface Modes (see Table Initial: "10", mode TDM1-0: Format Select (see Table 11,12) Mode TDM1 TDM0 SDTI Sampling Speed Normal, Double, Four Times Speed Normal Speed Double Speed
MS0287-E-01
2004/03
[AK4588]
Addr Register Name Control Default
CKS1
DFS1
LOOP1
LOOP0
SDOS
DFS0
ACKS
CKS0
ACKS: Master Clock Frequency Auto Setting Mode Enable Disable, Manual Setting Mode Enable, Auto Setting Mode Master clock frequency detected automatically ACKS "1". this case, setting DFS1-0 bits ignored. When this "0", DFS1-0 bits sampling speed mode. DFS1-0: Sampling speed mode (see Table setting DFS1-0 bits ignored ACKS "1". CKS0-1: Master clock frequency select (see Table SDOS: SDTO1 source select DAUX SDOS should "1". case PWADN ="0" PWDAN ="0", setting SDOS becomes invalid. selected. output SDTO1 becomes PWADN ="0".
LOOP1-0: Loopback mode enable Normal loop back) LOUT1, LOUT2, LOUT3, LOUT4 ROUT1, ROUT2, ROUT3, ROUT4 digital output (DAUX1 input SDOS "1") connected digital input. this mode, input data SDTI1-3 ignored. audio format SDTO1 loopback mode becomes mode mode mode mode respectively. SDTI1(L) SDTI2(L), SDTI3(L), SDTI4(L) SDTI1(R) SDTI2(R), SDTI3(R), SDTI4(R) this mode input data SDTI2-4 ignored. LOOP1-0 bits should "00" "1". case PWADN ="0" PWDAN ="0", setting LOOP1-0 bits become invalid. selected. becomes normal operation loop back).
MS0287-E-01
2004/03
[AK4588]
Addr
Register Name LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control LOUT4 Volume Control ROUT4 Volume Control Default
ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7
ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6
ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5
ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4
ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3
ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2
ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1
ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0
ATT7-0: Attenuation Level (see Table 15.)
Addr Register Name De-emphasis Default
DEMD1
DEMD
DEMA
DEMA
DEMB
DEMB
DEMC
DEMC
DEMA1-0: De-emphasis response control DAC1 data SDTI1 (see Table Initial: "01", DEMB1-0: De-emphasis response control DAC2 data SDTI2 (see Table Initial: "01", DEMC1-0: De-emphasis response control DAC3 data SDTI3 (see Table Initial: "01", DEMD1-0: De-emphasis response control DAC4 data SDTI4 (see Table Initial: "01",
MS0287-E-01
2004/03
[AK4588]
Addr Register Name speed Power Down Control Default
ATS1
ATS0
RSTN1
RSTN1: Internal timing reset Reset. DZF1-2 pins "H", registers initialized. Normal operation ATS1-0: Digital attenuator transition time setting (see Table 16.) Initial: "00", mode PD1-0: Power-down control Power-up, Power-down) PD1: Power down control DAC1 PD2: Power down control DAC2 PD3: Power down control DAC3 PD4: Power down control DAC4
Addr Register Name Zero detect Default
OVFE
DZFM3
DZFM2
DZFM1
DZFM0
PWVRN
PWADN
PWDAN
PWDAN: Power-down control DAC1-4 Power-down Normal operation PWADN: Power-down control Power-down Normal operation PWVRN: Power-down control reference voltage Power-down Normal operation DZFM3-0: Zero detect mode select (see Table 13.) Initial: "0111", disable OVFE: Overflow detection enable Disable, pin#33 becomes DZF2 pin. Enable, pin#33 becomes pin.
MS0287-E-01
2004/03
[AK4588]
OPERATION OVERVIEW (DIR/DIT part) Non-PCM (AC-3, MPEG, etc.) DTS-CD Bitstream Detection
AK4588 Non-PCM steam auto-detection function. When 32bit mode Non-PCM preamble based Dolby "AC-3 Data Stream IEC60958 Interface" detected, AUTO goes "1". 96bit sync code consists 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F. Detection this pattern will AUTO "1". Once AUTO "1", will remain until 4096 frames pass through chip without additional sync pattern being detected. When those preambles detected, burst preambles that follow those sync codes stored registers. AK4588 also DTS-CD bitstream auto-detection function. When AK4588 detects DTS-CD bitstreams, DTSCD goes "1". When next sync code does come within 4096 flames, DTSCD goes until when AK4114 detects stream again.
192kHz Clock Recovery
chip jitter wide lock range with 32kHz 192kHz lock time less than 20ms. AK4588 sampling frequency detect function. either clock comparison against X'tal oscillator using channel status, AK4588 detects sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz 192kHz). loses lock when received sync interval incorrect.
Master Clock
AK4588 clock outputs, MCKO1 MCKO2. These clocks derived from either recovered clock from X'tal oscillator. frequencies master clock outputs (MCKO1 MCKO2) OCKS0 OCKS1 shown Table 512fs clock will output when 96kHz 192kHz. 256fs clock will output when 192kHz. OCKS1 OCKS0 MCKO1 256fs 256fs 512fs 128fs MCKO2 256fs 128fs 256fs 64fs X'tal 256fs 256fs 512fs 128fs (max)
Default
Table Master Clock Frequency Select (Stereo mode)
Clock Operation Mode
CM0/CM1 pins bits) select clock source data source SDTO. Mode clock source switched from X'tal when goes unlock state. Mode3, clock source fixed X'tal, also operating recovered data such bits monitored. Mode2 recommended that frequency X'tal different from recovered frequency from PLL. UNLOCK X'tal Clock source SDTO Default ON(Note) X'tal DAUX X'tal DAUX X'tal DAUX Oscillation (Power-up), OFF: STOP (Power-down) Note When X'tal used clock comparison detection (i.e. XTL1,0= "1,1"), X'tal off. Table Clock Operation Mode select Mode
MS0287-E-01
2004/03
[AK4588]
Clock Source
following circuits available feed clock AK4588. X'tal
25k(typ)
AK4588
Figure X'tal mode Note: External capacitance depends crystal oscillator (Typ. 10-40pF)
External clock
External Clock External Clock
25k(typ)
25k(typ)
AK4588
AK4588
Figure (5V). (a).External clock mode mode (Input :CMOS Level) Note: Input clock must exceed DVDD.
Figure (3.3V). (b). External clock (Input 40%DVDD)
Fixed Clock Operation Mode
25k(typ)
AK4588
Figure mode
MS0287-E-01
2004/03
[AK4588]
Sampling Frequency Pre-emphasis Detection
AK4588 methods detecting sampling frequency follows. Clock comparison between recovered clock X'tal oscillator Sampling frequency information channel status Those could selected XTL1, bits. detected frequency reported FS3-0 bits. XTL1 XTL0 X'tal Frequency 11.2896MHz 12.288MHz 24.576MHz (Use channel status) Table Reference X'tal frequency XTL1,0= "1,1" Consumer Register output mode Professional mode Clock comparison (Note (Note Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 44.1kHz 44.1kHz 0000 0000 Reserved Reserved 0001 (Others) 48kHz 48kHz 0010 0000 32kHz 32kHz 0011 0000 88.2kHz 88.2kHz (1000) 1010 96kHz 96kHz (1010) 0010 176.4kHz 176.4kHz (1100) 1011 192kHz 192kHz (1110) 0011 Note1: least range identified value Table case intermediate frequency those two, FS3-0 bits indicate nearer value. When frequency much bigger than 192kHz much smaller than 32kHz, FS3-0 bits indicate "0001". Note2: When consumer mode, Byte3 Bit3-0 copied FS3-0 bits. Table Information Except XTL1,0= "1,1"
Default
pre-emphasis information detected reported bit. These information extracted from channel default. switched channel CS12 control register. Pre-emphasis Byte Bits 0X100 0X100
Table Consumer Mode Pre-emphasis Byte Bits
Table Professional Mode
MS0287-E-01
2004/03
[AK4588]
De-emphasis Filter Control
AK4588 includes digital de-emphasis filter (tc=50/15µs) filter corresponding four sampling frequencies (32kHz, 44.1kHz, 48kHz 96kHz). When DEAU bit="1", de-emphasis filter enabled automatically sampling frequency pre-emphasis information channel status. AK4588 goes this mode default. Therefore, Parallel Mode, AK4588 always placed this mode status bits channel control de-emphasis filter. Serial Mode, DEM0/1 bits control de-emphasis filter when DEAU "0". internal de-emphasis filter bypassed recovered data output without change either pre-emphasis de-emphasis Mode OFF. (Others) Mode 44.1kHz 48kHz 32kHz 96kHz
Table De-emphasis Auto Control DEAU (Default) DEM1 DEM0 Mode 44.1kHz 48kHz 32kHz 96kHz
Default
Table De-emphasis Manual Control DEAU
System Reset Power-Down
AK4588 power-down mode circuits partially powerd-down bit. RSTN initializes register resets internal timing. Parallel Mode, only control enabled. AK4588 should reset once bringing upon power-up. Pin: analog digital circuit placed power-down reset mode bringing "L". registers initialized, clocks stopped. Reading/Witting register disabled. RSTN2 (Address 00H; D0): registers except RSTN2 bits initialized bringing RSTN2 "0". internal timings also initialized. Witting register available except RSTN2 bits. Reading register disabled. (Address 00H; D1): clock recovery part initialized bringing "0". this case, clocks stopped. registers initialized mode settings kept. Writing Reading registers enabled.
MS0287-E-01
2004/03
[AK4588]
Biphase Input Through Output
Eight receiver inputs (RX0-7) available Serial Control Mode. Each input includes amplifier corresponding unbalance mode accept signal 200mV more. IPS2-0 bits selects receiver channel. When "1", Block start signal, output from each pins. IPS2 IPS1 IPS0 INPUT Data
Default
Table Recovery Data Select
1/4fs COUT U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
SDTO2
R190
L191
R191
LRCK2 (except I2S) LRCK2 (I2S)
Figure output/input timings
MS0287-E-01
2004/03
[AK4588]
Biphase Output
AK4588 output either through output(from DIR) transmitter output(DIT; data from DAUX2 transformed IEC60958 format.) from TX1/0 pins. Those could selected bit. source through output from could selected among RX0-8 OPS00,01 bits, TX1, OPS10,11 bits respectively. When output DAUX2 data, could controlled first bytes could controlled CT39-CT0 bits control registers. When bit0= "0"(consumer mode), bit20-23 (Audio channel) could controlled directly controlled CT20 bit. When CT20 "1", AK4588 outputs "1000" C20-23 left channel output "0100" C20-23 right channel automatically. When CT20 "0", AK4588 outputs "0000" "1000" frame "0100" frame bits fixed "0".as C20-23 both channel. could controlled UDIT follows; When UDIT "0", always "0". When UDIT "1", recovered bits used (DIR/DIT loop mode bit). This mode only available when locked master mode. OPS02 OPS01 OPS00 Output Data
Default
Table Output Data Select OPS12 OPS11 OPS10 Output Data DAUX2
Default
Table Output Data Select
LRCK2 (except LRCK2 (I2S) DAUX2
R191
Figure DAUX2 input timings
MS0287-E-01
2004/03
[AK4588]
Biphase signal input/output circuit
0.1uF Coax
AK4588
Figure Consumer Input Circuit (Coaxial Input) Note: case coaxial input, coupling level this input from next input line pattern exceeds 50mV, there possibility occur incorrect operation. this case, possible lower coupling level adding this decoupling capacitor.
Optical Receiver Optical Fiber
AK4588
Figure Consumer Input Circuit (Optical Input) case coaxial input, input level line small, Serial Mode, careful crosstalk among input lines. example, inserting shield pattern among them. Parallel Mode, only channel input (RX1) available RX2-4 change other pins audio format control. Those pins must fixed "L". AK4588 includes output buffer. output level meets combination 0.5V+/-20% using external resistor network. Figure transformer 1:1.
330±2% 100±2% DVSS cable
Figure External Resistor Network
MS0287-E-01
2004/03
[AK4588]
Q-subcode buffers
AK4588 Q-subcode buffer application. AK4588 takes Q-subcode into registers following conditions. sync word (S0,S1) constructed least "0"s. start "1". Those 7bits follows start bit. distance between start bits 8-16 bits. QINT control register goes when Q-subcode differs from one, goes when QINT read.
number min=0; max=8. Figure Configuration U-bit(CD)
TRACK NUMBER INDEX
CTRL
ADRS
MINUTE SECOND FRAME ZERO ABSOLUTE MINUTE ABSOLUTE SECOND ABSOLUTE FRAME G(x)=x^16+x^12+x^5+1
Figure Q-subcode
Addr Register Name
Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame
Figure Q-subcode register
MS0287-E-01
2004/03
[AK4588]
Error Handling
There following eight events that make INT0/1 pins "H". INT0/1 pins show status following conditions. UNLOCK: when loses lock. AK4588 loses lock when distance between preambles correct when those preambles correct. PAR: when parity error biphase coding error detected, keeps until this register read. Updated every sub-frame cycle. Reading this register resets itself. AUTO: when Non-PCM bitstream detected. Updated every 4096 frames cycle. DTSCD: when DTS-CD bitstream detected. Updated every DTS-CD sync cycle. AUDION: when "AUDIO" recovered channel status indicates "1". Updated every block cycle. PEM: when "PEM" recovered channel status indicates "1". Updated every block cycle. QINT: when Q-subcode differ from one, keeps until this register read. Updated every sync code cycle Q-subcode. Reading this register resets itself. CINT: when received bits differ from one, keeps until this register read. Updated every block cycle. Reading this register resets itself. Both INT0/1 fixed when (CM1,0= "01"). Once INT0 goes "H", this holds 1024/fs cycles (this value changed EFH0/1 bits) after those events removed. INT1 goes same time when those events removed. Each INT0/1 pins mask those eight events individually. Once PAR, QINT CINT goes "1", those registers held until those registers read. While AK4588 loses lock, registers regarding C-bit U-bits initialized keep previous value. INT0/1 output ORed signal among those eight events. However, each events masked each mask bits. When each masks those events, event does affect INT0/1 pins operation (those mask affect those registers (UNLOCK, PAR, etc.) themselves. Once INT0 goes "H", maintains 1024/fs cycles (this value changed EFH0-1 bits) after events removed. Once those PAR, QINT CINT goes "1", holds until reading those registers. While AK4588 loses lock, channel status Q-subcode bits updated holds previous data. initial state, INT0 outputs ORed signal between UNLOCK PAR, INT1 outputs ORed signal among AUTO, DTSCD AUDION. Register DTSCD AUDION QINT Table Error Handling CINT SDTO2 Previous Data Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
UNLOCK
AUTO
MS0287-E-01
2004/03
[AK4588]
Error (UNLOCK, PAR,.) INT0
(Error)
Hold Time (max: 4096/fs)
INT1 Register (PAR,CINT,QINT) Register (others) Command MCKO,BICK2,LRCK2 (UNLOCK) MCKO,BICK2,LRCK2 (except UNLOCK) SDTO2 (UNLOCK)
Hold Time
Hold
Reset
READ
Free (fs: around 20kHz)
SDTO2 (PAR error) SDTO2 (others) VOUT (UNLOCK) VOUT (except UNLOCK)
Previous Data
Normal Operation
Figure INT0/1 timing
MS0287-E-01
2004/03
[AK4588]
="L" Initialize Read
INT0/1 ="H"
Release Muting
Mute output
Read
(Each Error Handling)
Read (Res registers) INT0/1 ="H"
Figure Error Handling Sequence Example
MS0287-E-01
2004/03
[AK4588]
="L" Initialize Read
INT1 ="H"
Read Detect QSUB=
(Read Q-buffer)
QCRC INT1 ="L" data valid
data invalid
Figure Error Handling Sequence Example (for Q/CINT)
MS0287-E-01
2004/03
[AK4588]
Audio Serial Interface Format
DIF0, DIF1 DIF2 pins select eight serial data formats shown Table formats serial data MSB-first, complement format. SDTO2 clocked falling edge BICK2 DAUX2 latched rising edge BICK2. BICK2 outputs 64fs clock Mode 0-5. Mode Slave Modes, BICK2 available 128fs fs=48kHz. format equal less than 20bit (Mode0-2), LSBs sub-frame truncated. Mode 3-7, last 4LSBs auxiliary data (see Figure 32). When using Master mode, BICK2 KRCK2 output pins Hi-Z during from entering Master mode. When Parity Error, Biphase Error Frame Length Error occurs sub-frame, AK4588 continues output last normal sub-frame data from SDTO2 repeatedly until error removed. When Unlock Error occurs, AK4588 output from SDTO2. case using DAUX2 pin, data transformed output from SDTO2. DAUX2 used Clock Operation Mode unlock state Mode input data format DAUX2 should left justified except Mode5 7(Table 29). Mode5 both input data format DAUX2 output data format SDTO2 I2S. Mode6 Slave Mode that corresponding Master Mode Mode4 salve Mode, LRCK2 BICK2 should with synchronizing MCKO1/2.
sub-frame IEC60958
preamble Aux.
AK4588 Audio Data (MSB First)
Figure configuration
Mode
DIF2
DIF1
DIF0
DAUX2 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit,
SDTO2 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 24bit, Left justified 24bit,
LRCK2
BICK2 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
Default
Table Audio data format
MS0287-E-01
2004/03
[AK4588]
LRCK2
BICK2 (0:64fs)
SDTO2
15:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK2
BICK2 (0:64fs)
SDTO2
23:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK2
BICK2 (64fs) SDTO2
23:MSB, 0:LSB Data Data
Figure Mode Timing
Mode4 LRCK2, BICK2 Output Mode6 LRCK2, BICK2 Input
LRCK2
BICK2 (64fs) SDTO2
23:MSB, 0:LSB Data Data
Figure Mode Timing
Mode5 LRCK2, BICK2 Output Mode7 LRCK2, BICK2 Input
MS0287-E-01
2004/03
[AK4588]
Register
Addr
Register Name Power Down Control Format De-em Control Input/ Output Control Input/ Output Control INT0 MASK INT1 MASK Receiver status Receiver status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte
Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte
CS12 TX1E EFH1
DIF2 OPS12 EFH0
DIF1 OPS11 UDIT MCIT0 MCIT1 CINT CR13 CR21 CR29 CR37
CT13 CT21 CT29 CT39
DIF0 OPS10
OCKS1 DEAU TX0E
OCKS0 DEM1 OPS02 IPS2 MPE0 MPE1 CR10 CR18 CR26 CR34
CT10 CT18 CT26 CT39
DEM0 OPS01 IPS1 MAUD0 MAUD1 AUDION QCRC CR17 CR25 CR33
CT17 CT25 CT39
RSTN2 OPS00 IPS0 MPAR0 MPAR1 CCRC CR16 CR24 CR32
CT16 CT24 CT32
MQIT0 MAUT0 MQIT1 MAUT1 QINT CR15 CR23 CR31 CR39
CT15 CT23 CT31 CT39
MULK0 MDTS0 MULK1 MDTS1 UNLCK DTSCD CR12 CR20 CR28 CR36
CT12 CT20 CT28 CT39
AUTO CR14 CR22 CR30 CR38
CT14 CT22 CT30 CT39
CR11 CR19 CR27 CR35
CT11 CT19 CT27 CT39
Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second
PC15 PD15
PC14 PD14
PC13 PD13
PC12 PD12
PC11 PD11
PC10 PD10
Q-subcode Frame When goes "L", registers initialized their default values. When RSTN goes "0", internal timing reset registers initialized their default values. data written register even "0". should written data.
MS0287-E-01
2004/03
[AK4588]
Register Definitions Reset Initialize
Addr Register Name Power Down Control Default CS12 OCKS1 OCKS0 RSTN2
RSTN2: Timing Reset Register Initialize Reset Initialize Normal Operation PWN: Power Down Power Down Normal Operation OCKS1-0: Master Clock Frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start Output Mode When BCU=1, three Output Pins(BOUT, COUT, UOUT) become enabled. block signal goes high start frame remains high until frame CS12: Channel Status Select Channel Channel Selects which channel status used derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, de-emphasis filter controlled channel Parallel Mode.
Format De-emphasis Control
Addr Register Name Format De-em Control Default DIF2 DIF1 DIF0 DEAU DEM1 DEM0
DFS: 96kHz De-emphasis Control DEM1-0: 44.1, 48kHz De-emphasis Control (see Table 24.) DEAU: De-emphasis Auto Detect Enable Disable Enable DIF2-0: Audio Data Format Control (see Table 29.)
MS0287-E-01
2004/03
[AK4588]
Input/Output Control
Addr Register Name Input/ Output Control Default TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00
OPS02-00: Output Through Data Select OPS12-10: Output Through Data Select TX0E: Output Enable Disable. outputs "L". Enable TX1E: Output Enable Disable. outputs "L". Enable Addr Register Name Input/ Output Control Default EFH1 EFH0 UDIT IPS2 IPS1 IPS0
IPS2-0: Input Recovery Data Select DIT: Through data/Transmit data select Through data data). Transmit data (DAUX2 data). UDIT: control fixed Recovered used (loop mode bit) EFH1-0: Interrupt Hold Count Select LRCK2 1024 LRCK2 2048 LRCK2 4096 LRCK2
MS0287-E-01
2004/03
[AK4588]
Mask Control INT0
Addr Register Name INT0 MASK Default MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0
MPR0: Mask Enable MAN0: Mask Enable AUDN MPE0: Mask Enable MDTS0: Mask Enable DTSCD MUL0: Mask Enable UNLOCK MCI0: Mask Enable CINT MAT0: Mask Enable AUTO MQI0: Mask Enable QINT Mask disable Mask enable
Mask Control INT1
Addr Register Name INT1 MASK Default MQI1 MAT1 MCI1 MUL1 MDTS1 MPE1 MAN1 MPR1
MPR1: Mask Enable MAN1: Mask Enable AUDN MPE1: Mask Enable MDTS1: Mask Enable DTSCD MUL1: Mask Enable UNLOCK0 MCI1: Mask Enable CINT MAT1: Mask Enable AUTO MQI1: Mask Enable QINT Mask disable Mask enable
MS0287-E-01
2004/03
[AK4588]
Receiver Status
Addr Register Name Receiver status Default QINT AUTO CINT UNLCK DTSCD AUDION
PAR: Parity Error Biphase Error Status 0:No Error 1:Error Parity Error Biphase Error detected sub-frame. AUDION: Audio Output Audio Audio This made encoding channel status bits. PEM: Pre-emphasis Detect. This made encoding channel status bits. DTSCD: DTS-CD Auto Detect detect Detect UNLCK: Lock Status Locked Lock CINT: Channel Status Buffer Interrupt change Changed AUTO: Non-PCM Auto Detect detect Detect QINT: Q-subcode Buffer Interrupt change Changed QINT, CINT bits initialized when read.
Receiver Status
Addr Register Name Receiver status Default QCRC CCRC
CCRC: Cyclic Redundancy Check Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check Q-subcode 0:No Error 1:Error Validity channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (see Table 20.)
MS0287-E-01
2004/03
[AK4588]
Receiver Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CR15 CR23 CR31 CR39 CR14 CR22 CR30 CR38 CR13 CR21 CR29 CR37 CR12 CR20 CR28 CR36 CR11 CR19 CR27 CR35 CR10 CR18 CR26 CR34 CR17 CR25 CR33 CR16 CR24 CR32
initialized
CR39-0: Receiver Channel Status Byte
Transmitter Channel Status
Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CT15 CT23 CT31 CT39 CT14 CT22 CT30 CT38 CT13 CT21 CT29 CT37 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 CT10 CT18 CT26 CT34 CT17 CT25 CT335 CT16 CT24 CT32
CT39-0: Transmitter Channel Status Byte
Burst Preamble Pc/Pd non-PCM encoded Audio Bitstreams
Addr Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default PC15 PD15 PC14 PD14 PC13 PD13 PC12 PD12 PC11 PD11 PC10 PD10
initialized
PC15-0: Burst Preamble Byte PD15-0: Burst Preamble Byte
MS0287-E-01
2004/03
[AK4588]
Q-subcode Buffer
Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Default
initialized
MS0287-E-01
2004/03
[AK4588]
Burst Preambles non-PCM Bitstreams
sub-frame IEC958
preamble Aux.
bits bitstream
Burst_payload
stuffing
repetition time burst
Figure Data structure IEC60958 Preamble word Length field bits bits bits bits Contents sync word sync word Burst info Length code Value 0xF872 0x4E1F Table Numbers bits
Table Burst preamble words
MS0287-E-01
2004/03
[AK4588]
Bits
Value
Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 data MPEG-2 without extension MPEG-2 data with extension MPEG-2 ADTS MPEG-2, Layer1 sample rate MPEG-2, Layer2 sample rate reserved type type type ATRAC ATRAC2/3 reserved reserved, shall error-flag indicating valid burst_payload error-flag indicating that burst_payload contain errors data type dependent info stream number, shall Table Fields burst info
Repetition time burst IEC60958 frames 4096 1536
16-31
1152 1152 1024 1152 1024 2048 1024
8-12 13-15
MS0287-E-01
2004/03
[AK4588]
Non-PCM Bitstream timing
When Non-PCM preamble coming within 4096 frames,
stream
Repetition time
>4096 frames
AUTO
Register
Register
Figure Timing example
When Non-PCM bitstream stops (when MULK0=0),
INT0 <20mS (Lock time) stream Stop Syncs (B,M AUTO <Repetition time INT0 hold time
Register
Register
Figure Timing example
MS0287-E-01
2004/03
[AK4588]
OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part) Serial Control Interface
AK4588 registers, which ADC/DAC part (AK4628 compatible) DIR/DIT part (AK4114 compatible). Each register chip address pin. (1). 4-wire serial control mode (I2C "L") internal registers either written read 4-wire interface pins: CSN, CCLK, CDTI CDTO. data this interface consists Chip address (2bits, ADC/DAC part register CAD1/0 pins. DIR/DIT part C1-0 bits fixed "00"), Read/Write (1bit), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge CCLK data clocked falling edge. write operations, data latched after 16th rising edge CCLK, after high-to-low transition CSN. read operations, CDTO output goes high impedance after low-to-high transition CSN. maximum speed CCLK 5MHz. resets registers their default values. When state changed, AK4588 should reset "L". Register ADC/DAC part read.
CCLK
CDTI WRITE CDTO CDTI READ CDTO
Hi-Z
Hi-Z
Hi-Z
C1-C0: Chip Address: (Regarding ADC/DAC part, register CAD1/0 pins. This chip address must except "00".) (Fixed "00" DIR/DIT part) R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data Figure 4-wire Serial Control Timing
MS0287-E-01
2004/03
[AK4588]
(2). control mode (I2C "H") AK4588 supports standard-mode I2C-bus (max 100kHz). Then AK4588 does support fast-mode I2C-bus system (max: 400kHz). (2)-1. Data transfer commands preceded START condition. After START condition, slave address sent. After AK4588 recognizes START condition, device interfaced waits slave address transmitted over line. transmitted slave address matches address devices, designated slave device pulls line (ACKNOWLEDGE). data transfer always terminated STOP condition generated master device. (2)-1-1. Data validity data line must stable during HIGH period clock. HIGH state data line only change when clock signal line except START STOP condition.
DATA LINE STABLE DATA VALID
CHANGE DATA ALLOWED
Figure Data transfer (2)-1-2. START STOP condition HIGH transition line while HIGH indicates START condition. sequences start from START condition. HIGH transition line while HIGH defines STOP condition. sequences STOP condition.
START CONDITION
STOP CONDITION
Figure START STOP conditions
MS0287-E-01
2004/03
[AK4588]
(2)-1-3. ACKNOWLEDGE ACKNOWLEDGE software convention used indicate successful data transfers. transmitting device will release line (HIGH) after transmitting eight bits. receiver must pull down line during acknowledge clock pulse that that remains stable during period this clock pulse. AK4588 will generates acknowledge after each byte been received. read mode, slave, AK4588 will transmit eight bits data, release line monitor line acknowledge. acknowledge detected STOP condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await STOP condition. register ADC/DAC part generate acknowledge READ operations.
Clock pulse acknowledge
FROM MASTER
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER START CONDITION acknowledge
Figure Acknowledge I2C-bus (2)-1-4. FIRST BYTE first byte, which includes seven bits slave address bit, sent after START condition. transmitted slave address matches address device, receiver been addressed pulls down line. most significant five bits slave address fixed "00100". next bits CAD1 CAD0 (device address bits). These bits identify specific device bus. hard-wired input pins (CAD1 CAD0 pin) them. eighth (LSB) first byte (R/W bit) defines whether write read condition requested master. indicates that read operation executed. indicates that write operation executed. CAD1 CAD0
(Regarding ADC/DAC part, register CAD1/0 pins. "00" inhibited ADC/DAC.) (Fixed "00" DIR/DIT part) Figure First Byte
MS0287-E-01
2004/03
[AK4588]
(2)-2. WRITE Operations WRITE operation AK4588. After receipt start condition first byte, AK4588 generates acknowledge, awaits second byte (register address). second byte consists address control registers AK4588. format first, those most significant 3-bits "Don't care".
Don't care) Figure Second Byte After receipt second byte, AK4588 generates acknowledge, awaits third byte. Those data after second byte contain control data. format first, 8bits.
Figure Byte structure after second byte AK4588 capable more than byte write operation sequence. After receipt third byte, AK4588 generates acknowledge, awaits next data again. master transmit more than words instead terminating write cycle after first data word transferred. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten.
Data(n+x)
Slave Address
Register Address(n)
Data(n)
Data(n+1)
Figure WRITE Operation
MS0287-E-01
2004/03
[AK4588]
(2)-3. READ Operations READ operation AK4588. After transmission data, master read next address's data generating acknowledge instead terminating write cycle after receipt first data word. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten. AK4588 supports basic read operations: CURRENT ADDRESS READ RANDOM READ. ADC/DAC part register read. (2)-3-1. CURRENT ADDRESS READ AK4588 contains internal address counter that maintains address last word accessed, incremented one. Therefore, last access (either read write) address next CURRENT READ operation would access data from address n+1. After receipt slave address with "1", AK4588 generates acknowledge, transmits 1byte data which address internal address counter increments internal address counter master does generate acknowledge data generate stop condition, AK4588 discontinues transmission
Data(n+x)
Slave Address
Data(n)
Data(n+1)
Data(n+2)
Figure CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows master access memory location random. Prior issuing slave address with "1", master must first perform "dummy" write operation. master issues start condition, slave address(R/W="0") then register address read. After register address's acknowledge, master immediately reissues start condition slave address with "1". Then AK4588 generates acknowledge, 1byte data increments internal address counter master does generate acknowledge data generate stop condition, AK4588 discontinues transmission.
Slave Address
Word Address(n)
Slave Address
Data(n)
Data(n+1)
Data(n+x)
Figure RANDOM READ
MS0287-E-01
2004/03
[AK4588]
SYSTEM DESIGN
Figure shows system connection diagram. evaluation board available which demonstrates application circuits, optimum layout, power supply arrangements measurement results. Condition: serial control mode
Micro Controller
S/PDIF
S/PDIF sources
(S/PDIF sources)
Audio (MPEG/AC3)
DAUX2 CAD1 CAD0 TEST2 PVDD INT0 MCLK
0.1u
PVSS
(Shield) TEST1 AVSS AVDD 0.1u 0.1u (Shield)
INT1 BOUT TVDD DVDD DVSS TEST3 MCKO2
3.3V Digital Digital
0.1u
X'tal
VREFH VCOM
Analog
2.2u
MCKO1
(Micro Controller)
COUT UOUT VOUT SDTO2 BICK2 LRCK2 SDTO1 BICK1 LRCK1
AK4588
ROUT1 LOUT1 ROUT2 LOUT2 (Shield) MUTE (Shield) MUTE (Shield) MUTE (Shield) MUTE (Shield) MUTE
Audio (MPEG/AC3)
ROUT4
DAUX1
LOUT4
LOUT3
SDTI3
SDTI2
SDTI1
SDTI4
CDTO
MASTER
ROUT3
DZF2
DZF1
XTL1
XTL0
(Shield)
MUTE
(Shield)
MUTE
Micro Controller Audio (MPEG/AC3) Micro Controller
Digital Ground
Analog Ground
Figure Typical Connection Diagram Notes: depends crystal. AVSS, DVSS PVSS must connected same analog ground plane. Digital signals, especially clocks, should kept away from order avoid effect clock jitter performance. case coaxial input, ground connector terminator should connected PVSS AK4588 with impedance board. MS0287-E-01 2004/03
MUTE
(Shield)
(S/PDIF Source)
[AK4588]
Grounding Power Supply Decoupling AK4588 requires careful attention power supply grounding arrangements. AVDD, DVDD, PVDD TVDD usually supplied from analog supply system. Alternatively AVDD, DVDD, PVDD TVDD supplied separately, power sequence critical. AVSS, DVSS PVSS AK4588 must connected analog ground plane. System analog ground digital ground should connected together near where supplies brought onto printed circuit board. Decoupling capacitors should near AK4588 possible, with small value ceramic capacitor being nearest. Voltage Reference Inputs voltage VREFH sets analog input/output range. VREFH normally connected AVDD with 0.1µF ceramic capacitor. VCOM signal ground this chip. electrolytic capacitor 2.2µF parallel with 0.1µF ceramic capacitor attached VCOM eliminates effects high frequency noise. load current drawn from VCOM pin. signals, especially clocks, should kept away from VREFH VCOM pins order avoid unwanted coupling into AK4588. Analog Inputs inputs single-ended internally biased VCOM. input signal range scales with supply voltage nominally 0.62 VREFH (typ). output data format complement. offset removed internal HPF. AK4588 samples analog inputs 64fs. digital filter rejects noise above stop band except multiples 64fs. AK4588 includes anti-aliasing filter filter) attenuate noise around 64fs. Analog Outputs analog outputs also single-ended centered around VCOM voltage. input signal range scales with supply voltage nominally VREFH Vpp. input data format complement. output voltage positive full scale 7FFFFFH(@24bit) negative full scale 800000H(@24bit). ideal output VCOM voltage 000000H(@24bit). internal analog filters remove most noise generated delta-sigma modulator beyond audio passband. offsets analog outputs eliminated coupling since outputs have offsets
MS0287-E-01
2004/03
[AK4588]
PACKAGE
80-pin LQFP Unit
14.0±0.2
12.0±0.2
14.0±0.2
12.0±0.2
0.20±0.1 0.50 1.25TYP
1.40±0.2
0.08
0.125+0.10 -0.05
0.50±0.1
0.10
Material Lead finish Package: Epoxy Lead-frame: Copper Lead-finish Soldering free) plate
MS0287-E-01
+0.15 0.10 -0.10
1.85MAX
2004/03
[AK4588]
MARKING
AK4588VQ
XXXXXXX
indication Date Code: XXXXXXX(7 digits) Marking Code: AK4588VQ Asahi Kasei Logo
Revision History
Date (YY/MM/DD) 04/01/22 04/03/18 Revision Reason First Edition Error Correct Page Contents Digital Filte Group Delay: 19.1/fs 16/fs
MS0287-E-01
2004/03
[AK4588]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0287-E-01
2004/03
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