Emulation Module User's Manual Motorola reserves right make chang
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M68EM05V12
Emulation Module User's Manual
Motorola reserves right make changes without further notice products herein improve reliability, function, design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola Motorola logo registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
Motorola, Inc., 1996; Rights Reserved MOTOROLA
Table Contents
General Description Contents Introduction Emulation Module Layout Target Cable Assemblies Connector Information Target Cable Connector Assignments Logic Analyzer Connector Assignments Contents Introduction Setting M68EM05V12 Jumper Headers Converter Voltage Reference Headers BDLC XMIT Control Headers Control Header Volts Select Header Clock Source Select Header Gauge Control Headers -W8, Using Lever Terminal Connector Remaining System Installation Personality Files Usage MC68HC(7)05V12 Emulation Mask Option Register (MOR) Control Reading Mask Option Register IRQ/VPP Input Pullup Programming 256-Byte EEPROM Array Illegal Address Operation Contents M68EM05V12 Schematics
MMDS/MMEVS Configuration Operation
Schematics
M68EM05V12UM/D
MOTOROLA
Table Contents
Table Contents
M68EM05V12UM/D
Table Contents
MOTOROLA
Revision History
Revision History
This table summarizes differences between this revision previous revision this emulation module user's manual.
Previous Revision Current Revision Date
None Original Release 09/96
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Revision History
M68EM05V12UM/D
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General Description
Contents
Introduction Emulation Module Layout Target Cable Assemblies Connector Information Target Cable Connector Assignments Logic Analyzer Connector Assignments
Introduction
M68EM05V12 gives Motorola development tool ability emulate target systems based MC68HC705V12 MC68HC05V12 microcontroller units (MCUs). substituting different emulation module (EM), Motorola development tool enabled emulate other MCUs. Refer Motorola's Development Tool Selector Guide, order number SG173/D, complete list available EMs. This hardware user's manual explains connection, configuration, operation information specific M68EM05V12 emulation module. module installed Motorola development systems, MMDS MMEVS. configure your M68EM05V12 either development system, follow instructions given MMDS/MMEVS Configuration Operation page Motorola's complete emulation system consists emulation module described this manual well other separately purchased options described following paragraphs.
M68EM05V12UM/D
MOTOROLA
General Description
General Description
following items included with M68EM05V12 emulation module: M68EM05V12 emulation module (EM) printed circuit board that enables system functionality MC68HC(7)05V12 MCUs. female connectors, bottom module, mate with male connectors development system platform board. Configuration software 1/2-inch diskette containing personality files this module
Separately purchased Motorola modular development tool options include: MMEVS platform board (M68MMPFB0508) MMEVS economical development tool that provides real-time in-circuit emulation. unit's integrated design environment includes editor, assembler, user interface, source-level debugging program. MMDS0508 modular development system (M68MMDS0508) MMDS high-performance development tool that capabilities MMEVS. addition, also state analyzer real-time memory windows. Flex cable target assembly Refer Target Cable Assemblies page more information.
User-supplied components include: Host computer appropriate development tool user's manual minimum requirements. Power supply required MMEVS.
M68EM05V12UM/D
General Description
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General Description Emulation Module Layout
Emulation Module Layout
Figure shows layout M68EM05V12. Jumper header control voltage reference inputs analog-to-digital subsystem. Jumper headers used configuring BDLC subsystem. controls voltage applied IRQ/VPP pin. Jumper header lets select clock-signal source. Jumper headers ,W9, used configuring gauge driver subsystem with your target system. Target connectors interface target system; these connectors separately purchased target cable assembly. When install M68EM05V12 MMDS, target cable passes through slit station module enclosure. Connector connects optional logic analyzer. connectors connect development system platform board. Lever terminal connector inputting gauge driver battery voltage data link controller (BDLC) interface.
Figure M68EM05V12 Emulation Module
M68EM05V12UM/D
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General Description
General Description Target Cable Assemblies
connect your M68EM05V12 target system, separately purchased target cable assembly needed. Cable assemblies available support 68-pin PLCC packages. target cable connects emulator connectors M68EM05V12 emulation module. assignments signal descriptions connectors found Target Cable Connector Assignments page Figure represents target cable assembly. assembly consists flex cable target head adapter. flex cable plugs onto M68EM05V12 connectors with orientation shown Figure other flex cable plugs into target head adapter. target head adapter then inserts into PLCC socket target system. MC68HC705V12 target cable assembly consists Flex cable M68CBL05C Target head adapter M68TC05V12FN68
M68EM05V12UM/D
General Description
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General Description Target Cable Assemblies
EMULATION MODULE
FLEX CABLE
TARGET HEAD ADAPTER
TARGET HEAD ADAPTER EMULATION MODULE TARGET SYSTEM SOCKET
68-PIN PLCC
FLEX CABLE: M68CBL05C TARGET HEAD ADAPTER: M68TC05V12FN68
Figure Target Cable Assembly
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General Description
General Description Connector Information
connectors M68EM05V12 module provide access user mode emulation signals well select internal signals (J1). Connectors used cable interface user's target system, while connector used connect logic analyzer.
Target Cable Connector Assignments
Figure shows assignments connector Table lists signal descriptions connector Table lists signal descriptions connector
EMVCC OSC2 MIND2+ PB7/TCAP TRCV MINB1 MINB2- MINA1 EVDD TVREFH MINC2- MAJB2+ MAJB1+ TVGSUP MAJA2+ MAJA1+ MINA2- MINA2+ MINB2+ T-IRQ T-OSC1 T-RESET MINC2+ MIND2- MIND1 TXMIT
TVREFL MAJB2- MINC1 MAJB1- TVGREF TVPGC MAJA2- MAJA1-
Figure Target Connector Assignment
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General Description
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General Description Connector Information
Table Connector Signal Descriptions
Mnemonic PB0, PB4, PB6, PB7/TCAP EMVCC OSC2 PA6, PA4, PA2, EVDD GROUND PORT (Bits General-purpose lines controlled software data data direction registers subsystem enabled, becomes slave select input. subsystem enabled, becomes PWMA output. 16-bit timer enabled, becomes TCMP output becomes TCAP input. (Other port lines connector POWER Connection system voltage OSCILLATOR Output clock signal. Inversion OSC1 clock input PORT (Bits General-purpose lines controlled software data data direction registers (Other port lines connector EXTERNAL VOLTAGE DETECT Connected target VCC, used sense target power applied, target status MMDS status window. PORT (Bits General-purpose input lines LINES analog-to-digital subsystem enabled, these lines become converter input lines AD4, respectively. (Other port lines connector PORT (Bits General-purpose lines controlled software data data direction registers port interrupt capability external interrupt subsystem selected, each generate interrupt input. (Other port lines connector Possible source positive (high) reference voltage input subsystem. Input controlled jumper header connection MINC2- Minor gauge full H-bridge coil driver pins. (Other minor lines connector MIND2+ Minor gauge full H-bridge coil driver pins (Other minor lines connector MAJB2+, MAJB1+ Major gauge full H-bridge coil driver pins (Other major lines connector Vgsup regulated gauge voltage input. this input controlled jumper headers W10. MAJA2+, MAJA1+ Major gauge full H-bridge coil driver pins (Other major lines connector receive digital input (RXP) BDLC subsystem. this input controlled jumper headers MINB1, MINB2- Minor gauge full H-bridge coil driver pins (Other minor lines connector MINA2-, MINA1 Minor gauge full H-bridge coil driver pins (Other minor lines connector Signal
PD1,
PC6, PC4, PC1,
TVrefh MINC2- MIND2+ MAJB2+, MAJB1+ TVgsup MAJA2+, MAJA1+ TRCV MINB1, MINB2- MINA2-, MINA1
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General Description
General Description
Table Connector Signal Descriptions
Mnemonic TIRQ TOSC1 Signal TARGET INTERRUPT REQUEST Active-low input signal from target that asynchronously applies interrupt connection. OSCILLATOR possible clock source input M68EM05V12 board. System frequency OSC1 this signal controlled jumper header PORT (Bits General-purpose lines controlled software data data direction registers. (Other port lines connector subsystem enabled, PB2, PB1, become MISO, SCK, MOSI lines, respectively. subsystem enabled, becomes PWMB output. Active-low bidirectional signal to/from target system driven pull into reset. PORT (Bits General-purpose lines controlled software data data direction registers. (Other port lines connector GROUND PORT (Bits General-purpose input lines LINES analog-to-digital subsystem enabled, these lines become converter input lines AD2, AD3, AD0, respectively. (Other port lines connector PORT (Bits General-purpose lines controlled software data data direction registers. port interrupt capability external interrupt subsystem selected, each generate interrupt input. (Other port lines connector Possible source negative (low) reference voltage input subsystem. Input controlled jumper header MINC2+, MINC1 Minor Gauge full H-bridge coil driver pins (Other minor lines connector MIND2-, MIND1 Minor gauge full H-bridge coil driver pins (Other minor lines connector J2.) MAJB2-, MAJB1- Major gauge full H-bridge coil driver pins (Other major lines connector VGVref feedback gauge power regulator circuit. this input controlled jumper headers W10. VPGC gauge power control external pass device. this input controlled jumper headers W10. transmit digital output (TXP) BDLC subsystem. this output controlled jumper headers MAJA2-, MAJA1- Major gauge full H-bridge coil driver pins (Other major lines connector MINB2+ Minor gauge full H-bridge coil driver pins (Other minor lines connector MINA2+ Minor gauge full H-bridge coil driver pins (Other minor lines connector
PB2, PB1, PB3,
TRESET PA5, PA3, PD2, PD3,
17,19,
PC7, PC5, PC2,
TVrefl MINC2+, MINC1 MIND2-, MIND1 MAJB2-, MAJB1- TVgref TVPGC TXMIT MAJA2-, MAJA1- MINB2+ MINA2+
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General Description
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General Description Connector Information
Logic Analyzer Connector Assignments
Figure shows assignments logic analyzer connector This connector provides easy access many signals used internally. Table lists signal descriptions this connector.
LA11 LA10 LR/W RESET LA12 LA13 ACLK
Figure Connector Assignments
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General Description
General Description
Table Logic Analyzer Connector Signal Descriptions
Mnemonic LA13-LA12 connection GROUND LATCHED ADDRESSES (Bits 13-12) latched output address LATCHED ADDRESSES (Bits 11-0) latched output address DATA (Bits 7-0) multiplexed LATCHED READ/WRITE MCU's write signal latched used emulator control emulator memory accesses. LOAD INSTRUCTION REGISTER Active-low signal indicating opcode fetch cycle process. POWER Connection system voltage ANALYZER CLOCK latched addresses valid latched address rising edge ACLK. Also, data valid ACLK's rising edge. RESET Active-low signal; will asserted during internally externally caused resets Signal
LA11-LA0
AD7-AD0 LR/W ACLK
RESET
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General Description
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MMDS/MMEVS Configuration Operation
Contents
Introduction Setting M68EM05V12 Jumper Headers Converter Voltage Reference Headers BDLC XMIT Control Headers Control Header Volts Select Header Clock Source Select Header Gauge Control Headers Using Lever Terminal Connector Remaining System Installation Personality Files Usage MC68HC(7)05V12 Emulation Mask Option Register (MOR) Control Reading Mask Option Register IRQ/VPP Input Pullup Programming 256-Byte EEPROM Array Illegal Address Operation
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation Introduction
following paragraphs explain configure your M68EM05V12 part MMDS MMEVS system. other parts system installation configuration, either MMDS0508 Operations Manual (MMDS0508OM/D) MMEVS05/MMEVS08 Operations Manual (MMEVS0508OM/D). topics covered this chapter are: Setting M68EM05V12 Jumper Headers page explains M68EM05V12 jumper headers. Using Lever Terminal Connector page details usage other possible connections emulation module. Remaining System Installation page covers final steps system installation. Personality Files Usage page discusses personality file used M68EM05V12 board. MC68HC(7)05V12 Emulation page explains special considerations emulating with this module.
NOTE:
configure M68EM05V12 already installed system platform board. remove system power then follow guidance this chapter. sure switch power before reconfigure installed Reconfiguring jumper headers with power damage emulation circuits.
CAUTION:
M68EM05V12UM/D
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MMDS/MMEVS Configuration Operation Setting M68EM05V12 Jumper Headers
Setting M68EM05V12 Jumper Headers
M68EM05V12 jumper headers, W1-W10. Table provides quick reference configuration options. Refer paragraphs that follow more detailed explanation. Table Jumper Header Positions
Jumper Header Converter Voltage Reference Headers, Position Description Vrefl ground Vrefh Vdc. Vrefl Vrefh pins their respective input pins connectors Factory Setting
EM-VSS EM-VSS
EM-VDD EM-VDD 7020 HC57
pins their respective pins connectors
BDLC, TXP, Control Headers,
7020 HC57
HC57 position currently used.
pins HIP7020 transceiver circuits. Position 7020 position. Transceiver connection terminal HC57 position currently used.
7020 HC57 HC57 7020
Control Header,
connection HIP7020 transceiver circuits.
HC57
7020
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MMDS/MMEVS Configuration Operation
Table Jumper Header Positions (Continued)
Jumper Header Volts Select Header, Position Description Normal usage volts during reset, volts during operation. Vbatt voltage tied pin.
XTAL MMDS
Factory Setting
Select 4.194304-MHz crystal oscillator located board Select 4-MHz canned oscillator located board XY2. Select clock originating from platform board. frequency, power controlled command. Select user-supplied clock source. clock input TOSC1 connector through target cable assembly. Vgref, VGSUP, VPGC pins their respective pins connectors required external circuitry gauge driver power supply should target system.
Clock Source Select,
XTAL MMDS
XTAL MMDS
XTAL MMDS
Gauge Control Headers,
Utilize on-board voltage regulator. Ties Vgref, VGSUP, VPGC pins required circuits populated Vbatt voltage should connected Enable VGSUP drive gauges connected while utilizing on-board voltage regulator. Ties Vgref, VGSUP, VPGC pins required circuits populated Vbatt required
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MMDS/MMEVS Configuration Operation Setting M68EM05V12 Jumper Headers
Converter Voltage Reference Headers
voltage reference headers control input voltage reference (Vrefl) voltage reference high (Vrefh) MCU. factory configured position applies ground Vrefl volts Vrefh pin.
FABRICATED JUMPERS Vrefl Vrefh
Alternatively, reference voltages supplied through target cable connected connectors M68EM05V12 emulation module. reposition jumper position.
EM-VSS
EM-VDD
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
BDLC XMIT Control Headers transmit receive headers control path transmit receive signals BDLC subsystem. factory configured position, TGT, routes lines directly target connectors
HC57
7020
XMIT FABRICATED JUMPER
Alternatively, transmit receive lines routed utilize Harris HIP7020 circuits populated emulation module. configured this circuit, then header must configured 7020 position route transceiver's signal lever terminal connector HIP7020 transceiver circuits, position jumpers 7020 position. Ensure that associated components populated. They are:
HIP7020, 8-pin SOIC package
1-pin header connected loop back enable
Note that HC57 position jumpers used.
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MMDS/MMEVS Configuration Operation Setting M68EM05V12 Jumper Headers
Control Header
Jumper header controls path signal from HIP7020 transceiver circuits. 7020 position, signal from HIP7020 transceiver circuits connected lever terminal connector Note that proper configuration this header dependent configuration BDLC headers
HC57 7020
FABRICATED JUMPER
HC57 position used M68EM05V12 emulation module.
Volts Select Header
Jumper header controls source voltage applied MCU's IRQ/VPP pin. diagram below shows factory configuration. fabricated jumper between pins selects normal configuration. normal use, system applies +12-V charge pump voltage IRQ/VPP during reset. reset, system supplies volts IRQ/VPP pin, unless input asserted low.
FABRICATED JUMPER
volts from charge pump adequate program EPROM MC68HC705V12 MCU. Instead, program this EPROM, must apply Vepgm voltage (supplied through Vbatt terminal connector P3). reposition fabricated jumper between pins
CAUTION:
When removing power from system, remove Vbatt voltage before turn MMDS power switch. Doing otherwise could damage emulation circuits.
Using Lever Terminal Connector page more information about connector
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
Clock Source Select Header Jumper header used determine source clock signal. diagram here illustrates jumper header where pins marked indicate common pins. default configuration selects 4.194304- crystal clock source location 4-MHz canned oscillator clock source board location selected positioning shunt between There other possible clock sources. source, from platform board, requires repositioning jumper between pins MMDS then using system's command select frequency. user-supplied clock source, coming through target cable that connected reposition jumper between
XTAL MMDS
FABRICATED JUMPER
NOTE:
user-supplied source through target cable should CMOS-level square wave.
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MMDS/MMEVS Configuration Operation Setting M68EM05V12 Jumper Headers
Gauge Control Headers
gauge headers control path Vgref, VGSUP, VPGC signals gauge driver subsystem. factory-configured position, TGT, routes lines directly target connectors
Vgref VGSUP VPGC
Alternatively, these headers configured utilize voltage regulator circuits populated M68EM05V12 emulation module. this option, position fabricated jumpers position. Note that emulation module voltage regulator circuits used, must supply volts Vbatt lever terminal connector
FABRICATED JUMPERS
CAUTION:
When removing power from system, remove Vbatt voltage before turn development system power. Doing otherwise could damage emulation circuits.
want voltage regulator circuits drive gauges (through VGSUP) connected M68EM05V12 emulation module target connectors position additional jumper VGSUP (W9) header, that jumper resides both positions.
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MMDS/MMEVS Configuration Operation Using Lever Terminal Connector
Lever terminal connector 3-pin connector. diagram below illustrates component where Vbatt input would used inputting 12-Vdc supply power on-board voltage regulator circuits. terminal used transceiver when utilizing on-board transceiver circuit. terminal connecting on-board ground when utilizing other terminals.
Vbatt
CAUTION:
avoid damaging emulator circuits, development system voltage must turned before supply Vbatt source voltage through
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MMDS/MMEVS Configuration Operation Remaining System Installation
Remaining System Installation
When headers W1-W10 have been configured, have completed M68EM05V12 configuration. Ensure that power development tool off. installing M68EM05V12 MMDS station module, remove panel from station module top. together connectors bottom board platform board connectors. Snap corners onto plastic standoffs. Connect target cable, appropriate. installing MMDS, replace panel.
this point, ready make remaining cable connections, necessary, restore power. instructions, consult either MMEVS05/MMEVS08 Operations Manual (MMEVS0508OM/D) MMDS0508 Operations Manual (MMDS0508OM/D).
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation Personality Files Usage
development system uses specific personality file emulate MC68HC(7)05V12 MCU: file 00029Vxx.MEM. debugger software loads this personality file upon power-up. file individual disk shipped with M68EM05V12.
NOTE:
Note that personality file names follow pattern 00ZZZVxx.MEM, where identifier name version file.
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MMDS/MMEVS Configuration Operation MC68HC(7)05V12 Emulation
MC68HC(7)05V12 Emulation
NOTE:
aware that computer operating properly (COP) mask option been selected enabled, your code must clear watchdog timer counter avoid reset. counter cleared writing logic location $3FF0. This should first check when code operating expected.
following information details known differences between performance MC68HC705V12 single-chip operation versus certain features will perform during emulation.
Mask Option Register (MOR) Control
single-chip mode operation: mask options will determined which options have been programmed EPROM location ($3C00). This register must programmed using dedicated programmer. emulation: mask options initially determined which options have been programmed EPROM location ($3C00). This register must programmed using dedicated programmer. Alternatively, mask options controlled software allow setting mask options during debug session. procedure changing options during emulation session requires manipulation EPROM programming register location $000D location ($3C00). Option changes accomplished command entry (for instance, command) execution user code (for instance, instruction). First (MORON bit) writing EPROM programming register. memory modify (MM) command, "Write verify" message should ignored. Then write desired mask option register byte value location ($3C00). emulator, register will written when user attempts write location. will logical EPROM bits with bits. This results ability
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
select previously disabled mask option, previously selected mask options (programmed EPROM) cannot defeated. Mask option selections take effect immediately. reset will deselect mask options selected writing location.
Reading Mask Option Register
single-chip operation: data read location $3C00 determined MORON (bit programming register. setting MORON bit, data read $3C00 will contents EPROM mask option register. When MORON cleared, first byte boot code located $3C00. emulation: Like single-chip, user able verify contents EPROM location first setting MORON programming register. However, changes made mask options during debug session using method outlined Mask Option Register (MOR) Control above cannot verified directly reading back location. user must test mask option enabled verify that indeed being enabled.
IRQ/VPP Input
single-chip mode: IRQ/VPP drives asynchronous interrupt function CPU. also used programming voltage when programming user EPROM MOR. emulation: IRQ/VPP signal supplied connector through target cable drives only asynchronous interrupt function.
NOTE:
voltage should supplied IRQ/VPP target application while emulator connected.
M68EM05V12UM/D
MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation MC68HC(7)05V12 Emulation
Pullup
single-chip mode: pullup. Your application must pull level prevent interrupts. emulation: pulled module. aware that application without pulled high will emulate correctly will fail application because floating line. pulled high module causes these results.
Programming 256-Byte EEPROM Array
single-chip mode operation: 256-byte EEPROM array locations $0240 $033F programmed during normal operation device. User code modifies array single byte basis manipulation programming register located address $001C. emulation: Like single-chip, 256-byte EEPROM array programmed during normal operation device. User code modifies array single byte basis manipulation programming register located address $001C. Alternatively, array modified using memory altering commands debugger. commands that will modify array assemble (ASM), block fill (BF), load file (LOAD), memory modify (MM).
Illegal Address Operation
single-chip: will reset internally opcode fetch illegal address. emulation: reset will occur. Instead, will latched that read register $3F. cleared reset.
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MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation
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Schematics
Contents
M68EM05V12 Schematics Sheet Sheet Sheet Sheet Sheet Sheet
M68EM05V12 Schematics
Refer sheets schematics M68EM05V12 emulation module.
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Schematics
Schematics
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Schematics
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M68EM05V12UM/D
NOTES, UNLESS OTHERWISE SPECIFIED LOCATIONS GROUND LOCATIONS 7407 7407 DEVICE TYPE NUMBERS REFERENCE DESIGNATORS RESISTANCE VALUES OHMS. 0RCAD 386+ FLAT FILES |LINK |5V12R3S2.SCH |5V12R3S3.SCH |5V12R3S4.SCH |5V12R3S5.SCH |5V12R3S6.SCH
M68EM05V12 Schematics (Sheet
APPLIED 8-PIN IC's, 14-PIN IC's, 16-PIN IC's, 20-PIN IC's, ETC.
M68EM05V12 EMULATION MODULE
DESCRIPTION
First Correct logic used latching DDRC PORTC data. cuts jumps support swap silicon.
DATE
9/30/95 4/5/96 5/30/96
GROUND APPLIED 8-PIN IC's, 14-PIN IC's, 16-PIN IC's, 20-PIN IC's, ETC. DEVICE TYPE, NUMBERS, REFERENCE DESIGNATOR GATES SHOWN FOLLOWS
Decouple Caps labeled. caps
0.1UF
RESISTORS WATT, UNLESS OTHERWISE SPECIFIED. CAPACITANCE VALUES MICROFARADS, 10%. (MCU CAPACITORS) 10UF_RT_25V
Spare Gates
VCC-2 U15A U13A 74HC00 74HCU04 U15E GND-2 74HCU04 U15F 74HC14 GND-2 74HCU04 Title 74HC14 U11E U11D U15D 74HCU04
Schematics M68EM05V12 Schematics
CSIC DEVELOPMENT TOOLS M68EM05V12 EMULATION MODULE Size Document Number 63BSE90746W Date: 1996 Sheet
COMPUTER GENERATED DRAWING REVISE MANUALLY
Schematics
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Schematics
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M68EM05V12 Schematics (Sheet
Direct Target Connector LSByte Address/Data VCC-MCU LA[0.13] LOGIC ANALYZER CONNECTOR RN3I LA12 LA13 74HC573 RES_BUS9I_H_10K RN3H LIR* LR/W LA10 LA13 LA12 LA11 74HC573 AD[0.7]
MCU[1.68]
MCU[1.68] AD[0.7] LA[0.13]
MCU10 MCU11 MCU12 MCU13 MCU14 MCU15 MCU16 MCU17 PB0/SS PB1/SCK PB2/MOSI PB3/MISO PB4/PWMA PB5/PWMB PB6/TCMP PB7/TCAP
MCU23 MCU24 MCU25
MCU-LIR* MCU-R/W MCU-E PRTC-IRQ* A10/A13 A9/A12 A8/A11
RESET OSC2 OSC1 IRQ/VPP
LA11 LA10 LR/W
ACLK HDR220
74HC574 GND-2 VCC-2 VCC-2 PH2* 74HC74 MCU50 MCU51 MCU52 MCU53 MCU54 MCU55 MCU56
MCU27 MCU28 MCU29 MCU30 MCU31 MCU32 MCU33 MCU34 MCU35 MCU36 MCU37 MCU38 MCU39 MCU40 MCU41 MCU42 MCU43 VSSA VCCA PD0/AD0 PD1/AD1 PD2/AD2 PD3/AD3 PD4/AD4 VREFL VREFH VCC-2 IRQ* RESET* U15B 1UF_RT_16V 74HCU04 GND-A 74HCU04 4.194304MHZ_49US U15C RN1A RES_BUS9I_L_10K 74HC74 VCC-2 OSC1
RESET*39
LR/W 74HC00 LIR* LIR* 74HC00
Schematics
MCU18 MCU19 MCU22 IMAX MC68HC705V12FN68 GND-G GND-MCU GNDOUT 4MHZ_FS MMDSOSC T-OSC1 HDR204 27PF 27PF XTAL MMDS TARGET SOURCE
MCU45 MCU46 MCU47
MINB1 MINB2+ MINB2VSSG MINA1 MINA2+ MINA2MAJA1+ MAJA1MAJA2+ MAJA2VPGC VGSUP VGREF MAJB1+ MAJB1MAJB2+ MAJB2MINC1+ MINC1MINC2VSSG MIND2MIND2+ MIND1
IRQ* PRTC-IRQ* RESET*
CLOCK-IN
GND-2
74HC540
SCLK SCLK* SCLK*
CSIC DEVELOPMENT TOOLS Title M68EM05V12 EMULATION MODULE Size Document Number 63BSE90746W Date: 1996 Sheet
MMDSOSC T-OSC1
Schematics M68EM05V12 Schematics
OSC2
Schematics
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M68EM05V12 Schematics (Sheet
PA[0.6]
PA[0.6]
PC[0.7] U11F 74HC14
PC[0.7]
LOCKOUT* T-RST* (RESET-IN) PORTS* PFB_RESET* COP_RESET* (PRU-D*) 3.3K
LOCKOUT
T-RST*
LOCKOUT* T-RST* PORTS* RESET*
(PRU-PB7) (PRU-PB6) (PRU-PB5) (PRU-PB4) (PRU-PB3) RN1B (PRU-PB2) (PRU-PB1) RES_BUS9I_L_10K (PRU-PB0) (ID9) (ID8) (ID7) GND-2 (ID6) (ID5) (ID4) (ID3) (ID2) (ID1) (ID0) EVDD
MMDS05ID $029
Schematics
CON_DIN96 CON_DIN96 CON_DIN96 DAUGHTER BOARD CONNECTOR LA[0.13] AD[0.7] LIR* LR/W SCLK SCLK* (DACIA) (URAM*) (MRAM*) (MEPROM*) INTERNAL* (STACK_CAP) SWITCH (DACIA-CS*) (WE*) (U/M) (OE*) CON_DIN96 CON_DIN96
DAUGHTER BOARD CONNECTOR
EVDD
EVDD
LA[0.13]
AD[0.7]
(LA14)
GND-2
LIR* LR/W SCLK SCLK*
LA13 LA12 LA11 LA10
INTERNAL*
SWITCH
MMDSIRQ* CHRGPMP (ABT) MMDSOSC
MMDSIRQ* CHRGPMP MMDSOSC
Title
CON_DIN96
CSIC DEVELOPMENT TOOLS
Schematics M68EM05V12 Schematics
M68EM05V12 EMULATION MODULE Size Document Number 63BSE90746W Date: 1996 Sheet
Schematics
M68EM05V12UM/D
Schematics
MOTOROLA
MOTOROLA
M68EM05V12UM/D
M68EM05V12 Schematics (Sheet
TARGET CONNECTOR
MCU[1.68] MCU[1.68]
(PB0) (TMCU9) (TMCU6) (TMCU4) (TMCU2) (PB2) (PB1) (PB3) (PB5) (PD2/AD2) MCU10 OSC2 PA[0.6]
EVDD
EVDD
T-RST* T-OSC1 T-IRQ*
T-RST* T-OSC1 T-IRQ*
PA[0.6] MCU46 MCU39 MCU37 MCU50 T-XMIT MCU24 MCU28 MCU32 MCU30 MCU29 MCU17 T-RCV MCU23 MCU25 MCU27 HDR220 MCU42 MCU45 MCU47
OSC2
T-IRQ* T-OSC1 T-RST*
MCU12 MCU11 MCU13 MCU15 MCU52
PC[0.7]
PC[0.7]
(PB4) (PB6) (MCU18) (PD1/AD1) (PD4/AD4) (TMCU56) (TMCU58) (TMCU60) (MINC2-) (PD3/AD3) (TMCU55) (TMCU57) (MAJB2-) (MINC1) (MAJB1-) (TMCU36) (TMCU34) (MAJA2-) (MAJA1-) (MAJB2+) (MAJB1+) (MCU35) (MAJA2+) (MAJA1+) (MINA2-)
MCU14 MCU16 EVDD MCU51 MCU54 TVREFH MCU43
MCU53 TVREFL MCU40 MCU41 MCU38 T-VGREF T-VPGC MCU33 MCU31
(EMVCC) (TMCU5) (TMCU3) (TMCU1) (TMCU67) (TMCU65) (TMCU63) (TMCU61) (TMCU44) (MIND2+) (TMCU48) (TMCU49) (PB7/TCAP) (TMCU19) (MINB1) (MINB2-) (MINA1) (TMCU68) (TMCU66) (TMCU64) (TMCU62) (TMCU59) (MINC2+) (MIND2-) (MIND1) (PD0/AD0) (TMCU18) (TMCU22) (MINB2+) (TMCU26) (MINA2+) HDR220
T-RCV T-XMIT
MCU56 HDR103 MCU55 HDR103 T-VGSUP
T-VPGC HDR203 (VPGC) MCU34
Schematics
MTP2955E 0.1UF VBATT PWRTERM3 P6KE30A 1N5822 VBATT 0.1UF P6KE15A 0.1UF
T-VGSUP (~8V) 100UF_RE_25V T-VGREF HDR203 24.9K_1% 54.9K_1% XU14 HDR203
(VGSUP) MCU35
(VGREF) MCU36
MCU22 CSIC DEVELOPMENT TOOLS SKT_DIP14_3 4.75K_1% Rmax Title M68EM05V12 EMULATION MODULE Size Document Number 63BSE90746W Date: 1996 Sheet
Schematics M68EM05V12 Schematics
Schematics
M68EM05V12UM/D
Schematics
MOTOROLA
MOTOROLA
M68EM05V12UM/D
M68EM05V12 Schematics (Sheet
1N4001 2N4403 HDR103 IRQ* LOCKOUT* U11A 74HC14 U13D 74HC00 74HC00 74HC14 PC[0.7] AD[0.7] CLKPC PC-REGS* $0002,0006 INTERNAL* $0001,0003,0005,0007, $0008-003F,$0240-02BF $3C00 SWITCH $0050 PORTS* $0000,0002,0004 $0006 AD[0.7] PC[0.7] RES_SER5I_10K VBATT RN2E 2N4401 2N4401RES_SER5I_10K U11B 74HC00 U13B RN2D RES_SER5I_10K U13C RN2B LOCKOUT IRQ* RN2A
CHRGPMP
CHRGPMP
RES_SER5I_10K
LOCKOUT*
RN2C RES_SER5I_10K
T-IRQ*
MMDSIRQ*
Schematics
74HC27 74HC00 SWITCH INTERNAL* PORTS* U11C 74HC00 74HC14 LA[0.13] VCC-2 VCC-2 CLKDDRC DDRC0 CLKPC SWITCH INTERNAL* PORTS* MACH210-20JC PC-REGS* LOCKOUT* LA13 CLKDDRC LA12 LA11 LA10 IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 CLK1/I5 CLK0/I2 IO23 IO22 IO10 IO21 IO11 IO20 IO12 IO19 IO13 IO18 IO14 IO17 IO15 IO16 PC1-7IRQ VCC-2 74HC74 74HC74
DECODE TABLE
LR/W
74HC27 DDRC0 PC0-OUT 74HC27 PRTC-IRQ*
LA[0.13]
CSIC DEVELOPMENT TOOLS Title M68EM05V12 EMULATION MODULE Size Document Number 63BSE90746W Date: 1996 Sheet
Schematics M68EM05V12 Schematics
Schematics
M68EM05V12UM/D
Schematics
MOTOROLA
MOTOROLA
M68EM05V12UM/D
M68EM05V12 Schematics (Sheet
MCU18 (XMIT) HDR203 MCU19 (RCV) HDR203 RN3A RES_BUS9I_H_10K 0.1UF T-RCV T-XMIT
MCU[1.68]
MCU[1.68] T-XMIT
T-RCV
31.6K_1% 24.9K_1% BATT TIME HIP7020AB HDR103 RN3B RES_BUS9I_H_10K HDR101
Schematics
4321876 XU16 RN3C RES_BUS9I_H_10K VCC-2 OOLVLRR SSOSIEE CCTSTXX 12IAOTT VCC-2 SCLK SIMO SOMI PSEN VBATT LOAD VSSD NNNNNNN CCCCCCC 1111111 2345678 0.1UF GND-2 MC68HC57DLCS
VBATT
LOCKOUT*
FERRITE_SM 470PF
CSIC DEVELOPMENT TOOLS Title M68EM05V12 EMULATION MODULE Size Document Number 63BSE90746W Date: 1996 Sheet
Schematics M68EM05V12 Schematics
Schematics
M68EM05V12UM/D
Schematics
MOTOROLA
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