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M68EM05JP7UM / D

M68EM05JP7

M68EM05JP7UM / D
M68EM05JP7
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity / Affirmative Action Employer.
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M68EM05JP7UM / D
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Revision History
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Table of Contents
MMDS / MMEVS Configuration and Operation
Schematics
M68EM05JP7UM / D
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Table of Contents
M68EM05JP7UM / D
Table of Contents
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General Description
Contents
Introduction
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General Description
Emulation Components
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General Description
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General Description Emulation Module Layout
Emulation Module Layout
Figure 1 shows the layout of the M68EM05JP7. Jumper header W1 controls the low-power oscillator (LPO) source. Jumper header W2 lets you select the external pin oscillator (EPO) source. Jumper header W3 selects the software pulldown inhibit mask option for port A. Jumper header W4 controls the voltage applied to the IRQ / VPP pin. Jumper header W5 determines the source voltage for the IRQ / VPP pin. Target connector J2 is the interface to a target system this connector uses a separately purchased target cable assembly. When you install the M68EM05JP7 on the MMDS, the target cable passes through the slit in the station module enclosure. Connector J1 connects to a logic analyzer. Variable resistor VR1 controls the MCU operating voltage between 3.0 V and 5.0 V. Test point header TP1 is the monitor point for MCU operating voltage adjustment. The MC68HC705JP7 MCU is at location XU22. DIN connectors P1 and P2 connect the EM and a development system platform board. Lever terminal connector P3 is for inputting the personality EPROM (PEPROM) programming voltage.
J1 VR1 TP1
XU22 P3
Figure 1. M68EM05JP7 Emulation Module
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General Description
Target Cable Assemblies
To connect your M68EM05JP7 to a target system, you need a separately purchased target cable assembly. Cable assemblies are available for four MCU packages: 20- and 28-pin DIP and 20- and 28-pin SOIC packages. The target cable connects to the emulator via connector J2 on the M68EM05JP7 emulation module. Pin assignments and signal descriptions for connector J2 can be found in Target Cable Connector Pin Assignments on page 14. Figure 2 represents a target cable assembly. An assembly for DIP packages consists of a flex cable and a target head adapter. The assembly for SOIC packages requires an additional SOIC adapter. One end of the flex cable plugs onto M68EM05JP7 connector J2 with orientation shown in Figure 2. The other end of the flex cable plugs into the target head adapter. The target head adapter then inserts into either a DIP footprint in a target system or into the SOIC adapter. The MCU package in your target system determines the target cable assembly components required: · · · For a 20-pin DIP package (MC68HC(7)05JJx MCUs), use flex cable M68CBL05A and target head adapter M68TA05JJ7P20. For a 28-pin DIP package (MC68HC(7)05JPx MCUs), use flex cable M68CBL05A and target head adapter M68TA05JP7P28. For a 20-pin SOIC package (MC68HC(7)05JJx MCUs), use the flex cable assembly for the 20-pin DIP in conjunction with SOIC adapter M68DIP20SOIC. For a 28-pin SOIC package (MC68HC(7)05JPx MCUs), use the flex cable assembly for the 28-pin DIP in conjunction with SOIC adapter M68DIP28SOIC.
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General Description
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General Description Target Cable Assemblies
TO EMULATION MODULE
FLEX CABLE
TO TARGET HEAD ADAPTER
TARGET HEAD ADAPTER EMULATION MODULE TO TARGET SYSTEM MCU SOCKET
20-PIN DIP
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JJ7P20
28-PIN DIP
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JP7P28
20-PIN SOIC
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JJ7P20 DIP TO SOIC ADAPTER: M68DIP20SOIC
28-PIN SOIC
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JP7P28 DIP TO SOIC ADAPTER: M68DIP28SOIC
Figure 2. Target Cable Assembly
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General Description
Connector Information
Target Cable Connector Pin Assignments
Figure 3 shows the pin assignments for connector J2. Table 1 lists signal descriptions for connector J2.
PB0 / AN0 EVDD GND OSC1 OSC2 PC3 PC2 PC1 PC0 RESET IRQ PA0 PA1 PA2 GND GND GND GND GND GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB1 / AN1 PB2 / AN2 PB3 / AN3 / TCAP PB4 / AN4 / TCMP PB5 / SDO PC4 PC5 PC6 PC7 PB6 / SDI PB7 / SCK PA5 PA4 PA3 GND GND GND GND GND GND
Figure 3. Target Connector Pin Assignments
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General Description
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General Description Connector Information
Table 1. Connector J2 Signal Descriptions
NOTE: Port C is bonded out only on the MC68HC705JP7 MCU.
TARGET INTERRUPT REQUEST - Active-low input signal from the target that asynchronously applies an MCU interrupt
NOTE: The VPP programming voltage should not be applied to this
pin. Doing so will damage the development system. Connector P3 is available for programming voltage input.
RESET PA0, PA5, PA1, PA4, PA2, PA3
Active-low bidirectional signal to / from the target system is driven low to pull the MCU into reset. PORT A (bits 0, 5, 1, 4, 2, 3) - General-purpose I / O lines are controlled by software via data direction and data registers. Port A has high-current sink capability on all pins and external interrupt capability on bits 0-3.
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General Description
Logic Analyzer Connector Pin Assignments Figure 4 shows the pin assignments for logic analyzer connector J1. This connector provides easy access to many of the signals used internally. Table 2 lists signal descriptions for this connector.
- - LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LR / W - - - VCC RESET 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND - GND LA12 - - - AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR - - ACLK -
Figure 4. Connector J1 Pin Assignments
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General Description
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General Description Connector Information
Table 2. Logic Analyzer Connector J1 Signal Descriptions
AD7-AD0 LR / W LIR VCC ACLK
RESET
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General Description
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General Description
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MMDS / MMEVS Configuration and Operation
Contents
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MMDS / MMEVS Configuration and Operation
Introduction
The following paragraphs explain how to configure and use your M68EM05JP7 as part of an MMDS or MMEVS system. For other parts of system installation and configuration, see either the MMDS0508 Operations Manual (MMDS0508OM / D) or MMEVS05 / MMEVS08 Operations Manual (MMEVS0508OM / D). The topics covered in this chapter are: · · · · · · Setting M68EM05JP7 Jumper Headers on page 21 explains how to set the M68EM05JP7 jumper headers. Remaining System Installation on page 25 covers the final steps to system installation. Setting Emulation Voltage on page 26 explains how to adjust the MC68HC705JP7 MCU operating voltage. Personality Files Usage on page 27 discusses the personality file used on the M68EM05JP7 board. Personality EPROM Programming on page 27 covers programming procedures for the 64-bit personality EPROM. Emulation Specifics on page 29 explains special considerations for emulating with this module.
NOTE:
You can configure an M68EM05JP7 already installed in the system platform board. To do so, remove system power and then follow the guidance of this chapter. Be sure to switch off power before you reconfigure an installed EM. Reconfigure EM jumper headers with the power on can damage emulation circuits.
CAUTION:
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MMDS / MMEVS Configuration and Operation
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MMDS / MMEVS Configuration and Operation Setting M68EM05JP7 Jumper Headers
Setting M68EM05JP7 Jumper Headers
Your M68EM05JP7 has five jumper headers - W1 through W5. The following explains how to configure these components.
Internal Clock Control Header, W1
The internal clock control header provides access to the emulated internal low-power oscillator (LPO) frequency generated by the Y1 crystal circuit. The LPO on the M68EM05JP7 module operates at 500 kHz, the nominal LPO frequency. The LPO frequency passes through jumper header W1 and gives the user the ability to supply an alternate LPO frequency. To use an alternate internal clock source, remove the fabricated jumper from W1 and connect the source to the OUT pin of header W1. A digital ground connection is available at the GND pin.
NOTE:
The user-supplied LPO source should be a CMOS level square wave.
W1 LPO IN OUT GND
FABRICATED JUMPER
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MMDS / MMEVS Configuration and Operation
NOTE:
The user-supplied source through the target cable should be a CMOS level square wave.
The fourth possible external clock source is a user-supplied crystal oscillator circuit. The M68EM05JP7 has been designed with an unpopulated crystal circuit. For this source, reposition the W2 jumper between pins Y2 and C and supply the components for the Y2 crystal circuit. The IC device at location U1 is an 74HCU04 inverter and provides the inverter for a standard single inverter oscillator. The user supplies the appropriate crystal, resistors, and capacitors for operating the external clock at a particular frequency. See M68EM05JP7 Schematics (Sheet 4 of 7) on page 39 for schematic details of the crystal circuit.
W2 CLK SRC Y2 CAN MMDS TGT-OSC C C C C FABRICATED JUMPER
NOTE:
To use any of the external clock sources, the external pin oscillator must be selected as the MCU clock source through manipulation of the OM2:OM1 bits in the IRQ status and control register (ISCR)
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MMDS / MMEVS Configuration and Operation Setting M68EM05JP7 Jumper Headers
SWPDI Mask Option Control Header, W3
Jumper header W3 controls the software pulldown inhibit mask option for port A. With the jumper in the ENABL position, the mask option bit is clear and the port A pulldowns can be controlled via software. With the jumper in the INHIB position, the mask option is set and the port A pulldowns are inhibited.
NOTE:
The port B pulldowns are not controlled by this jumper. They are controlled by what is programmed in the SWPDI bit of the mask option register in the resident MC68HC705JP7 MCU.
W3 SWPDI
FABRICATED JUMPER ENABL
INHIB
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MMDS / MMEVS Configuration and Operation
IRQ / VPP Level Control Header, W4 When the resident MC68HC705JP7 is in reset, the IRQ / VPP voltage level is at the voltage determined by IRQ / VPP source control header W5. The IRQ / VPP level control header W4 controls the voltage level the IRQ / VPP pin will be at during routine operation when the external IRQ is not asserted and the part is not in reset. If jumper header W4 is in the NORMAL position, the IRQ / VPP level will drop to the MCU operating voltage once the part comes out of reset. If jumper header is in the 2XHOLD position, the IRQ / VPP level will be held at the voltage determined by IRQ / VPP source control header W5.
NOTE:
The W4 jumper header should be in the 2XHOLD position for personality EPROM programming only.
W4 IRQ LVL
NORMAL
2XHOLD
FABRICATED JUMPER
IRQ / VPP Source Control Header, W5
Jumper header W5 determines the source for high voltage applied to the IRQ / VPP pin. In the NORMAL position, the voltage is supplied from the development systems charge pump (~12 V). In the VPP position, the voltage is supplied from the user through lever terminal connector P3.
NOTE:
The W5 jumper header should be in the VPP position for personality EPROM programming only.
W5 IRQ VPP
FABRICATED JUMPER
NORMAL
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MMDS / MMEVS Configuration and Operation Remaining System Installation
Remaining System Installation
When you have configured headers W1-W5, M68EM05JP7 configuration is completed. At that time, make sure of these points: · · · Ensure that the power to the development tool is off. Remove the panel from the station module top, if installing the M68EM05JP7 in an MMDS station module. Fit together EM connectors P1 and P2 on the bottom of the board and platform board DIN connectors. Snap the corners of the EM onto the plastic standoffs. Connect the target cable, if appropriate. Replace the panel, if installing in an MMDS.
At this point, you are ready to make remaining cable connections, as necessary, and restore power. For instructions, consult either the MMEVS05 / MMEVS08 Operations Manual (MMEVS0508OM / D) or MMDS0508 Operations Manual (MMDS0508OM / D).
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MMDS / MMEVS Configuration and Operation
Setting Emulation Voltage
VR1 TP1 GND
ADJUST
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MMDS / MMEVS Configuration and Operation Personality Files Usage
Personality Files Usage
The development system uses a specific personality file to emulate MC68HC(7)05JJx and MC68HC(7)05JPx MCU devices: file 0002BVxx.MEM. The debugger software loads this personality file upon power up. The file is on an individual disk shipped with the M68EM05JP7.
NOTE:
Note that personality file names follow the pattern 00ZZZVxx.MEM, where ZZZ is the EM identifier or MCU name and xx is the version of the file.
Personality EPROM Programming
The MC68HC705JP7 and MC68HC705JJ7 MCUs have a 64-bit personality EPROM (PEPROM) that is controlled through MCU registers and the IRQ / VPP voltage. To program this array on the resident MCU, the user must write or obtain code that will modify the array correctly.
NOTE:
The MC68HC05JJ6 MCU does not have the personality EPROM. When emulating the MC68HC05JJ6 MCU, user code should not manipulate the PEPROM status and control register (PEBSR) or the PEPROM bit select register (PEBSR).
Refer to the general release specification for proper programming sequence. The required programming voltage must be supplied by the user through lever terminal connector P3. Proper configuration of jumper headers W4 and W5 is also required.
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MMDS / MMEVS Configuration and Operation
The following sequence shows how to program the PEPROM: 1. Ensure that power to the development system is off.
2. On the M68EM05JP7 emulation module, set jumper header W4 to the 2XHOLD position and the W5 jumper header to the VPP position. 3. On the M68EM05JP7 emulation module, make connections to P3 to supply the required programming voltage. Do not turn the VPP supply voltage on. 4. Turn on power to the development system. 5. Turn on the VPP supply voltage. At this point, the proper programming voltage is applied to the resident MCU. 6. Start running debugger software. 7. Load and execute the necessary code to program the PEPROM. 8. Once the PEPROM programming is complete, exit the debugger software. 9. Remove VPP source voltage from connector P3. 10. Turn off development system power. 11. Reposition jumper headers W4 and W5 to the normal position.
NOTE:
To program the PEPROM, VDD must be greater than 4.5 Vdc. To avoid damaging emulator circuits, the development system voltage must be turned on before you supply the VPP source voltage through the P3 connector. Also, the source voltage should be removed from P3 before turning off the development system voltage.
CAUTION:
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MMDS / MMEVS Configuration and Operation Emulation Specifics
Emulation Specifics
The following paragraphs detail differences between the performance of MC68HC(7)05JPx and MC68HC(7)05JJx MCUs run in single-chip operation and how certain features will perform during emulation.
IRQ / VPP Input Pin
In single-chip mode operation: The IRQ / VPP pin drives the asynchronous IRQ interrupt function of the CPU. The pin is also used for programming voltage when programming the personality EPROM, the user EPROM, or the MOR. In emulation: The IRQ / VPP signal supplied to connector J2 through a target cable drives only the asynchronous IRQ interrupt function. A VPP voltage should not be supplied to the IRQ / VPP pin in a target application while the emulator is connected. Connector P3 is available for VPP programming voltage input.
Pullup on IRQ
In single-chip mode operation: There is no pullup on the IRQ pin. Your application must pull the IRQ pin to VDD level to prevent interrupts. In emulation: The IRQ pin is pulled up on the module. Be aware that an application without the IRQ pin pulled high will emulate correctly but will fail in the application because of a floating IRQ line. The IRQ pin pulled high on the module causes these results.
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MMDS / MMEVS Configuration and Operation
Personality EPROM In single-chip mode operation: The MC68HC05JJ6 does not have a personality EPROM and accesses to the PEPROM registers are undefined. In emulation: The MC68HC05JJ6 device is emulated with a MC68HC705JP7 device resident on the M68EM05JP7 module. For accurate emulation, the PEPROM registers should not be accessed when emulating the MC68HC05JJ6 MCU.
Mask Option Register (MOR) Control
In single-chip mode operation: The MCU mask options will be determined by which options have been programmed in the MOR EPROM location of the resident MC68HC705JP7 MCU. This register must be programmed using a dedicated programmer. In emulation: Like single-chip, the mask option register should be programmed to the desired value using a dedicated programmer prior to insertion in the M68EM05JP7 module. The exception is the SWPDI mask option, which is detailed in SWPDI Mask Option Bit.
SWPDI Mask Option Bit
In single-chip mode operation: The software programmable pulldown inhibit option is determined by what has been programmed in the mask option register (MOR). If the bit is set, all I / O pulldowns are inhibited. In emulation: The programmed software programmable pulldown inhibit option only controls the pulldowns for port B. The port A and port C pulldown inhibit option is emulated with jumper header W3.
NOTE:
Port C is bonded out only on the MC68HC705JP7 MCU.
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Schematics
Contents
M68EM05JP7 Schematics
Refer to the following pages for the seven sheets of schematics for the M68EM05JP7 emulation module.
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Schematics
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Schematics
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MOTOROLA Schematics 33
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M68EM05JP7 Schematics (Sheet 1 of 7)
M68EM05JP7 EMULATION MODULE
ECN # 110
PCB REV O
SCH REV 2
Make LIR to PFB be low true.
Decouple Caps for ICs as labeled. All caps are 0.1 uF @ 50 V
VCC C3 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 GND VCC
C34 GND
TP1 3 TEST POINT FOR LVDD ADJUST 2 1 HDR103 C19 C23 C33 CAPACITANCE VALUES ARE IN MICROFARADS.
U18 VIN VOUT 2 R8 240
CHRGPMP
C30 0.1UF GND
ADJUST LM317T
Spare Gates
VCC-1 VCC-1 U28C 9 8 10 9 74ACT00 U27C 74HC4066 12 U28D 12 11 13 74ACT00 10 11 U27D 74HC4066 GND-1 1 2 11 13 74HC32 U16D 8 6
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title
COMPUTER GENERATED DRAWING : DO NOT REVISE MANUALLY
M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 1 of
Schematics
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Schematics
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M68EM05JP7 Schematics (Sheet 2 of 7)
Direct Target Connector Bus LSByte Address / Data Bus LVDD MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 2 3 4 5 6 7 8 9 11 1 U11 D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 19 18 17 16 15 14 13 12 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0
MCU1.28 MCUAD0.7 LA0.14
R10 10K MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 R11 10K GND
LOGIC ANALYZER CONNECTOR
J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 VCC 35 37 COP-RESET 39 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 LR / W HDR220 LR / W U6A 1 74HC04 COP-RESET SH 7 2 SH 3, 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND LA12 AD0.7 SH 7
C OC 74HCT573
A8 / A9 A10 / A11 A12 LIR / RW E LV-OSC1
U20 D1 D2 D3 D4 D5 D6 D7 D8
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR ACLK
C OC 74HCT573
TST-RNG
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0
CLK OC 74HCT574 E
VCC-1 VCC-1 A8 / A9 A10 / A11 A12 LIR / RW E LV-OSC1 R7 10K PH2 4 2 3 P R CLK C L 1 D U7A Q 5 12 11 Q 6 E-EM 74HCT74 D 1 0 P R CLK C L Q U7B U15D 9 12 11 13 8 74HCT32 3 74HC04 4 U6B 11
U6E 10 74HC04 SCLK SH 3
U16C Q 9 8 10 74HC32 GND SCLK SH 3
1 74HCT74 3 VCC-1
VCC-1 GND PH2 PH2 SH 4
LV-OSC2
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 2 of REV 2 7
Schematics
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Schematics
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VCC GND 1 3 GND PRU NOT
M68EM05JP7 Schematics (Sheet 3 of 7)
PA0.5 TGT-PC0.7 LOCKOUT LOCKOUT T-IRQ TOSC2 TGT-OSC
MCU1.28
TARGETJ2 CONNECTOR
(PB0) MCU28 EVDD GND 1 3 5 7 TOSC1 9 TOSC2 TGT-PC3 11 TGT-PC2 13 TGT-PC1 15 TGT-PC0 17 T-RESET 19 21 T-IRQ TGT-PA0 23 TGT-PA1 25 TGT-PA2 27 29 31 33 35 37 39 HDR220 GND TGT-PA0.5 GND TGT-PA0.5 SH 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 MCU1 (PB1) MCU2 (PB2) MCU3 (PB3) MCU4 (PB4) MCU5 (PB5) TGT-PC4 TGT-PC5 TGT-PC6 TGT-PC7 MCU10 (PB6) MCU11 (PB7) TGT-PA5 TGT-PA4 TGT-PA3
MCU1.28
VPRU EVDD VCC GND
AD0.7 LA0.14 P1B P1C P1A 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 GND DAUGHTER BOARD CONNECTOR #1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 (LA14) (LA13) LA12 LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 GND-1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 LIR LR / W SCLK SCLK B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LA0.14 SH 2
LIR LR / W SCLK SCLK
INTERNAL SWITCH
INTERNAL SWITCH (WE) (U / M) (OE)
MMDSIRQ CHRGPMP (ABT) MMDSOSC
MMDSIRQ CHRGPMP MMDSOSC
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS VCC Title M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 3 of REV 2 7
Schematics
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Schematics
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VPP FOR PEP
M68EM05JP7 Schematics (Sheet 4 of 7)
IRQ VPP
W5 (VPP) 1 2 3 RN8B 4
IRQ W4 LEVEL
(NORMAL) 1 2 R12
1 0 Q8 2N4401
LPO HEADER
10 11 U2 9 CLK Q1 7 Q2 6 RST Q3 5 Q4 3 Q5 2 Q6 4 Q7 Q8 13 Q9 12 Q10 14 Q11 15 1 Q12 74HC4040
LA0.14 LOCKOUT
DECODE AND OSC SWITCH
VCC R4 10K
DECODE TABLE
XY3 1 NC VCC 14
IO31 IO0 IO1 IO30 IO2 IO29 IO28 IO3 IO4 IO27 IO5 IO26 IO25 IO6 IO7 IO24 I0 CLK1 / I5 I4 I1 CLK0 / I2 I3 IO8 IO23 IO9 IO22 IO10 IO21 IO20 IO11 IO12 IO19 IO13 IO18 IO17 IO14 IO15 IO16 VSS VSS VSS VSS MACH215-12JC
LV-OSC1 E-EM AD0.7
Schematics M68EM05JP7 Schematics
CLK SRC
W2 2 4 6 8 Title M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 4 of REV 2 7 CSIC DEVELOPMENT TOOLS
Schematics
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Schematics
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SH 3 PA0.5 TO / FROM PRU PA0 PA1 PA2 PA0.5 PA3 PA4 PA5 SH 6 SH 6 PDICH PDICL PDICH PDICL DDRA0 SH 4 SH 3 SH 4 WR-PDRA LOCKOUT WR-DDRA PA0 PA1 1 2 PA2 PA3 9 10 SH 7 AD0.7
M68EM05JP7 Schematics (Sheet 5 of 7)
TGT-PA4
12 13 2 1 5 3 DDRA3 DDRA4 DDRA5 6 11 10 9
TGT-PA3
TGT-PA2
PORT A HIGH CURRENT
DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 WR-PDRA LOCKOUT WR-DDRA PA5 PA4 PA0 PA3 TGT-PA3 TGT-PA0 PAPULL3 PAPULL0
IO0 IO31 IO1 IO30 IO2 IO29 IO3 IO28 IO4 IO27 IO5 IO26 IO6 IO25 IO7 IO24 I0 CLK1 / I5 I1 I4 CLK0 / I2 I3 IO8 IO23 IO9 IO22 IO10 IO21 IO11 IO20 IO12 IO19 IO13 IO18 IO14 IO17 IO15 IO16 VSS VSS VSS VSS MACH215-12JC
TGT-PA0
SWPDI MASK OPTION W3
3 2 1 HDR103 1-2 ENABLE 2-3 INHIBIT VCC
PAPULL0 PAPULL1
Schematics M68EM05JP7 Schematics
Schematics
M68EM05JP7UM / D
Schematics
MOTOROLA
MOTOROLA Schematics 43
M68EM05JP7UM / D
SH 7 AD0.7 AD0.7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 SH 4 SH 3 WR-DDRC LOCKOUT WR-DDRC LOCKOUT 3 4 7 8 13 14 17 18 11 1 SH 5 SH 5 SWPDI PDICL SWPDI 1 PDICL 2 4 SH 5 PDICH PDICH 5
M68EM05JP7 Schematics (Sheet 6 of 7)
TGT-PC0.7
PORT C PULLDOWN
TGT-PC0 TGT-PC1 TGT-PC2
U4A 74HC125 4
U4B 74HC125 10
U4C 74HC125 13
U4D 74HC125
DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRC7
U9 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
CLK CLR 74HCT273
1G 2G 74HC244
2 4 U3A 74HC125 3
5 10 U3B 74HC125 6
9 13 U3C 74HC125 8
U16A 3 74HC32 U16B 6
U3D 74HC125 1 1
7 74HC32 5 3 1 RN1A 2 RN1B 4 RN1C 6
RN1D 8
TGT-PC4
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 6 of REV 2 7
Schematics
M68EM05JP7UM / D
Schematics
MOTOROLA
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M68EM05JP7 Schematics (Sheet 7 of 7)
ADDRESS / DATA BUS CONVERSION
EM RESET CIRCUIT
LVDD AD7 AD6 AD5 AD4 AD3 AD2
G1 G2 74ACT541
LVDD AD1 AD0 OSC1 PA-IRQ LVDD-1 U6D 8 9 74HC04 OSCBUF SH 4 PA-IRQ SH 5
CR2 1N5817
LV-PA-IRQ LV-OSC2 LV-OSC1
TGT-RESET LEVEL CONVERSION
GND-1 GND
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number B 63BSE90840W Date: May 7, 1996 Sheet 7 of REV 2 7
Schematics
M68EM05JP7UM / D
Schematics
MOTOROLA
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M68EM05JP7UM / D