M68EM05JP7 EMULATION MODULE USER'S MANUAL M68EM05JP7 Em
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M68EM05JP7UM/D
M68EM05JP7
EMULATION MODULE USER'S MANUAL
M68EM05JP7
Emulation Module User's Manual
Motorola reserves right make changes without further notice products herein improve reliability, function, design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola Motorola logo registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
Motorola, Inc., 1996; Rights Reserved
MOTOROLA
Revision History
Revision History
following table summarizes differences between this revision previous revision this emulation module user's manual.
Previous Revision Current Revision Date Changes Location
NONE 06/96
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Revision History
M68EM05JP7UM/D
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Table Contents
General Description Contents Introduction Emulation Components Emulation Module Layout Target Cable Assemblies Connector Information Target Cable Connector Assignments Logic Analyzer Connector Assignments Contents Introduction Setting M68EM05JP7 Jumper Headers Internal Clock Control Header, External Clock Source Select Header, SWPDI Mask Option Control Header, IRQ/VPP Level Control Header, IRQ/VPP Source Control Header, Remaining System Installation Setting Emulation Voltage Personality Files Usage Personality EPROM Programming Emulation Specifics IRQ/VPP Input Pullup Personality EPROM Mask Option Register (MOR) Control SWPDI Mask Option Contents M68EM05JP7 Schematics
MMDS/MMEVS Configuration Operation
Schematics
M68EM05JP7UM/D
MOTOROLA
Table Contents
Table Contents
M68EM05JP7UM/D
Table Contents
MOTOROLA
General Description
Contents
Introduction Emulation Components Emulation Module Layout Target Cable Assemblies Connector Information Target Cable Connector Assignments Logic Analyzer Connector Assignments
Introduction
Your M68EM05JP7 gives your Motorola development tool ability emulate target systems based MC68HC705JP7, MC68HC705JJ7, MC68HC05JJ6 microcontroller units (MCUs). M68EM05JP7 designed low-voltage emulator, operating range maximum rated frequencies general release specification. substituting different emulation module (EM), enable your Motorola development tool emulate other MCUs. Refer Motorola's Development Tool Selector Guide, order number SG173/D, complete list available EMs. This hardware user's manual explains connection, configuration, operation information specific M68EM05JP7 emulation module. module installed Motorola development systems. configure your M68EM05JP7 either MMDS MMEVS, follow instructions given MMDS/MMEVS Configuration Operation page
M68EM05JP7UM/D
MOTOROLA
General Description
General Description
Emulation Components
Motorola's complete emulation system consists emulation module described this manual well other separately purchased options described following paragraphs. These items included with M68EM05JP7 emulation module: M68EM05JP7 emulation module (EM) printed circuit board that enables system functionality MC68HC705JP7 MCUs. female connectors, bottom module, mate with male connectors development system platform board. also connector target cable assembly. Configuration software 1/2-inch diskette containing personality files this module.
Separately purchased Motorola modular development tool options include: MMEVS platform board (M68MMPFB0508) MMEVS economical development tool that provides real-time in-circuit emulation. unit's integrated design environment includes editor, assembler, user interface, source-level debugging program. MMDS0508 modular development system (M68MMDS0508) MMDS high-performance development tool that capabilities MMEVS. addition, also power supply, state analyzer, real-time memory windows. Flex cable target assembly Refer Target Cable Assemblies page more information.
User supplied components include: Host computer appropriate development tool user's manual minimum requirements. Power supply required MMEVS.
M68EM05JP7UM/D
General Description
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General Description Emulation Module Layout
Emulation Module Layout
Figure shows layout M68EM05JP7. Jumper header controls low-power oscillator (LPO) source. Jumper header lets select external oscillator (EPO) source. Jumper header selects software pulldown inhibit mask option port Jumper header controls voltage applied IRQ/VPP pin. Jumper header determines source voltage IRQ/VPP pin. Target connector interface target system; this connector uses separately purchased target cable assembly. When install M68EM05JP7 MMDS, target cable passes through slit station module enclosure. Connector connects logic analyzer. Variable resistor controls operating voltage between Test point header monitor point operating voltage adjustment. MC68HC705JP7 location XU22. connectors connect development system platform board. Lever terminal connector inputting personality EPROM (PEPROM) programming voltage.
XU22
Figure M68EM05JP7 Emulation Module
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General Description
General Description
Target Cable Assemblies
connect your M68EM05JP7 target system, need separately purchased target cable assembly. Cable assemblies available four packages: 28-pin 28-pin SOIC packages. target cable connects emulator connector M68EM05JP7 emulation module. assignments signal descriptions connector found Target Cable Connector Assignments page Figure represents target cable assembly. assembly packages consists flex cable target head adapter. assembly SOIC packages requires additional SOIC adapter. flex cable plugs onto M68EM05JP7 connector with orientation shown Figure other flex cable plugs into target head adapter. target head adapter then inserts into either footprint target system into SOIC adapter. package your target system determines target cable assembly components required: 20-pin package (MC68HC(7)05JJx MCUs), flex cable M68CBL05A target head adapter M68TA05JJ7P20. 28-pin package (MC68HC(7)05JPx MCUs), flex cable M68CBL05A target head adapter M68TA05JP7P28. 20-pin SOIC package (MC68HC(7)05JJx MCUs), flex cable assembly 20-pin conjunction with SOIC adapter M68DIP20SOIC. 28-pin SOIC package (MC68HC(7)05JPx MCUs), flex cable assembly 28-pin conjunction with SOIC adapter M68DIP28SOIC.
M68EM05JP7UM/D
General Description
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General Description Target Cable Assemblies
EMULATION MODULE
FLEX CABLE
TARGET HEAD ADAPTER
TARGET HEAD ADAPTER EMULATION MODULE TARGET SYSTEM SOCKET
20-PIN
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JJ7P20
28-PIN
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JP7P28
20-PIN SOIC
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JJ7P20 SOIC ADAPTER: M68DIP20SOIC
28-PIN SOIC
FLEX CABLE: M68CBL05A TARGET HEAD ADAPTER: M68TA05JP7P28 SOIC ADAPTER: M68DIP28SOIC
Figure Target Cable Assembly
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General Description
General Description
Connector Information
connectors M68EM05JP7 module provide access user mode emulation signals (J2) well select internal signals (J1). Connector used cable interface user's target system, while connector used connect logic analyzer.
Target Cable Connector Assignments
Figure shows assignments connector Table lists signal descriptions connector
PB0/AN0 EVDD OSC1 OSC2 RESET PB1/AN1 PB2/AN2 PB3/AN3/TCAP PB4/AN4/TCMP PB5/SDO PB6/SDI PB7/SCK
Figure Target Connector Assignments
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General Description
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General Description Connector Information
Table Connector Signal Descriptions
Mnemonic PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3/TCAP PB4/AN4/TCMP EVDD OSC1 OSC2 PB5/SDO PB6/SDI PB7/SCK PC3, PC4, PC2, PC5, PC1, PC6, PC0, Signal PORT (bits General-purpose lines controlled software data direction data registers. Pins become AN0, AN1, AN2, AN3, lines respectively when analog subsystem enabled. become TCAP TCMP pins respectively when programmable timer subsystem enabled. EXTERNAL VOLTAGE DETECT Connected target VCC; used sense target power applied target status MMDS05 status window GROUND TARGET OSCILLATOR possible external clock source input M68EM05JP7 board; system frequency OSC1 this signal controlled jumper header OSCILLATOR Output clock signal. Inversion OSC1 clock. PORT (bits General-purpose lines controlled software data direction data registers. Pins become SDO, SDI, lines respectively when simple serial interface subsystem enabled. PORT (bits 0-7) General-purpose lines controlled software data direction data registers.
29-40
NOTE: Port bonded only MC68HC705JP7 MCU.
TARGET INTERRUPT REQUEST Active-low input signal from target that asynchronously applies interrupt
NOTE: programming voltage should applied this
pin. Doing will damage development system. Connector available programming voltage input.
RESET PA0, PA5, PA1, PA4, PA2,
Active-low bidirectional signal to/from target system driven pull into reset. PORT (bits General-purpose lines controlled software data direction data registers. Port high-current sink capability pins external interrupt capability bits 0-3.
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General Description
General Description
Logic Analyzer Connector Assignments Figure shows assignments logic analyzer connector This connector provides easy access many signals used internally. Table lists signal descriptions this connector.
LA11 LA10 LR/W RESET LA12 ACLK
Figure Connector Assignments
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General Description
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General Description Connector Information
Table Logic Analyzer Connector Signal Descriptions
Mnemonic LA12 LA11-LA0 connection GROUND LATCHED ADDRESS (bit latched output address LATCHED ADDRESSES (bits 11-0) latched output address DATA (bits 7-0) multiplexed LATCHED READ/WRITE MCU's write signal latched used emulator control emulator memory accesses. LOAD INSTRUCTION REGISTER Active signal indicating opcode fetch cycle process. POWER Connection system voltage ANALYZER CLOCK latched addresses valid latched address rising edge ACLK. Also, data valid ACLK's rising edge. RESET Active-low signal; will asserted during internally externally caused resets Signal
AD7-AD0 LR/W ACLK
RESET
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General Description
General Description
M68EM05JP7UM/D
General Description
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MMDS/MMEVS Configuration Operation
Contents
Introduction Setting M68EM05JP7 Jumper Headers Internal Clock Control Header, External Clock Source Select Header, SWPDI Mask Option Control Header, IRQ/VPP Level Control Header, IRQ/VPP Source Control Header, Remaining System Installation Setting Emulation Voltage Personality Files Usage Personality EPROM Programming Emulation Specifics IRQ/VPP Input Pullup Personality EPROM Mask Option Register (MOR) Control SWPDI Mask Option
M68EM05JP7UM/D
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
Introduction
following paragraphs explain configure your M68EM05JP7 part MMDS MMEVS system. other parts system installation configuration, either MMDS0508 Operations Manual (MMDS0508OM/D) MMEVS05/MMEVS08 Operations Manual (MMEVS0508OM/D). topics covered this chapter are: Setting M68EM05JP7 Jumper Headers page explains M68EM05JP7 jumper headers. Remaining System Installation page covers final steps system installation. Setting Emulation Voltage page explains adjust MC68HC705JP7 operating voltage. Personality Files Usage page discusses personality file used M68EM05JP7 board. Personality EPROM Programming page covers programming procedures 64-bit personality EPROM. Emulation Specifics page explains special considerations emulating with this module.
NOTE:
configure M68EM05JP7 already installed system platform board. remove system power then follow guidance this chapter. sure switch power before reconfigure installed Reconfigure jumper headers with power damage emulation circuits.
CAUTION:
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MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation Setting M68EM05JP7 Jumper Headers
Setting M68EM05JP7 Jumper Headers
Your M68EM05JP7 five jumper headers through following explains configure these components.
Internal Clock Control Header,
internal clock control header provides access emulated internal low-power oscillator (LPO) frequency generated crystal circuit. M68EM05JP7 module operates kHz, nominal frequency. frequency passes through jumper header gives user ability supply alternate frequency. alternate internal clock source, remove fabricated jumper from connect source header digital ground connection available pin.
NOTE:
user-supplied source should CMOS level square wave.
FABRICATED JUMPER
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
External Clock Source Select Header, Jumper header determines source external clock signal. diagram here illustrates jumper header where pins marked indicate common pins. default configuration selects 4-MHz canned oscillator clock source board location XY3). There three other possible sources external clock. source, from platform board, requires repositioning jumper between pins MMDS then using system's command select frequency. user-supplied clock source, coming through target cable connected reposition jumper between pins TGT_OSC
NOTE:
user-supplied source through target cable should CMOS level square wave.
fourth possible external clock source user-supplied crystal oscillator circuit. M68EM05JP7 been designed with unpopulated crystal circuit. this source, reposition jumper between pins supply components crystal circuit. device location 74HCU04 inverter provides inverter standard single inverter oscillator. user supplies appropriate crystal, resistors, capacitors operating external clock particular frequency. M68EM05JP7 Schematics (Sheet page schematic details crystal circuit.
MMDS TGT-OSC FABRICATED JUMPER
NOTE:
external clock sources, external oscillator must selected clock source through manipulation OM2:OM1 bits status control register (ISCR)
M68EM05JP7UM/D
MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation Setting M68EM05JP7 Jumper Headers
SWPDI Mask Option Control Header,
Jumper header controls software pulldown inhibit mask option port With jumper ENABL position, mask option clear port pulldowns controlled software. With jumper INHIB position, mask option port pulldowns inhibited.
NOTE:
port pulldowns controlled this jumper. They controlled what programmed SWPDI mask option register resident MC68HC705JP7 MCU.
SWPDI
FABRICATED JUMPER ENABL
INHIB
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
IRQ/VPP Level Control Header, When resident MC68HC705JP7 reset, IRQ/VPP voltage level voltage determined IRQ/VPP source control header IRQ/VPP level control header controls voltage level IRQ/VPP will during routine operation when external asserted part reset. jumper header NORMAL position, IRQ/VPP level will drop operating voltage once part comes reset. jumper header 2XHOLD position, IRQ/VPP level will held voltage determined IRQ/VPP source control header
NOTE:
jumper header should 2XHOLD position personality EPROM programming only.
NORMAL
2XHOLD
FABRICATED JUMPER
IRQ/VPP Source Control Header,
Jumper header determines source high voltage applied IRQ/VPP pin. NORMAL position, voltage supplied from development systems charge pump (~12 position, voltage supplied from user through lever terminal connector
NOTE:
jumper header should position personality EPROM programming only.
FABRICATED JUMPER
NORMAL
M68EM05JP7UM/D
MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation Remaining System Installation
Remaining System Installation
When have configured headers W1-W5, M68EM05JP7 configuration completed. that time, make sure these points: Ensure that power development tool off. Remove panel from station module top, installing M68EM05JP7 MMDS station module. together connectors bottom board platform board connectors. Snap corners onto plastic standoffs. Connect target cable, appropriate. Replace panel, installing MMDS.
this point, ready make remaining cable connections, necessary, restore power. instructions, consult either MMEVS05/MMEVS08 Operations Manual (MMEVS0508OM/D) MMDS0508 Operations Manual (MMDS0508OM/D).
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
Setting Emulation Voltage
M68EM05JP7 module on-board voltage regulator that adjusted provide low-voltage emulation range. adjustment that variable voltage variable resistor VR1. Test point used connection voltmeter during voltage adjustment. adjust operating voltage, first ensure that target cable connected target cable connector Then connect voltmeter across LVDD pins test point header adjust variable resistor desired voltage level. Make sure that target system's operating voltage newly adjusted level before connecting target signals through connector.
ADJUST
LVDD
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MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation Personality Files Usage
Personality Files Usage
development system uses specific personality file emulate MC68HC(7)05JJx MC68HC(7)05JPx devices: file 0002BVxx.MEM. debugger software loads this personality file upon power file individual disk shipped with M68EM05JP7.
NOTE:
Note that personality file names follow pattern 00ZZZVxx.MEM, where identifier name version file.
Personality EPROM Programming
MC68HC705JP7 MC68HC705JJ7 MCUs have 64-bit personality EPROM (PEPROM) that controlled through registers IRQ/VPP voltage. program this array resident MCU, user must write obtain code that will modify array correctly.
NOTE:
MC68HC05JJ6 does have personality EPROM. When emulating MC68HC05JJ6 MCU, user code should manipulate PEPROM status control register (PEBSR) PEPROM select register (PEBSR).
Refer general release specification proper programming sequence. required programming voltage must supplied user through lever terminal connector Proper configuration jumper headers also required.
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
following sequence shows program PEPROM: Ensure that power development system off.
M68EM05JP7 emulation module, jumper header 2XHOLD position jumper header position. M68EM05JP7 emulation module, make connections supply required programming voltage. turn supply voltage Turn power development system. Turn supply voltage. this point, proper programming voltage applied resident MCU. Start running debugger software. Load execute necessary code program PEPROM. Once PEPROM programming complete, exit debugger software. Remove source voltage from connector Turn development system power. Reposition jumper headers normal position.
NOTE:
program PEPROM, must greater than Vdc. avoid damaging emulator circuits, development system voltage must turned before supply source voltage through connector. Also, source voltage should removed from before turning development system voltage.
CAUTION:
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MMDS/MMEVS Configuration Operation
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MMDS/MMEVS Configuration Operation Emulation Specifics
Emulation Specifics
following paragraphs detail differences between performance MC68HC(7)05JPx MC68HC(7)05JJx MCUs single-chip operation certain features will perform during emulation.
IRQ/VPP Input
single-chip mode operation: IRQ/VPP drives asynchronous interrupt function CPU. also used programming voltage when programming personality EPROM, user EPROM, MOR. emulation: IRQ/VPP signal supplied connector through target cable drives only asynchronous interrupt function. voltage should supplied IRQ/VPP target application while emulator connected. Connector available programming voltage input.
Pullup
single-chip mode operation: There pullup pin. Your application must pull level prevent interrupts. emulation: pulled module. aware that application without pulled high will emulate correctly will fail application because floating line. pulled high module causes these results.
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MMDS/MMEVS Configuration Operation
MMDS/MMEVS Configuration Operation
Personality EPROM single-chip mode operation: MC68HC05JJ6 does have personality EPROM accesses PEPROM registers undefined. emulation: MC68HC05JJ6 device emulated with MC68HC705JP7 device resident M68EM05JP7 module. accurate emulation, PEPROM registers should accessed when emulating MC68HC05JJ6 MCU.
Mask Option Register (MOR) Control
single-chip mode operation: mask options will determined which options have been programmed EPROM location resident MC68HC705JP7 MCU. This register must programmed using dedicated programmer. emulation: Like single-chip, mask option register should programmed desired value using dedicated programmer prior insertion M68EM05JP7 module. exception SWPDI mask option, which detailed SWPDI Mask Option Bit.
SWPDI Mask Option
single-chip mode operation: software programmable pulldown inhibit option determined what been programmed mask option register (MOR). set, pulldowns inhibited. emulation: programmed software programmable pulldown inhibit option only controls pulldowns port port port pulldown inhibit option emulated with jumper header
NOTE:
Port bonded only MC68HC705JP7 MCU.
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MMDS/MMEVS Configuration Operation
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Schematics
Contents
M68EM05JP7 Schematics Sheet Sheet Sheet Sheet Sheet Sheet Sheet
M68EM05JP7 Schematics
Refer following pages seven sheets schematics M68EM05JP7 emulation module.
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Schematics
Schematics
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Schematics
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MOTOROLA Schematics
M68EM05JP7UM/D
NOTES, UNLESS OTHERWISE SPECIFIED LOCATIONS GROUND LOCATIONS 7407 7407 DEVICE TYPE NUMBERS REFERENCE DESIGNATORS RESISTANCE VALUES OHMS. RESISTORS WATT, VCC-1 74HCU04 74HCU04 ORCAD FLAT FILES |LINK |05JPR2S2.SCH |05JPR2S3.SCH |05JPR2S4.SCH |05JPR2S5.SCH |05JPR2S6.SCH |05JPR2S7.SCH
M68EM05JP7 Schematics (Sheet
APPLIED 8-PIN IC's, 14-PIN IC's, 16-PIN IC's, 20-PIN IC's, ETC.
M68EM05JP7 EMULATION MODULE
DESCRIPTION
Make true.
DATE
5/7/96
GROUND APPLIED 8-PIN IC's, 14-PIN IC's, 16-PIN IC's, 20-PIN IC's, ETC. DEVICE TYPE, NUMBERS, REFERENCE DESIGNATOR GATES SHOWN FOLLOWS
Decouple Caps labeled. caps
TEST POINT LVDD ADJUST HDR103 CAPACITANCE VALUES MICROFARADS.
LVDD
VOUT
CHRGPMP
0.1UF
ADJUST LM317T
LVDD 2,3,4,5,7 0.1UF 1UF_RT_16V
Spare Gates
VCC-1 VCC-1 U28C 74ACT00 U27C 74HC4066 U28D 74ACT00 U27D 74HC4066 GND-1 74HC32 U16D
1K_POT
RN1E RES_ISO5I_47K RES_ISO5I_10K RN7E
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title
COMPUTER GENERATED DRAWING REVISE MANUALLY
M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet
Schematics
M68EM05JP7UM/D
Schematics
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MOTOROLA Schematics
M68EM05JP7UM/D
LVDD XU22 MCU11 MCU10 MCU5 MCU4 MCU3 MCU2 MCU1 MCU28 PB7/SCK PB6/SDI PB5/SDO PB4/AN4/TCMP PB3/AN3/TCAP PB2/AN2 PB1/AN1 PB0/AN0 RESET IRQ/VPP OSC1 OSC2 MC68HC705JP7EP 1UF_RT_16V MCU11 MCU10 MCU5 MCU4 MCU3 MCU2 MCU1 MCU28 XU23 MCU-RESET* IRQ* LVDD PB7/SCK PB6/SDI PB5/SDO PB4/AN4/TCMP PB3/AN3/TCAP PB2/AN2 PB1/AN1 PB0/AN0 RESET IRQ/VPP OSC1 OSC2 MC68HC705JP7EDW MCU-RESET* IRQ* LV-PA-IRQ LV-OSC1 LV-PA-IRQ LV-OSC2
M68EM05JP7 Schematics (Sheet
Direct Target Connector LSByte Address/Data LVDD MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0
MCU[1.28] MCUAD[0.7] LA[0.14]
MCU[1.28] MCUAD[0.7] LA[0.14]
SHTS
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0
LOGIC ANALYZER CONNECTOR
COP-RESET* LA11 LA10 LR/W HDR220 LR/W 74HC04 COP-RESET* LA12 AD[0.7]
74HCT573
LA10 LA11 LA12 LR/W LIR*
A8/A9 A10/A11 LIR/RW LV-OSC1
GND-1
GND-1 PRE_LIR GND-1
LIR* ACLK
LIR*
74HCT573
TST-RNG
MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0
74HCT574
VCC-1 VCC-1 A8/A9 A10/A11 LIR/RW LV-OSC1 PH2* E-EM 74HCT74 U15D 74HCT32 74HC04
74HC04 SCLK
U16C 74HC32 SCLK*
74HCT74 VCC-1
VCC-1
E-EM
E-EM
LV-OSC2
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet
Schematics
M68EM05JP7UM/D
Schematics
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MOTOROLA Schematics
M68EM05JP7UM/D
M68EM05JP7 Schematics (Sheet
PA[0.5] DAUGHTER BOARD CONNECTOR RES_ISO5I_10K RN7A PA6-HC26 PA7-HC26 RN7B RES_ISO5I_10K PORT USED TGT-PC0 TGT-PC1 TGT-PC2 TGT-PC3 TGT-PC4 TGT-PC5 TGT-PC6 TGT-PC7 LOCKOUT* T-RST* (RESET-IN) PORTS* MMDS-RESET* COP-RESET* (PRU-D*) 74HC04 LOCKOUT* TGT-PC[0.7]
PA[0.5] TGT-PC[0.7] LOCKOUT LOCKOUT* T-IRQ* TOSC2 TGT-OSC
4,5,6
MCU[1.28]
TARGETJ2 CONNECTOR
(PB0) MCU28 EVDD TOSC1 TOSC2 TGT-PC3 TGT-PC2 TGT-PC1 TGT-PC0 T-RESET* T-IRQ TGT-PA0 TGT-PA1 TGT-PA2 HDR220 TGT-PA[0.5] TGT-PA[0.5] MCU1 (PB1) MCU2 (PB2) MCU3 (PB3) MCU4 (PB4) MCU5 (PB5) TGT-PC4 TGT-PC5 TGT-PC6 TGT-PC7 MCU10 (PB6) MCU11 (PB7) TGT-PA5 TGT-PA4 TGT-PA3
MCU[1.28]
VPRU EVDD
MMDSID $02B
2,4,5
CON_DIN96 LVDD COP-RESET* MMDS-RESET* PORTS* T-RST* T-RESET* AD[0.7]
CON_DIN96 LVDD COP-RESET* MMDS-RESET* PORTS*
CON_DIN96
AD[0.7] LA[0.14] DAUGHTER BOARD CONNECTOR (LA14) (LA13) LA12 LA11 LA10 GND-1 LIR* LR/W SCLK SCLK* LA[0.14]
LIR* LR/W SCLK SCLK*
INTERNAL* SWITCH
INTERNAL* SWITCH
INTERNAL* SWITCH (WE*) (U/M) (OE*)
MMDSIRQ* CHRGPMP (ABT) MMDSOSC
MMDSIRQ* CHRGPMP MMDSOSC
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet
CON_DIN96
CON_DIN96
CON_DIN96
Schematics
M68EM05JP7UM/D
Schematics
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MOTOROLA Schematics
M68EM05JP7UM/D
PWRTERM2 LVDD-1 RN8A RES_ISO5I_10K CHRGPMP LOCKOUT VPP-IN T-IRQ* MMDSIRQ* 74HCU04 4MHZ_49US 27PF 27PF 74HCU04 DATAOUT-EN* DATAIN-EN* TST-RNG INTERNAL* WR-DDRA WR-DDRC WR-PDRA PORTS* LR/W SWITCH OSCBUF LR/W 74HCU04 USER_DEFINED_XTL USER_DEFINED_RES USER_DEFINED_CAP MMDSOSC TGT-OSC
M68EM05JP7 Schematics (Sheet
2N4403 RN8D RES_ISO5I_10K RN9C RES_ISO5I_1K RN9D RES_ISO5I_1K (NORMAL) RES_ISO5I_10K HDR103 U28A 74ACT00 (2xVDD) HDR103 HDR103 U28B 74ACT00 LOCKOUT* LA[0.14] RN8C 2N4401 RN9E RES_ISO5I_1K 2N4401 2N4403 RN8E RES_ISO5I_10K 1N5817 LVDD
(VPP) RN8B
RN9A RES_ISO5I_1K
LEVEL
(NORMAL)
2N4401
IRQ*
HEADER
74HC4040
RES_ISO5I_10K 74HC04
LA[0.14] LOCKOUT*
DECODE SWITCH
INTERNAL* WR-DDRA WR-DDRC WR-PDRA PORTS* WR-ISCR LPO-FREQ DATAOUT-EN*15 DATAIN-EN* TST-RNG LR/W WR-ISCRIN SWITCH OSCBUF* USER_DEFINED_CAP GNDOUT 4MHZ_FS HDR204
DECODE TABLE
CLK-E EPO-FREQ LOCKOUT* LV-OSC1 E-EM LA12 LA11 LA10 CLK-L INTERNAL* SWITCH PORTS* WR-ISCR WR-PDRA WR-DDRA WR-DDRC TST-RNG $0001,0003,0005,0007, $0008-001F $0050 $0000,0002,0004,0006 /LRW $000D /LRW $0010 /LRW $0004 /LRW $0006 $0080-$00FF
74HCU04 USER_DEFINED_RES
IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 CLK1/I5 CLK0/I2 IO23 IO22 IO10 IO21 IO20 IO11 IO12 IO19 IO13 IO18 IO17 IO14 IO15 IO16 MACH215-12JC
LV-OSC1 E-EM AD[0.7]
LV-OSC1 E-EM AD[0.7]
Schematics M68EM05JP7 Schematics
Title M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet CSIC DEVELOPMENT TOOLS
Schematics
M68EM05JP7UM/D
Schematics
MOTOROLA
MOTOROLA Schematics
M68EM05JP7UM/D
PA[0.5] TO/FROM PA[0.5] PDICH PDICL PDICH PDICL DDRA0 WR-PDRA LOCKOUT* WR-DDRA AD[0.7]
M68EM05JP7 Schematics (Sheet
<-INPUT PATH DDRA0 DDRA1 DDRA2 74HC4053 74HC4053 DDRA[0.5] DDRA3 PAPULL[0.5] TGT-PA[0.5] PA[0.5] U15A U15B 74HCT32 U15C 74HCT32 AD[7.0] 74HCT32 Title M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet PA-IRQ CSIC DEVELOPMENT TOOLS PA-IRQ SWPDI SWPDI XU17 DDRA2 PAPULL2 PAPULL5 TGT-PA2 TGT-PA5 SWPDI TGT-PA4 TGT-PA1 PAPULL4 PAPULL1 LVDD-1 U27A 74HC4066 LVDD-1 DDRA1 DDRA0 RN6E RN5C RES_ISO5I_47K TGT-PA0 TGT-PA1 TO/FROM TARGET TGT-PA2 LVDD-1 U26A 74HC4066 LVDD-1 TGT-PA3 TGT-PA4 TGT-PA5 DDRA4 LVDD-1 U26C 74HC4066 LVDD-1 DDRA5 RN5A RES_ISO5I_47K PAPULL4 PAPULL5 TGT-PA[0.5] RN6A RES_ISO5I_1K U26B 74HC4066 RN6B RES_ISO5I_1K RN5B RES_ISO5I_47K TGT-PA5
TGT-PA4
DDRA3 DDRA4 DDRA5
RN6C RES_ISO5I_1K U26D 74HC4066 RN6D RES_ISO5I_1K
TGT-PA3
TGT-PA2
PORT HIGH CURRENT
RN5D RES_ISO5I_47K PAPULL2 PAPULL3 TGT-PA1
DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 WR-PDRA LOCKOUT* WR-DDRA TGT-PA3 TGT-PA0 PAPULL3 PAPULL0
IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 CLK1/I5 CLK0/I2 IO23 IO22 IO10 IO21 IO11 IO20 IO12 IO19 IO13 IO18 IO14 IO17 IO15 IO16 MACH215-12JC
RES_ISO5I_1K U27B RN9B 74HC4066 RES_ISO5I_1K RN5E RES_ISO5I_47K
TGT-PA0
RN2E RES_ISO5I_47K
SWPDI MASK OPTION
HDR103 ENABLE INHIBIT
PAPULL0 PAPULL1
Schematics M68EM05JP7 Schematics
Schematics
M68EM05JP7UM/D
Schematics
MOTOROLA
MOTOROLA Schematics
M68EM05JP7UM/D
AD[0.7] AD[0.7] WR-DDRC LOCKOUT* WR-DDRC LOCKOUT* SWPDI PDICL SWPDI PDICL PDICH PDICH
M68EM05JP7 Schematics (Sheet
TGT-PC[0.7]
RN2D RN2C RN2B RES_ISO5I_47K
PORT PULLDOWN
RN2A RES_ISO5I_47K
TGT-PC0 TGT-PC1 TGT-PC2
RES_ISO5I_47K TGT-PC3 RES_ISO5I_47K
RES_BUS9_10K 234567890
74HC125
74HC125
74HC125
74HC125
DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRC7
74HCT273
74HC244
74HC125
74HC125
74HC125
U16A 74HC32 U16B
74HC125
74HC32 RN1A RN1B RN1C
RN1D
TGT-PC4
RES_ISO5I_47K TGT-PC5
RES_ISO5I_47K TGT-PC6 TGT-PC7
RES_ISO5I_47K
RES_ISO5I_47K
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet
Schematics
M68EM05JP7UM/D
Schematics
MOTOROLA
MOTOROLA Schematics
M68EM05JP7UM/D
MCUAD[0.7] DATAOUT-EN* 4.7K MMDS-RESET* 2N4401 MCU-RESET* COP-RESET* DATAIN-EN* RN4A RES_ISO5I_10K TO/FROM MMDS T-RST* T-RST*
M68EM05JP7 Schematics (Sheet
ADDRESS/DATA CONVERSION
MCUAD[0.7] DATAOUT-EN* AD[0.7] DATA MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 MCUAD7 MCUAD6 MCUAD5 MCUAD4 MCUAD3 MCUAD2 MCUAD1 MCUAD0 LVDD V_REG LV_74AC541 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 AD[0.7] 2,3,4,5,6
RESET CIRCUIT
RN7C RES_ISO5I_10K
RN7D RES_ISO5I_10K
LVDD
74ACT541
LV_74HC4050
LVDD OSC1 PA-IRQ LVDD-1 74HC04 OSCBUF PA-IRQ
1N5817
LV_74HC4050
DATA <-DATAIN-EN RN4B RES_ISO5I_10K 2N4401 2N4401 74HC4053 RN4C RES_ISO5I_10K RN4D RES_ISO5I_10K 1N5817 TO/FROM TARGET T-RESET* RN4E RES_ISO5I_10K LVDD-1 LV-PA-IRQ LV-OSC2 LV-OSC1 TOSC2
LV-PA-IRQ LV-OSC2 LV-OSC1
TGT-RESET LEVEL CONVERSION
GND-1
Schematics M68EM05JP7 Schematics
CSIC DEVELOPMENT TOOLS Title M68EM05JP7 EMULATION MODULE Size Document Number 63BSE90840W Date: 1996 Sheet
Schematics
M68EM05JP7UM/D
Schematics
MOTOROLA
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 20912; Phoenix, Arizona 85036.1-800-441-2447 602-303-5454 MFAX: RMFAX0@email.sps.mot.com TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298
M68EM05JP7UM/D
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