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M68332EVK EVALUATION USER'S MANUAL MOTOROLA, INC., 1991, 1993; Ri


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M68332EVK/D October 1993
M68332EVK EVALUATION USER'S MANUAL
MOTOROLA, INC., 1991, 1993; Rights Reserved
Motorola reserves right make changes without further notice products herein improve reliability, function design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
CPU32Bug trademark Motorola Inc. White Knight trademark FreeSoft Company. MacTerminal, Apple, Macintosh trademarks Apple Computer, Inc. IBM-PC registered trademark International Business Machines Corporation. ProComm trademark Datastorm Technologies,Inc.
computer program stored Read Only Memory device contains material copyrighted Motorola Inc., first published 1991, used only under license such License Computer Programs (Article contained Motorola's Terms Conditions Sale, Rev. 1/79.
TABLE CONTENTS
TABLE CONTENTS
CHAPTER GENERAL INFORMATION Introduction. Features. Specifications. General Description Equipment Required CHAPTER HARDWARE PREPARATION INSTALLATION Introduction. Unpacking Instructions. Hardware Preparation 2.3.1 Configuration 2.3.1.1 VSTBY Select Header (J1) 2.3.1.2 Chip Enable Select Header (J2). 2.3.1.3 EPROM Chip Select Header (J3). 2.3.1.4 Select Header (J4) 2.3.1.5 Select Header (J5). 2.3.1.6 Clock Input Select Header (J6). 2.3.2 Configuration 2-11 2.3.2.1 Enable Header (J1). 2-13 2.3.2.2 Enable Header (J2) 2-14 2.3.2.3 Enable Header (J3) 2-15 2.3.2.4 RAM/EPROM Select Header (J4). 2-16 2.3.2.5 EPROM Select Header (J5). 2-17 2.3.2.6 EPROM Select Header (J6). 2-18 2.3.2.7 RAM/EPROM Select Header (J7). 2-19 2.3.2.8 Revision Level Select Headers J13). 2-20 2.3.2.9 IFETCH Select Header (J14). 2-21 2.3.2.10 VSTBY Battery Backup Connector (P10) 2-23 2.3.2.11 Coprocessor Socket (U5). 2-23 Installation Instructions 2-24 2.4.1 Interconnection. 2-24 2.4.2 Target System Interconnection. 2-25 2.4.3 Power Supply Connection. 2-28 2.4.4 Terminal Connection. 2-29 2.4.5 Terminal Connection. 2-31 2.4.6 Logic Analyzer Connection 2-33
M68332EVK/D
MOTOROLA
TABLE CONTENTS
CHAPTER OPERATING INSTRUCTIONS Introduction. General Information. Control Switches. Limitations. 3.4.1 Chip Select Usage 3.4.2 Other Resources Used CPU32Bug. Operating Procedure Monitor Description. 3.6.1 Memory Register Display Modification Commands. 3.6.2 Breakpoint Capabilities 3.6.3 System Calls 3-10 3.6.4 Diagnostic Monitor. 3-12 Assembling/Disassembling Procedures. 3-14 Downloading Procedures. 3-18 3.8.1 Apple Macintosh (with MacTerminal) EVK. 3-19 3.8.2 Apple Macintosh (with White Knight) 3-21 3.8.3 IBM-PC (with KERMIT) EVK. 3-22 3.8.4 IBM-PC (with PROCOMM) EVK. 3-23 CHAPTER FUNCTIONAL DESCRIPTION Introduction. Description Description. 4.3.1 Summary 4.3.1.1 32-Bit Central Processor Unit 4.3.1.2 Time Processor Unit. 4.3.1.3 Queued Serial Module. 4.3.1.4 Random Access Memory 4.3.1.5 External Interface 4.3.1.6 Chip Selects. 4.3.1.7 System Clock. 4.3.1.8 Test Module. 4.3.2 User Memory. 4.3.3 Connectors 4.3.3.1 64-Pin Expansion Connectors 4.3.3.2 Serial Communication Connectors. 4.3.3.3 Background Mode Interface Connector Description 4.4.1 Floating-Point Coprocessor Socket (U5) 4.4.2 Logic Analyzer Connectors.
M68332EVK/D
MOTOROLA
TABLE CONTENTS
CHAPTER SUPPORT INFORMATION Introduction. Connector Signal Descriptions APPENDIX S-RECORD INFORMATION
LIST ILLUSTRATIONS
Figure Page
M68332EVK Evaluation Jumper Header Connector Location Diagram Jumper Header Connector Location Diagram 2-12 Expansion Connector Assignments. 2-26 Target System Connector Dimension Requirements. 2-27 Terminal/PC Cable Diagram 2-30 Terminal/PC Cable Diagram 2-32 Block Diagram. Block Diagram. Memory
M68332EVK/D
MOTOROLA
TABLE CONTENTS
LIST TABLES
Table 5-10 5-11 5-12 5-13 Page
Specifications. Specifications External Equipment Requirements Socket Memory Device Compatibility 2-11 BCC/PFB Compatibility. 2-24 Control Switches Rev. Chip Selection Summary. Rev. Chip Selection Summary Rev. Chip Selection Summary CPU32Bug Exception Vectors Connector Descriptions Expansion Connector Assignments Expansion Connector Assignments Background Mode Connector Assignments Connector Assignments Logic Analyzer Connector Assignments Logic Analyzer Connector Assignments 5-10 Logic Analyzer Connector Assignments 5-10 Logic Analyzer Connector Assignments 5-11 Logic Analyzer Connector Assignments 5-13 Logic Analyzer Connector Assignments 5-15 Connector Assignments 5-16 Connector Assignments 5-17
M68332EVK/D
MOTOROLA
GENERAL INFORMATION
CHAPTER GENERAL INFORMATION INTRODUCTION
This manual provides general information, hardware preparation, installation instructions, functional description, support information M68332EVK Evaluation (hereafter referred EVK). Appendix contains downloading S-record information. consists printed circuit boards software program: M68332BCC Business Card Computer (BCC) M68300PFB Platform Board (PFB) CPU32BUG Debug Monitor (CPU32Bug)
FEATURES
consists MC68332 Microcontroller Unit (MCU) bit, erasable programmable read only memories (EPROMs). Programmed into EPROMs M68CPU32BUG Debug Monitor. Refer M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. bit, byte addressable random access memory (RAM) RS-232C compatible terminal/host computer input/output (I/O) port Background mode interface port expansion connectors
consists expansion connectors M68300DI Development Interface External power supply connector RS-232C compatible terminal/host computer ports Background mode interface port Memory expansion sockets Socket MC68881 MC68882 Coprocessor Logic analyzer interface
M68332EVK/D
MOTOROLA
GENERAL INFORMATION
CPU32Bug includes: Commands display modification memory Breakpoint capabilities assembler/disassembler useful patching programs power-up self test feature which verifies system integrity command-driven user-interactive software debugger (the debugger) user interface which accepts commands from system console terminal parameter area user customization CPU32Bug described detail M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1.
SPECIFICATIONS
Tables list specifications.
Table 1-1. Specifications
CHARACTERISTICS Internal Clock External Clock Memory EPROM SPECIFICATIONS 32.768 kHz(1) 85ns clock cycle access 16.7 MHz) 200ns clock cycle access 16.7 MHz) RS-232C compatible (with internal DC-DC converters +/-10 volts, +25° +85° (non-condensing) milliamps (min.) microamps (min.) 2.25 3.875 (5.7 9.84
Terminal/Host Port Temperature Operating Storage Relative humidity Power Requirements Power Supply Battery Backup Dimensions
optional high frequency clock source high 16.77 MHz) used MODCK (P2, pulled logic level. hybrid oscillator recommended external clock.
M68332EVK/D
MOTOROLA
GENERAL INFORMATION
Table 1-2. Specifications
CHARACTERISTICS External Clock SPECIFICATIONS
Expanded Memory Sockets 25ns clock cycle access (U1, 16.7 MHz) 85ns clock cycle access 16.7 MHz) EPROM EPROM Terminal/Host Ports Temperature Operating Storage Relative humidity Power Requirements Power Supply Battery Backup Dimensions 200ns clock cycle access 16.7 MHz) 200ns clock cycle access 16.7 MHz) RS-232C compatible +25° +85° (non-condensing) milliamps (min.) microamps (min.) 6.25 (15.88 25.4
M68332EVK/D
MOTOROLA
GENERAL INFORMATION
GENERAL DESCRIPTION
Using EVK, user design, debug, evaluate MC68332 MCU-based target systems. simplifies user evaluation prototype hardware/software products. requires user-supplied power supply RS-232C compatible terminal functional operation. consists printed circuit boards, PFB. operates single board computer, well-defined core larger applications. Mounted microcontroller, on-board memory, serial level converter circuitry. also 4-pin connector serial communication. 64-pin expansion connectors provide access most MC68332 pins. physical location installing Development Interface (DI). user also expand user accessible memory installing EPROM sockets PFB. RAM/EPROM sockets configured autoboot. terminal ports communicating with from host computer terminal. also power connector. Chapter connector pin-outs Chapter interface connector assignments signal descriptions. M68CPU32BUG Debug Monitor (CPU32Bug) stored EPROMs. CPU32Bug software evaluation debug tool that used develop systems built around MCU. Using debug monitor, user interacts with through monitor commands that entered terminal/host computer keyboard. These commands perform functions such modification memory, modification internal registers, program execution under various levels control, access various peripherals itself. User programs downloaded into PFB. detailed description CPU32Bug refer M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. program EPROMs must remove EPROMs EPROM programmer.
M68332EVK/D
MOTOROLA
GENERAL INFORMATION
EQUIPMENT REQUIRED
Table lists external equipment requirements operation.
Table 1-3. External Equipment Requirements
EXTERNAL EQUIPMENT terminal host computer (RS-232C compatible) with terminal emulation package (PCKERMIT, PROCOMM, MacTerminal, White Knight, etc.)(1) Serial communication cable terminal host computer(2). power supply(2)
Refer Chapter details downloading using host computer with terminal emulation package. Refer Chapter details.
M68332EVK/D
MOTOROLA
GENERAL INFORMATION
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
CHAPTER HARDWARE PREPARATION INSTALLATION INTRODUCTION
This chapter provides unpacking instructions, hardware preparation, installation instructions EVK. This description ensures properly configured target system operation.
UNPACKING INSTRUCTIONS
Unpack from shipping carton. Refer packing list verify that items present. Save packing material storing shipping BCC.
NOTE product arrives damaged, save packing material, contact carrier's agent.
HARDWARE PREPARATION
been factory tested shipped with installed jumpers. user reposition these jumpers when application requires customization functionality. There also several connectors EVK. These connectors provide power, communication, access features. Figure shows installation PFB, expansion connectors. Figures show locations switches, jumpers connectors boards.
CAUTION caution when handling EVK; signals buffered sensitive static discharge.
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
MC68332 EPROM
RS-232C Connector Background Mode Connector
M68332BCC
Optional EPROM Optional
Connectors
RS-232C (DI) Connector RS-232C (BCC) Connector
Connectors
M68300PFB
Figure 2-1. M68332EVK Evaluation
There EPROM BCC. located under EPROM U2). access RAM, remove EPROM from sockets. caution when removing installing EPROM.
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1
Configuration
factory tested shipped with installed jumpers. user reposition these jumpers customize functionality. Refer Figure location jumper headers. CAUTION Depending application, necessary wiring trace shorts (cut-trace shorts) PCB. careful adjacent wiring traces.
64-Pin Expansion Connector Background Mode Connector Clock Input Select 64-Pin Expansion Connector Select Select RS-232C Serial Communication VSTBY Select Chip Select EPROM Chip Select
Figure 2-2. Jumper Header Connector Location Diagram
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1.1
VSTBY Select Header (J1)
two-pin jumper header (shown below) select voltage standby (VSTBY) power supply source. VSTBY provides battery backup contained MC68332 device. shipped from factory with VSTBY connected ground (GND) cut-trace short. power VSTBY with external supply, trace bottom connect external power supply between ground pin. Refer schematic diagram more detail VSTBY signal wiring.
64-Pin Expansion Connector Fabricated Jumper
VSTBY
VSTBY MC68332
NOTE cut-trace short jumper header cut, user-supplied fabricated jumper must installed return default setting.
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1.2
Chip Enable Select Header (J2)
three-pin jumper header (shown below) enable/disable selection on-board RAM. shipped from factory with chip select connected cut-trace short bottom between pins fabricated jumper also installed between pins cut-trace short fabricated jumper between pins enables on-board RAM.
BR/CS0 BGACK/CS2 BG/CS1
MCM6206
MCM6206
Fabricated Jumper
disable from memory map, trace solder side board between pins move fabricated jumper pins This jumper disables selection on-board connecting chip enable +5V. chip selects free other uses. Refer schematic diagram more detail chip select signal wiring. CAUTION connect jumper between pins before removing cut-trace short between pins Installing jumper before cut-trace short removed connects +5Vdc ground. +5Vdc shorted ground power supply damaged. NOTE cut-trace short jumper header cut, fabricated jumper must reinstalled pins return default setting.
M68332EVK/D MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1.3
EPROM Chip Select Header (J3)
When power applied reset occurs, MC68332 device resets itself downloads program EPROM U2). EPROM contains boot program. three-pin jumper header (shown below) disable on-board EPROM. shipped from factory with EPROM connected bootstrap chip select (CSBOOT cut-trace short bottom between pins fabricated jumper also installed between pins boot from program stored memory located target system, this trace, move jumper pins connect CSBOOT target system Cutting cut-trace short moving fabricated jumper pins removes from memory map. Refer schematic diagram more detail CSBOOT signal wiring.
Fabricated Jumper CSBOOT MC68332 64-Pin Expansion Connector 27C512 27C512 OE/VPP OE/VPP
CAUTION connect jumper between pins before removing cut-trace short between pins Installing jumper before cut-trace short removed connects +5Vdc (CSBOOT +5Vdc shorted (CSBOOT damaged. NOTE cut-trace short jumper header cut, fabricated jumper must reinstalled pins return default setting.
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1.4
Select Header (J4)
Jumper header allows user disconnect transmit serial data MC68332 device (U5) from RS-232C receiver/driver (U6) target system receiver/driver. shipped from factory with receiver/driver connected (pin cut-trace short bottom between pins (shown below). fabricated jumper also installed pins disconnect serial MCU, this trace remove jumper.
64-Pin Expansion Connector MC68332 64-Pin Expansion Connector Fabricated Jumper
MC145407
NOTE cut-trace short jumper header cut, fabricated jumper must reinstalled return default setting.
Refer schematic diagram more detail signal wiring.
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1.5
Select Header (J5)
Jumper header allows user disconnect receive serial data MC68332 device (U5) from RS-232C receiver/driver (U6) target system receiver/driver. shipped from factory with receiver/driver connected cut-trace short bottom between pins (shown below). fabricated jumper also installed pins disconnect MCU, this trace remove jumper.
64-Pin Expansion Connector MC68332 64-Pin Expansion Connector Fabricated Jumper
MC145407
NOTE cut-trace short jumper header cut, fabricated jumper must reinstalled return default setting.
Refer schematic diagram more detail signal wiring.
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.1.6
Clock Input Select Header (J6)
three-pin jumper header (shown below) select on-board clock source external clock source. on-board clock source crystal, which frequency multiplied MC68332 programmable operating frequency. shipped with on-board crystal selected clock source. cut-trace short bottom between pins fabricated jumper also supplied, required when user uses on-board clock source. Refer schematic diagram more detail EXTAL signal wiring.
On-Board Oscillator
XTAL EXTAL MC68332
Fabricated Jumper
EXTAL
64-Pin Expansion Connector
M68332EVK/D
MOTOROLA
HARDWARE PREPARATION INSTALLATION
optional high frequency oscillator 16.77 MHz) used MODCK (connector pulled logic level. target-system, external-source CMOS clock; follow these steps: Turn power BCC. printed circuit trace bottom between pins Move fabricated jumper between pins pins Supply external oscillator connector (EXTAL). Ground connector (MODCK). Apply power BCC, start external oscillator, drive connector (RESET), low.
NOTES cut-trace short jumper header cut, fabricated jumper must reinstalled pins return default setting.
hybrid oscillator when driving from external source.
change MC68332 device clock speed causes corresponding change baud rate. operational speed determined clock synthesizer control register value (SYNCR). baud rate then based this system clock frequency. changes made speed terminal baud rate changed appropriately, terminal communication will fail. Refer Appendix M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1.
M68332EVK/D
2-10
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2
Configuration
This section manual describes inspection preparation PFB. factory tested shipped with installed jumpers. user reposition these jumpers customize functionality. There several connectors associated with PFB. Through these connectors power, communicate with, access available features. Figure shows locations switches, jumpers connectors PFB. shipped from factory with M68332BCC Business Card Computer (BCC) installed expansion connectors. Configure desired mode operation paragraphs 2.4.1 2.4.2. remove BCC, take care fully reinsert when installing back PFB. contains ABORT RESET switches, power connector, battery backup connector, jumpers (see Figure 2-1). pairs I.C. sockets (U1/U2, U3/U4) user-supplied memory devices (RAM EPROM). table below RAM/EPROM capabilities. EPROM installed PFB, used instead on-board EPROM. expands onboard RAM. jumper headers must configured utilize user installed EPROM. configure these jumpers, follow instructions paragraphs that follow.
Table 2-1. Socket Memory Device Compatibility
SOCKET U1/U3 U2/U4 MEMORY DEVICE bytes socket bytes socket, bytes EPROM socket, bytes EPROM socket
M68332EVK/D
2-11
MOTOROLA
HARDWARE PREPARATION INSTALLATION
RS-232C CONNECTOR POWER SUPPLY CONNECTOR RS-232C CONNECTOR
RAM/EPROM SELECT HEADER EPROM SELECT HEADER RAM/EPROM SELECT HEADER COPROCESSOR SOCKET LOGIC ANALYZER CONNECTORS
ENABLE HEADER
ENABLE HEADER REVISION LEVEL SELECT HEADERS ENABLE HEADER
EPROM SELECT HEADER
BCC-P1 BCC-P2 BCCDI-P1 BCCDI-P2
VOLTAGE STANDBY (VSTBY) CONNECTOR
64-PIN EXPANSION HEADER CONNECTOR BACKGROUND MODE CONNECTOR
64-PIN EXPANSION HEADER CONNECTOR
IFETCH SELECT HEADER
Figure 2-3. Jumper Header Connector Location Diagram
M68332EVK/D
2-12
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.1
Enable Header (J1)
Sockets user-supplied RAM. jumper header enable this additional memory. shipped from factory with jumper installed pins disabled (shown below). enable sockets move fabricated jumper pins Refer schematic diagram more detail enable select signal wiring.
A23/CS10
A21/CS8 A22/CS9
FABRICATED JUMPER
60L256
60L256
/CS10 /CS8 /CS9 default signals. Jumpers J12, J13, respectively, select alternates.
M68332EVK/D
2-13
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.2
Enable Header (J2)
user install user-supplied byte RAM, byte EPROM, byte EPROM socket jumper header select between CSBOOT chip selects memory device installed shipped from factory with jumper installed pins (shown below). install EPROM desire program execute during reset power-up, place fabricated jumper across pins disable EPROM (refer paragraph 2.3.1.4). Jumper headers must configured same EPROMs installed locations Refer schematic diagram more detail chip enable signal wiring.
FABRICATED JUMPER
60L256
CSBOOT
default signals. Jumpers J11, respectively, select alternates.
M68332EVK/D
2-14
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.3
Enable Header (J3)
user install user-supplied byte RAM, byte EPROM, byte EPROM socket jumper header select between CSBOOT chip selects memory device installed shipped from factory with jumper installed pins (shown below). install EPROM desire program execute during reset power-up, place fabricated jumper across pins disable EPROM (refer paragraph 2.3.1.4). Jumper headers must configured same EPROMs installed locations Refer schematic diagram more detail chip enable signal wiring.
FABRICATED JUMPER
60L256
CSBOOT
default signals. Jumpers J10, respectively, select alternates.
M68332EVK/D
2-15
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.4
RAM/EPROM Select Header (J4)
jumper header select EPROM memory device type. shipped from factory with fabricated jumpers installed pins pins (shown below). This correct installed When EPROM installed place jumpers pins pins (refer paragraph 2.3.2.5). Refer schematic diagram more detail RAM/EPROM type select signal wiring.
60L256
FABRICATED JUMPERS
EPROM SELECT JUMPER HEADER
default signal. Jumpers select alternate.
M68332EVK/D
2-16
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.5
EPROM Select Header (J5)
jumper header (shown below) when EPROM installed types EPROM used: 27C256 27C512. 27C256, install fabricated jumper between pins 27C512, install jumper between pins Paragraph 2.3.2.4 explains jumper header configuration match memory device location Locations must have same type memory devices; either both both EPROM. Refer schematic diagram more detail EPROM type selection signal wiring.
FABRICATED JUMPERS
60L256
JUMPER EPROM 27C256 27C512
Above diagram shows EPROM select mode. default signal. Jumpers select alternate.
M68332EVK/D
2-17
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.6
EPROM Select Header (J6)
jumper header (shown below) when EPROM installed types EPROM used: 27C256 27C512. 27C256, install fabricated jumper between pins 27C512, install fabricated jumper between pins Paragraph 2.3.2.7 explains jumper header configuration match memory device location Locations must have same type memory devices; either both both EPROM. Refer schematic diagram more detail EPROM type selection signal wiring.
FABRICATED JUMPERS
60L256
JUMPER EPROM 27C256 27C512
Above diagram shows EPROM select mode. default signal. Jumpers select alternate.
M68332EVK/D
2-18
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.7
RAM/EPROM Select Header (J7)
jumper header select EPROM memory device type. shipped from factory with fabricated jumpers installed pins pins (shown below). This correct installed When EPROM installed place jumpers pins pins (refer paragraph 2.3.2.6). Refer schematic diagram more detail RAM/EPROM type select signal wiring.
60L256
FABRICATED JUMPERS
EPROM SELECT JUMPER HEADER
default signal. Jumpers select alternate.
M68332EVK/D
2-19
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.8
Revision Level Select Headers J13)
Jumpers through (shown below) configure either revision BCC. shipped from factory configured operation with revision cut-trace shorts between pins J13. configure function with revision BCC, traces between pins place fabricated jumpers between pins J13. fabricated jumpers traces must same state, either between pins Refer schematic diagram more detail revision level signal wiring.
NOTE cut-trace shorts jumper headers through cut, user-supplied fabricated jumpers must installed through (pins return factory setting.
M68332EVK/D
2-20
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.9
IFETCH Select Header (J14)
jumper header (shown below) select latched IFETCH IFETCH signal. shipped from factory with fabricated jumpers installed between pins J14; this routes IFETCH directly from MC68332 logic analyzer connector, When jumper installed pins latched IFETCH signal routed logic analyzer connector, Refer schematic diagram more detail IFETCH signal wiring.
74AC10 CLKOUT
74AC10
IFETCH/DSI
FABRICATED JUMPER
74AC74
74AC10
LOGIC ANALYZER CONNECTOR
IFETCH
M68332EVK/D
2-21
MOTOROLA
HARDWARE PREPARATION INSTALLATION
Latched IFETCH active high signal (opposite IFETCH that signals logic analyzer decode instruction from data bus. signal characteristics are: When IFETCH goes low, latched IFETCH goes high rising edge CLKOUT (beginning S2). Latched IFETCH goes (inactive) nanoseconds after address strobe goes high. timing diagram these signals
CLKOUT
IFETCH
LATCHED IFETCH
M68332EVK/D
2-22
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.3.2.10
VSTBY Battery Backup Connector (P10)
maintain memory during power-down, trace solder side jumper header (per paragraph 2.3.1.1). Then attach user supplied battery external power supply PFB. This provides required voltage preserve data static portion Refer schematic diagram more detail VSTBY signal wiring.
Volt Battery Backup
64-Pin Expansion Connector
VSTBY MC68332 VSTBY
2.3.2.11
Coprocessor Socket (U5)
68-pin gate array (PGA) socket (U5) installing user-supplied MC68881 MC68882 floating point coprocessor, floating point instructions execute concurrently with integer instructions. Execution floating point instructions requires user supplied interface routines. Addition floating-point coprocessor substantially decreases processor instruction execution time floating-point arithmetic.
M68332EVK/D 2-23 MOTOROLA
HARDWARE PREPARATION INSTALLATION
INSTALLATION INSTRUCTIONS
following paragraphs describe interconnections, expansion connector assignments, target system dimensions, power supply interconnections, serial communication connector cable, logic analyzer connectors. 2.4.1 Interconnection
interconnection mounts (shown below). This configuration standalone configuration. used evaluate verify functionality user developed code. this configuration match BCC-P1 BCC-P2. Figure illustrates expansion header assignments PFB. Table shows revision level compatibility between PFB.
M68300PFB
M68332BCC
Interconnection
Table 2-2. BCC/PFB Compatibility
REV. Level REV. Level
M68332EVK/D
2-24
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.4.2
Target System Interconnection
target-system-to-BCC interconnection mounts target system shown below. this configuration evaluate your hardware design. 64-pin expansion connectors provide access most MC68332 device pins. Figure illustrates expansion header assignments BCC. Figure shows physical dimension requirements installing target system.
M68332BCC
Connectors Target System
Target System Interconnection
M68332EVK/D
2-25
MOTOROLA
HARDWARE PREPARATION INSTALLATION
13-24V 13-24V TP11 S0/SS BKPT /DSC RESET IPIPE/D T2CLK TP14 TP12 TP10 MISO FREEZE/Q IFET CH/DSI
A23/CS10 A21/CS8 A19/CS6 1/CS4 BGAC K/CS2 BR/CS0 BERR DSACK1 CLKOUT HALT
CSBOOT ME/TSC
A22/CS9 A20/CS7 FC2/CS5 FC0/CS3 BG/CS1 IRQ1 IRQ3 IRQ5 IRQ7 DSACK0 AVEC
ESET
EXTAL
Figure 2-4. Expansion Connector Assignments
M68332EVK/D
2-26
MOTOROLA
HARDWARE PREPARATION INSTALLATION
.100 (2.54
(7.87
(5.08 VIEW:
Figure 2-5. Target System Connector Dimension Requirements
M68332EVK/D
2-27
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.4.3
Power Supply Connection
requires milliamps power supply operation. connector connect power EVK. Contact ground; black lever. Contact volts); lever. wire power connections. each wire, trim back insulation (.635 cm), lift appropriate lever release tension contacts, then insert bare wire into close lever.
CAUTION wire larger than connector Such wire could damage connector.
Turn power when installing removing from PFB. Sudden power surges could damage integrated circuits.
M68332EVK/D
2-28
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.4.4
Terminal Connection
9-pin serial ports connection terminal host computer (with terminal emulation). communicate with from terminal host computer. used with EVK. connect RS-232C compatible terminal host computer, user-supplied cable assembly, shown Figure 2-6. Connect cable assembly connector (shown below). Connect other cable assembly user-supplied terminal host computer. Refer Chapter connector assignments signal descriptions connector
Terminal/PC Port
M68332EVK/D
2-29
MOTOROLA
HARDWARE PREPARATION INSTALLATION
IBM-PC/ TERMINAL SERIAL PORT NOTE
DP-9 MALE
Some serial communication cards require CTS, DSR, DTR, shorted together before they will function properly with EVK. Make this modification side cable.
(DB-25)
Figure 2-6. Terminal/PC Cable Diagram
M68332EVK/D
2-30
MOTOROLA
HARDWARE PREPARATION INSTALLATION
2.4.5
Terminal Connection
4-pin serial port (P4) connection terminal host computer (with terminal emulation). communicate with from terminal host computer. connect RS-232C compatible terminal host computer, user-supplied cable assembly, shown Figure 2-7. Connect cable assembly connector (shown below). Connect other cable assembly user-supplied terminal host computer. Refer Chapter connector assignments signal descriptions connector
XMIT
Terminal/PC Port
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IBM-PC/ TERMINAL SERIAL PORT
NOTE Some serial communication cards require CTS, DSR, DTR, shorted together before they will function properly with EVK. Make this modification side cable.
(DB-25)
Figure 2-7. Terminal/PC Cable Diagram
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2.4.6
Logic Analyzer Connection
logic analyzer connected PFB, debugging target system hardware software. Logic analyzer connector assignments shown below. connectors signal descriptions, refer Chapter
T2CLK TP14 TP12 TP10
TP15 TP13 TP11
DSACK1
DSACK0 BG/CS1 CLKOUT A22/CS9 EB1* CLKOUT
AVEC BR/CS0 CSBOOT A23/CS10 A21/CS8 A19/CS6
CLKOUT BKPT/DSCLK RESET IPIPE/DSO DSACK1 FC2/CS5 FC0/CS3 SIZ0 BGACK/CS2
BERR FREEZE/QUOT HALT IFETCH DSACK0 FC1/CS4 SIZ1
IRQ1 IRQ3 IRQ5 IRQ7 PCS0/SS PCS2 MOSI
MODCK IRQ2 IRQ4 IRQ6 PCS1 PCS3 MISO
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CHAPTER OPERATING INSTRUCTIONS INTRODUCTION
This chapter provides general information, control switch descriptions, limitations, operating procedure, monitor description debug monitor (CPU32Bug). assembling/disassembling downloading procedures also provided. This information this order: General information Control switch descriptions Limitations Operating procedure Monitor description Assembling/disassembling procedures Downloading procedures
factory tested target system evaluation. monitor resident firmware (CPU32Bug) EVK, which provides self-contained operating environment. monitor interacts with user through commands entered terminal. These commands perform functions such memory display modification, internal register display modification, program execution under various levels control, control access various peripherals connected EVK.
GENERAL INFORMATION
EPROMs contain M68CPU32BUG debug monitor program (hereafter referred CPU32Bug). CPU32Bug software tool evaluating debugging systems built around MC68332 MCU. CPU32Bug allows loading, debugging, executing user programs. Various CPU32Bug routines that handle I/O, data conversion, timer, string functions available user programs through system calls. detailed description CPU32Bug functions, refer M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1.
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CPU32Bug consists Memory register display modification commands Breakpoint capabilities System calls Diagnostic commands single-line assembler/disassembler parameter area user customization
There modes operation CPU32Bug monitor; debugger mode diagnostic mode. When user debugger directory prompt CPU32Bug> appears, user access debugger commands (refer paragraph 3.5). When user diagnostic mode prompt CPU32Diag> appears, user access diagnostic commands (refer paragraph 3.5.4). These modes also called directories. CPU32Bug command-driven performs various operations response user commands entered keyboard. CPU32Bug executes entered commands; upon completion prompt reappears. However, command entered which causes execution user target code (i.e., GO), control return CPU32Bug. This depends upon user program function. Entering help (HE) command provides list possible commands their structure.
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CONTROL SWITCHES
switches (PFB switches SW2) control reset abort functions. Table lists these switches name, description, function.
Table 3-1. Control Switches
Name RESET Switch (PFB SW1) Description Function reset switch returns known state. Reset causes total initialization equivalent power-up sequence. static variables restored their default states. serial ports reset their default state. breakpoint table cleared. offset registers cleared. target registers invalidated. Input output character queues cleared. On-board devices (timer, serial ports, etc.) reset. reset MC68332 halts, example, after halt monitor fault, user program environment lost (vector table destroyed, etc.). ABORT Switch (PFB SW2) abort switch terminates in-process instructions. When abort switch pressed while running target code, snapshot processor state captured stored target registers. this reason abort appropriate when terminating user program that being debugged. abort regain control program gets caught loop, etc. target stack pointers, etc. help pinpoint malfunctions. Abort generates non-maskable, level-seven interrupt. target registers reflect MC68332 device state time abort displayed terminal screen. breakpoints installed user code removed breakpoint table remains intact. Control then returned user.
LIMITATIONS
CPU32Bug requires these system resources operate properly: several chip selects, level interrupt, periodic interrupt timer (for timer system calls; SYSCALL), system exception vectors.
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3.4.1
Chip Select Usage
MC68332 chip select signals that enable peripheral devices. requires some these chip selects operation making them unavailable user. remove chip selects used BCC, CPU32Bug will operate. addition chip selects employed BCC, other chip selects used elsewhere M68332EVK (refer Tables through 3-4). Depending user's environment, chip selects re-configured alternate function (i.e., address lines). Chip select pins used cannot used their alternate capacities. Although chip select (CS8 Rev. Rev. Rev. BCCs) dedicated ABORT switch, used. Instead chip select decodes interrupt acknowledge (IACK) cycle response level interrupt generated ABORT switch. Refer System Integration Module User's Manual (SIM32UM/AD) more information. When mounted PFB, these chip selects available user. Also RAM/EPROM socket pairs (U1/U3, U2/U4) coprocessor socket populated, chip selects available user.
Table 3-2. Rev. Chip Selection Summary
Signal CSBOOT CS10 Board/Chip U1/U3 <unused> <unused> write enable MSB=UPPER=EVEN cut/jump U3-27 from CS10 required. ABORT push-button autovector CPU32Bug EPROM read/write enable MSB=UPPER=EVEN read/write enable LSB=LOWER=ODD read enable MSB/LSB=BOTH write enable LSB=LOWER=ODD read enable MSB=UPPER=EVEN read enable LSB=LOWER=ODD chip enable MC68881/882 RAM/EPROM RAM/EPROM Description Memory Type
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Table 3-3. Rev. Chip Selection Summary
Signal CSBOOT CS10 Board/Chip U3/U1 <unused> U1/U3 ABORT push-button autovector chip enable MC68881/882. cut/-jump U5-J3 from required. read enable LSB=LOWER=ODD read enable MSB=UPPER=EVEN read enable MSB/LSB=BOTH write enable LSB=LOWER=ODD write enable MSB=UPPER=EVEN RAM/EPROM RAM/EPROM CPU32Bug EPROM write enable MSB=UPPER=EVEN write enable LSB=LOWER=ODD read enable MSB/LSB=BOTH Description Memory Type
Table 3-4. Rev. Chip Selection Summary
Signal CSBOOT CSBOOT CS10 Board/Chip U3/U1 <unused> U1/U3 Description CPU32Bug EPROM MSB=UPPER=EVEN CPU32Bug EPROM LSB=LOWER=ODD write enable MSB=UPPER=EVEN write enable LSB=LOWER=ODD read enable MSB/LSB=BOTH ABORT push-button autovector chip enable MC68881/882. cut/-jump U5-J3 from required. read enable LSB=LOWER=ODD read enable MSB=UPPER=EVEN read enable MSB/LSB=BOTH write enable LSB=LOWER=ODD write enable MSB=UPPER=EVEN Memory Type
RAM/EPROM RAM/EPROM
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3.4.2
Other Resources Used CPU32Bug
Avoid writing value zero port assignment register (PFPAR); such value disables ABORT switch. software watchdog timer disabled write-once register (SYPCR) during power-up reset, software watchdog timer cannot used re-enabled user unless user modifies SYPCR_OR SYPCR_AND parameters. Modification SYPCR_OR SYPCR_AND parameters detailed Appendix M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. monitor uses system exception vectors, they unavailable user. monitor debug exception vectors listed Table 3-5. associated debugger facilities (breakpoints, trace mode, etc.) will operate vector offsets target program vector table changed.
Table 3-5. CPU32Bug Exception Vectors
Vector Number Offset $108 Exception Illegal Trace Level interrupt TRAP User Defined ABORT switch System calls (see Chapter M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1) Timer Trap Calls ($4X) CPU32Bug Commands Instruction breakpoints (Used
change MC68332 device clock speed causes corresponding change baud rate. operational speed determined clock synthesizer control register value (SYNCR) external clock signal applied EXTAL MCU. baud rate then based this system clock frequency. changes made system clock frequency, changes must made customization parameter area (FCRYSTAL FEXTAL) correct baud rate calculated communications CPU32Bug. M68CPU32BUG Debug Monitor User's Manual (M68CPU32BUG/AD1), Appendix details. Additionally, CPU32Bug writes module mapping (MM) module control register (MCR). This configures register block start address $FFF000. write-once bit, user cannot clear move register block memory ($7FF000). user move register block modifying MCR_AND parameter detailed Appendix M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1.
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OPERATING PROCEDURE
Power Reset (POR) occurs when user applies power EVK. This resets user port circuitry, passes processing control monitor program. MC68332 registers their reset state during monitor power-up. input serial format terminal port must configured data bits, stop bit, parity, 9600 baud. terminal then displays this message: CPU32Bug Debugger/Diagnostics Copyright 1991 Motorola Inc. CPU32Bug> Version X.XX
where: X.XX software revision level
After initialization return control monitor, terminal displays prompt "CPU32Bug>" waits response. incorrect response entered, terminal displays "Invalid command" followed prompt "CPU32Bug>". CPU32Bug waits command line input from user terminal. When proper command entered, operation continues basic modes. command causes execution user program, monitor reentered, depending upon desire user. alternate case, command executed under control monitor, system returns waiting condition after command completed. During command execution, additional user input required, depending command function. user commands supported monitor. standard input routine controls operation while user types command line. Command processing begins only after command line been terminated pressing keyboard carriage return <CR> key.
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MONITOR DESCRIPTION
CPU32Bug performs various operations response user commands entered keyboard. When debugger prompt CPU32Bug> appears terminal screen, debugger ready accept commands. command line entered stored internal buffer. Execution begins only after carriage return entered. This lets user correct entry errors using control characters described M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. After debugger executes command returns with CPU32Bug> prompt. However, entered command causes execution user target code, (i.e., GO), then control return debugger. This depends user program function. example, breakpoint specified, control returns debugger when breakpoint encountered during user program execution. user program also returns control debugger means TRAP system call function, .RETURN. Included part CPU32Bug firmware single-line assembler/disassembler function. assembler interactive assembler/editor which source programs saved. Each source line translated into MC68332 machine language code stored line-by-line into memory entered. order display instruction, machine code disassembled instruction mnemonic operands displayed. valid MC68332 instructions supported. CPU32Bug assembler effectively subset M68000 Family Structured Assembler (M68MASM). some limitations compared with M68MASM assembler, such allowing line numbers labels; however, useful tool creating, modifying, debugging MC68332 code.
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3.6.1
Memory Register Display Modification Commands
Various commands available user displaying modifying memory. more information, refer Chapter M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. memory display modification commands are: (block memory fill) fills specified range memory with data pattern. (block memory move) copies contents memory addresses defined <RANGE> another place memory, beginning <ADDR>. (block memory search) searches specified range memory match with user-entered data pattern. (block memory verify) compares specified range memory against data pattern. (memory display) displays contents multiple memory locations. (memory modify) examines changes memory locations. (memory set) writes data memory starting specified address. (register display) displays contents registers. (register modify) examines changes register contents. (register set) writes data specified register. 3.6.2 Breakpoint Capabilities
breakpoint lets user target code instruction address stopping point debugging purposes. Target code execution halts when breakpoint encountered. more information breakpoints, refer Chapter M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. breakpoint commands are: BR/NOBR (breakpoint insert/delete) lets user target code instruction address breakpoint address debugging purposes. direct) starts target code execution ignores breakpoints. temporary breakpoint) sets temporary breakpoint address next instruction, that following current instruction. temporary breakpoint) sets temporary breakpoint current instruction starts target code execution. (trace temporary breakpoint) sets temporary breakpoint specified address traces until encountering breakpoint.
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3.6.3
System Calls
CPU32Bug TRAP handler allows system calls from user programs. system call accesses selected functional routines contained CPU32Bug, including input output routines. TRAP also transfers control CPU32Bug user program. more information system calls, refer Chapter M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. System calls include: .INCHR (input character) reads character from default input port. .INSTAT (input serial port status) checks characters default input port buffer. .INLN (input line (pointer/pointer format)) reads line from default input port. .READSTR (input string (pointer/count format)) reads string characters from default input port into buffer. .READLN (input line (pointer/count format)) reads string characters from default input port. .CHKBRK (check break) returns zero status condition code register break status detected default input port. .OUTCHR (output character) outputs character default output port. .OUTSTR (output string pointer/pointer format) outputs string characters default output port. .OUTLN (output line pointer/pointer format) outputs character strings followed carriage return (<CR>) line feed (<LF>) sequence. .WRITE (output string pointer/count format) formats character strings with count byte outputs string default output port. After formatting, count byte first byte string. .WRITELN (output line pointer/count format) formats character strings with count byte outputs string default output port. After formatting, count byte first byte string. .PCRLF (output carriage return line feed) sends <CR> <LF> sequence default output port. .ERASLN (erase line) erases line present cursor position. .WRITD (output string with data pointer/count format) uses monitor routine which outputs user string containing embedded variable fields. user passes starting address string data stack address containing data which inserted into string. output goes default output port.
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.WRITDLN (output line with data pointer/count format) uses monitor routine which outputs user string containing embedded variable fields. user passes starting address string data stack address containing data which inserted into string. output goes default output port. .SNDBRK (send break) sends break default output port. .TM_INI (timer initialization) initializes MC68331 device periodic interrupt timer. .TM_STR0 (start timer T=0) resets timer zero starts .TM_RD (read timer) reads timer count. .DELAY (timer delay) generates timing delays. .RETURN (return CPU32Bug) returns control CPU32Bug from target program. .BINDEC (convert binary Binary Coded Decimal) calculates equivalent specified binary number. .CHANGEV (parse value) parses value user specified buffer. .STRCMP (compare strings pointer/count format) compares equality returns Boolean flag caller. .MULU32 (multiply 32-bit unsigned integers) multiplies 32-bit unsigned integers returns product stack 32-bit unsigned integer. .DIVU32 (divide 32-bit unsigned integers) divides 32-bit unsigned integers returns quotient stack 32-bit unsigned integer.
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3.6.4
Diagnostic Monitor
diagnostic monitor series self-tests MC68332 device. diagnostic monitor programmed into EPROM. more information diagnostic monitor, refer Chapter M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. diagnostic monitor commands are: (help) displays menu level directory. (self test) executes self-test diagnostics. (switch directories) toggles between CPU32Bug directory CPU32Diag directory. (loop-on-error) loops test point where error detected. (Stop-On-Error) halts test point where error detected. (loop-continue) loops test series tests. (non-verbose)suppresses error messages except PASSED FAILED. (display error counters) displays results particular test. (clear error counters) resets error counters zero. (display pass count) displays number passes loop-continue mode. conclusion each pass, this command also displays other information. (zero pass count) resets pass counter zero. Available utilities are: Write Loop Read Loop Read/Write Loop tests diagnostics tests portion MC68332 MCU: Register Test Instruction Test Address Mode Test Exception Processing Test
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Memory tests verify random access memory that reside PFB: Function Code Start Address Stop Address Data Width March Address Test Walk Test Refresh Test Random Byte Test Program Test Test error test (BERR) tests internal access time-out internal external access time-out error conditions, including: errors when accessing RAM. errors when reading EPROM. errors when accessing optional memory. Internal access time-outs when reading writing from undefined function code/memory location internal MCU. Internal external access time-outs reading writing undefined function code/memory location external MCU.
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ASSEMBLING/DISASSEMBLING PROCEDURES
assembler/disassembler interactive, one-line assembler/editor which source program saved. Each source line converted into machine language code stored memory line-by-line basis time entry. order display instruction, machine code disassembled instruction mnemonic operands displayed. valid opcodes converted assembly language mnemonic. invalid opcodes return Declare Constant Word (DC.W) conversion. memory modify ;di) command lets user create, modify, debug MC68332 code. Assembler input must have exactly space between mnemonic operand. There must space inside operand field. Assembler input must terminated carriage return. comments allowed after instruction input line labels permitted. After each assembler input line, line disassembled user before stepping instruction. line assemble different number bytes than previous one. Branch Higher Same (BHS)/Branch Carry Clear (BCC) mnemonics, disassembly displays mnemonic. Branch Lower (BLO)/Branch Carry (BCS) mnemonics, disassembly displays mnemonic. Branch address offsets automatically calculated assembler, user should input destination address rather than offset value. assembler terminated entering period followed carriage return only entry command input line. Entering carriage return alone input line steps next instruction. following pages describe operate assembler/disassembler creating typical program loop, debugging program using CPU32Bug monitor commands. typical program loop first assembled. Routine examples then illustrate breakpoint, proceed from breakpoint, display modify registers, initiate user program execution.
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Enter periodic interrupt timer (PIT) time-out program starting address $5000:
EXAMPLE PROGRAM
CPU32Bug>MM 5000;DI<CR> 5000 5008 5012 5018 501C 5020 5024 502C 502E 5034 5036 503A MOVE.L #$501C,$78<CR> MOVE.L #$061E0120,$FFFA22<CR> LPSTOP #$2500<CR> BRA.W $5012<CR> MOVEA.W #$5100,A0<CR> MOVEA.W #$510E,A1<CR> BTST.B #$0,$FFFC0C<CR> BEQ.B $5024<CR> MOVE.B (A0)+,$FFFC0F<CR> CMPA.W A0,A1<CR> BNE.W $5024<CR> RTE<CR>
PROGRAM DESCRIPTION Memory modify location $5000 with disassembly option. Set-up level vector table. Initialize PIT. Execute LPSTOP Instruction. Loop Beginning message. message. Check busy. Branch until free. Send message byte. Check message. Branch until done. Return from print routine.
Enter ASCII code output message, TIME-OUT. Each time this message appears when running program, indicates program completed loop. Enter following ASCII code memory location $5100:
CPU32Bug>MS 5100 'PIT TIME-OUT'ODOA<CR>
Memory modify location $5100.
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After entering time-out program display instructions location $5000
EXAMPLE PROGRAM
CPU32Bug>MD 5000;DI<CR> 21FC0000 23FC061E FA22 5012 F80001C0 5018 6000FFF8 501C 307C5100 5020 327C510E 5024 08390000 502C 67F6 CPU32Bug><CR> 502E 13D800FF 5034 B2C8 5036 6600FFEC 503A 4E73 503C 0000FFFF 5040 0000FFFF 5044 0000FFFF 5048 0000FFFF 5000 5008 501C0078 012000FF 2500 MOVE.L MOVE.L LPSTOP.W BRA.W MOVEA.W MOVEA.W BTST.B BEQ.B MOVE.B CMPA.W BNE.W ORI.B ORI.B ORI.B ORI.B
PROGRAM DESCRIPTION Display memory location $5000 with disassembly option.
#$501C,($78).W #$061E0120,($FFFA22).L #$2500 $5012 #$5100,A0 #$510E,A1 #$0,($FFFC0C).L $5024
00FFFC0C
Display next eight instructions.
FC0F (A0)+,(FFFC0F).L A0,A1 $5024 #$FF,D0 #$FF,D0 #$FF,D0 #$FF,D0
message displayed terminal
CPU32Bug>MD 5100<CR> 00005100 5049 5420 5449 4D45
2D4F 5554 0D0A FFFF
TIME-OUT.
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following routines performed preceding program loop: TERMINAL
CPU32Bug>MD 5000;DI<CR> 00005000 21FC0000 501C0078 00005008 23FC061E 012000FF FA22 00005012 F80001C0 2500 00005018 6000FFF8 0000501C 307C5100 00005020 327C510E 00005024 08390000 00FFFC0C 0000502C 67F6 CPU32Bug>MM 500C<CR> 0000500C 0120? 00FF. CPU32Bug>g 5000<CR> Effective address: 00005000 TIME-OUT TIME-OUT TIME-OUT MOVE.L MOVE.L LPSTOP.W BRA.W MOVEA.W MOVEA.W BTST.B BEQ.B
ROUTINE DESCRIPTION Display memory address 5000
#$501C,($78).W #$061E0120, (FFFA22) #$2500 $5012 #$5100,A0 #$510E,A1 #$0,($FFFC0C).L $5024
Modify memory location 500C. Change time-out speed. address 5000 begin execution. Periodic interrupt timer time-out message.
Press ABORT switch terminate loop program.
Exception: ABORT =00005018 =2500=TR:OFF_S_5_. =5=SD =5=SD =0000FC00 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =0000510E =0000510E =00000000 =00000000 =00000000 =00000000 00005018 6000FFF8 BRA.W.W $5012 CPU32Bug>T 1<CR> Trace instruction. =00005018 =2500=TR:OFF_S_5_. =5=SD =5=SD =0000FC00 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =0000510E =0000510E =00000000 =00000000 =00000000 =00000000 00005012 F80001C0 2500 LPSTOP.W #$2500 CPU32Bug>BR 5034<CR> breakpoint 5034. BREAKPOINTS 00005034 CPU32Bug>g 5000<CR> address 5000 begin Effective address: 00005018 Breakpoint =00005034 =2600=TR:OFF_S_6_. =5=SD =5=SD =0000FC00 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00005101 =0000510E =00000000 =00000000 =00000000 =00000000 00005034 B2C8 CMPA.W A0,A1 SSP* =00000000 =00010000 =00000000 =00000000 =00000000 =00010000
SSP*
=00000000 =00010000 =00000000 =00000000 =00000000 =00010000
execution.
SSP* =00000000 =0000FFF8 =00000000 =00000000 =00000000 =0000FFF8
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DOWNLOADING PROCEDURES
Downloading transfers information from host computer EVK, load (LO) command. procedure described below lets user download with personal computer (PC) Apple Macintosh host computer. command moves data S-record format (see Appendix from external host computer user pseudo ROM. Subsections 3.8.1 through 3.8.4 list instructions downloading from Apple Macintosh with MacTerminal Ryder, from IBM-PC with Kermit PROCOMM.
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3.8.1
Apple Macintosh (with MacTerminal)
MacTerminal downloading program serves terminal emulator Apple Macintosh computer. download Motorola S-record file from Apple Macintosh computer EVK, follow these steps: Select these menu terminal settings: Terminal: Mode: Cursor Shape: Line Width: Select: Click Baud rate: Bits Character: Parity: Handshake: Connection: Connection Port: Click Settings Pasting Sending Text: File Transfer Protocol: Settings Saving Lines Top: Click VT100 ANSI Underline Columns Line Auto Repeat 9600 Bits None XOn/XOff Another Computer Modem
Select these menu compatibility settings:
Select these menu file transfer settings: Word Wrap Outgoing Text Text Retain Line Breaks
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Apply power EVK. Press carriage return (<CR>) display applicable monitor prompt. computer displays CPU32Bug> prompt. CPU32Bug>LO (Press <CR> after entering LO.) Enter monitor download command: Operate pull-down File menu, select (choose): Send File dialog select applicable S-record object file. Click Send Motorola S-record file transferred EVK.
NOTE S-record file displayed during file transfer EVK.
underline cursor flashes beeper sounds when S-record finishes downloading. Press carriage return twice return CPU32Bug prompt: <CR> <CR> CPU32Bug>
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3.8.2
Apple Macintosh (with White Knight)
White Knight downloading program serves terminal emulator Apple Macintosh computer. download Motorola S-record file from Apple Macintosh computer EVK, follow these steps: Execute White Knight program. computer program match baud rate (typically): 9600 baud, parity, bits, stop bit, full duplex Apply power EVK. Press computer keyboard carriage return (<CR>) display applicable monitor prompt. Enter monitor download command: CPU32Bug>LO Send File ASCII. dialog select applicable S-record object file. Click Send Motorola S-record file transferred EVK. NOTE S-record file displayed during file transfer EVK. underline cursor flashes beeper sounds when S-record finishes downloading. Press carriage return twice return CPU32Bug prompt: <CR> <CR> CPU32Bug> (Press <CR> after entering LO.)
Operate pull-down File menu, select (choose):
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3.8.3
IBM-PC (with KERMIT)
Before performing IBM-PC operation, ensure that both IBM-PC baud rates 9600, that IBM-PC asynchronous port configured terminal mode operation. asynchronous port hard wired host mode operation cannot re-configured terminal mode operation, null modem (cross-coupled transmit (TxD), receive (RxD), associated handshake lines) required. NOTE IBM-PC connection requires serial communication cable assembly. This cable connected terminal port connector downloading operations. perform IBM-PC downloading procedure: EXAMPLE
C>KERMIT<CR> IBM-PC Kermit-MS VX.XX Type help Kermit-MS>SET BAUD 9600<CR> Kermit-MS>CONNECT<CR>
DESCRIPTION
IBM-PC prompt. Enter Kermit program.
IBM-PC baud rate. Connect IBM-PC EVK.
[Connecting host, type Control-] return <CR> CPU32Bug>LO<CR> (CTRL)]C Kermit-MS>PUSH<CR> Personal Computer Version X.XX (C)Copyright Corp. 1981, 1982, 1983 C>TYPE (File Name) COM1<CR> C>EXIT<CR> Kermit-MS>CONNECT<CR> Motorola S-record file name. S-record downloading completed. Return monitor program.
download port) entered.
command (via terminal
underline cursor flashes beeper sounds when S-record finishes downloading. Press carriage return twice return CPU32Bug prompt.
<CR> <CR> CPU32Bug> CPU32Bug>(CTRL) KERMIT-MS>EXIT<CR> Exit Kermit program.
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3.8.4
IBM-PC (with PROCOMM) Execute PROCOMM.EXE program. PROCOMM match baud rate protocol (type Alt-P, then number follows: 9600 baud, parity, bits, stop bit, full duplex Setup ASCII transfer parameters (type Alt-S, then number follows: Echo Local Expand Blank Lines Pace Character Character pacing (milliseconds) Line Pacing Translation None Translation None Save above settings disk future use. Apply power EVK. Press keyboard carriage return (<CR>) display applicable monitor prompt. Enter monitor download command: CPU32Bug>LO (Press <CR> after entering LO.)
Press key, instruct PROCOMM send S-record file. Then follow PROCOMM instructions screen select S-record file using ASCII protocol. file transfer done when beeper sounds underline cursor flashes. Press carriage return twice return CPU32Bug prompt. <CR> <CR> CPU32Bug>
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FUNCTIONAL DESCRIPTION
CHAPTER FUNCTIONAL DESCRIPTION INTRODUCTION
This chapter functional description components.
DESCRIPTION
configured either ways; mounted mounted target system. Figure block diagram. When mounted PFB, evaluate debug user developed code. this connect terminal host computer connector CPU32Bug debug monitor program. Logic analyzer connection made connectors through PFB. Mount target system verify hardware design. With mounted target system, MC68332 device emulation with hardware breakpoints possible connecting connector running CPU32Bug debug monitor. Logic analyzer connection made connectors BCC.
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FUNCTIONAL DESCRIPTION
LOGIC ANALYZER
TERMINAL/HOST COMPUTER (BCC)
LOGIC ANALYZER CONNECTORS EXPANSION CONNECTORS 512K RAM/ EPROM 512K RAM/ EPROM
TERMINAL/ HOST COMPUTER
TERMINAL/HOST COMPUTER (DI)
BACKGROUND MODE CONNECTOR POWER SUPPLY CONNECTOR
BACKGROUND MODE CONNECTOR
Figure 4-1. Block Diagram
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FUNCTIONAL DESCRIPTION
DESCRIPTION
tool designing, debugging, evaluating MC68332 based target systems. simplifies user evaluation prototype hardware/software products. used itself, part EVK, part M68300EVS Evaluation System (EVS). Figure block diagram. consists these functional circuits: Microcontroller unit User memory connectors
TIMER CHANNELS TERMINAL/ HOST COMPUTER RS-232C INTERFACE
ADDRESS CONTROL LINES
BACKGROUND MODE EPROM EPROM
INTERRUPT SIGNALS DATA CONTROL LINES
Figure 4-2. Block Diagram
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FUNCTIONAL DESCRIPTION
4.3.1
Summary
resident MC68332 Microcontroller Unit (MCU) provides resources designing, debugging, evaluating MC68332 based target systems simplifies user evaluation prototype hardware/software products. device 32-bit integrated microcontroller, combining high-performance data manipulation capabilities with powerful peripheral subsystems. includes: 32-bit central processor unit (CPU32) Time processor unit (TPU) Queued serial module (QSM) Random access memory (RAM) External interface Chip selects System clock Test module 4.3.1.1 32-Bit Central Processor Unit
CPU32 central processor MC68332 device. CPU32 source object code compatible with MC68000 MC68010. user programs executed unchanged. CPU32 features are: 32-Bit internal data path arithmetic hardware 16-bit external data 32-Bit internal address 24-bit external address Powerful instruction Eight 32-bit general purpose data registers Seven 32-bit general purpose address registers Separate user supervisor stack pointers address spaces Separate program data address spaces Flexible addressing modes Full interrupt processing
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MOTOROLA
FUNCTIONAL DESCRIPTION
4.3.1.2
Time Processor Unit
Time Processor Unit (TPU) optimizes performance time-related activities. dedicated execution unit, tri-level prioritized scheduler, data storage RAM, dual time bases, microcode which drastically reduces need intervention. controls sixteen independent, orthogonal channels; each channel associated perform time function. Each channel also contains dedicated event register, both match input capture functions. Each channel synchronized either 16-bit, free-running counters with pre-scaler. counter, based system clock, provides resolution system clock divided second counter, based external reference, also provides resolution system clock divided Channels also linked together, allowing user reference operations channel occurrence specified action another channel, providing inter-task control. 4.3.1.3 Queued Serial Module
contains serial ports. queued serial peripheral interface (QSPI) port provides easy peripheral expansion inter-processor communications full-duplex, synchronous, three-line bus: data-in, data-out, serial clock. Four programmable peripheral select pins provide address-ability many peripheral devices. QSPI enhancement added queue small RAM. This lets QSPI handle many serial transfers 16-bits each, transmit stream data long bits without intervention. special wrap-around mode lets user continuously sample serial peripheral, automatically updating QSPI efficient interfacing serial peripheral devices (such analog-to-digital converters). serial communications interface (SCI) port provides standard non-return zero (NRZ) mark/space format. Advanced error detection circuitry catches noise glitches 1/16 time duration. Word length software selectable between 9-bits, modulus-type, baud rate generator provides baud rates from 524k baud, based 16.77 system clock. features full- half-duplex operation, with separate transmitter receiver enable bits double buffering data. Optional parity generation detection provide either even parity check capability. Wake-up functions uninterrupted until either true idle line detected address byte received. 4.3.1.4 Random Access Memory
bytes static contained within MC68332 device. used storage variable temporary data. data size 8-bits (byte), 16-bits (word), 32-bits (longword). mapped byte boundary address map.
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MOTOROLA
FUNCTIONAL DESCRIPTION
4.3.1.5
External Interface
external consists address lines 16-bit data bus. data allows dynamic sizing between 16-bit data accesses. read-modify-write cycle (RMC) signal prevents cycle interruption. External arbitration accomplished three-line handshaking interface. 4.3.1.6 Chip Selects
Twelve independently programmable chip selects provide fast, two-cycle external memory, peripheral access. Block size programmable from kilobytes through megabyte. Accesses selected either 16-bit transfers. many wait states programmed insertion during access. interface signals automatically handled chip select logic. 4.3.1.7 System Clock
on-chip phase locked loop circuit generates system clock signal device 16.78 from 32.768 watch crystal. system speed changed dynamically, providing either high performance power consumption under software control. system clock fully-static CMOS design, possible completely stop system clock power stop instruction, while still retaining contents registers on-board RAM. 4.3.1.8 Test Module
test module consolidates microcontroller test logic into single block facilitate production testing, user self-test, system diagnostics. Scan paths throughout MC68332 provide signature analysis checks internal logic. User self-test initiated asserting test enter test mode. This test provides pass/fail response various externally supplied test vectors. 4.3.2 User Memory
board bits bits EPROM. debug monitor storage area user accessible memory space; M68CPU32BUG Debug Monitor stored EPROMs. debug monitor functionality M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. Figure memory map. sockets EPROM. and/or EPROM, supplied user, user-accessible memory space.
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MOTOROLA
FUNCTIONAL DESCRIPTION
XXX7FF INTERNAL
XXX000 INTERNAL MODULES OPTIONAL FPCP PFB: ALTERNATE INTERNAL MODULES LOCATION FFFFFF
FFF000 FFE800 800000
7FF000 OPTIONAL RAM/EPROM PFB: CPU32BUG EPROM BCC: 110000 /120000 100000 0E0000 OPTIONAL PFB: TARGET BCC: SYSTEM BCC:
CPU32BUG INTERNAL STACK CPU32BUG INTERNAL VARIABLES CPU32BUG VECTOR TABLE TARGET VECTOR TABLE
020000 010000 003000 000000
Consult device user's manual. XXbase address user programmable. Internal modules, such internal RAM, configured power-up/reset using initilization table (INITTBL) covered Appendix M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. Floating point coprocessor MC68881/MC68882. Appendix M68CPU32BUG Debug Monitor User's Manual, M68CPU32BUG/AD1. Depends memory device type used.
Figure 4-3. Memory
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MOTOROLA
FUNCTIONAL DESCRIPTION
4.3.3
Connectors
There 64-pin expansion connectors P2). Through these connectors communicates with target system. Background mode operation available through serial communication through Chapter contains description interface connectors assignments. 4.3.3.1 64-Pin Expansion Connectors
expansion connectors interconnect target system. pin-outs MC68332 device, serial communication, background mode interface available expansion connectors. 4.3.3.2 Serial Communication Connectors
terminal host computer with terminal emulation (PCKERMIT.EXE, PROCOMM, etc.), connected PFB. Terminal connections provided through serial communication connectors, 4.3.3.3 Background Mode Interface Connector
background debug mode implemented microcode. background mode, registers viewed altered, memory read written, test features executed. Background mode initiated several sources: externally generated breakpoints, internal peripherally generated breakpoints, software, catastrophic exception conditions. Instruction execution suspended duration background mode. Background mode communications between development system serial link (P3).
DESCRIPTION
physical location installing BCC. user expand user accessible memory. connectors available communication, power, logic analyzer. 4.4.1 Floating-Point Coprocessor Socket (U5)
Socket accommodates optional coprocessor EVK. Either MC68881 MC68882 coprocessor used socket coprocessor software interface part EVK, must provided user. developing coprocessor software interface, application note MC68881 Floating-Point Coprocessor Peripheral M68000 System, AN947. coprocessor interface transparent, logical extension MC68332 device registers instructions. external environment coprocessor execution model appear same chip.
M68332EVK/D MOTOROLA
FUNCTIONAL DESCRIPTION
coprocessor interface execution model based sequential instruction execution coprocessor. optimum performance, coprocessor interface lets floating point instructions execute concurrently with integer instructions. Concurrent instruction execution further extended coprocessor, which executes multiple floating-point instructions simultaneously. 4.4.2 Logic Analyzer Connectors
debug hardware software developed MC68331 device, connect logic analyzer desired pins connectors
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MOTOROLA
FUNCTIONAL DESCRIPTION
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SUPPORT INFORMATION
CHAPTER SUPPORT INFORMATION INTRODUCTION
This chapter provides connector signal descriptions, parts lists associated parts location diagrams, schematic diagrams M68332EVK Evaluation (EVK) components (BCC PFB).
CONNECTOR SIGNAL DESCRIPTIONS
connector assignments defined Tables through 5-12. Connector signals identified number, signal mnemonic, signal name description. Table connector descriptions PFB.
Table 5-1. Connector Descriptions
Connector BCC-P1 BCCDI-P1 BCCDI-P2 Description Interconnect PFB. Interconnect PFB. Background mode connector. Serial communication between BCC. Interconnect BCC. Interconnect BCC. Interconnect Interconnect Logic analyzer connections. Supplies power EVK. Serial communication between Serial communication between BCC. Battery backup MC68332 internal RAM. Background mode connector. Table 5-10 None 5-11 5-12 None
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SUPPORT INFORMATION
Table 5-2. Expansion Connector Assignments
Signal Mnemonic Number DTROUT EPROM-W EPROM-VPP +13-24V VSTBY +13-24V T2CLK TP15 MOSI GROUND SYSTEM POWER SUPPLY volt power source. DATA TERMINAL READY RS-232C handshake signal from ADDRESS Three-state output address bus. EPROM WRITE Active-low input write strobe that enables on-board EPROM. EPROM PROGRAMMING VOLTAGE 12.5 input programming voltage. +13-24 VOLTS DEVELOPMENT INTER-FACE Power converter voltage volts). VOLTAGE STANDBY Input standby voltage source on-chip RAM. +13-24 VOLTS DEVELOPMENT INTER-FACE Power converter voltage volts). CLOCK External input clock source TPU. TIME PROCESSOR UNIT CHANNELS Input/output channels. MASTER-OUT SLAVE-IN Serial output from OSPI master mode, serial input QSPI slave mode. MASTER-IN SLAVE-OUT Serial input QSPI master mode, serial output from QSPI slave mode. Signal Name Description
MISO
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MOTOROLA
SUPPORT INFORMATION
Table 5-2. Expansion Connector Assignments (continued)
Signal Mnemonic Number PCS0 PCS2 PCS1 PCS3 BKPT DSCLK RESET FREEZE QUOT Signal Name Description PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select signal. SLAVE SELECT Bi-directional active-low signal that places QSPI slave mode. QSPI SERIAL CLOCK Input/output QSPI clock source. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select. TRANSMIT DATA Serial data output line. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select. BREAKPOINT active-low input signal that places CPU32 background debug mode. DEVELOPMENT SYSTEM CLOCK Serial input clock background debug mode. RECEIVE DATA Serial data input line. RESET Active-low input/output signal initiating system reset. FREEZE Output signal that indicates that CPU32 entered background debug mode. QUOTIENT Output signal that furnishes quotient polynomial divider test purposes.
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SUPPORT INFORMATION
Table 5-2. Expansion Connector Assignments (continued)
Signal Mnemonic Number IPIPE Signal Name Description INSTRUCTION PIPE Active-low output signal that tracks movement words through instruction pipeline. DEVELOPMENT SERIAL Serial output background debug mode. INSTRUCTION FETCH Active-low output signal that indicates when performing instruction word pre-fetch when instruction pipeline been flushed. DEVELOPMENT SERIAL Serial data input background debug mode. VOLT INPUT POWER GROUND
IFETCH
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MOTOROLA
SUPPORT INFORMATION
Table 5-3. Expansion Connector Assignments
Signal Mnemonic Number MODB CSBOOT MODCK TSTME GROUND VOLT INPUT POWER DATA bi-directional data pins. RECEIVE DATA DEVELOPMENT INTER-FACE receive data. TRANSMIT DATA DEVELOPMENT INTER-FACE transmit data. MODE DEVELOPMENT INTERFACE MC68HC11 mode TRANSMIT DATA Serial data output signal. BOOT CHIP SELECT active-low output chip select. RECEIVE DATA Serial data input signal. READ/WRITE Active-high output signal that indicates direction data transfer bus. CLOCK MODE SELECT Input signal that selects source internal system clock. TEST MODE ENABLE Active-low input signal that enables hardware test mode. THREE STATE CONTROL When volts VDD), this input signal forces output drivers high-impedance state. ADDRESS 19-23 Three-state output address bus. CHIP SELECTS 6-10 Output signals that select peripheral/memory devices programmed addresses. Signal Name Description
A23/CS10 A22/CS9 A21/CS8 A20/CS7 A19/CS6
M68332EVK/D
MOTOROLA
SUPPORT INFORMATION
Table 5-3. Expansion Connector Assignments (continued)
Signal Mnemonic Number FC2/CS5 FC1/CS4 FC0/CS3 Signal Name Description FUNCTION CODES Three-state output signals that identify processor state address space current cycle. CHIP SELECTS Output signals that select peripheral/memory devices programmed addresses. BGACK GRANT ACKNOWLEDGE Active-low input signal that indicates that external device assumed control bus. CHIP SELECT Output signal that selects peripheral/memory devices programmed addresses. GRANT Active-low output signal that indicates that current cycle complete MC68332 relinquished bus. CHIP SELECT Output signal that selects peripheral/memory devices programmed addresses. REQUEST Active-low input signal that indicates that external device requests master-ship. CHIP SELECT Output signal that selects peripheral/memory devices programmed addresses. INTERRUPT REQUEST (1-7) Seven prioritized active-low input lines that request synchronous interrupts. IRQ7 highest priority. ERROR Active-low input signal that indicates erroneous operation attempt.
IRQ1 IRQ7
BERR
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MOTOROLA
SUPPORT INFORMATION
Table 5-3. Expansion Connector Assignments (continued)
Signal Mnemonic Number DSACK0 DSACK1 Signal Name Description DATA SIZE ACKNOWLEDGE Active-low input signals that allow asynchronous data transfers dynamic sizing between MC68332 external devices. AUTOVECTOR Active-low input signal that requests automatic vector during interrupt acknowledge cycle. READ-MODIFY-WRITE CYCLE Active-low output signal that identifies cycle part indivisible read-modify-write operation. DATA STROBE Active-low output signal, that during read cycle, indicates that external device should place valid data data bus. During write cycle, indicates that valid data data bus. ADDRESS STROBE Active-low output signal that indicates that valid address address bus. TRANSFER SIZE Active-high output signals that indicate number bytes remaining transferred during this cycle. MC68HC11 RESET -.Active-low input signal that resets HC11. SYSTEM CLOCK Output signal that MC68332 internal system clock. EXTERNAL CLOCK INPUT External clock input MC68332 device. HALT Active-low input/output signal that suspends external activity, request retry when used with BERR single-step operation. VOLT INPUT POWER GROUND
AVEC
SIZ0, SIZ1
11RESET CLKOUT EXTAL HALT
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SUPPORT INFORMATION
Table 5-4. Background Mode Connector Assignments
Signal Mnemonic Number BKPT DSCLK FREEZE QUOT RESET IFETCH GROUND BREAKPOINT active-low input signal that places CPU32 background debug mode. DEVELOPMENT SYSTEM CLOCK Serial input clock background debug mode. GROUND FREEZE Indicates that acknowledged breakpoint entered background mode. QUOTIENT Output signal that furnishes quotient polynomial divider test purposes. RESET Active-low input/output signal initiating system reset. INSTRUCTION FETCH Active-low output signal that indicates when performing instruction word pre-fetch when instruction pipeline been flushed. DEVELOPMENT SERIAL Serial data input background debug mode. VOLT INPUT POWER INSTRUCTION PIPE Active-low output signal that tracks movement words through instruction pipeline. DEVELOPMENT SERIAL Serial output background debug mode. Signal Name Description
IPIPE
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MOTOROLA
SUPPORT INFORMATION
Table 5-5. Connector Assignments
Signal Mnemonic Number XMIT +10V Signal Name Description TRANSMIT DATA RS-232C serial output data. GROUND RECEIVE DATA RS-232C serial input data. VOLTS Output voltage that used drive RS-232C handshake lines.
Table 5-6. Logic Analyzer Connector Assignments
Signal Mnemonic Number Signal Name Description connected. ADDRESS STROBE Active-low output signal that indicates valid address address bus. DATA bi-directional data pins. GROUND
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MOTOROLA
SUPPORT INFORMATION
Table 5-7. Logic Analyzer Connector Assignments
Signal Mnemonic Number T2CLK TP15 Signal Name Description connected. CLOCK External input clock source TPU. TIME PROCESSOR UNIT CHANNELS input/output channels. GROUND
Table 5-8. Logic Analyzer Connector Assignments
Signal Mnemonic Number DSACK1 Signal Name Description connected. DATA SIZE ACKNOWLEDGE Active-low input signals that allow asynchronous data transfers dynamic sizing between MC68332 external devices. ADDRESS Three-state output address bus. GROUND
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SUPPORT INFORMATION
Table 5-9. Logic Analyzer Connector Assignments
Signal Mnemonic Number DSACK0 Signal Name Description connected. DATA SIZE ACKNOWLEDGE Active-low input signals that allow asynchronous data transfers dynamic sizing between MC68332 external devices. AUTOVECTOR Active-low input signal that requests automatic vector during interrupt acknowledge cycle. READ-MODIFY-WRITE CYCLE Active-low output signal that identifies cycle part indivisible read-modify-write operation. ADDRESS STROBE Active-low output signal that indicates that valid address address bus. DATA STROBE Active-low output signal, that during read cycle, indicates that external device should place valid data data bus. During write cycle, indicates that valid data data bus. REQUEST Active-low input signal that indicates that external device requires master-ship. CHIP SELECT Output signal that selects peripheral/memory devices programmed addresses. GRANT Active-low output signal that indicates that current cycle complete MC68332 relinquished bus. CHIP SELECT Output signal that selects peripheral/memory devices programmed addresses.
AVEC
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SUPPORT INFORMATION
Table 5-9. Logic Analyzer Connector Assignments (continued)
Signal Mnemonic Number CSBOOT CLKOUT A23/CS10 A22/CS9 A21/CS8 A20/CS7 A19/CS6 Signal Name Description BOOT CHIP SELECT active-low output chip select. SYSTEM CLOCK OUTPUT internal clock output signal. ADDRESS 19-23 5-bits 24-bit address bus. CHIP SELECTS 6-10 Enables peripherals programmed addresses.
ADDRESS 16-18 Three bits 24-bit address bus. GROUND
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SUPPORT INFORMATION
Table 5-10. Logic Analyzer Connector Assignments
Signal Mnemonic Number CLKOUT BERR BKPT DSCLK FREEZE QUOT RESET HALT IPIPE IFETCH Signal Name Description connected. SYSTEM CLOCK OUTPUT internal clock output signal. ERROR Active-low input signal that indicates that erroneous operation being attempted. BREAKPOINT Active-low input signal that places CPU32 background debug mode. DEVELOPMENT SYSTEM CLOCK Serial input clock background debug mode. FREEZE Indicates that acknowledged breakpoint entered background mode QUOTIENT Furnishes quotient polynomial divider test purposes. RESET System reset. HALT Suspend external activity. INSTRUCTION PIPE Tracks movement words through instruction pipeline. DEVELOPMENT SERIAL Serial output background debug mode. INSTRUCTION FETCH IFETCH either normal IFETCH latched IFETCH, configuration jumper header J14.
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SUPPORT INFORMATION
Table 5-10. Logic Analyzer Connector Assignments (continued)
Signal Mnemonic Number DSACK1 DSACK0 FC2/CS5 FC1/CS4 FC0/CS3 Signal Name Description DATA SIZE ACKNOWLEDGE Terminates asynchronous data transfers dynamic sizing. FUNCTION CODES Identify processor state address space current cycle. CHIP SELECTS Enable peripherals programmed addresses. SIZE Indicates number bytes remaining transferred during this cycle. READ/WRITE Indicates direction data transfer bus. GRANT ACKNOWLEDGE Indicates that external device assumed control bus. CHIP SELECT Enables peripherals programmed addresses. GROUND
SIZ1, SIZ0 BGACK
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SUPPORT INFORMATION
Table 5-11. Logic Analyzer Connector Assignments
Signal Mnemonic Number Signal Name Description connected. DATA STROBE During read cycle, indicates that external device should place valid data data bus. During write cycle, indicates that valid data data bus. CLOCK MODE SELECT Active-high input signal that selects source internal system clock. INTERRUPT REQUEST (1-7) Seven prioritized active input lines that requests synchronous interrupts. IRQ7 highest priority. TRANSMIT DATA Serial data output line. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select signal. SLAVE SELECT Bi-directional active-low signal that places QSPI slave mode. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select. PERIPHERAL CHIP SELECT Active-low output QSPI peripheral chip select. QSPI SERIAL CLOCK Furnishes clock from QSPI master mode QSPI slave mode.
MODCK IRQ1 IRQ7
PCS0
PCS1 PCS2 PCS3
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SUPPORT INFORMATION
Table 5-11. Logic Analyzer Connector Assignments (continued)
Signal Mnemonic Number MISO Signal Name Description MASTER-IN SLAVE-OUT Serial input QSPI master mode, serial output from QSPI slave mode. MASTER-OUT SLAVE-IN Serial output from OSPI master mode, serial input QSPI slave mode. GROUND
MOSI
Table 5-12. Connector Assignments
Signal Mnemonic Number Signal Name Description DATA CARRIER DETECT connected. RECEIVE DATA RS-232C serial input signal. TRANSMIT RS-232C serial output signal. DATA TERMINAL READY connected. GROUND DATA READY output signal (held high) that indicates on-line/in-service/active status. REQUEST SEND connected. CLEAR SEND output signal that indicates ready-to-transfer data status. connected.
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SUPPORT INFORMATION
Table 5-13. Connector Assignments
Signal Mnemonic Number Signal Name Description DATA CARRIER DETECT connected. RECEIVE DATA RS-232C serial input signal. TRANSMIT RS-232C serial output signal. DATA TERMINAL READY output line that indicates on-line/in-service/active status. GROUND DATA READY output signal (held high) that indicates on-line/in-service/active status. REQUEST SEND connected. CLEAR SEND output signal that indicates ready-to-transfer data status. connected.
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SUPPORT INFORMATION
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APPENDIX
APPENDIX S-RECORD INFORMATION
S-record format output modules devised purpose encoding programs data files printable format transportation between computer systems. transportation process thus visually monitored S-records more easily edited.
S-RECORD CONTENT
When viewed user, S-records essentially character strings made several fields which identify record type, record length, memory address, code/data checksum. Each byte binary data encoded 2-character hexadecimal number; first character representing high-order bits, second low-order bits byte. five fields which comprise S-record shown below:
TYPE
RECORD LENGTH
ADDRESS
CODE/DATA
CHECKSUM
Where fields composed follows:
Printable Characters 4,6,or S-records type etc. count character pairs record, excluding type record length. 4-byte address which data field loaded into memory. From bytes executable code, memory-loadable data, descriptive information. compatibility with teletypewriters, some programs limit number bytes printable characters S-record). least significant byte one's complement values represented pairs characters making records length, address, code/data fields.
Field type record length address code/data
Contents
checksum
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APPENDIX
Each record terminated with CR/LF/NULL. Additionally, S-record have initial field accommodate other data such line numbers generated some time-sharing systems. S-record file normal ASCII text file operating system origin. Accuracy transmission ensured record length (byte count) checksum fields.
S-RECORD TYPES
Eight types S-records have been defined accommodate several needs encoding, transportation decoding functions. various Motorola upload, download other records transportation control programs, well cross assemblers, linkers other filecreating debugging programs, utilize only those S-records which serve purpose program. specific information which S-records supported particular program, user's manual program must consulted. 332Bug supports records. S-record format module contain S-records following types:
Type Description header record each block S-records, code/data.field contain descriptive information identifying following block S-records. address field normally zeros. record containing code/data 2-byte address which code/data reside. record containing code/data 3-byte address which code/data reside. record containing code/data 4-byte address which code/data reside. record containing number records transmitted particular block. This count appears address field. There code/data field. termination record block records, address field optionally contain 4byte address instruction which control passed. There code/data field. termination record block records. address field optionally contain 3byte address instruction which control passed. There code/data field. termination record block records. address field optionally contain 2byte address instruction which control passed. specified, first entry point specification encountered object module input will used. There code/data field.
Only termination record used each block S-records. records usually used only when control passed byte address. Normally, only header record used, although possible multiple header records occur.
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APPENDIX
S-RECORDS CREATION
S-record format files produced dump utilities, debuggers, linkage editors, cross assemblers cross linkers. Several pro- grams available downloading file S-record format from host system microprocessor-based system. EXAMPLE Shown below typical S-record format module, printed displayed: S00600004844521B S113003000144ED492 S9030000FC module consists record, four records, record. record comprised following character pairs: S-record type indicating that header record. Hexadecimal (decimal indicating that character pairs ASCII bytes) follow. Four-character, 2-byte, address field; zeros this example.
ASCII "HDR". checksum.
first record explained follows: S-record type indicating that code/data record loaded/verified 2-byte address. Hexadecimal (decimal 19), indicating that character pairs, representing bytes binary data, follow. Four-character, 2-byte, address field; hexadecimal address 0000, where data which follows loaded.
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APPENDIX
next character pairs first record ASCII bytes actual program code/data. this assembly language example, hexadecimal opcodes program written sequence code/data fields records:
OPCODE 285F 245F 2212 226A0004 24290008 237C
INSTRUCTION MOVE.L MOVE.L MOVE.L MOVE.L MOVE.L MOVE.L (A7)+,A4 (A7)+,A2 (A2),D1 4(A2),A1 FUNCTION(A1),D2 #FORCEFUNC,FUNCTION(A1)
(The balance this code continued code/data fields remaining records stored memory.) checksum first record.
second third records also each contain (19) character pairs ended with checksums respectively. fourth record contains character pairs checksum record explained follows: S-record type indicating that termination record. Hexadecimal indicating that three character pairs bytes) follow. address field, zeros. checksum record.
Each printable character S-record encoded hexadecimal (ASCII this example) representation binary bits which actually transmitted. example, first record above sent
TYPE
LENGTH
ADDRESS
CODE/DATA
CHECKSUM
0101 0011 0011 0001 0011 0001 0011 0011 0011 0000 0011 0000 0011 0000 0011 0000 0011 0010 0011 1000 0011 0101 0100 0110 0011 0010 0100 0001
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