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Intel® 815E Chipset Platform
with Universal Socket Design Guide
Document Number: 298350-001
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two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation.
Alert result Intel-IBM Advanced Manageability Alliance trademark IBM. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Intel, Celeron, Pentium Pentium III, trademarks registered trademarks Intel Corporation subsidiaries United States other countries. *Other names brands claimed property others. Copyright 2001, Intel Corporation
Intel 815E Chipset Platform Design Guide
Contents
Introduction Terminology Reference Documents System Overview 1.3.1 System Features 1.3.2 Component Features.21 1.3.2.1 Intel 82815 GMCH Features 1.3.2.2 Intel 82801BA Controller (ICH2) 1.3.2.3 Firmware (FWH).23 1.3.3 Platform Initiatives 1.3.3.1 Universal Motherboard Design 1.3.3.2 Intel 133.23 1.3.3.3 Accelerated Architecture Interface 1.3.3.4 Internet Streaming SIMD Extensions.23 1.3.3.5 2.0.24 1.3.3.6 Integrated Controller 1.3.3.7 Ultra ATA/100 Support.24 1.3.3.8 Expanded Support 1.3.3.9 Manageability Other Enhancements 1.3.3.10 AC'97 6-Channel Support 1.3.3.11 Low-Pin-Count (LPC) Interface.27 Nominal Board Stack-up
General Design Considerations.29 Component Layouts.31 Universal Motherboard Design Universal Motherboard Definition Details.35 Processor Design Requirements 4.2.1 Universal Motherboard Design With Incompatible GMCH 4.2.2 Identifying Processor Socket.39 4.2.3 Setting Appropriate Processor Level 4.2.4 Processor 4.2.5 Identifying Processor GMCH.41 4.2.6 Configuring Non-VTT Processor Pins 4.2.7 VCMOS Reference.43 4.2.8 Processor Signal PWRGOOD.43 4.2.9 APIC Clock Voltage Switching Requirements 4.2.10 GTLREF Topology Layout.45 Power Sequencing Wake Events 4.3.1 Gating Intel CK-815 VTTPWRGD 4.3.2 Gating PWROK ICH2.48
Intel 815E Chipset Platform Design Guide
System Design Guidelines System Routing Guidelines 5.1.1 Initial Timing Analysis General Topology Layout Guidelines.52 5.2.1 Motherboard Layout Rules AGTL/AGTL+ Signals 5.2.1.1 Motherboard Layout Rules Non-AGTL/AGTL+ (CMOS) Signals 5.2.1.2 THRMDP THRMDN 5.2.1.3 Additional Routing Placement Considerations Electrical Differences Universal PGA370 Designs 5.3.1 THERMTRIP Circuit 5.3.1.1 THERMTRIP Timing PGA370 Socket Definition Details BSEL[1:0] Implementation Differences.62 CLKREF Circuit Implementation Undershoot/Overshoot Requirements Processor Reset Requirements.64 Processor Filter Recommendations 5.9.1 Topology.65 5.9.2 Filter Specification 5.9.3 Recommendation Intel Platforms.67 5.9.4 Custom Solutions Voltage Regulation Guidelines.69 Decoupling Guidelines Universal PGA370 Designs 5.11.1 VCCCORE Decoupling Design 5.11.2 Decoupling Design 5.11.3 VREF Decoupling Design.70 Thermal Considerations.71 5.12.1 Heatsink Volumetric Keepout Regions.71 Debug Port Changes System Memory Routing Guidelines.75 System Memory 2-DIMM Design Guidelines 6.2.1 System Memory 2-DIMM Connectivity 6.2.2 System Memory 2-DIMM Layout Guidelines System Memory 3-DIMM Design Guidelines 6.3.1 System Memory 3-DIMM Connectivity 6.3.2 System Memory 3-DIMM Layout Guidelines System Memory Decoupling Guidelines Compensation.82 Interface 7.1.1 Graphics Performance Accelerator (GPA) 7.1.2 Universal Retention Mechanism (RM) 7.2.1 Interface Signal Groups
5.10 5.11
5.12 5.13
System Memory Design Guidelines.75
AGP/Display Cache Design Guidelines.83
Intel 815E Chipset Platform Design Guide
Standard Routing Guidelines 7.3.1 Timing Domain Routing Guidelines 7.3.1.1 Flexible Motherboard Guidelines 7.3.1.2 AGP-Only Motherboard Guidelines.88 7.3.2 2X/4X Timing Domain Routing Guidelines 7.3.2.1 Flexible Motherboard Guidelines 7.3.2.2 AGP-Only Motherboard Guidelines.90 7.3.3 Routing Guideline Considerations Summary.91 7.3.4 Clock Routing 7.3.5 Signal Noise Decoupling Guidelines.92 7.3.6 Routing Ground Reference.93 Down Routing Guidelines 7.4.1 Down Option Timing Domain Routing Guidelines 7.4.2 2X/4X Down Timing Domain Routing Guidelines 7.4.3 Routing Guideline Considerations Summary.95 7.4.4 Clock Routing 7.4.5 Signal Noise Decoupling Guidelines.96 7.4.6 Routing Ground Reference.96 Power Delivery Guidelines 7.5.1 VDDQ Generation TYPEDET#.97 7.5.2 VREF Generation Additional Design Guidelines.101 7.6.1 Compensation .101 7.6.2 Pull-ups .101 7.6.2.1 Signal Voltage Tolerance List.102 Motherboard Add-in Card Interoperability.102 Display Cache Shared Interface.103 7.8.1 Card Considerations .103 7.8.1.1 Mechanical Considerations.103 7.8.2 Display Cache Clocking.104 Designs That Port .104 Analog RGB/CRT.105 8.1.1 RAMDAC/Display Interface .105 8.1.2 Reference Resistor (Rset) Calculation .107 8.1.3 RAMDAC Board Design Guidelines .107 8.1.4 RAMDAC Layout Recommendations .109 8.1.5 HSYNC/VSYNC Output Guidelines.109 Digital Video .110 8.2.1 Interface Routing Guidelines .110 8.2.2 Interface Considerations.110 8.2.3 Leaving Port Unconnected .110
Integrated Graphics Display Output.105
Interface .111 9.1.1 Data Signals .112 9.1.2 Strobe Signals .112 9.1.3 HREF Generation/Distribution.112 9.1.4 Compensation .113
Intel 815E Chipset Platform Design Guide
Controller (ICH2) .115 10.1 10.2 10.3 10.4 Decoupling .115 1.85V/3.3V Power Sequencing .116 Power Sequencing Wake Events .117 Power Plane Splits .118 Interface .119 11.1.1 Cabling .119 Cable Detection Ultra ATA/66 Ultra ATA/100 .119 11.2.1 Combination Host-Side/Device-Side Cable Detection .120 11.2.2 Device-Side Cable Detection.121 11.2.3 Primary Connector Requirements .122 11.2.4 Secondary Connector Requirements .123 AC'97 .124 11.3.1 Communications Network Riser (CNR).125 11.3.2 AC'97 Audio Codec Detect Circuit Configuration Options.126 11.3.2.1 Valid Codec Configurations .129 11.3.3 SPKR Considerations.129 11.3.4 AC'97 Routing .130 11.3.5 Motherboard Implementation .131 USB.131 11.4.1 Using Native Interface.131 11.4.2 Disabling Native Interface ICH2.132 IOAPIC Design Recommendation .133 11.5.1 PIRQ Routing Example .133 SMBus/SMLink Interface .134 11.6.1 SMBus Architecture Design Considerations .135 11.6.1.1 General Design Issues Notes .136 .138 RTC.138 11.8.1 Crystal .138 11.8.2 External Capacitors .139 11.8.3 Layout Considerations .139 11.8.4 External Battery Connection .140 11.8.5 External RTCRST Circuit.141 11.8.6 Power-Well Isolation Control Strap Requirements.141 11.8.7 Routing Guidelines.142 11.8.8 VBIAS Voltage Noise Measurements .142 Layout Guidelines .142 11.9.1 ICH2 Interconnect Guidelines .143 11.9.1.1 Topologies .144 11.9.1.2 Point-to-Point Interconnect .144 11.9.1.3 LOM/CNR Interconnect.145 11.9.1.4 Signal Routing Layout .145 11.9.1.5 Crosstalk Consideration.146 11.9.1.6 Impedances .146 11.9.1.7 Line Termination .146
Subsystem .119 11.1 11.2
11.3
11.4
11.5 11.6
11.7 11.8
11.9
Intel 815E Chipset Platform Design Guide
11.10
General Routing Guidelines Considerations .147 11.9.2.1 General Trace Routing Considerations.147 11.9.2.2 Power Ground Connections .148 11.9.2.3 4-Layer Board Design.150 11.9.2.4 Common Physical Layout Issues .150 11.9.3 Intel 82562EH Home/PNA* Guidelines.152 11.9.3.1 Power Ground Connections .152 11.9.3.2 Guidelines Intel 82562EH Component Placement.152 11.9.3.3 Crystals Oscillators .152 11.9.3.4 Phoneline HPNA Termination .153 11.9.3.5 Critical Dimensions .154 11.9.4 Intel 82562ET Intel 82562EM Guidelines .155 11.9.4.1 Guidelines Intel 82562ET Intel 82562EM Component Placement .155 11.9.4.2 Crystals Oscillators .155 11.9.4.3 Intel 82562ET Intel 82562EM Termination Resistors.156 11.9.4.4 Critical Dimensions .156 11.9.4.5 Reducing Circuit Inductance .158 11.9.5 Intel 82562ET/82562EM Disable Guidelines .159 11.9.6 Intel 82562ET Intel 82562EH Dual Footprint Guidelines .160 LPC/FWH.161 11.10.1 In-Circuit Programming.162 11.10.2 Design Guidelines .162 11.10.3 Decoupling .162 2-DIMM Clocking .163 3-DIMM Clocking .165 Clock Routing Guidelines.167 Clock Driver Frequency Strapping .169 Clock Skew Assumptions .170 Intel CK-815 Power Gating Wake Events .171 Thermal Design Power .176 13.1.1 Pull-Up Pull-Down Resistor Values .177 Power Supply PWRGOOD Requirements.177 Power Management Signals .178 13.3.1 Power Button Implementation .179 13.3.2 1.85V/3.3V Power Sequencing.180 13.3.3 3.3V/V5REF Sequencing.181 Power Plane Splits .182 Glue Chip (ICH2 Glue Chip) .183 Design Review Checklist .185 Processor Checklist .185 14.2.1 Checklist.185 14.2.2 CMOS Checklist .186 14.2.3 Checklist 370-Pin Socket Processors .186 14.2.4 Miscellaneous Checklist 370-Pin Socket Processors .187
11.9.2
Clocking .163 12.1 12.2 12.3 12.4 12.5 12.6
Power Delivery.173 13.1 13.2 13.3
13.4 13.5 14.1 14.2
System Design Checklist.185
Intel 815E Chipset Platform Design Guide
14.3
14.4
14.5 14.6 14.7 14.8 14.9 14.10
GMCH Checklist .188 14.3.1 Interface Mode Checklist.188 14.3.2 Designs That Port .189 14.3.3 System Memory Interface Checklist.189 14.3.4 Interface Checklist .190 14.3.5 Digital Video Output Port Checklist .190 ICH2 Checklist .190 14.4.1 Interface .190 14.4.2 Interface.191 14.4.3 Interface .191 14.4.4 EEPROM Interface.191 14.4.5 FWH/LPC Interface .191 14.4.6 Interrupt Interface .192 14.4.7 GPIO Checklist.193 14.4.8 .193 14.4.9 Power Management .194 14.4.10 Processor Signals .195 14.4.11 System Management .195 14.4.12 .195 14.4.13 AC'97 .196 14.4.14 Miscellaneous Signals .197 14.4.15 Power .198 14.4.16 Checklist.199 Checklist .201 System Checklist .202 Checklist .202 Clock Synthesizer Checklist.203 System Memory Checklist .204 Power Delivery Checklist .204
Third-Party Vendor Information .205
Appendix Customer Reference Board CRB) .207
Intel 815E Chipset Platform Design Guide
Figures
Figure System Block Diagram Figure Component Block Diagram Figure AC'97 Audio Modem Connections.26 Figure Board Construction Example Nominal Stack-up Figure GMCH 544-Ball µBGA* Quadrant Layout (Top View).31 Figure ICH2 360-Ball EBGA Quadrant Layout (Top View) Figure Firmware (FWH) Packages Figure Future 0.13 Micron Socket Processor Safeguard Universal Motherboard Designs Using GMCH Figure Processor Detect Mechanism Socket/TUAL5 Generation Circuit Figure Selection Switch Figure Switching AG1.41 Figure Processor Identification Strap GMCH Figure VTTPWRGD Configuration Circuit Figure GTL_REF/VCMOS_REF Voltage Divider Network Figure Resistor Divider Network Processor PWRGOOD.44 Figure Voltage Switch Processor APIC Clock.45 Figure GTLREF Circuit Topology Figure Gating Power Intel CK-815 Figure PWROK Gating Circuit ICH2 Figure Topology 370-Pin Socket Designs with Single-Ended Termination (SET).52 Figure AGTL/AGTL+ Trace Routing.53 Figure Routing THRMDP THRMDN.56 Figure Example Implementation THERMTRIP Circuit Figure BSEL[1:0] Circuit Implementation PGA370 Designs.62 Figure Examples CLKREF Divider Circuit.63 Figure RESET#/RESET2# Routing Guidelines Figure Filter Specification Figure Example Filter Using Discrete Resistor Figure Example Filter Using Buried Resistor Figure Core Reference Model Figure Capacitor Placement Motherboard.70 Figure Heatsink Volumetric Keepout Regions.72 Figure Motherboard Component Keepout Regions.72 Figure Connector Comparison Figure System Memory Routing Guidelines Figure System Memory Connectivity DIMM) Figure System Memory 2-DIMM Routing Topologies.77 Figure System Memory Routing Example Figure System Memory Connectivity DIMM) Figure System Memory 3-DIMM Routing Topologies.80 Figure Intel Chipset Platform Decoupling Example Figure Intel Chipset Decoupling Example.82 Figure Left-Handed Retention Mechanism Figure Left-Handed Retention Mechanism Keepout Information.85 Figure 2X/4X Routing Example Interfaces inches GPA/AGP Solutions.89 Figure Decoupling Capacitor Placement Example Figure Down 2X/4X Routing Recommendations Figure VDDQ Generation Example Circuit
Intel 815E Chipset Platform Design Guide
Figure VREF Generation Distribution.100 Figure Display Cache Input Clocking.104 Figure Schematic RAMDAC Video Interface.106 Figure Cross-Sectional View Four-Layer Board .107 Figure Recommended RAMDAC Component Placement Routing .108 Figure Recommended RAMDAC Reference Resistor Placement Connections Figure Interface Signal Routing Example .111 Figure Single Interface Reference Divider Circuit.113 Figure Locally Generated Interface Reference Dividers .113 Figure ICH2 Decoupling Capacitor Layout .116 Figure 1.85V/3.3V Power Sequencing Circuit Example .117 Figure Power Plane Split Example .118 Figure Combination Host-Side Device-Side Cable Detection .120 Figure Device-Side Cable Detection.121 Figure Connection Requirements Primary Connector.122 Figure Connection Requirements Secondary Connector.123 Figure ICH2 AC'97- Codec Connection .124 Figure Interface.125 Figure CDC_DN_ENAB# Support Circuitry Single Codec Motherboard .126 Figure CDC_DN_ENAB# Support Circuitry Multi-Channel Audio Upgrade.127 Figure CDC_DN_ENAB# Support Circuitry Two-Codecs Motherboard OneCodec .127 Figure CDC_DN_ENAB# Support Two-Codecs Motherboard Two-Codecs CNR.128 Figure Example Speaker Circuit.129 Figure Data Signals.132 Figure Example PIRQ Routing .134 Figure SMBus/SMLink Interface.135 Figure Unified VCC_Suspend Architecture .136 Figure Unified VCCCORE Architecture.137 Figure Mixed VCC_Suspend/VCCCORE Architecture .137 Figure Layout Example.138 Figure External Circuitry ICH2 .139 Figure Diode Circuit Connect External Battery.140 Figure RTCRST External Circuit ICH2 .141 Figure ICH2 Connect Section .143 Figure Single-Solution Interconnect.144 Figure LOM/CNR Interconnect .145 Figure LAN_CLK Routing Example .146 Figure Trace Routing.147 Figure Ground Plane Separation .149 Figure Intel 82562EH Termination .153 Figure Critical Dimensions Component Placement.154 Figure Intel 82562ET/Intel 82562EM Termination .156 Figure Critical Dimensions Component Placement.157 Figure Termination Plane .159 Figure Intel 82562ET/82562EM Disable Circuit.159 Figure Dual-Footprint Connect Interface .160 Figure Dual-Footprint Analog Interface .160 Figure Isolation Circuitry .162 Figure Platform Clock Architecture 2-DIMM Solution.164 Figure Platform Clock Architecture 3-DIMM Solution.166 Figure Clock Routing Topologies .167 Figure 100. Power Delivery Map.174
Intel 815E Chipset Platform Design Guide
Figure 101. Pull-Up Resistor Example .177 Figure 102. Example 1.85V/3.3V Power Sequencing Circuit .180 Figure 103. 3.3V/V5REF Sequencing Circuitry .181 Figure 104. Power Plane Split Example .182 Figure 105. Data Line Schematic .194 Figure 106. ICH2 Oscillator Circuitry .196 Figure 107. SPKR Circuitry.197 Figure 108. V5REF Circuitry.198 Figure 109. Host/Device Side Detection Circuitry.200 Figure 110. Device Side Only Cable Detection .200
Intel 815E Chipset Platform Design Guide
Tables
Table Processor Considerations Universal Motherboard Design Table GMCH Considerations Universal Motherboard Design.37 Table ICH2 Considerations Universal Motherboard Design.37 Table Clock Synthesizer Considerations Universal Motherboard Design Table Determining Installed Processor Hardware Mechanisms Table Intel Pentium Processor AGTL/AGTL+ Parameters Example Calculations Table Example TFLT_MAX Calculations Table Example TFLT_MIN Calculations (Frequency Independent) Table Trace Guidelines Figure Table Trace Width:Space Guidelines.52 Table Routing Guidelines Non-AGTL/AGTL+ Signals Table Processor Definition Comparison.58 Table Resistor Values CLKREF Divider (3.3V Source).63 Table RESET#/RESET2# Routing Guidelines Table Component Recommendations Inductor.67 Table Component Recommendations Capacitor Table Component Recommendation Resistor Table System Memory 2-DIMM Solution Space.77 Table System Memory 3-DIMM Solution Space.80 Table Retention Mechanism Vendors Table Signal Groups Table Data/Strobe Associations.87 Table Routing Summary Table Down Routing Summary Table TYPDET#/VDDQ Relationship Table Connector/Add-in Card Interoperability .102 Table Voltage/Data Rate Interoperability.102 Table Decoupling Capacitor Recommendation .115 Table Signal Descriptions .128 Table Codec Configurations .129 Table IOAPIC Interrupt Inputs thru Usage.133 Table Pull-up Requirements SMBus SMLink .135 Table Connect .142 Table Single-Solution Interconnect Length Requirements .144 Table LOM/CNR Length Requirements.145 Table Critical Dimensions Component Placement.154 Table Critical Dimensions Component Placement.157 Table Intel 82562ET Operating States.160 Table Intel CK-815 (2-DIMM) Clocks.163 Table Intel CK-815 (3-DIMM) Clocks.165 Table Simulated Clock Routing Solution Space .168 Table Simulated Clock Skew Assumptions .170 Table Power Delivery Definitions .173 Table Recommendations Unused Port.189
Intel 815E Chipset Platform Design Guide
Revision History
Rev. -001 Initial Release. Description Rev. Date
Intel 815E Chipset Platform Design Guide
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Intel 815E Chipset Platform Design Guide
Introduction
Introduction
This design guide organizes Intel design recommendations Intel® 815E chipset platform with universal socket 370. addition providing motherboard design recommendations (e.g., layout routing guidelines), this document also addresses system design issues (e.g., thermal requirements) chipset platform. This design guide contains design recommendations, board schematics, debug recommendations, system checklist. These design guidelines developed ensure maximum flexibility board designers while reducing risk board-related issues. Board designers schematics Appendix "Customer Reference Board (CRB)" reference. While included schematics cover specific designs, core schematics will remain same most Intel 815E chipset platforms that universal socket 370. Consult debug recommendations when debugging your design. However, these debug recommendations should understood before completing board design ensure that debug port, addition other debug features, implemented correctly. Intel 815E chipset platform supports following processors: Intel® Pentium® processor based 0.18 micron technology (CPUID 068xh). Intel® Celeronprocessor based 0.18 micron technology (CPUID 068xh). This applies Celeron 533A processors Future 0.13 micron socket processors Note: system speed supported design based capabilities processor, chipset, clock driver. Note: chipset with universal socket compatible with Intel® Pentium® processor (CPUID 066xh) 370-pin socket.
Intel 815E Chipset Platform Design Guide
Introduction
Terminology
This section describes some terms used this document. Additional power delivery term definitions provided beginning Chapter13, "Power Delivery".
Term
AGTL/AGTL+ Accelerated Graphics Port Refers processor signals that implemented using either Assisted Gunning Transceiver Logic (AGTL+) lower voltage variant (AGTL), depending which processor being used. component group components that, when combined, represent single load AGTL+ bus. reception victim network signal imposed aggressor network(s) through inductive capacitive coupling between networks. Backward Crosstalk-coupling that creates signal victim network that travels opposite direction aggressor's signal. Forward Crosstalk-coupling that creates signal victim network that travels same direction aggressor's signal. Even Mode Crosstalk-coupling from single multiple aggressors when aggressors switch same direction that victim switching. Mode Crosstalk-coupling from single multiple aggressors when aggressors switch opposite direction that victim switching. GMCH Graphics Memory Controller Hub. component Intel® chipset platform with Universal Socket Intel® 82801AA Controller component. Inter-symbol interference effect previous signal transition) interconnect delay. example, when signal transmitted down line reflections transition have completely dissipated, following data transition launched onto affected. dependent upon frequency, time delay line, reflection coefficient driver receiver. impact both timing signal integrity. distance between agent pins agent pins bus. electrical contact point semiconductor package substrate. only observable simulation. contact point component package traces substrate such motherboard. Signal quality timings measured pin. voltage that signal rings back after achieving maximum absolute value. Ringback reflections, driver oscillations, other transmission line phenomena. time between beginning Setup Clock (TSU_MIN) arrival valid clock edge. This window different each type agent system.
Description
Agent
Crosstalk
Network Length
Ringback
Setup Window
Intel 815E Chipset Platform Design Guide
Introduction
Term
Description
Simultaneous Switching Output (SSO) Effects refers difference electrical timing parameters degradation signal quality caused multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) opposite direction from single signal (e.g., low-to-high) same direction (e.g., highto-low). These respectively called odd-mode switching even-mode switching. This simultaneous switching multiple outputs creates higher current swings that cause additional propagation delay "push-out"), decrease propagation delay "pull-in"). These effects impact setup and/or hold times always taken into account simulations. System timing budgets should include margin effects. branch from trunk terminating agent. system processor bus. main connection, excluding interconnect branches, from agent other agent pad. Minimum voltage observed signal extend below device pad. Refers Intel 815E chipset using "universal" PGA370 socket. general, these designs support 66/100/133 system operation, Intel® guidelines future 0.13 micron processors, Intel® Celeronprocessors (CPUID=068xh), Intel® Pentium® processor (CPUID=068xh), future Pentium processors single-microprocessor based designs. network that receives coupled crosstalk signal from another network called victim network.
Stub System Trunk
Undershoot Universal Socket
Victim
Intel 815E Chipset Platform Design Guide
Introduction
Reference Documents
Document Intel® Chipset Family: 82815 Graphics Memory Controller (GMCH) with Universal Socket Datasheet Intel® 82802AB/82802AC Firmware (FWH) Datasheet Intel 82801BA Controller (ICH2) Intel 82801BAM Controller (ICH2-M) Datasheet Intel® Pentium® Processor Specification Update (latest revision from website)
Document Number Location 298351 290658 290687 http://developer.intel.co m/design/PentiumIII/sp ecupdt/ 245085 243330 243332
Intel® Pentium® Processor Power Distribution Guidelines AP-585 Intel Pentium Processor AGTL+ Guidelines AP-587 Intel Pentium Processor Power Distribution Guidelines Accelerated Graphics Port Interface Specification, Revision Graphics Performance Accelerator Specification
ftp://download.intel.co m/technology/agp/dow nloads/agp20.pdf
Local Specification, Revision AC'97 Specification http://developer.intel.co m/pcsupp/platform/ac97/ind ex.htm. (Doc 278313) http://developer.intel.co (Doc 278314) http://developer.intel.co http://developer.intel.co m/technology/cnr/
82562EH HomePNA Mb/s Physical Layer Interface Datasheet
82562EH HomePNA Mb/s Physical Layer Interface Brief Datasheet
Communication Network Riser Specification, Revision Universal Serial Bus, Revision Specification
Intel 815E Chipset Platform Design Guide
Introduction
System Overview
Intel 815E chipset platform with universal socket contains Graphics Memory Controller (GMCH) component Controller (ICH2) component desktop platforms. GMCH provides processor interface (optimized Pentium processor (CPUID 068xh) future 0.13 micron socket processors), DRAM interface, interface, Accelerated Graphics Port (AGP) interface internal graphics. This product provides flexibility scalability graphics memory subsystem performance. Competitive internal graphics scaled card interface, PC100 SDRAM system memory scaled PC133 system memory. Accelerated Architecture interface (i.e., chipset component interconnect) designed into chipset provide efficient, high-bandwidth communication channel between GMCH controller hub. chipset architecture also enables security manageability infrastructure through Firmware component. ACPI-compliant Intel 815E chipset platform support Full-on (S0), Stop Grant (S1), Suspend (S3), Suspend Disk (S4), Soft-off (S5) power management states. chipset also supports wake-on-LAN* remote administration troubleshooting. chipset architecture removes requirement expansion that traditionally integrated into subsystem PCIsets/AGPsets. This removes many conflicts experienced when installing hardware drivers into legacy systems. elimination provides true plug-and-play platform. Traditionally, interface used audio modem devices. addition AC'97 allows software-configurable AC'97 audio modem coder/decoders (codecs), instead traditional devices.
Intel 815E Chipset Platform Design Guide
Introduction
1.3.1
System Features
Intel 815E chipset platform contains components: Intel® 82815 Graphics Memory Controller (GMCH) Intel® 82801BA Controller (ICH2). GMCH integrates 66/100/133 MHz, family system controller, integrated 2D/3D graphics accelerator (2X/4X) discrete graphics card, 100/133 SDRAM controller, highspeed accelerated architecture interface communication with ICH2. ICH2 integrates UltraATA/100 controller, Universal Serial (USB) host controllers with total ports, Count (LPC) interface controller, Firmware (FWH) interface controller, interface controller, Intel® AC'97 digital link, integrated controller, interface communication with GMCH.
Figure System Block Diagram
rocessor
66/100/133 system 815E Chipset 2X/4X 82815
graphics card display cache (AGP in-line odule)
Analog display Digital video interface Audio codec Modem codec connect ponent connect AC97 82801BA ICH2
100/133 SDRAM
slots
KBC/SIO
Flash BIOS
Sys_Blk_815E_B0
Intel 815E Chipset Platform Design Guide
Introduction
1.3.2
Component Features
Figure Component Block Diagram
System (66/100/133 MHz)
Processor
System memory
SDRAM 100/133 MHz,
Primary display 2X/4X card Data stream control dispatch Overlay cursor pipeline (blit engine) Internal graphics RAMDAC TVout Monitor Digital video
Local memory
comp_blk_1
1.3.2.1
Intel® 82815 GMCH Features
Processor/System Support Optimized Intel® Pentium® processors system frequency Support Intel® Celeronprocessors (CPUID 068xh) system bus) Supports 32-bit AGTL AGTL+ addressing Supports uniprocessor systems Utilizes AGTL AGTL+ driver technology (gated AGTL/AGTL+ receivers reduced power) Integrated DRAM controller using 16Mb/64Mb/128 technology Supports double-sided DIMMS rows) MHz, SDRAM interface 64-bit data interface Standard Synchronous DRAM (SDRAM) support (x-1-1-1 access) Supports only 3.3V DIMM DRAM configurations registered DIMM support Support symmetrical asymmetrical DRAM addressing Support DRAM device widths Refresh mechanism: CAS-before-RAS only Support DIMM serial (presence detect) scheme SMbus interface Suspend-To-RAM (STR) power management support self-refresh mode using
Intel 815E Chipset Platform Design Guide
Introduction
Accelerated Graphics Port (AGP) Interface Supports 2.0, including data transfers, 2X/4X Fast Write protocol universal connector support dual-mode buffers allow 3.3V 1.5V signaling 32-deep request queue address translation mechanism with integrated fully associative 20-entry High-priority access support Delayed transaction support reads that serviced immediately semantic traffic DRAM snooped system therefore coherent with processor caches Integrated Graphics Controller Full 2D/3D/DirectX acceleration Texture-mapped with point sampled, bilinear, trilinear, anisotropic filtering Hardware setup with support strips fans Hardware motion compensation assist software MPEG/DVD decode Digital Video interface support digital displays TV-Out PC99A/PC2001 compliant Integrated Integrated Local Graphics Memory Controller (Display Cache) (via Graphics Performance Accelerator) using zero, parts 32-bit data interface memory clock Supports ONLY 3.3V SDRAMs Packaging/Power with local memory port 1.85V within margins 1.795 core mixed 3.3V, 1.5V, AGTL, AGTL+
1.3.2.2
Intel® 82801BA Controller (ICH2)
Intel® Controller allows subsystem access rest system, follows: Upstream accelerated architecture interface access GMCH interface Request/Grant pairs) channel Ultra ATA/100 Master controller controller (Expanded capabilities ports) APIC SMBus controller interface interface AC'97 interface Integrated system management controller Alert-on-LAN* Integrated controller Packaging/Power EBGA 1.8V within margins 1.795 core 3.3V standby
Intel 815E Chipset Platform Design Guide
Introduction
1.3.2.3
Firmware (FWH)
hardware features firmware include: integrated hardware Random Number Generator (RNG) Register-based locking Hardware-based locking General Purpose Interrupts (GPI) Packaging/Power TSOP PLCC 3.3V core 3.3V fast programming
1.3.3
1.3.3.1
Platform Initiatives
Universal Motherboard Design
Intel 815E chipset platform with universal socket allows systems designers build system that compatible with Pentium processor (CPUID=068xh), Celeron processor (CPUID=068xh), future 0.13 micron socket processors. When implemented, Intel 815E chipset universal socket platform detect which processor present socket function accordingly.
1.3.3.2
Intel®
Intel® PC133 initiative provides memory bandwidth necessary obtain high performance from processor graphics controller. platform's SDRAM interface supports operation. latter delivers 1.066 GB/s theoretical memory bandwidth compared with MB/s theoretical memory bandwidth SDRAM systems.
1.3.3.3
Accelerated Architecture Interface
speeds increase, demand placed bridge becomes significant. With addition AC'97 Ultra ATA/100, coupled with existing USB, requirements could impact performance. Intel 815E platform's accelerated architecture ensures that subsystem, both integrated features (IDE, AC'97, USB, LAN), receives adequate bandwidth. placing bridge accelerated architecture interface instead PCI, functions integrated into ICH2 peripherals ensured bandwidth necessary peak performance.
1.3.3.4
Internet Streaming SIMD Extensions
Pentium processors provide SIMD (single instruction, multiple data) instructions. extensions floating-point SIMD extensions. Intel® MMXtechnology provides integer SIMD instructions. Internet Streaming SIMD extensions complement technology SIMD instructions provide performance boost floating-point-intensive applications.
Intel 815E Chipset Platform Design Guide
Introduction
1.3.3.5
interface allows graphics controllers access main memory over GB/s, twice bandwidth previous platforms. provides infrastructure necessary photorealistic conjunction with Internet Streaming SIMD extensions, delivers next level graphics performance.
1.3.3.6
Integrated Controller
Intel 815E chipset platform incorporates ICH2 integrated Controller. master capabilities enable component process high-level commands perform multiple operations; this lowers processor utilization off-loading communication tasks from processor. ICH2 functions with several options connect components target desired market segment. Intel® 82562EH provides HomePNA Mbit/sec connection. Intel® 82562ET provides basic Ethernet 10/100 connection. Intel® 82562EM provides Ethernet 10/100 connection with added flexibility Alert LAN. More advanced solutions implemented with Intel® 82550 other based product offerings.
1.3.3.7
Ultra ATA/100 Support
Intel 815E chipset platform incorporates controller with sets interface signals (primary secondary) that independently enabled, tri-stated driven low. component supports Ultra ATA/100, Ultra ATA/66, Ultra ATA/33, multiword modes transfers MB/sec.
1.3.3.8
Expanded Support
Intel 815E chipset platform contains Host Controllers. Each Host Controller includes root with separate ports each, total ports. addition second Host Controller expands functionality platform.
1.3.3.9
Manageability Other Enhancements
Intel 815E chipset platform integrates several functions designed manage system lower total cost ownership (TCO) system. These system management functions designed report errors, diagnose system, recover from system lockups, without external microcontroller.
SMBus
ICH2 integrates SMBus controller. SMBus provides interface managing peripherals such serial presence detection (SPD) thermal sensors. slave interface allows external microcontroller access system resources.
Interrupt Controller
interrupt capabilities platform expand support interrupt pins message-based interrupts. addition, ICH2 supports system interrupt delivery.
Intel 815E Chipset Platform Design Guide
Introduction
Firmware (FWH)
platform supports firmware BIOS memory sizes increased system flexibility.
1.3.3.10
AC'97 6-Channel Support
Audio Codec (AC'97) Specification defines digital interface that used attach audio codec (AC), modem codec (MC), audio/modem codec (AMC), both AC'97 Specification defines interface between system logic audio modem codec known AC'97 Digital Link. Intel 815E chipset platform's AC'97 (with appropriate codecs) only replaces audio modem functionality, also improves overall platform integration incorporating AC'97 digital link. Using platform's integrated AC'97 digital link reduces cost eases migration from ISA. using audio codec, AC'97 digital link allows cost-effective, high-quality, integrated audio. addition, AC'97 soft modem implemented with modem codec. Several system options exist when implementing AC'97. Intel 815E chipset platform's integrated digital link allows several external codecs connected ICH2. system designer provide audio with audio codec, modem with modem codec, integrated audio/modem codec (Figure 3c). digital link expanded support audio codecs (Figure combination audio modem codec (Figure 3b). Modem implementation different countries must taken into consideration, telephone systems vary. implementing split design, audio codec board, modem codec placed riser. Intel developing AC'97 digital link connector. With single integrated codec, AMC, both audio modem routed connector near rear panel where external ports located. digital link ICH2 AC'97 Rev. compliant, supporting codecs with independent functions audio modem. Microphone input left right audio channels supported high-quality, two-speaker audio solution. Wake-on-ring-from-suspend also supported with appropriate modem codec. Intel 815E chipset platform expands audio capability with support channels audio output (i.e., full decode). Six-channel audio consists Front Left, Front Right, Back Left, Back Right, Center Woofer, complete surround sound effect. ICH2 expanded support audio codecs AC'97 digital link.
Intel 815E Chipset Platform Design Guide
Introduction
Figure AC'97 Audio Modem Connections
AC'97 with Audio Codecs (4-Channel Secondary)
ICH2 EBGA
AC'97 Digital Link
AC'97 Audio Codec Audio Port
AC'97 Audio Codec Audio Port AC'97 with Modem Audio Codecs Modem Port
ICH2 EBGA
AC'97 Digital Link
AC'97 Modem Codec
AC'97 Audio Codec Audio Port
AC'97 with Audio/Modem Codec Modem Port
ICH2 EBGA
AC'97 Digital Link
AC'97 Audio/ Modem Codec
Audio Port
AC97_connections
Intel 815E Chipset Platform Design Guide
Introduction
1.3.3.11
Low-Pin-Count (LPC) Interface
Intel 815E chipset platform, Super (SIO) component migrated Low-PinCount (LPC) interface. Migration interface allows lower-cost Super designs. Super component requires same feature traditional Super components. should include keyboard mouse controller, floppy disk controller, serial parallel ports. addition Super features, integrated game port recommended because AC'97 interface does provide support game port. systems with audio, game port typically existed audio card. fifteen-pin game port connector provides joysticks two-wire MPU-401 MIDI interface. Consult your preferred Super vendor comprehensive list devices offered features supported. addition, depending system requirements, specific system requirements integrated into Super I/O. example, integrated connect ICH2 output extend multiple connectors. Other integration targets include device controller ISA-IRQ-to-serial-IRQ converter support PCI-to-ISA bridge. Contact your Super vendor ensure availability desired Super features.
Intel 815E Chipset Platform Design Guide
Introduction
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Intel 815E Chipset Platform Design Guide
General Design Considerations
General Design Considerations
This design guide provides motherboard layout routing guidelines systems based Intel 815E chipset with universal socket 370. document does discuss functional aspects layout guidelines add-in device. guidelines listed this document followed, very important that thorough signal integrity timing simulations completed each design. Even when guidelines followed, critical signals should simulated ensure proper signal integrity flight time. speeds increase, imperative that guidelines documented followed precisely. deviation from these guidelines should simulated. trace impedance typically noted (i.e., 15%) "nominal" trace impedance mil-wide trace. That impedance trace when subjected fields created changing current neighboring traces. When calculating flight times, important consider minimum maximum impedance trace, based switching neighboring traces. wider spaces between traces minimize this trace-to-trace coupling. addition, these wider spaces reduce crosstalk settling time. Coupling between traces function coupled length, distance separating traces, signal edge rate, degree mutual capacitance inductance. minimize effects trace-to-trace coupling, follow routing guidelines documented this section. routing guidelines this design guide have been created using stack-up similar that shown Figure this stack-up used, extremely thorough simulations every interface must completed. Using thicker dielectric (prepreg) will make routing very difficult impossible.
Nominal Board Stack-up
Intel 815E chipset platform requires board stack-up yielding target impedance with nominal trace width. Figure shows example stack-up that achieves this. 4-layer printed circuit board (PCB) construction using 53%-resin material.
Figure Board Construction Example Nominal Stack-up
Component-side layer 4.5-mil prepreg Power plane layer
~48-mil core
Ground layer 4.5-mil prepreg Solder-side layer
Total thickness: mils
board_4.5mil_stackup
Intel 815E Chipset Platform Design Guide
General Design Considerations
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Intel 815E Chipset Platform Design Guide
Component Layouts
Component Layouts
Figure illustrates relative signal quadrant locations GMCH ballout. does represent actual ballout. Refer Intel® 82815 Chipset Family: 82815 Graphics Memory Controller (GMCH) with Universal Socket Datasheet actual ballout. Figure GMCH 544-Ball µBGA* Quadrant Layout (Top View)
corner
System
Interface
GMCH
Display Cache
System
Video
Quad_GMCH
Intel 815E Chipset Platform Design Guide
Component Layouts
Figure illustrates relative signal quadrant locations ICH2 ballout. does represent actual ballout. Refer Intel® 82801BA Controller (ICH2) Intel® 82801BAM Controller (ICH2-M) Datasheet actual ballout. Figure ICH2 360-Ball EBGA Quadrant Layout (Top View)
interface Processor
ICH2
AC'97
Quad_ICH2
Intel 815E Chipset Platform Design Guide
Component Layouts
Figure Firmware (FWH) Packages
Interface (32-Lead PLCC, 0.450" 0.550") View
Interface (40-Lead TSOP)
pck_fwh.vsd
Intel 815E Chipset Platform Design Guide
Component Layouts
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Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Universal Motherboard Design
Universal Motherboard Definition Details
universal socket platform supports Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) well future 0.13 micron socket processors. Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) have different requirements functioning properly platform than future 0.13 micron socket processors. necessary understand these differences they affect design platform. Refer Table through
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Table high-level description differences that require additional circuitry motherboard. Specific details implementing this circuitry discussed further this chapter. detailed description differences between Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), future 0.13 micron socket processor pins, refer Section 5.4. Table Processor Considerations Universal Motherboard Design
Signal Name Number Function Intel® Pentium® Processor (CPUID=068xh) Intel® CeleronProcessor (CPUID=068xh) Function Future 0.13 Micron Socket Processors Implementation Universal Socket Design
AF36
connect
Addition circuitry that generates processor identification signal used configure board-level operation. Addition switch ground VTT, controlled processor identification signal. Note: must have more than milliohms resistance between source drain.
RESET
Addition stuffing option pull-down ground, which lets designer prevent future 0.13 micron socket processors from being used with incompatible stepping Intel® 82815 GMCH. Addition resistor-divider network provide 1.0V, which will satisfy voltage tolerance requirements Intel® Pentium® processor (CPUID=068xh) Intel® Celeronprocessor (CPUID=068xh) well future 0.13 micron socket processors. Addition switch provide proper voltage, controlled processor identification signal. Addition resistor-divider network provide 2.1V, which will satisfy voltage tolerance requirements Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) well future 0.13 micron socket processors. Modification generation circuit switch between 1.5V 1.25V, controlled processor identification signal.
AK22
GTL_REF
VCMOS_REF
PICCLK
Requires 2.5V
Requires 2.0V
PWRGOOD
Requires 2.5V
Requires 1.8V
Requires 1.5V
Requires 1.25V
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Signal Name Number
Function Intel® Pentium® Processor (CPUID=068xh) Intel® CeleronProcessor (CPUID=068xh) used
Function Future 0.13 Micron Socket Processors
Implementation Universal Socket Design
VTTPWRGD
Input signal future 0.13 micron socket processors indicate that signals stable
Addition VTTPWRGD generation circuit.
Table GMCH Considerations Universal Motherboard Design
Name/Number SMAA[12] Issue strap required determining Intel Pentium Processor (CPUID=068xh) Intel® CeleronProcessor (CPUID=068xh) Future 0.13 micron socket processors
Implementation Universal Socket Design Addition switch controlled processor identification signal.
Table ICH2 Considerations Universal Motherboard Design
Signal PWROK Issue GMCH Intel® CK-815 must sample BSEL[1:0] until VTTPWRGD asserted. ICH2 must initialize before Intel CK-815 clocks stabilize. Implementation Universal Motherboard Design Addition circuitry have VTTPWRGD gate PWROK from power supply ICH2. ICH2 will hold GMCH reset until VTTPWRGD asserted plus time delay allow Intel CK-815 clocks stabilize.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Table Clock Synthesizer Considerations Universal Motherboard Design
Signal Issue Intel® CK-815 does support VTTPWRGD Implementation Universal Motherboard Design Addition switch that supplies power only when VTTPWRGD asserted. Note: must have more than milliohms resistance between source drain.
4.2.1
Processor Design Requirements
Universal Motherboard Design With Incompatible GMCH
universal socket design intended with Intel® chipset platform with universal socket 370. universal socket design populated with earlier stepping GMCH compatible with future 0.13 micron socket processors and, used, will cause eventual failure these processors. prevent future 0.13 micron socket processor from being used with incompatible stepping GMCH, recommendation site pull-down ground processor AJ3. This RESET# signal future 0.13 micron socket processors and, populating resistor, these future processors will prevented from functioning when placed board with incompatible stepping GMCH. Pentium (CPUID=068xh) Celeron (CPUID=068xh) processors will continue boot normally. populating resistor will allow future 0.13 micron socket processors boot. Refer Figure example implementation.
Figure Future 0.13 Micron Socket Processor Safeguard Universal Motherboard Designs Using GMCH
Future 0.13 Micron Socket Processors
Tual_pin_aj3
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
4.2.2
Identifying Processor Socket
platform configure requirements processor socket, must first identify whether processor Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), future 0.13 micron socket processors. AF36 ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh); AF36 unconnected future 0.13 micron Socket processors. Referring Figure platform uses detect circuit connected this processor pin. future 0.13 micron Socket processor present socket, TUAL5 reference schematic signal will pulled rail TUAL5# reference schematic signal will pulled ground. Otherwise, Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), TUAL5 reference schematic signal will pulled ground TUAL5# will pulled rail.
Figure Processor Detect Mechanism Socket/TUAL5 Generation Circuit
VCC5
VCC5
TUAL5 MOSFET
Processor AF36
TUAL5#
Proc_Detect_815E_B0
4.2.3
Setting Appropriate Processor Level
Because Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), future 0.13 micron socket processors require different levels, platform must able provide appropriate voltage level after determining which processor socket. Referring Figure TUAL5 reference schematic signal serves control FET, doing determines whether voltage regulator supplies 1.25V 1.5V AGTL AGTL+, respectively.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Figure Selection Switch
VCC3_3
LT1587-ADJ Vout 49.9 Tantalum
SFET TUAL5
Vtt_Sel_Sw_815E_B0
4.2.4
Processor
Processor requires additional attention since ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) future 0.13 micron socket processor. separate switch controlled TUAL5 reference schematic signal determines whether pulled ground VTT. Refer Figure example implementation.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Figure Switching
TUAL5 Processor
Note: have than illiohm resistance between source drain.
AG1_Switch_815E_B0
4.2.5
Identifying Processor GMCH
GMCH determines whether socket contains future 0.13 micron socket processor Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) based input SMAA12 GMCH. system using future 0.13 micron socket processors, SMAA12 will pulled down during reset indicate GMCH that future 0.13 micron socket processor socket. Refer Figure implementation example.
Figure Processor Identification Strap GMCH
SMAA[12]
TUAL5
Proc_ID_Strap_815E_B0
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Table provides logic decoding determine which processor installed PGA370 design. Table Determining Installed Processor Hardware Mechanisms
Processor AF36 Hi-Z CPUPRES# Notes Future 0.13 micron socket processor installed. Intel® Pentium® processor (CPUID=068xh) Intel® Celeronprocessor (CPUID=068xh) installed. processor installed.
4.2.6
Configuring Non-VTT Processor Pins
When asserted, VTTPWGRD signal must level-shifted properly drive gating circuitry Intel® CK-815. Furthermore, while VTTPWRGD signal connected VTTPWRGD future 0.13 micron socket processor, Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) that same ground. provide proper functionality, resistor must placed series between circuitry that generates signal VTTPWRGD processor VTTPWRGD. Refer Figure example implementation. Voltage regulators that generate standard VTTPWRGD signal available.
Figure VTTPWRGD Configuration Circuit
VCC12
VCC5
VTTPW
BAT54C VCC5
VCC5 V1_8SB
ASSERTED V1_8SB
MOSFET
VTTPW
VCC5
MOSFET
LM393
LM393 VTTPW RGD5#
delay inal
onfig_815E_B0
NOTE:
diode included that repeated pressing reset power button does cause capacitor build enough charge circumvent delay.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
4.2.7
VCMOS Reference
previous platforms supporting Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), VCMOS generated same power plane VTT. future 0.13 micron socket processors generate VCMOS, universal platform required generate this separately motherboard. Processor AK22, which GTL_REF Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), been changed VCMOS_REF future 0.13 micron socket processors. Referring Figure network resistors capacitor must added that this operates appropriately whichever processor socket.
Figure GTL_REF/VCMOS_REF Voltage Divider Network
Processor AK22
GTL_CMOS_Ref_815E_B0
4.2.8
Processor Signal PWRGOOD
processor signal PWRGOOD specified different voltage levels depending whether Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), whether future 0.13 micron socket processor. there overlap between ranges accepted voltage levels these processor groups, resistor divider network that provides 2.1V will satisfy requirements supported processors. Figure example implementation.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Figure Resistor Divider Network Processor PWRGOOD
VCC2_5
RGOOD from ICH2
RGOOD Processor
RGOO D_Divider_815E_B0
4.2.9
APIC Clock Voltage Switching Requirements
processor's APIC clock also specified different voltage levels depending whether Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) whether future 0.13 micron socket processor. There overlap range accepted voltage levels processor groups, voltage switch required ensure proper operation. Figure shows example implementation.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Figure Voltage Switch Processor APIC Clock
IOAPIC
APICCLK_CPU
TUAL5
MOSFET
API_CLK_SW _815E_B0
NOTE:
resistor represents series resistor typically used connecting APIC clock processor.
4.2.10
GTLREF Topology Layout
platform supporting future 0.13 micron socket processors, voltage requirements GTLREF different processor chipset. GTLREF processor specified VTT, while GTLREF chipset VTT. This difference requires that separate resistor sites added layout split GTLREF sources. universal motherboard design, Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) will unaffected difference GTLREF. recommended GTLREF circuit topology shown Figure
Note: stepping GMCH used with universal motherboard design, GTLREF GMCH should VTT. This requires changing 63.4 resistor GMCH side
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Figure GTLREF Circuit Topology
63.4
GMCH
Processor
gtlref_circuit
GTLREF Layout Routing Guidelines
Place resistor sites GTLREF generation close GMCH. Route GTLREF with wide trace possible. decoupling capacitor every GTLREF pins processor (four capacitors total). Place close possible (within mils) Socket GTLREF pins. decoupling capacitor each GTLREF pins GMCH (two capacitors total). Place close possible GMCH GTLREF balls. Given higher GTLREF level GMCH, debug test hook should added validation purposes. debug test hook should placed processor signal ADS# consists laying down site pull-up VTT. resistor site should located within mils GMCH, placed close ADS# signal trace possible.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
Power Sequencing Wake Events
addition mechanism identifying processor socket, special handling wake events required Intel chipset platform that support functionality future 0.13 micron socket processors. When wake event triggered, GMCH Intel CK-815 must sample BSEL[1:0] until signal VTTPWRGD asserted. This handled setting following sequence events: Power connected Intel CK-815-compliant clock driver until VTTPWRGD12 asserted. Clocks ICH2 stabilize before power supply asserts PWROK ICH2. There guarantee this will occur implementation previous step relies supply. Thus necessary gate PWROK ICH2 from power supply while Intel CK-815 given sufficient time clocks become stable. amount time required minimum ICH2 takes GMCH reset. GMCH samples BSEL[1:0]. Intel CK-815 will have sampled BSEL[1:0] much earlier.
4.3.1
Gating Intel® CK-815 VTTPWRGD
System designers must ensure that VTTPWRGD signal asserted before Intel CK-815compliant clock driver receives power. This handled having 3.3V rail clock driver gated VTTPWRGD12 reference schematic signal. Unlike previous Intel 815E chipset designs, 3.3V standby rail used power clock because VTTPWRGD12 reference schematic signal will power clock when going into sleep state. Refer Figure example implementation.
Figure Gating Power Intel CK-815
VCC3_3
SFET
RGD12 CK-815
Note: have than illiohm resistance between source drain.
Intel 815E Chipset Platform Design Guide
Universal Motherboard Design
4.3.2
Gating PWROK ICH2
With power being gated Intel CK-815 signal VTTPWRGD12, important that clocks ICH2 stable before power supply asserts PWROK ICH2. clocking power gating circuitry relies supply, there guarantee that these conditions will met. This estimated minimum time delay must added after power connected Intel CK-815 give clock driver sufficient time stabilize. This time delay will gate power supply's assertion PWROK ICH2. After time delay, power supply safely assert PWROK ICH2, with ICH2 subsequently taking GMCH reset. Refer Figure example implementation.
Figure PWROK Gating Circuit ICH2
CK-815 VCC3_3 Note: delay 20ms after CK-815 powered
1.0uF
PWROK
ICH2_PWROK
ICH2_PWROK_GATING
NOTE:
diode included that repeated pressing reset power button does cause capacitor build enough charge circumvent 20ms delay.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
System Design Guidelines
Pentium processor delivers higher performance integrating Level cache into processor running processor's core speed. Pentium processor runs higher core system speeds than previous-generation IA-32 processors while maintaining hardware software compatibility with earlier Pentium processors. Flip Chip-Pin Grid Array (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin Grid Array (FC-PGA) packages using PGA370 socket. This section presents considerations designs capable using Intel 815E universal platform with full range Pentium processors using PGA370 socket.
System Routing Guidelines
following layout guide supports designs using Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), future 0.13 micron socket processors with Intel chipset platform. solution covers system speeds 66/100/133 Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh), future 0.13 micron socket processors. processors must also configured on-die termination.
5.1.1
Initial Timing Analysis
Table lists AGTL/AGTL+ component timings processors Intel 815E universal platform's GMCH defined pins. Note: These timings reference only. Obtain each processor's specifications from respective processor datasheet chipset values from appropriate Intel chipset datasheet.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Table Intel Pentium Processor AGTL/AGTL+ Parameters Example Calculations
Parameters Intel® Pentium® Processor System GMCH Notes
Clock Output maximum (TCO_MAX) Clock Output minimum (TCO_MIN) Setup time (TSU_MIN)
3.25 (for 66/100/133 system speeds) 0.40 (for 66/100/133 system bus) 1.20 BREQ Lines 0.95 other AGTL/AGTL+ Lines 1.20 other AGTL/AGTL+ Lines 66/100
1.05 2.65
Hold time (THOLD)
(for 66/100/133 system speeds)
0.10
NOTES: times nanoseconds. Numbers table reference only. These timing parameters subject change. Check appropriate component documentation valid timing parameter values. TSU_MIN 2.65 assumes that GMCH sees minimum edge rate equal V/ns.
Table contains example AGTL+ initial maximum flight time, Table contains example minimum flight time calculation MHz, uniprocessor system using Pentium processor Intel 815E chipset platform's system bus. Note that assumed values were used clock skew clock jitter. Note: clock skew clock jitter values depend clock components distribution method chosen particular design, must budgeted into initial timing equations appropriate each design. Table Table were derived assuming following: CLKSKEW 0.20 (Note: This assumes that clock driver pin-to-pin skew reduced tying host clock outputs together (i.e., "ganging") clock driver output pins, that clock routing skew system timing budget must assume 0.175 clock driver skew outputs tied together well clock driver that meets Intel CK-815 Clock Synthesizer/Driver Specification.) CLKJITTER 0.250
Intel 815E Chipset Platform Design Guide
System Design Guidelines
respective processor datasheet appropriate Intel chipset platform documentation details clock skew jitter specifications. Exact details regarding host clock routing topology provided with platform design guideline. Table Example TFLT_MAX Calculations
Driver Receiver Period2 TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended TFLT_MAX
Processor GMCH
GMCH Processor
7.50 7.50
3.25
2.65 1.20
0.20 0.20
0.25 0.25
0.40 0.40
1.35
NOTES: times nanoseconds BCLK period 7.50 133.33
Table Example TFLT_MIN Calculations (Frequency Independent)
Driver Receiver THOLD ClkSKEW TCO_MIN Recommended TFLT_MIN
Processor GMCH
NOTE:
GMCH Processor
0.10 1.00
0.20 0.20
0.40 1.05
0.10 0.15
times nanoseconds
flight times Table include margin account following phenomena that Intel observed when multiple bits switching simultaneously. These multi-bit effects adversely affect flight time signal quality sometimes accounted during simulation. Accordingly, maximum flight times depend baseboard design, additional adjustment factors margins recommended. push-out pull-in Rising falling edge rate degradation receiver caused inductance current return path, requiring extrapolation that causes additional delay Crosstalk inside package which cause variation signals Additional effects exist that necessarily covered multi-bit adjustment factor should budgeted appropriate baseboard design. These effects included MADJ example calculations Table Examples include: effective board propagation constant (SEFF), which function Dielectric constant material Type trace connecting components (stripline microstrip) Length trace load components trace. Note that board propagation constant multiplied trace length component flight time, necessarily equal flight time.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
General Topology Layout Guidelines
Figure Topology 370-Pin Socket Designs with Single-Ended Termination (SET)
PGA370 Socket
sys_bus_topo_PGA370
Table Trace Guidelines Figure
Description
Min. Length (inches)
Max. Length (inches)
GMCH PGA370 socket trace
1.90
4.50
NOTES: AGTL/AGTL+ signals should referenced ground plane entire route. intragroup AGTL/AGTL+ spacing line width dielectric thickness ratio least 2:1:1 microstrip geometry. 4.5, this should limit coupling 3.4%. example, intragroup AGTL+ routing could spacing, traces, prepreg between signal layer plane references (assuming 4-layer motherboard design). recommended trace width mils, greater than mils.
Table contains trace width: space ratios assumed this topology. Three types crosstalk considered this guideline: Intragroup AGTL/AGTL+, Intergroup AGTL/AGTL+, AGTL/AGTL+ non-AGTL/AGTL+. Intragroup AGTL/AGTL+ crosstalk involves interference between AGTL/AGTL+ signals within same group. Intergroup AGTL/AGTL+ crosstalk involves interference from AGTL/AGTL+ signals particular group AGTL/AGTL+ signals different group. example AGTL/AGTL+ non-AGTL/AGTL+ crosstalk when CMOS AGTL/AGTL+ signals interfere with each other. AGTL/AGTL+ signals consist following groups: data signals, control signals, clock signals, address signals. Table Trace Width:Space Guidelines
Crosstalk Type Trace Width:Space Ratios1,
Intragroup AGTL/AGTL+ signals (same group AGTL/AGTL+) Intergroup AGTL/AGTL+ signals (different group AGTL/AGTL+) AGTL/AGTL+ System Memory Signals AGTL/AGTL+ non-AGTL/AGTL+
NOTES: Edge-to-edge spacing. Units mils.
5:10 6:12 5:15 6:18 5:30 6:36 5:25 6:24
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.2.1
Motherboard Layout Rules AGTL/AGTL+ Signals
Ground Reference
strongly recommended that AGTL/AGTL+ signals routed signal layer next ground layer (referenced ground). important provide effective signal return path with inductance. best signal routing directly adjacent solid plane with splits cuts. Eliminate parallel traces between layers separated power ground plane. signal through routing layers, recommendations are: Note: Following these layout rules critical AGTL/AGTL+ signal integrity, particularly 0.18 micron smaller process technology. signals going from ground reference power reference, capacitors between ground power near vias provide return path. capacitor should used every three signal lines that change reference layers. Capacitor requirements follows: C=100nF, ESR=80m, ESL=0.6nH. Refer Figure example switching reference layers. signals going from ground reference another, separate ground reference, vias between ground planes provide better return path.
Figure AGTL/AGTL+ Trace Routing
GMCH Layer Layer
0-500 mils 1.5-3.5 inches
Processor 1.2V Power Plane Ground Plane Socket
AGTL_trace_route
Reference Plane Splits
Splits reference planes disrupt signal return paths increase overshoot/undershoot significantly increased inductance.
Processor Connector Breakout
strongly recommended that AGTL/AGTL+ signals traverse multiple signal layers. Intel recommends breaking signals from connector same layer. routing tight, break from connector opposite routing layer over ground reference cross over main signal layer near processor connector.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Minimizing Crosstalk
following general rules minimize impact crosstalk high-speed AGTL/AGTL+ design: Maximize space between traces. Where possible, maintain minimum mils (assuming trace) between trace edges. necessary tighter spacing when routing between component pins. When traces must close parallel each other, minimize distance that they close together maximize distance between sections when spacing restrictions relaxed. Avoid parallelism between signals adjacent layers, there reference plane between them. rule thumb, route adjacent layers orthogonally. Since AGTL/AGTL+ low-signal-swing technology, important isolate AGTL/AGTL+ signals from other signals least mils. This will avoid coupling from signals that have larger voltage swings (e.g., PCI). AGTL/AGTL+ signals must well isolated from system memory signals. AGTL/AGTL+ signal trace edges must least mils from system memory trace edges within mils ball Intel 82815 GMCH. Select board stack-up that minimizes coupling between adjacent signals. Minimize nominal characteristic impedance within AGTL/AGTL+ specification. This done minimizing height trace from reference plane, which minimizes crosstalk. Route AGTL/AGTL+ address, data, control signals separate groups minimize crosstalk between groups. Keep least mils between each group signals. Minimize dielectric used system. This makes traces closer their reference plane thus reduces crosstalk magnitude. Minimize dielectric process variation used fabrication. Minimize cross-sectional area traces. This done means narrower traces and/or using thinner copper, trade-off this smaller cross-sectional area higher trace resistivity, which reduce falling-edge noise margin because loss along trace.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.2.1.1
Motherboard Layout Rules Non-AGTL/AGTL+ (CMOS) Signals
Table Routing Guidelines Non-AGTL/AGTL+ Signals
Signal Trace Width Spacing Other Traces Trace Length
A20M# FERR# FLUSH# IERR# IGNNE# INIT# LINT[0] (INTR) LINT[1] (NMI) PICD[1:0] PREQ# PWRGOOD SLP# SMI# STPCLK THERMTRIP#
NOTE:
mils mils mils mils mils mils mils mils mils mils mils mils mils mils mils
mils mils mils mils mils mils mils mils mils mils mils mils mils mils mils
Route these signals layer combination layers.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.2.1.2
THRMDP THRMDN
These traces (THRMDP THRMDN) route processor's thermal diode connections. thermal diode operates very currents susceptible crosstalk. traces should routed close together reduce loop area inductance.
Figure Routing THRMDP THRMDN
Signal
Maximize (min. mils)
THRMDP
Minimize
THRMDN
Maximize (min. mils)
Signal
bus_routing_thrmdp-thrmdn
NOTES: Route these traces parallel equalize lengths within inch. Route THRMDP THRMDN same layer.
5.2.1.3
Additional Routing Placement Considerations
Distribute with wide trace. 0.050 inch minimum trace recommended minimize losses. Route trace components host bus. sure include decoupling capacitors. voltage should 1.5V static conditions, 1.5V worst-case transient conditions when Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) present socket. future 0.13 micron socket processor being used, voltage should then 1.25V static conditions, 1.25V worst-case transient conditions. Place resistor divider pairs VREF generation GMCH component. VREF also delivered processor.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Electrical Differences Universal PGA370 Designs
There several electrical changes between previous PGA370 designs universal PGA370 design, follows: Changes PGA370 socket definitions. Addition VTTPWRGD signal ensure stable selection future 0.13 micron socket processors. Addition THERMTRIP circuit allow processor detect catastrophic overheat. Addition VID[25mV] signal support future 0.13 micron socket processors. Processor level switchable 1.25V 1.5V, depending which processor present socket. designs using future 0.13 micron socket processors, processor does generate VCMOS_REF.
5.3.1
THERMTRIP Circuit
ensure that processor detects prevents catastrophic overheat, THERMTRIP required designs that support future 0.13 micron socket processors. Figure offers possible implementation that makes Power Button feature ICH2.
Figure Example Implementation THERMTRIP Circuit
1.8V 1.5V Therm trip# _ON#
CPU_RST#
Thermstrip_2
NOTES: pull-up voltage collector required 1.8V derived from 3.3V source. THERMTRIP valid until after CPU_RST# deasserted. This handled gating assertion THERMTRIP with CPU_RST#. Using CPU_RST# this manner minimal impact signal quality. THERMTRIP must higher than VccCMOS levels. pull-up THERMTRIP connected 1.5V. CPU_RST# must gate SW_ON# from ground. This prevents glitching SW_ON# during power-up power-down. resistance base transistor gating CPU_RST# must least proper levels CPU_RST#.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.3.1.1
THERMTRIP Timing
When THERMTRIP signal asserted, both supplies processor must turned prevent thermal runaway processor. time required from THERMTRIP asserted rail nominal THERMTRIP asserted rail nominal System designers must ensure that decoupling scheme used these rails does violate THERMTRIP timing specifications.
PGA370 Socket Definition Details
Table compares names functions Intel® processors supported Intel 815E universal platform.
Table Processor Definition Comparison
Name Intel® CeleronProcessor (CPUID=068xh) Name Intel® Pentium® Processor (CPUID=068xh) Name Future 0.13 Micron Socket Processors Function
AA33 AA35 AB36
Reserved Reserved VCCCMOS
VCCCMOS
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage CMOS voltage level Intel® Pentium® processor (CPUID=068xh) Intel® Celeronprocessor (CPUID=068xh). AGTL termination voltage future 0.13 micron socket processors.
AD36
VCC1.5
VCC1.5
VCC1.5 Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). future 0.13 micron socket processors.
AF36
Ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). connect future 0.13 micron socket processors.
AG11
Ground Pentium processor (CPUID=068xh) Celeronprocessor (CPUID=068xh). future 0.13 micron socket processors
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Name Intel® CeleronProcessor (CPUID=068xh)
Name Intel® Pentium® Processor (CPUID=068xh)
Name Future 0.13 Micron Socket Processors
Function
Reserved
RESET#
RESET#
Processor reset Pentium processor (068xh) Future 0.13 micron socket processors AGTL/AGTL+ termination voltage Ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). RESET future 0.13 micron socket processors
AH20 AJ31
Reserved
RESET
VTTPWRGD
Ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). control signal future 0.13 micron socket processors.
AK16 AK22
Reserved GTL_REF
GTL_REF
VCMOS_REF
AGTL/AGTL+ termination voltage reference voltage Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). CMOS reference voltage future 0.13 micron socket processors
AK36
VID[25mV]
Ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). 25mV step select future 0.13 micron socket processors
AL13 AL21
Reserved Reserved
DYN_OE
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage Ground Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). Dynamic output enable future 0.13 micron socket processors
AN11
Reserved
AGTL/AGTL+ termination voltage
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Name Intel® CeleronProcessor (CPUID=068xh)
Name Intel® Pentium® Processor (CPUID=068xh)
Name Future 0.13 Micron Socket Processors
Function
AN15 AN21
Reserved Reserved Reserved Reserved Reserved
Reserved
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage Reserved Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). AGTL termination voltage future 0.13 micron socket processors
N372
NCHCTRL
connect Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). NCHCTRL future 0.13 micron socket processors
Reserved Reserved Reserved Reserved Reserved RESET#
A34# RESET2#
A34#
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage Additional AGTL/AGTL+ address Processor reset Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). Ground future 0.13 micron socket processors
X342
Reserved VCCCORE
A32# VCCCORE
A32#
Additional AGTL/AGTL+ address Reserved Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). AGTL termination voltage future 0.13 micron socket processors
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Name Intel® CeleronProcessor (CPUID=068xh)
Name Intel® Pentium® Processor (CPUID=068xh)
Name Future 0.13 Micron Socket Processors
Function
Reserved
Reserved
Reserved Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). connect future 0.13 micron socket processors
Z362
Reserved VCC2.5
CLKREF VCC2.5
CLKREF
1.25V reference VCC2.5 Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). connect future 0.13 micron socket processors
NOTES: Refer Section Refer Section 14.2
Intel 815E Chipset Platform Design Guide
System Design Guidelines
BSEL[1:0] Implementation Differences
future 0.13 micron socket processor will select system frequency setting from clock synthesizer. Pentium processor (CPUID=068xh) utilizes BSEL1 select either system frequency setting from clock synthesizer. Celeron processor (CPUID=068xh) will both BSEL pins select system frequency from clock synthesizer. Processors FC-PGA FC-PGA2 3.3V tolerant these signals, clock chipset. Intel CK-815 been designed support selections MHz, MHz, MHz. input been redefined frequency selection strap (BSEL1) during power-on then becomes reference clock output. Figure details BSEL[1:0] circuit design universal PGA370 designs. Note that BSEL[1:0] pulled using resistors. Also refer Figure more details. Note: design supporting future 0.13 micron socket processors, BSEL[1:0] lines valid until VTTPWRGD asserted. Refer Section full details.
Figure BSEL[1:0] Circuit Implementation PGA370 Designs
3.3V 3.3V Processor
BSEL0
BSEL1
Clock Driver
Chipset
sys_ bus_BSEL_PG A370
Intel 815E Chipset Platform Design Guide
System Design Guidelines
CLKREF Circuit Implementation
CLKREF input (used Pentium processor (CPUID=068xh), Celeron processor (CPUID=068xh), future 0.13 micron socket processors) requires 1.25V source. generated from voltage divider VCC2.5 VCC3.3 sources utilizing tolerant resistors. decoupling capacitor should included this input. Figure Table example CLKREF circuits. source this reference!
Figure Examples CLKREF Divider Circuit
Vcc2.5
PGA370 CLKREF
Vcc3.3
PGA370 CLKREF
sys_bus_CLKREF_divider
Table Resistor Values CLKREF Divider (3.3V Source)
CLKREF Voltage
1.243 1.243 1.226 1.242
Undershoot/Overshoot Requirements
Undershoot overshoot specifications become more critical process technology microprocessors shrinks thinner gate oxide. Violating these undershoot overshoot limits will degrade life expectancy processor. Pentium processor (CPUID=068xh), Celeron processor (CPUID=068xh), future 0.13 micron socket processors have more restrictive overshoot undershoot requirements system signals than previous processors. These requirements stipulate that signal output driver buffer input receiver buffer must exceed maximum absolute overshoot voltage limit minimum absolute undershoot voltage limit. Exceeding either these limits will damage processor. There also time-dependent, non-linear overshoot undershoot requirement that depends amplitude duration overshoot/undershoot. appropriate processor datasheet more details processor overshoot/undershoot specifications.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Processor Reset Requirements
Universal PGA370 designs must route AGTL/AGTL+ reset signal from chipset pins processor well debug port connector. This reset signal connected following pins PGA370 socket: (RESET#). reset signal connected this Pentium processor (CPUID=068xh), Celeron processor (CPUID=068xh), future 0.13 micron socket processors (Reset2# GND, depending processor). RESET2# Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh). future 0.13 micron socket processors. additional resistor connected series with reset circuitry since ground future 0.13 micron socket processors. Note: AGTL/AGTL+ reset signal must always terminate motherboard. Designs that support debug port will utilize series resistor connection RESET# debug port connector. RESET2# required platforms that support Intel® Celeronprocessor (CPUID=068xh). should then connected ground. routing rules AGTL/AGTL+ reset signal shown Figure
Figure RESET#/RESET2# Routing Guidelines
lenITP
cs_rtt_stub
Daisy chain cpu_rtt_stub
Chipset lenCS lenCPU
Processor
sys_bus_reset_routin
Table RESET#/RESET2# Routing Guidelines (see Figure
Parameter Minimum (in) Maximum (in)
LenCS LenITP LenCPU cs_rtt_stub cpu_rtt_stub
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Processor Filter Recommendations
Intel® PGA370 processors have internal phase lock loop (PLL) clock generators that analog require quiet power supplies minimize jitter.
5.9.1
Topology
general desired topology these PLLs shown Figure shown parasitic routing local decoupling capacitors. Excluded from external circuitry parasitics associated with each component.
5.9.2
Filter Specification
function filter protect from external noise through low-pass attenuation. low-pass specification, with input VCCCORE output measured across capacitor, follows: gain pass band attenuation pass band (see drop next requirements) attenuation from attenuation from core frequency filter specification graphically shown Figure
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Figure Filter Specification
0.2dB -0.5 Forbidden Zone
Forbidden Zone -28dB
-34dB
passband
fpeak
fcore
high frequency band
filter_spec
NOTES: Diagram scale. specification frequencies beyond fcore. fpeak should less than 0.05 MHz.
Other requirements: shielded-type inductor minimize magnetic pickup. Filter should support current voltage drop from PLL1 should which practice implies series This also means pass-band (from attenuation 0.35
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.9.3
Recommendation Intel Platforms
following tables contains examples components that meet Intel's recommendations when configured topology Figure
Table Component Recommendations Inductor
Part Number Value Tolerance Rated Current (Typical)
MLF2012A4R7KT Murata LQG21N4R7K00T1 Murata LQG21C4R7N00
0.56 max.) (±50%) max.
Table Component Recommendations Capacitor
Part Number Value Tolerance
Kemet T495D336M016AS TPSD336M020S0200
0.225
Table Component Recommendation Resistor
Value Tolerance Power Note
1/16
Resistor implemented with trace resistance, which case discrete needed. Figure
satisfy damping requirements, total series resistance filter (from VCCCORE plate capacitor) must least 0.35 This resistor form discrete component routing both. example, chosen inductor minimum 0.25 then routing resistance least 0.10 required. careful exceed maximum resistance rule example, using discrete 1%), maximum (trace plus inductor) should less than which precludes some inductors sets max. trace length. Other routing requirements: capacitor should close PLL1 PLL2 pins, route. These routes count towards minimum damping requirement. PLL2 route should parallel next PLL1 route (i.e., minimize loop area). inductor should close routing resistance should inserted between VCCCORE discrete resistor should inserted between VCCCORE
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Figure Example Filter Using Discrete Resistor
CORE Discrete resistor Processor PLL2
<0.1 route
PLL1
<0.1 route
PLL_filter_1
Figure Example Filter Using Buried Resistor
CORE race resistance Processor PLL2
<0.1 route
PLL1
<0.1 route
PLL_filter_2
5.9.4
Custom Solutions
long designers satisfy filter performance requirements specified outlined Section 5.9.2, other solutions acceptable. Custom solutions should simulated against standard reference core model, which shown Figure
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Figure Core Reference Model
PLL1 Processor
PLL2
sys_bus_core_ref_model
NOTES: resistors represent package routing. capacitor represents internal decoupling capacitor. resistor represents small signal resistance. sure include component routing parasitics. Sweep across component/parasitic tolerances. observe drop, current minimum VCCCORE level. other modules (interposer, DMM, etc.), adjust routing resistor desired, minimum numbers.
5.10
Voltage Regulation Guidelines
universal PGA370 design will need voltage regulation module (VRM) on-board voltage regulator (VR) compliant with Intel® guidelines future 0.13 micron processors.
5.11
Decoupling Guidelines Universal PGA370 Designs
These preliminary decoupling guidelines universal PGA370 designs estimated meet specifications Intel guidelines future 0.13 micron processors.
5.11.1
VCCCORE Decoupling Design
Sixteen more capacitors 1206 packages. capacitors should placed within PGA370 socket cavity mounted primary side motherboard. capacitors arranged minimize overall inductance between VCCCORE/VSS power pins, shown Figure
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Figure Capacitor Placement Motherboard
5.11.2
Decoupling Design
(max.) Twenty capacitors 0603 packages placed closed possible processor pins. capacitors shown exterior Figure
5.11.3
VREF Decoupling Design
Four capacitors 0603 package placed near VREF pins (within mils).
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.12
5.12.1
Thermal Considerations
Heatsink Volumetric Keepout Regions
Current heatsink recommendations only valid supported Celeron Pentium processor frequencies. Figure shows system component keepout volume above socket connector required reference design thermal solution high frequency processors. This keepout envelope provides adequate room heatsink, attach hardware under static conditions well room installation these components socket. heatsink must compatible with Integrated Heat Spreader (IHS) used higher frequency Pentium processors. Figure shows component keepouts motherboard required prevent interference with reference design thermal solution. Note portions heatsink attach hardware hang over motherboard. Adhering these keepout areas will ensure compatibility with Intel boxed processor products Intel enabled third-party vendor thermal solutions high frequency processors. While keepout requirements should provide adequate space reference design thermal solution, systems integrators should check with their vendors ensure their specific thermal solutions within their specific system designs. Please ensure that thermal solutions under analysis comprehend specific thermal design requirements higher frequency Pentium processors. While thermal solutions lower frequency processors require full keepout area, larger thermal solutions will required higher frequency processors, failure adhere guidelines will result mechanical interference.
Intel 815E Chipset Platform Design Guide
System Design Guidelines
Figure Heatsink Volumetric Keepout Regions
Figure Motherboard Component Keepout Regions
Intel 815E Chipset Platform Design Guide
System Design Guidelines
5.13
Debug Port Changes
lower voltage technology employed with newer processors, changes required support debug port. Previously, test access port (TAP) signals used 2.5V logic, case with Celeron processor PPGA package. Pentium processor (CPUID=068xh), Celeron processor (CPUID=068xh), future 0.13 micron socket processors utilize 1.5V logic levels TAP. result, type debug port connecter used universal PGA370 designs dependent processor that currently socket. 1.5V connector mirror image older 2.5V connector. Either connector will into same printed circuit board layout. Only numbers change (Figure 34). Also required, along with connector, In-Target Probe* (ITP) that capable communicating with appropriate logic levels.
Figure Connector Comparison
connector, 104068-3 vertical plug, view
RESET#
connector, 104078-4 vertical receptacle, view
RESET#
sys_bus_TAP_conn
Caution: Pentium processor (CPUID=068xh) Celeron processor (CPUID=068xh) require intarget probe (ITP) compatible with 1.5V signal levels TAP. Previous ITPs were designed work with higher voltages damage processor connected these specified processors. processor datasheet more information regarding debug port.
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System Design Guidelines
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Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
System Memory Design Guidelines
System Memory Routing Guidelines
Ground plane reference system memory signals. provide good current return path limit noise system memory signals, signals should ground referenced from GMCH DIMM connectors from DIMM connector-to-DIMM connector. ground referencing possible, system memory signals should minimum, referenced single plane. single plane referencing possible, stitching capacitors should added more than mils from signal field. System memory signals backside under GMCH without stitching capacitor long trace topside less than mils. Note: Intel recommends that parallel plate capacitor between VCC3.3SUS added account current return path discontinuity (See Decoupling section). .01uf capacitor every system memory signals that switch plane references. more than vias allowed system memory signal. group system memory signals must change layers, field should created decoupling capacitor should added field. route signals middle field, this causes noise generated current return path these signals lead issues these signals (see Figure 35). traces shown layer only. figure shows signals that changing layer signals that changing layer. Note that signals around field create keepout zone where signals that change layer should routed. Figure System Memory Routing Guidelines
route signal middle field that change layers
0.01 capacitor signals that
Stagger vias field avoid power/ground plane because antipad internal layers
sys-mem-route
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
6.2.1
System Memory 2-DIMM Design Guidelines
System Memory 2-DIMM Connectivity
Figure System Memory Connectivity DIMM)
Double-Sided, Unbuffered Pinout without
SCSA[3:2]# SCSA[1:0]#
SCKE[1:0] SCKE[3:2] SCSB[3:2]# SCSB[1:0]# SRAS# SCAS# 82815 SWE# SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SDQM[7:0] SMD[63:0] CK815 DIMM_CLK[3:0] DIMM_CLK[7:4]
Notes: Min. Mbit) Max. Mbit) Max. (128 Mbit)
SMB_CLK SMB_DATA DIMM
sys_mem_conn_2DIMM
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
6.2.2
System Memory 2-DIMM Layout Guidelines
Figure System Memory 2-DIMM Routing Topologies
82815 Topology Topology Topology Topology Topology DIMM DIMM
sys_mem_2DIMM_routing_topo
Table System Memory 2-DIMM Solution Space
Signal Top. Trace (mils) Width Spacing Min. Max. Min. Max. Min. Trace Lengths (inches) Max. Min. Max. Min. Max. Min. Max.
SCS[3:2]# SCS[1:0]# SMAA[7:4] SMAB[7:4]# SCKE[3:2] SCKE[1:0] SMD[63:0] SDQM[7:0] SCAS#, SRAS#, SWE# SBS[1:0], SMAA[12:8,3:0]
1.75
addition meeting spacing requirements outlined Table system memory signal trace edges must least mils from other non-system memory signal trace edge.
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
Figure System Memory Routing Example
sys_mem_routing_ex
NOTE:
Routing this figure example purposes only. does necessarily represent complete correct routing this interface.
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
6.3.1
System Memory 3-DIMM Design Guidelines
System Memory 3-DIMM Connectivity
Figure System Memory Connectivity DIMM)
Double-Sided, Unbuffered Pinout without
SCSA[5:4]# SCSA[3:2]# SCSA[1:0]#
Notes: Min. Mbit) Max. Mbit) Max. (128 Mbit)
SCKE[1:0] SCKE[3:2] SCKE[5:4] SCSB[5:4]# SCSB[3:2]# SCSB[1:0]# SRAS# SCAS#
82815
SWE# SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SMAC[7:4]# SDQM[7:0] SMD[63:0]
DIMM_CLK[3:0] CK815 DIMM_CLK[7:4] DIMM_CLK[11:8] SMB_CLK SMB_DATA DIMM
sys_mem_conn_3DIMM
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
6.3.2
System Memory 3-DIMM Layout Guidelines
Figure System Memory 3-DIMM Routing Topologies
82815 Topology Topology Topology Topology Topology Topology Topology Topology DIMM DIMM DIMM
sys_mem_3DIMM_routing_topo
addition meeting spacing requirements outlined Table system memory signal trace edges must least mils from other non-system memory signal trace edge. Table System Memory 3-DIMM Solution Space
Signal Top. Trace (mils) Width Spacing Min. Max. Min. Max. Min. Max. Min. Trace Lengths (inches) Max. Min. Max. Min. Max. Min. Max.
SCS[5:4]# SCS[3:2]# SCS[1:0]# SMAA[7:4] SMAB[7:4]# SMAC[7:4} SCKE[5:4] SCKE[3:2] SCKE[1:0] SMD[63:0] SDQM[7:0] SCAS#,SRAS#, SWE#
SBS[1:0], SMAA[12:8,3:0]
1.75
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
System Memory Decoupling Guidelines
minimum eight low-ESL ceramic capacitors (e.g., 0603 body type, dielectric) required must close possible GMCH. They should placed within most mils edge GMCH package edge VSUS_3.3 decoupling, they should evenly distributed around system memory interface signal field including side GMCH where system memory interface meets host interface. There power balls throughout system memory ball field GMCH that need good local decoupling. Make sure least drilled vias wide traces from pads capacitor power ground plane create inductance path. possible multiple vias capacitor recommended further reduce inductance. decoupling capacitors within mils GMCH and/or close vias, trace spacing reduced traces around each capacitor. narrowing space between traces should minimal short distance possible (500mils max). further de-couple GMCH provide solid current return path system memory interface signals recommended that parallel plate capacitor added under GMCH. topside bottom side copper flood under center GMCH create parallel plate capacitor between VCC3.3 (see Figure 41). dashed lines indicate power plane splits layer layer depending stack-up. filled region middle GMCH indicates ground plate layer power plane layer layer power layer layer
Figure Intel Chipset Platform Decoupling Example
Intel 815E Chipset Platform Design Guide
System Memory Design Guidelines
Yellow lines show layer plane splits. Note that layer shapes cross plane splits. bottom shape fill over VddSDRAM. left-side shape fill over VddAGP. larger upper-right-side shape fill over VddCORE. Additional decoupling capacitors should added between DIMM connectors provide current return path reference plane discontinuity created DIMM connectors themselves. 0.01 capacitor should added every SDRAM signals. Capacitors should placed between DIMM connectors evenly spread across SDRAM interface. debug purposes, four more 0603 capacitor sites should placed backside board, evenly distributed under Intel 815E chipset platform's system memory interface signal field. Figure Intel Chipset Decoupling Example
Compensation
system memory compensation resistor (SRCOMP) used GMCH adjust buffer characteristics specific board operating environment characteristics. Refer Intel® Chipset Family: 82815 Graphics Memory Controller (GMCH) with Universal Socket Datasheet details compensation. SRCOMP GMCH pull-up resistor Vsus (3.3V standby) mil-wide, inch trace (targeted nominal impedance
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
AGP/Display Cache Design Guidelines
detailed interface functionality (e.g., protocols, rules, signaling mechanisms), refer latest Interface Specification, Revision 2.0, which obtained from http://www.agpforum.org. This design guide focuses only specific Intel chipset platform recommendations.
Interface
single connector supported GMCH interface. LOCK# SERR#/PERR# supported. display cache discussion description display cache/AGP muxing well description Graphics Performance Accelerator (GPA). buffers operate selectable modes, support universal connector: 3.3V drive, safe. This mode compliant with specification 1.5V drive, 3.3V safe. This mode compliant with specification must operate only differential clocking mode. operate interface supports signaling, though fast writes supported. semantic cycles DRAM snooped host bus. GMCH supports PIPE# SBA[7:0] address mechanisms, both simultaneously. Either PIPE# SBA[7:0] mechanism must selected during system initialization. GMCH contains 32-deep request queue. High-priority accesses supported. semantic accesses hitting graphics aperture pass through address translation mechanism with fully-associative, 20-entry TLB. Accesses between interface limited interface-originated memory writes AGP. Cacheable accesses from queue flow through path, while aperture accesses follow another path. Cacheable (SBA, PIPE#, FRAME#) reads DRAM snoop cacheable global write buffer (GWB) system data coherency. Aperture (SBA, PIPE#) reads DRAM snoop aperture queue (GCMCRWQ). Aperture (FRAME#) reads writes DRAM proceed through FIFO there capability, snoop required. interface clocked from clock (3V66). AGP-to-host/memory interface synchronous with clock ratio MHz: MHz), MHz: MHz) MHz: MHz).
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
7.1.1
Graphics Performance Accelerator (GPA)
GMCH multiplexes signal interface with integrated graphics' display cache interface. result, universal motherboard that supports both integrated graphics addin video cards, display cache (for integrated graphics) must populated card universal slot. card called Graphics Performance Accelerator (GPA) card. Intel provides specification this card separate document (Graphics Performance Accelerator Specification). guidelines presented this section motherboards that support population card their slot well those that not, "down" implementations which AGP-compliant devices implemented directly motherboards. Where there distinct guidelines dependent whether motherboard will support card, section detailing standard routing guidelines divided into subsections, follows: Flexible Motherboard Guidelines subsection complied with motherboard supports card populated slot. AGP-Only Motherboard Guidelines subsection complied with motherboard does support card populated slot.
7.1.2
Universal Retention Mechanism (RM)
Environmental testing field reports indicate that cards Graphics Performance Accelerator (GPA) cards come unseated during system shipping handling without proper retention. avoid disengaged cards modules, Intel recommends that AGP-based platforms retention mechanism (RM). mounting bracket that used properly locate card with respect chassis assist with card retention. available different handle orientations: left-handed (see Figure right-handed. Most system boards accommodate left-handed manufacturing capacity left-handed currently exceeds right-handed capacity, result Intel recommends that customers design their systems insure they left-handed version right-handed identical left-handed except position actuation handle. This handle located same primary design, extends from opposite side (mirrored about center axis running parallel length part). Figure contains keepout information left hand retention mechanism. this information make sure that motherboard design leaves adequate space install retention mechanism. interconnect design requires that card must retained extent that card back more than 0.99 (0.039 within connector. accomplish this recommended that cards implement additional notch feature mechanical keying allow anchor point card interfacing with retention mechanism's round engages with card's retention prevents card from disengaging during dynamic loading. additional notch feature mechanical keying required 1.5Volt cards recommended 3.3Volt cards.
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
Figure Left-Handed Retention Mechanism
Figure Left-Handed Retention Mechanism Keepout Information
Engineering Change Request number (ECR #48) specification details which recommended cards. These approved changes Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends incorporate changes into later revisions Interface Specification. addition, Intel defined reference design mechanical device utilize features defined #48. viewed Intel website
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
More information regarding this component (AGP available from following vendors. Table Retention Mechanism Vendors
Resin Color Supplier Part Number "Left Handed" Orientation (Preferred) "Right Handed" Orientation (Alternate)
Black
Foxconn
136427-1 006-0002-939 009-0004-008
136427-2 006-0001-939 009-0003-008
Green
Foxconn
Rev. Interface Specification enhances functionality original Interface Specification, Revision 1.0, allowing data transfers data samples clock) 1.5V operation. operation interface provides "quad-pumping" (address/data) (side-band addressing) buses. That data sampled four times during each clock, which means that each data cycle MHz) clock, 3.75 Note that 3.75 data cycle time, clock cycle time. During operation, data sampled twice during clock cycle, data cycle time allow such high-speed data transfers, mode operation uses source-synchronous data strobing. During operation, interface uses differential source-synchronous strobing. With data-cycle times small 3.75 setup/hold times propagation delay mismatch critical. addition reducing propagation delay mismatch, important minimize noise. Noise data lines causes settling time long. mismatch between data line associated strobe great there noise interface, incorrect data will sampled. low-voltage operation (1.5 requires even more noise immunity. example, during 1.5V operation, Vilmax Without proper isolation, crosstalk could create signal integrity issues.
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
7.2.1
Interface Signal Groups
signals interface broken into three groups: timing domain signals, 2X/4X timing domain signals, miscellaneous signals. Each group different routing requirements. addition, within 2X/4X timing domain signals, there three sets signals. signals 2X/4X timing domain must meet minimum maximum trace length requirements well trace width spacing requirements. However, trace length matching requirements only must satisfied within each 2X/4X timing domain signals. signal groups listed Table
Table Signal Groups
Groups Signal
Timing Domain 2X/4X Timing Domain
(3.3 RBF#, WBF#, ST[2:0], PIPE#, REQ#, GNT#, PAR, FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#
AD[15:0], C/BE[1:0]#, AD_STB0, AD_STB0# SBA[7:0], SB_STB, SB_STB#
AD[31:16], C/BE[3:2]#, AD_STB1, AD_STB1#
Miscellaneous, async.
USB+, USB-, OVRCNT#, PME#, TYPDET#, PERR#, SERR#, INTA#, INTB#
NOTE:
These signals used mode ONLY.
Table Data/Strobe Associations
Data Associated Strobe Associated Strobe Associated Strobes
AD[15:0] C/BE[1:0]# AD[31:16] C/BE[3:2]# SBA[7:0]
Strobes used mode. data sampled rising clock edges. Strobes used mode. data sampled rising clock edges. Strobes used mode. data sampled rising clock edges.
AD_STB0
AD_STB0, AD_STB0#
AD_STB1
AD_STB1, AD_STB1#
SB_STB
SB_STB, SB_STB#
Throughout this section term data refers AD[31:0], C/BE[3:0]#, SBA[7:0]. term strobe refers AD_STB[1:0], AD_STB[1:0]#, SB_STB, SB_STB#. When term data used, refers three sets data signals, listed Table When term strobe used, refers strobes relates data associated group. routing guidelines each group signals timing domain signals, 2X/4X timing domain signals, miscellaneous signals) will addressed separately.
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
7.3.1
7.3.1.1
Standard Routing Guidelines
Timing Domain Routing Guidelines
Flexible Motherboard Guidelines
timing domain signals (Table have maximum trace length inches motherboards that support Graphics Performance Accelerator (GPA) card. This maximum applies signals listed timing domain signals Table signals multiplexed with display cache signals (listed below) should routed with trace width-to-spacing ratio. other timing domain signals routed with minimum trace separation. There trace length matching requirements timing domain signals. following multiplexed AGP1X signals flexible motherboards: RBF# ST[2:0] PIPE# REQ# GNT# FRAME# IRDY# TRDY# STOP# DEVSEL#
7.3.1.2
AGP-Only Motherboard Guidelines
timing domain signals (Table have maximum trace length inches motherboards that will support Graphics Performance Accelerator (GPA) card. This maximum applies signals listed timing domain signals Table timing domain signals routed with minimum trace separation. There trace length matching requirements timing domain signals.
7.3.2
2X/4X Timing Domain Routing Guidelines
These trace length guidelines apply signals listed Table 2X/4X timing domain signals. These signals should routed using traces. maximum line length length mismatch requirements depend routing rules used motherboard. These routing rules were created provide design freedom making trade-offs between signal coupling (trace spacing) line lengths. maximum length interface defines which routing guidelines must used. Guidelines short interfaces (e.g., inches) long interfaces (e.g., inches 7.25 inches) documented separately. maximum length allowed interface AGP-only motherboards) 7.25 inches.
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
7.3.2.1
Flexible Motherboard Guidelines
motherboards that support either card card slot, maximum length 2X/4X timing domain signals inches. trace width-to-spacing required 2X/4X signal traces. 2X/4X signals must matched with their associated strobe outlined Table 21), within inch. example, strobe signals (e.g., AD_STB0 AD_STB0#) inches long, data signals associated with those strobe signals (e.g., AD[15:0] C/BE[2:0]#) inches inches long (since there inches max. length). Another strobe (e.g., SB_STB SB_STB#) could inches long, that associated data signals (e.g., SBA[7:0]) inches inches long. strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#) clocks source-synchronous interface. Therefore, special care must taken when routing these signals. Since each strobe pair truly differential pair, pair should routed together (e.g., AD_STB0 AD_STB0# should routed next each other). strobes strobe pair should routed using traces with least mils space (1:3) between them. This pair should separated from rest signals (and other signals) least mils (1:4). strobe pair must length-matched less than inch (i.e., strobe complement must same length within inch).
Figure 2X/4X Routing Example Interfaces inches GPA/AGP Solutions
5-mil trace mils 5-mil trace mils 5-mil trace mils 5-mil trace mils 5-mil trace mils
2X/4X signal 2X/4X signal 2X/4X signal 2X/4X signal STB# STB# 2X/4X signal 2X/4X signal 2X/4X signal 2X/4X signal
STB/STB# length Associated 2X/4X data signal length 0.5" Min. 0.5" Max.
AGP_2x-4x_routing
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
7.3.2.2
AGP-Only Motherboard Guidelines
motherboards that will support card populated slot, maximum 2X/4X signal trace length 7.25 inches. However, there different guidelines interfaces shorter than inches (e.g., 2X/4X signals shorter than inches) those longer than inches shorter than 7.25 inches maximum.
Interfaces Shorter Than Inches
following guidelines designs that require less than inches between connector GMCH: trace width-to-spacing required 2X/4X timing domain signal traces. 2X/4X signals must matched with their associated strobe outlined Table 21), within inch. example, strobe signals (e.g., AD_STB0 AD_STB0#) inches long, data signals associated with those strobe signals (e.g., AD[15:0] C/BE[2:0]#) inches inches long. Another strobe (e.g., SB_STB SB_STB#) could inches long, data signals associated with those strobe signals (e.g., SBA[7:0]) could inches inches long. strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#) clocks source-synchronous interface. Therefore, special care must taken when routing these signals. Because each strobe pair truly differential pair, pair should routed together (e.g., AD_STB0 AD_STB0# should routed next each other). strobes strobe pair should routed traces with least mils space (1:3) between them. This pair should separated from rest signals (and other signals) least mils (1:4). strobe pair must length-matched less than inches (i.e., strobe complement must same length, within inches). Refer Table illustration these requirements.
Interfaces Longer Than Inches
Since longer lines have more crosstalk, they require wider spacing between traces reduce skew. following guidelines designs that require more than inches (but less than 7.25 inches max.) between connector GMCH: trace width-to-spacing required 2X/4X timing domain signal traces. 2X/4X signals must matched with their associated strobe outlined Table 21), within 0.125 inches. example, strobe signals (e.g., AD_STB0 AD_STB0#) inches long, data signals associated with those strobe signals (e.g., AD[15:0] C/BE[2:0]#) 6.475 inches 6.625 inches long. Another strobe (e.g., SB_STB SB_STB#) could inches long, data signals associated with those strobe signals (e.g., SBA[7:0]) could 6.075 inches 6.325 inches long. strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#) clocks source-synchronous interface. Therefore, special care must taken when routing these signals. Because each strobe pair truly differential pair, pair should routed together (e.g., AD_STB0 AD_STB0# should routed next each other). strobes strobe pair should routed traces with least mils space (1:4) between them. This pair should separated from rest signals (and other
Intel 815E Chipset Platform Design Guide
AGP/Display Cache Design Guidelines
signals) least mils (1:4). strobe pair must length-matched less than ±0.1 inch (i.e., strobe complement must same length, within inch).
7.3.3
Routing Guideline Consider
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