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PEB20256 Multichannel Newtork Interface Controler HDLC/PPP Munich V2.1
Datacom
Edition 2000-04-01 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 2000.
Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
PEB20256 Multichannel Newtork Interface Controler HDLC/PPP Munich V2.1
Datacom
Munich Revision History: Previous Version: Page Subjects (major changes since last revision) 2000-04-01
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
Application Note M256/F/FM Applications
Table Contents 2.1.1 2.1.2 Page
Introduction MUNICH256/F/FM Architecture MUNICH256 MUNICH256 16-Port Configuration MUNICH256 28-Port Configuration MUNICH256F MUNICH256FM Interfaces Interface Local Interface (LBI) Serial Interface Synchronous Serial Peripheral Interface (SPI) Serial Interface Application Examples MUNICH256 QuadFALC(s) MUNICH256F QuadLIU(s) MUNICH256FM Puccini MUNICH256F with M13FX Puccini MUNICH256F SDH/Sonet Mapper MUNICH256 xDSL Transceiver
System Integration Application Examples Simple Card with/without Local Intelligence Intelligent card with MUNICH256/F/FM (I2O Architecture)
Application Note
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Application Note M256/F/FM Applications
Table Contents Page
Application Note
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Application Note M256/F/FM Applications
List Tables Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Page
MUNICH256 Architecture 16-Port Mode Interface Configuration 16-port Mode Interface Timing 28-Port Mode Interface Configuration 28-Port Mode Interface Timing with Gapped Clocks MUNICH256F Block Diagram MUNICH256FM Block Diagram Simple Multiport T1/E1 Linecard with MUNICH256 QuadFALC(s). Linecard with MUNICH256F QuadLIU Simple Linecard Application with MUNICH256FM PUCCINI. MUNICH256F Fully Channelized Linecard MUNICH256 High Port Density xDSL Solutions Local Microprocessor Layer1 Support Active linecard using Intel i960RD integrated processor
Application Note
2000-04-01
Application Note M256/F/FM Applications
List Tables Page
Application Note
2000-04-01
Application Note M256/F/FM Applications
Introduction
Introduction
This document provides application hints different versions MUNICH256/F/FM typical applications systems. Multichannel Network Interface Controller HDLC MUNICH256/F/FM designed wide area telecommunication data communication applications. This Application Note first summarizes architecture MUNICH256/F/FM described Data Sheet. Then, functions usage various interfaces device benefits several variations provided. This document intended dictate restrictions device, rather give some hints ideas efficient system design effective scaling with MUNICH256/F/FM.
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture
MUNICH256/F/FM Architecture
There three different kinds MUNICH256/F/FM family: MUNICH256, MUNICH256F, MUNICH256FM. These devices afford four configurations: MUNICH256 configured either 16-port 28-port device. MUNICH256F 28-port device containing 28-T1 21-E1 framers addition MUNICH256 core. MUNICH256FM based MUNICH256F concentrates internal 28-T1 21-E1 ports into line built-in multiplexer framer. Note: evaluation purposes, MUNICH256FM setup behave like MUNICH256F MUNICH256. This document first describes MUNICH256, then describes additional features other product family members. This architectural summary intended replace careful study individual data sheets. does, however, provide general overview architecture MUNICH256/F/FM.
MUNICH256
MUNICH256 highly integrated Wide Area Network (WAN) protocol controller that performs High Level Data Link Control (HDLC), Point-to-Point Protocol (PPP), Transparent (TMA) protocol processing full-duplex serial channels configurable port mode with either links. Depending port mode selected, link operated T1/E1, channelized 4.096 MHz/8.192 mode (16-port mode only), unchannelized mode. 16-port mode, system interface consists receive clock input, receive synchronization pulse input, receive data input each receive line. transmit direction, each link consists transmit clock input, transmit synchronization input, transmit data output. Synchronization pulses supported unchannelized mode. 28-port mode, system interface consists receive clock input receive data input. transmit direction, transmit clock input transmit data output provided. Frame boundaries indicated clock gaps. device provides maximum aggregate data rate Mbit/s direction, assuming frequency Mbit/s MHz). following clock rates supported where clock rates does exceed indicated throughput limitations: 16-port mode, clock rates are: mode with 1.544 port. mode with 2.048 port.
Application Note 2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture Channelized mode with 4.096 port. Channelized mode with 8.192 port. Unchannelized mode with Port Unchannelized mode with 8.192 other ports. 28-port mode, clock rates are: mode (1.544 MHz) with gapped clock port. mode (2.048 MHz) with gapped clock port. Unchannelized mode with port zero. Unchannelized mode with 8.192 other ports. interfaces connect device system environment: Rev. compliant interface 16-bit Intel/Motorola style interface. Device configuration channel operation provided through interface. local interface provides access internal mailbox. MUNICH256 supports capability loading subsystem subsystem vendor into configuration space Synchronous Serial Peripheral Interface (SPI) interface.
Figure
MUNICH256 Architecture
2000-04-01
Application Note
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture MUNICH256 several internal functional blocks. internal function blocks direct interconnections data transfer connections configuration inter-module communication (such interrupt buses). core functionality channelized data transmission reception shown right side block diagram Figure interface module works interface between internal configuration data buses. slave mode provides access internal modules device configuration. master mode provides access external memory integrated Data Management Unit (DMU). provides master capability device. this way, device able autonomously packet memory orienting itself descriptor data buffer structures which have been previously setup software. data itself read stored device master accesses (via interface). other side, faces Internal Transmit Receive Buffers which de-couple constant regular data transfer requests from protocol engine towards system. Protocol Handler performs HDLC protocol works transparently mode. Beyond this module, data flow contains protocol-specific overhead (flags, bit-stuffing, etc.). next module then Timeslot Handler. maps timeslot-port pairs logical channels channels) internal tables called timeslot assignment tables. Below Timeslot Assigner (TSA), data handled channel context-it always assigned specific logical channel. Above TSA, data flows port timeslot context. Finally, Port Interface manages synchronization data between interior (running with frequency) serial ports, which operated with applied transmit receive clock respectively. Most functional blocks able generate interrupts. interrupt information centrally transferred Interrupt Controller. This module processes information assigns specific interrupt queues shared memory. interrupt information written 32-bit vector format these circular interrupt queues (the device acts master). slave, Interrupt Controller provides some configuration registers status register containing information about interrupt queues written since last interrupt acknowledge. Some additional peripheral blocks integrated into device: JTAG boundary scan interface interface serial EEPROM Local Interface (LBI) with master/slave capability, mailbox, bridge. serial EEPROM side allows configuration space contents downloaded automatically after RESET. this way, values different from built-in reset values read into configuration space, such Sub-Vendor SubSystem some generic configurations Plug-in Play support, PCI-2-LBI bridging support enable.
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture Local Interface (LBI) 16-bit slave 8/16-bit master interface. slave, provides access registers blocks shown right hand side block diagram Figure (Mailbox, interrupt FIFO, Framer-, M13-Register other MUNICH derivatives). registers accessible from also controlled from interface. Please note that possible control register left side mailbox Figure LBI. Mailbox provides registers direction each 16-bit width communication between host connected LBI. master mode, Local Interface uses bridge functionality Mailbox block. this mode, memory accesses address range defined BAR2 register (PCI Configuration Space) mapped LBI. Both 16-bit accesses possible. this way, peripherals Local interface controlled from side processor without extra side. Note: switch between 16-port 28-port configurations MUNICH256, register (CONF1.16/28) must changed.
2.1.1
MUNICH256 16-Port Configuration
this configuration, MUNICH256 provides sixteen fully functional highway interfaces. Each port three pins direction (transmit/receive): Data, Clock, Frame-Synchronization, total pins port. Table identifies pins: Table Function Data Clock Frame-Sync-Pulse Highway Pins Port Transmit TCLKx TSPx Receive RCLKx RSPx
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture
Figure
16-Port Mode Interface Configuration
clock used define data rate, sample frame sync signals receive data, latch transmit data. transition frame-sync signal from high state specifies beginning frame. Table specifies pins each port 16-port mode Figure shows interface configuration. 16-port mode, there five possible configurations each individual port: frame mode, running nominal 1.544 MBit/s: clock rate 1.544 general applications. However, MUNICH256 allows wide range tolerance this clock needs only fixed relation 1:193 between Frame Sync frequency corresponding clock. this mode, MUNICH256 provides access timeslots frame. frame synchronization pulse also operated multiframe mode, e.g. frame sync pulse applied every 12th 24th frame only. frame mode, running nominal 2.048 MBit/s: clock rate 2.048 general applications. However, MUNICH256 allows wide range tolerance this clock needs only fixed relation 1:256 between Frame Sync frequency corresponding clock. this mode, MUNICH256 provides access timeslots frame. frame synchronization pulse also operated multiframe mode, e.g. frame sync pulse applied every 16th frame only.
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture 4.096 MBit/s frame mode, running nominal 4.096 MBit/s: clock rate 4.096 general applications. However, MUNICH256 allows wide range tolerance this clock needs only fixed relation 1:512 between Frame Sync frequency corresponding clock. this mode, MUNICH256 provides full access timeslots frame each port. 8.192 MBit/s frame mode, running nominal 8.192 MBit/s: clock rate 8.192 general applications. However, MUNICH256 allows wide range tolerance this clock needs only fixed relation 1:1024 between Frame Sync frequency corresponding clock. this mode, MUNICH256 provides full access timeslots frame each port. Unframed (unchannelized) mode, running 8.192 MBit/s: (and MBit/s Port This mode channelized, device does need Frame Sync signal. Furthermore, this mode implemented subset mode, timeslots virtual frame must assigned channel. Figure shows timing MUNICH256 16-port mode.
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture
Figure
16-port Mode Interface Timing
2.1.2
MUNICH256 28-Port Configuration
This configuration provides twenty-eight ports T1/E1 speed unchannelized operation. Unchannelized operation works 16-port mode with only clocks required drive data; framing information needed. modes, device does need framing information. This configuration device does have dedicated Frame Sync Pins; this information encoded clock signal. This done gapping clock position F/DL-Bit mode Timeslot mode. shown Figure each port needs only pins direction: clock data. clocking shown Figure
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture
Figure
28-Port Mode Interface Configuration
Figure
28-Port Mode Interface Timing with Gapped Clocks
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture
MUNICH256F
MUNICH256F contains functional blocks MUNICH256. Additionally, includes T1/E1 framers corresponding Facility Data Link (FDL) controllers. block diagram Munich256F shown Figure blocks logically assigned internal configuration which connected LBI. this way, Framer block registers configured default. bridge Mailbox block also allows configuration these registers from side. multiple buses needed this, duration each configuration cycle (especially read cycles) could increase compared performance LBI.
Figure
MUNICH256F Block Diagram
Logically, framer devices located between interface MUNICH256F line interface. Physically, MUNICH256F uses behavior different from port interface. transmit direction, MUNICH256F maps framing information into data stream. receive direction, obtains received data analysis. framer searches embedded framing information data stream supplies this framing information internally back port interface. this way, external Receive Synchronization Pulse (RSP) signal from MUNICH256F generated internally.
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture Transmit Clocks (TCLKx) Transmit Sync Pulses (TSPx) port derived from common input signals: Common Transmit Clock (CTCLK) Common Transmit Clock (CTFS). Optionally, these signals configured derived from receiver part each single port. Thus, transmitter operates exactly same data rate receiver. data sheet, this special feature called "Looped Timing". Each port configured unchannelized data traffic T1/E1 mode. unchannelized traffic, corresponding framer function. unchannelized feature configured described previous MUNICH256 section. There several limitations ports: Port handle MBit/s Ports 1.15 operate 8.192 MBit/s (based PCI-Clock) Ports 16.27 operate speeds 2.048 MBits/s (based PCI-Clock) build T1/E1 interface, Line Interface Unit (LIU) needed each port. Another possibility building T1/E1 interface would connection multiplexer capable concentrating ports onto SDH/Sonet line onto line. Such multiplexer integrated into MUNICH256FM.
MUNICH256FM
MUNICH256FM contains blocks functional modules MUNICH256F. But, unlike MUNICH256F, MUNICH256FM does provide framed ports directly. Between former port interface pins, multiplexer maps these lines onto stream which then handed over line framer. configuration this Mapper Framer part done from side default. Optionally, bridge function used perform these configurations interface. Block Diagram MUNICH256FM shown Figure Note: test port interface allows break single line testing debugging purposes.
Application Note
2000-04-01
Application Note M256/F/FM Applications
MUNICH256/F/FM Architecture
Figure
MUNICH256FM Block Diagram
Application Note
2000-04-01
Application Note M256/F/FM Applications
Interfaces
Interfaces
MUNICH256/F/FM devices provide Interface, Local Interface, Serial Interface Interface.
Interface
Interface main configuration interface MUNICH256/F/FM. internal registers accessible this interface. slave, device accepts 32-bit wide memory read write cycles. access Local Interface (using PCI-to-LBI bridging feature) only wide accesses accepted. data transmission, device uses Interface master. Therefore, software prepares data buffer transmit receive direction organizes them attachments linked lists descriptors. DMUs (Direct Memory access Units) MUNICH256/F/FM work independently along these descriptors read data from attached buffers write received data these memory sections.
Local Interface (LBI)
Local Interface master slave capabilities configured either Intel Motorola mode. slave mode Interface always bits wide. master mode handle wide cycles. slave mode, interface provides access registers framers, controllers, multiplexer, framer, Mailbox. does allow configuration core registers (such unit, protocol engines, port interface) shown left side block diagrams Figure Figure Figure slave capability allows dedicated control only Layer1 functions. master mode, provides PCI-to-LBI bridging functionality. 16-bit wide memory accesses from memory regions from PCI-ConfigSpace-BAR2 mapped Local Interface. this way, possible control peripherals side from system's main processor side. This helpful, instance low-cost card applications.
Serial Interface
Serial Interface provides either interfaces interface, depending type configuration MUNICH256/F/FM. Appropriate clocks frame sync pulses must provided device. general, there nominal frequency specified clocks common applications. MUNICH256/F/FM some upper limits interface; but, flexible below this limit
Application Note
2000-04-01
Application Note M256/F/FM Applications
Interfaces regarding clock speeds. maximum throughput ranges MUNICH256/F/FM shown Table Table Ports 1.15 16.27 MUNICH256/F/FM Maximum Port Throughput Device Type MUNICH256-16 MUNICH256-28 MUNICH256F MUNICH256FM MBit/s (UC) MBit/s (UC) MBit/s (UC) -8.192 MBit/s (CH) 2.048 MBit/s (CH) 2.048 MBit/s (CH) 8.192 MBit/s(CH) 8.192 MBit/s (UC) 8.192 MBit/s (UC) -2.048 MBit/s (CH) 2.048 MBit/s (CH) -2.048 MBit/s -2.048 MBit/s MBit/s
Unchannelized Port Configuration Channelized Port Configuration
Synchronous Serial Peripheral Interface (SPI)
standard serial EEPROM with compliant interface connected MUNICH256/F/FM. There applications SPI. Each used independently: Plug-in Play Support: After Reset, Configuration Space loaded from serial EEPROM. this way, user assign various card identifications using sub-IDs. General data storage: supports serial EEPROM space bytes. When config space loaded from EEPROM, full bytes used. Otherwise, upper part after PCI-Config Space used data storage.
Application Note
2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples
Serial Interface Application Examples
MUNICH256 QuadFALC(s)
MUNICH256 offers channels which assigned ports. However, there mismatch between these values that using available timeslots independent channels requires more than channels. Running fully channelized ports (each 64-kbit/s timeslot driven channel) allows MUNICH256 supply ports ports. ports used multiple timeslots assigned single channel complete channel driven unchannelized T1/E1 mode support high speed links. order accomplish this, required number QuadFALC devices connected directly highway ports MUNICH256. Control QuadFALC framers done dedicated side. details differences, refer Chapter 5.1.
passive Linecard
Main Processor
Bridge
MUNICH256 PEB20256
Ports
local System
QuadFALC PEB20554
QuadFALC PEB20554
QuadFALC PEB20554
Figure
Simple Multiport T1/E1 Linecard with MUNICH256 QuadFALC(s)
block diagram Figure shows integration passive T1/E1 linecard basic system. This example implementation could used cost-effective Network Interface Controller (NIC) PC-based applications. basic principle that there processor linecard. peripherals card-the QuadFALCs this case-are controlled main processor using PCI-to-LBI bridge integrated into MUNICH256/F/FM. EEPROM used load generic configuration
Application Note 2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples space. This enables manufacturer card provide unique identification board bus. Connection Interface between QuadFALC MUNICH256 accomplished variety approaches: Connect each port QuadFALC separate MUNICH256 ports: main benefit this approach that each port different speed. Thus, slight tolerances T1/E1 data rates will affect other ports SLIP situations QuadFALC Slip Buffer will minimized even eliminated. available speeds used: 1.544 MBit/s only) 2.048 MBit/s, 4.096 MBit/s 8.192 MBit/s channel translation mode QuadFALC). latter ones will subset 64/128 timeslots. Connect four ports QuadFALC port MUNICH256: main benefit this implementation minimized connections between MUNICH256 QuadFALC devices minimized number ports used MUNICH256. highway configured 8.192 MBit/s clock rate MUNICH256 QuadFALC. Theoretically, port density could increased ports reality, this condensed number ports limited maximum aggregate clock rate active ports MBit/s with Mbit/s with PCI). number available channels MUNICH256 limited 256, this approach primarily used high number high-speed channels using multiple timeslots even complete T1/E1 port. disadvantage this solution potentially higher SLIP rate combined four T1/E1 lines. 8.192 Mbit/s highway, clock rate four T1/E1 links fixed. This forces four T1/E1 lines identical speed. even slight tolerances from nominal T1/E1 speed, SLIP buffers QuadFALC will have periodic overflows underruns. subset second approach 4.096 MBit/s interface between MUNICH256 QuadFALC, combining T1/E1 ports onto highway. advantages, disadvantages, limitations second approach also apply this variation.
MUNICH256F QuadLIU(s)
Another possibility providing T1/E1 links framer functionality integrated into MUNICH256F device. framers QuadFALC(s) longer required. instead QuadLIU used: QuadFALC framers QuadLIU framers QuadFALCs more complex provide many more features than those integrated into MUNICH256F. system designer must decide additional features provided QuadFALC framers required.
Application Note 2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples benefit using MUNICH256F+QuadLIU solution potential high port density: T1/E1 ports implemented without limitations different line speeds. QuadLIU smaller package than QuadFALC, significant reduction board space achieved, especially high port density designs. total aggregate bandwidth limitations line speeds, must still considered: MHz, total bandwidth limited MBit/s, which corresponds lines. This limitation does exist with clock rate above 2.048 Mbit/s).
passive Linecard
CTCLK
CTFS
Standard Timing TCLK
QuadLIU PEB20504
RCLK
MUNICH256F PEB20256F
Ports
QuadLIU PEB20504
CTCLK
CTFS
QuadFALC PEB20504
Looped Timing TCLK RCLK
Figure
Linecard with MUNICH256F QuadLIU
There different clocking concepts this combination devices: Standard Timing: default, transmit ports MUNICH256F clocked internally with CTCLK (Common Transmit Clock). transmit ports same data rate, given CTCLK pin. looped timing feature selected Individually each port. Then, transmit clock derived from corresponding receive clock this port. this configuration, transmitter runs same speed given receiver
Looped Timing:
both these configurations, TCLK drives transmit clock synchronously transmit data. used provide transmit clock LIU.
Application Note
2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples
MUNICH256FM Puccini
MUNICH256FM provides digital dual rail interface which used glueless connection Puccini device providing line interface. this way, both channelized unchannelized operations possible. MUNICH256FM thus provides channels; this sufficient most applications. clocks must provided devices.
passive Linecard
Ports
MUNICH256FM
PEB20256M
Puccini PEB3452
ClockGen
Figure
Simple Linecard Application with MUNICH256FM PUCCINI
channelized applications, channels supported. They assigned independently internal ports with timeslots each ports with timeslots each E1). These internal ports mapped line internal multiplexer framer. ports mapped according G.747 specification. unchannelized applications, multiplexer bypassed (M13 full payload mode). this configuration, internal Port configured unchannelized operation, running speed with about MBit/s. design-specific delays signals devices, transmit clock from clock generator provided MUNICH256FM phase-shifted relative transmit data line MUNICH256FM. dedicated transmit clock output MUNCH256FM
Application Note
2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples provides synchronous clock signal which used Puccini's transmit input path.
MUNICH256F with M13FX Puccini
MUNICH256F combined with M13FX Puccini devices from Infineon Technologies. M13FX task lines framed line, which then handed over PUCCINI analog processing. channelized applications with channels, there functional benefit compared integrated solution described above (MUNICH256FM Puccini) except that dedicated lines accessible from outside silicon. main benefit combination MUNICH256F with M13FX PUCCINI support more than channels, such fully channelized with channels. Therefore, three MUNICH256F devices connected interface M13FX. There different port mappings M13FX applications, shown Table Table MUNICH256F Port Usage Fully Channelized ports connected ports connected (=256 channels/24 timeslots) (=256 channels/32 timeslots)
superset both, minimum solution connected default. enabling disabling lines, there will collision signals when only subset configuration used. However, most redundant solution would simply connect interface lines each MUNICH256F M13FX device. lines used must disabled. Figure block diagram shows MUNICH256F with M13FX Puccini highly scalable line card application. details multi processor integration approaches integration MUNICH256/F/FM scalable systems described Chapter
Application Note
2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples
fully channelized active linecard
Line Card Processor
MUNICH256F PEB20256F
Ports
Local 16bit
Local System Packet
Bridge
MUNICH256F PEB20256F
Ports
M13FX 3445 Multiplexer
PUCCINI PEB3452 Transceiver
MUNICH256F PEB20256F
Figure
MUNICH256F Fully Channelized Linecard
linecard processor handles data transfer over three MUNICH256F devices even there three MUNICH256F devices integrated this system; load linecard processor will stay only MUNICH256F handling full data rate about MBit/s. busload will potentially increase slightly under certain circumstances, but, this will affect total system traffic primarily stays within linecard's bus.
MUNICH256F SDH/Sonet Mapper
This application looks similar Chapter 4.4, but, instead M13FX, SDH/Sonet Mapper with corresponding transceiver unit used system.
MUNICH256 xDSL Transceiver
Similar T1/E1 configuration shown Chapter MUNICH256 used high port density xDSL line card application. Some xDSL transceivers like Infineon device MuBIC2 (PEB 22522 V2.1) have system interface.
Application Note
Ports
2000-04-01
Application Note M256/F/FM Applications
Serial Interface Application Examples MUNICH256 excellent device handle data traffic multiple ports applications. each MUNICH256 provides 16/28 single ports xDSL.
local
xDSL transceiver
MUNICH256 PEB20256
Ports
xDSL transceiver
xDSL transceiver
Figure
MUNICH256 High Port Density xDSL Solutions
Either local used configure transceivers this done PCI-to-LBi bridge MUNICH256. case MuBIC2 transceiver device, there even small embedded controller that used this. Communication this controller done MUNICH256's Mailbox.
Application Note
2000-04-01
Application Note M256/F/FM Applications
System Integration Application Examples
System Integration Application Examples
Simple Card with/without Local Intelligence
application example Chapter describes simple card with multiple T1/E1 ports MUNCIH256 design using QuadFALC framer line interface unit. framers configured from main system processor Local Interface MUNICH256. Several buses must crossed each transfer: entire transfer goes from processor over local bus, across bridge, finally over MUNICH internal buses QuadFALCs. Each these buses must arbitrated (even local because bridge acts alternate busmaster). worst case, such when long burst transfer takes place system, some arbitration latency must also considered calculation. This shows that accesses peripherals possible, could potentially consume significant portions valuable processor performance loads. From this point view, configuration control framer line interface generally less critical. traffic should handled well. Enhanced processing larger data traffic (such handling protocol timeslots using QuadFALC) could potentially cause bottleneck doing this from main processor intermediate buses. depending implemented feature QuadFALC, worth considering this increasing data traffic when designing system. easy avoid overhead traffic over local processor integrate dedicated small processor Layer processing directly QuadFALC devices: local processor supports main system controlling Layer1 corresponding linecard. Communication between main processor Layer1 processor done Mailbox MUNICH256. provides eight 16-bit registers each direction inter-processor communication. main processor easily give general instructions Layer1 processor (such Close Local Loop, InitE1). local processor then translates this necessary read write accesses QuadFALCs normally done device driver. Even some basic protocol stacks communication handled locally. Even entire system function without Layer processor, bottleneck could develop when upgrading system with additional linecards. using intelligence local side MUNICH256 makes easier less critical scale system.
Application Note
2000-04-01
Application Note M256/F/FM Applications
System Integration Application Examples
passive Linecard
local
Main Processor
Bridge
MUNICH256 PEB20256
Ports
local System
QuadFALC PEB20554
QuadFALC PEB20554
QuadFALC PEB20554
Figure
Local Microprocessor Layer1 Support
Intelligent card with MUNICH256/F/FM (I2O Architecture)
Highly scalable systems will encounter problems many cards with MUNICH256 attached bus. Increasing number installed linecards will also raise load main processor which must handle each linecard data traffic. router applications particular, most time, necessary transfer entire data traffic main processor's bus. Often, even main processor does need know about each transferred packet because main task control management entire system. Decoupling single linecard's data traffic done using dedicated linecard processors. example already been shown Chapter Figure This application shows that system decoupled bridge (PCI-to-LBI PCI-PCI). linecard located bus, assuming that built-in bridge connected dedicated bridge. linecard's packet used storage transferred data from system. general, descriptor data structures MUNICH256/F/FM located RAM. this way, data traffic does need cross bridges additional arbitration required. However, there
Application Note
2000-04-01
Application Note M256/F/FM Applications
System Integration Application Examples known market with integrated interface. This example also assumes some kind bridge between PCI; but, there additional busmaster between this bridge RAM. Because arbitration this "RAM"-bus necessary, accesses succeed immediately. linecard does device driver tasks handles upper layer protocol software locally. Thus, main traffic handling must done main system processor. Additionally, Layer processor side MUNICH256/F/FM handle Layer1 tasks communicate with linecard processor Mailbox. Some solutions market integrate linecard processor, PCI-to-PCI bridge, memory interface. example, some members intel960Rx series provide these features (such i960RD processor). some linecard applications, absolutely necessary separate packet memory processor's code data memory; they combined memory unit. System setups according Intel's specifications possible with this architecture.
fully channelized active linecard
MUNICH256F PEB20256F
Ports
Local 16bit
line card processor (i960RD)
MUNICH256F PEB20256F
Ports
M13FX PEB3445 Multiplexer
PUCCINI PEB3452 Transceiver
Backplane
DSCC4 PEB20534
MUNICH256F PEB20256F
Figure
Active linecard using Intel i960RD integrated processor
Application Note
Ports
Ports
2000-04-01
Application Note M256/F/FM Applications
System Integration Application Examples Support plug-in play using serial EEPROM generally necessary because devices local linecard's hidden from primary main system. primary recognition configuration linecard done i960RD towards primary main system. DSCC4 shown Figure above provides general data connection backplane. DSCC4 could used support unchannelized high speed data streams. Potentially, this task could done instead dedicated high speed port(s) more MUNICH256/F/FM devices, they used other way. mentioned Chapter 4.4, only subset ports absolutely required this application). Alternatively, other high speed interface device (preferably with interface) could provide backplane data transport (such ethernet controller).
Application Note
2000-04-01
Total Quality Management
eine umfassende Bedeutung. wollen allen Ihren Weise gerecht werden. geht also nicht unsere Anstrengungen gelten Logistik, Service Support sowie allen sonstigen Beratungs- Betreuungsleistungen. Dazu eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality Denken Handeln Kollegen, Lieferanten Ihnen, unserem Kunden. Unsere Leitlinie jede Aufgabe ,,Null Fehlern" offener Sichtweise auch eigenen Arbeitsplatz hinaus verbessern. Unternehmensweit orientieren dabei auch ,,top" (Time Optimized Processes), Ihnen durch Schnelligkeit entscheidenden Wettbewerbsvorsprung verschaffen. Geben Chance, hohe Leistung durch umfassende beweisen. werden Quality takes allencompassing significance Semiconductor Group. means living each every your demands best possible way. only concerned with product quality. direct efforts equally quality supply logistics, service support, well other ways which advise attend you. Part this very special attitude staff. Total Quality thought deed, towards co-workers, suppliers you, customer. guideline everything with zero defects", open manner that demonstrated beyond your immediate workplace, constantly improve. Throughout corporation also think terms Time Optimized Processes (top), greater speed part give that decisive competitive edge. Give chance prove best performance through best quality will convinced.
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Published Infineon Technologies

Datacom Edition 2000-04-01 Published Infineon Technologies St.-Ma

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