Using LVDS APEX 20KE Devices designs continually demand more band

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Using LVDS APEX 20KE Devices designs continually demand more band

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Using LVDS APEX 20KE Devices
designs continually demand more bandwidth. address this need, Altera added low-voltage differential signaling (LVDS) technology APEXdevice family. LVDS meets requirements high data rates power consumption. With LVDS, chip interface with high-speed, low-voltage backplanes data channels. Board design simplified because dedicated circuitry like LVDS integrated into PLD. LVDS integration saves board space, reduces usage, improves performance. This white paper explains advantages describes LVDS technology APEX 20KE devices.
LVDS Standards
industry standards define LVDS: IEEE Std. 1596.3 SCI-LVDS ANSI/TIA/EIA-644. Both standards have similar features, IEEE Std. 1596.3 SCI-LVDS standard supports maximum data transfer rate million bits second (Mbps). APEX 20KE devices designed meet ANSI/TIA/EIA-644 standard Mbps.
ANSI/TIA/EIA-644
ANSI/TIA/EIA-644 standard defines driver output receiver input characteristics. Additionally, this standard recommends maximum data rate Mbps theoretical maximum 1.923-gigabits second (Gbps), based loss-less media. also documents fail-safe operation receiver under fault conditions. Figure shows current-mode LVDS driver works.
Figure LVDS Current Mode Driver
Current Source (~3.5
Driver
Receiver
~350
Low-Voltage Differential Signaling
LVDS voltage swing, general-purpose standard that high-speed, low-power, low-noise advantages. LVDS capable extremely high data transfer across variety interconnect media: traces, backplanes, cables. LVDS utilizes differential input without need input reference voltage. Typical uses LVDS high-bandwidth data transfer, backplane driver, clock distribution applications.
M-WP-LVDSAPEX-01
January 2000, ver.
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Using LVDS APEX 20KE Devices
faster transition time (i.e., edge rate), higher potential data rate. provide switching speeds hundreds-of-Mbps range, LVDS standard typically low-voltage signal level Since there little margin noise with swing that small, differential data transmission scheme used. Differential transmission means that every LVDS signal uses lines. voltage difference between lines defines logic state LVDS signal. each signal pair, there true signal denoted LVDSRX<number>, complement signal denoted LVDSRX<number>a where channel number ranges from differential signal channel LVDSRX01 minus LVDSRX01a. more information LVDS naming convention refer Using Standards Quartus Software White Paper. differential scheme advantages over single-ended schemes:
low-voltage swing reduces power consumption increases performance Less susceptible electromagnetic interference (EMI)
Increased Performance
voltage swing important high performance. provide switching speeds hundreds Mbps range, LVDS standard defined low-voltage signal level smaller voltage swing, faster signal change logic levels. faster transition time (i.e., edge rate), higher potential data rate. Since there little margin noise with small voltage swing, differential data transmission scheme used. signals referenced each other, another static signal level. Therefore, differential standard have much smaller switching region. same bandwidth LVCMOS data achieved with LVDS using fewer pins operating LVDS signals frequency. Figure shows 128-bit LVCMOS data that implemented with LVDS channels pins).
Figure LVDS uses Fewer Pins than LVCMOS
With LVCMOS (256 Pins) With LVDS Pins)
Microprocessor
Microprocessor
128-Bit 77.76 GBPS Switch
128-Bit 77.76
LVDS Channels 622.08 Mbps GBPS Switch
LVDS Channels 622.08 Mbps
Memory
Memory
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Power-Efficiency
LVDS power-efficient standard. Because low-switching voltage (typically current channel, power dissipation signal small. Table shows equations that calculate load power dissipation.
Table Calculating Load Power Dissipation
Calculation
power channel (PDC) power channel (PAC) Total Power
Equation
(PDC (PAC 2CV2F)
Example
1.225 (0.35V)2 0.610 1.225 0.610 1.835
understand LVDS power consumption compares LVTTL, consider following example which both LVDS LVCMOS operating 622.08 Mbps bandwidth. comparison shown Table
Table LVDS Consumes Less Power than CMOS
Parameter
Number Pins/Channels Frequency Bandwidth Data Voltage Swing Power Total Power
LVDS
channel 622.08 622.08 0.35 1.835
LVCMOS
pins 77.76 622.08 3.387 27.09
Unit
MBPS
Reduced Electromagnetic Interference (EMI)
Electromagnetic interference (EMI) radiated noise created from acceleration electric charge within device across transmission medium between devices. Device-generated dependent frequency, output voltage swing, slew rate. voltage swing LVDS standard, effects much smaller than CMOS, TTL, other standards. Reduced effects major advantage using LVDS standard. Furthermore, LVDS less susceptible common-mode noise because differential standard. Figure shows that system power supply noise equally coupled both LVDS signals, thus affecting signal quality.
Figure System Level Noise Rejection
Common Mode Noise from Power Supply Rejected
Common Mode Range
LVDS receiver tolerate maximum ground shift between driver receiver ground. recommended input voltage ranges from Because typical voltage offset common mode range receiver LVDS driver will have output voltage swing between with respect ground. When there ground shift, voltage swing ranges from which
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within input voltage range. Similarly, there -1.0 shift, output voltage swing ranges from Figure shows ground shift tolerance.
Figure Common Mode Voltage Range
Driver Output Receiver Input
LVDS Timing
This section discusses timing waveforms parameters LVDS APEX 20KE devices. APEX 20KE devices incorporate deskew circuitry, which ensures successful data capture high rates when LVDS used modes. designs using LVDS mode, deskew circuitry required.
Deskew Circuitry
deskew circuitry implemented inside APEX 20KE device compensate board skew clock skew within APEX 20KE devices, shown Figure
Figure Channel-to-Channel Clock-to-Channel Skew
Data Stream Skewed from Others Receiver Cannot Capture Data
Channel
Channel
Clock Channel
Channel Skew
APEX 20KE devices deskew circuitry provide high-data transfer rates. Because LVDS inputs have high bandwidth, over-sampling circuit used accurately capture data. inputs captured four separate clocks, results examined determine which clock successfully captured data. deskew circuitry compensate time period.
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calibration pattern required phase align clock with incoming LVDS data. calibration data values depend operating mode LVDS phase-locked loop (PLL). Contrary user mode data, first calibration data first after input clock. calibration data shown Table
Table Calibration Data Pattern Deskew Circuitry
LVDS ClockBoostMultiplication Rate
Calibration Pattern
0011 0000111 00001111
dual-function DESKEW places LVDS inputs calibration mode. calibration pattern must applied three input clock cycles (see Figure deskew should controlled falling edge input clock. channels calibrated simultaneously. Each LVDS input channel independently align clock with received data account differences routing. After channels have been successfully calibrated, LVDS data pins ready transmit receive data.
Figure Deskew Circuitry Calibration Waveform Mode
least cycles
DESKEW
Input Clock
Input Data
First valid data (MSB)
Changes temperature voltage affect receiver input skew margin (RSKM). RSKM tolerance difference between input clock input data. LVDS mode, deskew only required worst case board skew between clock data channels more than deskew circuitry needs recalibrated often enough satisfy RSKM specification 0.7ns. analysis circuit must performed determine RSKM specification violated.
Timing Budget Definitions
Data synchronization necessary successful data transmission with LVDS high frequencies. operation 622.08 MBPS, external clock multiplied phase aligned coincide with sampling window each data bit. Figure shows data orientation defined altlvds_rx megafunction Quartus software 8-to-1 data conversion mode.
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Figure Internal Data Synchronization
External Input Slow Clock
LVDS Data Byte
Input Data
Internal Multiplied Clock
internally-generated clock positioned meet requirements timing budget. Figure shows timing budget that available capturing serial data 622.08 MHz.
Figure LVDS Timing Budget
Transmit Receiver
Clock Placement Internal Clock Synchronization
Transmitter Output Data
TCCS RSKM RSKM
TCCS/2
Receiver Input Data
TSWBEGIN
TSWEND
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Table shows LVDS timing specifications terminology.
Table LVDS Timing Specifications Terminology
LVDS Timing Specification
Sampling Window (SW)
Terminology
This parameter defines window where internal receiver clock rising edge should placed capture data. setup hold times determine ideal strobe position within sampling window. input data must valid sampling window. (TSW TSWEND TSWBEGIN) This parameter defines beginning sampling window each word data. From beginning sampling window input data must valid meet setup hold time requirements. This parameter defines sampling window each word data. From beginning sampling window input data must valid meet setup hold time requirements. channel-to-channel skew defined timing difference between fastest slowest output edges, including variation clock skew. Skew variation arrival time signals specified arrive same time. skew occurs registered output pins because differences propagation delay clock signal through clock network. Receiver input skew margin timing margin between clock input data input user board design, which allows LVDS cable skew, jitter LVDS PLL. RSKM (Bit Time Period TCCS SW)/2. time period period internal receiver LVDS divided multiplication ratio. This timing budget allowed skew, propagation delays, data sampling window (Bit Time Period 1/(Receiver Input Clock Frequency Multiplication Factor)).
Begin Sampling Window (TSWBEGIN) Sampling Window (TSWEND) Channel-to-Channel Skew (TCCS)
Receiver Input Skew Margin (RSKM)
Time Period
input timing waveform shown Figure cycle phase delay from input clock input data account clock insertion delay. clock insertion delay delay from clock input arrival rising edge LVDS conversion circuitry.
Figure Input Timing Waveforms
Input Clock
Previous Cycle
Current Cycle
Next Cycle
TSWBEGIN TSWCENTER TSWEND
output timing waveform Figure shows relationship between output LVDS clock serial output data stream.
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Figure Output Timing Waveforms
Output LVDS Clock
Previous Cycle
Current Cycle
Next Cycle
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7
Sampling Window
these internally-generated LVDS PLLs properly phase-aligned serial-to-parallel converter data capture, data sampling window must properly positioned with respect clock. Tables through show sampling window positions 8-to-1, 7-to-1, 4-to-1 data conversion modes.
Table 8-to-1 Mode Receive Window (622.08 Mbps transfer)
Symbol
TSWBEGIN
0.50 2.11 3.72 5.33 6.93 8.54 10.15 11.76
TSWCENTER
0.80 2.41 4.02 5.63 7.23 8.84 10.45 12.06
TSWEND
1.10 2.71 4.32 5.93 7.53 9.14 10.75 12.36
Units
Table 8-to-1 Mode Transmitter Pulse Positions (622.08 Mbps transfer)
Symbol
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7
-0.20 1.41 3.02 4.62 6.23 7.84 9.45 11.05
0.00 1.61 3.22 4.82 6.43 8.04 9.65 11.25
0.20 1.81 3.42 5.02 6.63 8.24 9.85 11.45
Units
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Table 7-to-1 Mode Receive Window (462 Mbps transfer)
Symbol
TSWBEGIN
0.73 2.90 5.06 7.23 9.39 11.55 13.72
TSWCENTER
1.08 3.25 5.41 7.58 9.74 11.90 14.07
TSWEND
1.43 3.60 5.76 7.93 10.09 12.25 14.42
Units
Table 7-to-1 Mode Transmitter Pulse Positions (462 Mbps transfer)
Symbol
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6
-0.35 1.81 3.98 6.14 8.31 10.47 12.64
0.00 2.16 4.33 6.49 8.66 10.82 12.99
0.35 2.51 4.68 6.84 9.01 11.17 13.34
Units
Table 4-to-1 Mode Receive Window (320 Mbps transfer)
Symbol
TSWBEGIN
1.06 4.19 7.31 10.44
TSWCENTER
1.56 4.69 7.81 10.94
TSWEND
2.06 5.19 8.31 11.44
Units
Table 4-to-1 Mode Transmitter Pulse Positions (320 Mbps transfer)
Symbol
TPPos0 TPPos1 TPPos2 TPPos3
-0.4 2.73 5.85 8.98
3.13 6.25 9.38
3.53 6.65 9.78
Units
LVDS Specifications
Table shows recommended operating conditions LVDS block.
Table 3.3-V LVDS Specifications
Symbol
VCCINT VCCIO Supply voltage Differential output voltage Change between Output offset voltage Change between Differential Input threshold Receiver differential input resistor -100 1.125 1.25
Parameter
Supply voltage internal logic input buffers
Conditions
Typical
1.375
Units
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Using LVDS APEX 20KE Devices
Data Conversion Modes
successful transmission high data rates supported LVDS. minimizes skew, phase-aligns clock parallel-to-serial serial-to-parallel data converters. EP20K300E larger devices, ClockLockPLLs configured LVDS interfaces. LVDS used input block, another used output block. Figure shows block diagram APEX 20KE LVDS PLLs, including LVDS-specific names.
Figure LVDS Block Diagram
Dedicated Clocks
LVDSTXOUTCLK1p LVDSTXOUTCLK1n LVDSTXINCLK1p LVDSTXINCLK1n PLL4 CLK4p
PLL3 LVDSRXINCLK1p LVDSRXINCLK1n
CLK3p
CLK2p PLL2
PLL1 CLK1p
CLKLK_FB2p CLKLK_OUT2p
CLKLK_FB1 CLKLK_OUT1p
Notes: These outputs only used LVDS mode. PLL3 PLL4 only used LVDS general-purpose PLL.
When using LVDS, these clocks multiplied support high-speed data transfer rates convert between LVDS CMOS data. multiply input clock dedicated data conversion circuitry. general-purpose should used LVDS bypass mode. Figure shows connections LVDS receiver side.
Figure LVDS Block Diagram
Allows conversion parallel CMOS Data
LVDS Clock
LVDS
Dedicated Silicon Serial-to-Parallel Converter
Dedicated Clock
LVDS used boost LVDS input clock from 77.76 622.08 internally clocking LVDS data. also phase-aligns clock with incoming data. incoming serial LVDS channels either bypass serial-to-parallel converter. parallel converter operate different data-conversion modes (e.g., 8-to-1, 7-to-1, 4-to-1). When operating 1-to-1 mode, dedicated LVDS circuitry bypassed, data directly feeds LEs. generated clock from LVDS
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also used clock internal logic within device. Figure shows block diagram LVDS input circuitry.
Figure Dedicated LVDS Receiver Circuitry Block Diagram
APEX 20KE LVDS
Serial Data Mbps
data[7.0] Built-in Serial-to-Parallel Converter
CLK_LVDS2 77.75 Clock
(8x)
PLL3
77.75 (1x)
Dedicated Clock
Figure shows block diagram LVDS output circuitry. transmitter driven externally output receiver internal global. output transmitter driven off-chip clock other LVDS devices system.
Figure Dedicated LVDS Transmitter Circuitry Block Diagram
APEX LVDS Interface
Serial Data Mbps
data[6.0] Built-in Parallel-to-Serial Converter
66-MHz CLK_LVDS3
(7x)
PLL4
(1x)
Internal Global Clock
CLKLVDS_OUT3
Internal Global Clocks
more information ClockLock ClockBoost, refer Application Note (Using ClockLock ClockBoost Features APEX Devices).
LVDS Interface
Figure shows LVDS receiver transmitter internally interface with logic other devices system. There input LVDS channels input block, with LVDS used clock serial-to-parallel converter receiver. PLLs (PLL receiver transmitter) generate phase-locked clock signals serial-to-parallel parallel-to-serial data converters. receiver input channels, transmitter output LVDS channels. LVDS receiver converts maximum LVDS signals into CMOS data bits, which feeds internal within device. Similarly, LVDS transmitter converts maximum CMOS on-chip data bits into LVDS data streams, using 8-to-1 parallel-to-serial converter.
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Figure LVDS Receiver Transmitter Interface
Loadable Shift Register Synchronization Registers Loadable Shift Register
LVDSRX01p LVDSRX01n
LVDSTX01p LVDSTX01n
User Logic
LVDSRXINCLK1p LVDSRSINCLK1n
LVDSTXOUTCLK1p LVDSTXOUTCLK1n
LVDSTXINCLK1p LVDSTXINCLK1n
internal LVDS clocks have maximum multiplication rate. LVDS transmitter ability drive locked clock off-chip. external transmitter clock output output data signals in-phase. Every cycle transmit receive clock data-up bits input output data-are sampled LVDS channels. LVDS input pins pins located right side device. Each LVDS input channel interfaces with dedicated shift registers drive lines. Similarly, LVDS output pins also pins located left side device. Each LVDS output channel interfaces with dedicated shift registers, driven peripheral logic elements (LEs).
APEX 20KE Structure
APEX 20KE devices have eight programmable banks dedicated LVDS blocks. Figure shows representation APEX 20KE banks. LVDS receiver block located right, transmitter block located left. APEX 20KE devices EP20K400E larger support using LVDS dedicated clock signals, LVDS data bypass (x1) mode, dedicated serializer deserializer modes. EP20K400E larger devices with x-suffix their ordering codes support LVDS modes. EP20K300E devices, which have x-suffix their ordering codes, support using LVDS dedicated clock signals LVDS data bypass (x1) mode 652-pin ball-grid array (BGA) 672-pin FineLine BGApackages. EP20K200E smaller devices support using LVDS dedicated clock signals. EP20K200E smaller devices, x-suffix indicates PLL-enabled support. APEX 20KE devices, including devices without xsuffix their ordering codes, support LVDS dedicated clocks.
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Figure APEX 20KE Blocks
Bank Bank
Bank
LVDS Transmitter Block
Regular Banks Support: LVTTL LVCMOS GTL+ SSTL-2 Class SSTL-3 Class HSTL Class Individual Power
Bank
LVDS Receiver Block
Bank
Bank
Bank
Bank
LVDS transmitter receiver blocks support standards used input, output, bidirectional pins 3.3-V, 2.5-V, 1.8-V. first pins that border LVDS blocks input only maintain acceptable noise level VCCIO plane. programmable input/output element (IOE) blocks have individual power planes with separate VCCIO pins each bank. VCCIO planes support 3.3-V, 2.5-V, 1.8-V levels. pins used LVDS standards, always connect LVDS power bus-associated VCCIO pins LVDS blocks support standards supported APEX 20KE devices. When using LVDS, power conserved powering-down LVDS VCCIO power pins. LVDS blocks have their VCCIO pins.
Board Termination
LVDS standard requires termination resistor between signals receiver side. This termination resistor generates differential output voltage (VOD) across resistive termination load receiver input. termination resistor should match differential load impedance (typically values range between Figure shows LVDS board termination receiver.
Figure LVDS Board Termination Receiver
Transmitting Device Receiving Device
multi-drop configurations where transmitter drives multiple receivers, only termination resistor allowed, should placed furthest receiver from transmitter device, shown Figure
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Figure Multi-Drop Configuration Termination
LVDS Design Recommendations
Because high data rates used with LVDS, skew problem. prevent skew maintain signal integrity, follow recommendations below:
Stub lengths must kept less than 12mm (0.5 Place drivers receivers close connectors possible Match electrical lengths LVDS lines avoid skew Minimize distance between traces pair LVDS lines maximize CMRR Separate TTL/CMOS signals from LVDS signals onto different board layers multi-layer printed circuit board (PCB) with ground plane beneath LVDS lines Avoid degree bends multiple vias. same number bends vias each signal pair match delays good decoupling techniques. four surface mount bypass capacitors (2.2uF, 0.1uF, 0.01uF, 0.001uF) placed close GND_CKLK2/VCC_CKLK2 GND_CKLK3/VCC_CKLK3 pairs eliminate switching noise Place parallel termination resistor receiver input
Packaging
Because high frequency effects packages, LVDS feature available 1.27-mm 1.0-mm FineLine packages. important keep signal paths same length short possible. balls used LVDS signals located outer rows balls FineLine package. Figure shows LVDS ball placement 672-pin FineLine package EP20K400E EP20K600E devices. marked pins include LVDS input signals LVDS clock input left package (bottom view). LVDS output signals, clock signal, clock output signal shown right package.
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Figure Location LVDS Balls 672-Pin FineLine Package
LVDSTXINCLK LVDSTXOUTCLK
LVDS input pairs placed outer rows balls minimize skew
LVDS Transmitter Data Channels
LVDSRXINCLK
Applications
This section will discuss various LVDS topologies. There various methods interfacing multiple LVDS devices. APEX devices offer different modes with multiple ways connect receiver transmitter LVDS PLLs. following LVDS applications supported with APEX 20KE devices:
Point-to-Point Configurations Multi-Drop LVDS Bypassing Dedicated LVDS Converter Circuitry
Point-to-Point Configurations
Point-to-point LVDS applications involve devices communicating data LVDS. point-to-point communication, receiver clocked from sources: same source transmitter, output clock generated transmitter. Figures show both cases.
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Figure Receiver PLLs Clocked Board Clock
Device Device
Data
channels Internal Logic
Bridges clock domain
FIFO Internal Logic
Clocked different frequency
Clock
timing parameters (setup time clock-to-output) must taken into consideration application shown Figure Using source synchronous clocking scheme shown Figure recommended. source synchronous application, designers need follow LVDS timing budget defined "Timing Budget Definitions" page
Figure Transmitter Clocks Receiver (Source Synchronous Clocking Scheme)
Device
External Clock
Device
Data
channels Internal Logic
Bridges clock domain
FIFO Internal Logic
Clocked different frequency
Clock
Multi-Drop Configurations
Multi-Drop Configuration transmitter multiple receivers. transmitter clock from source device used clock LVDS PLLs receiving devices. performance will affected number loads that transmitter required drive. Preliminary information shows that APEX 20KE device support loads MHz. Contact Altera Applications up-to-date information Multi-Drop Configuration. Figure shows Multi-Drop Configuration with loads.
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Figure Multi-Drop Configuration
Receivers Transmitter
Clock Data
channels
Bypassing Dedicated LVDS Converter Circuitry
data rate LVDS signals that less than Mbps, data bypass dedicated serial-to-parallel converters feed directly, shown Figure setup hold times sufficient meet Mbps requirements. this application, clock data running same rate. clock standard, general-purpose PLLs should used mode clock registers. general-purpose supports LVDS signals operate input frequency MHz.
Figure Data Feed directly frequencies less than equal
DATA
Registers
General Purpose
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Summary
APEX 20KE device first offer on-chip LVDS solution. LVDS standard simplifies board design minimizing number devices used interface with backplanes. APEX 20KE devices also offer increased performance with increased data rates (622.08 Mbps data transfer).
References:
Electrical Characteristics Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunication Industry Association/Electronic Industries Association.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 2000 Altera Corporation. Altera, APEX, ClockBoost, ClockLock, EP20K300E, EP20K400E, EP20K600E, FineLine trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.

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