Bi-CMOS LV2700V Spread Spectrum Communications Overview

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Bi-CMOS LV2700V Spread Spectrum Communications Overview

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Ordering number EN5651B
Bi-CMOS
LV2700V
Spread Spectrum Communications
Overview
LV2700V provides reception transmission functions necessary half-duplex communication spread-spectrum communications systems.
sequence code length (511, 255, 127, chips) demodulation Lock detector 150k through
Features
used weak radio wave band without frequency conversion (direct signal processing MHz) also used band (900MHz, 2.4GHz) with frequency conversion Wide spread-spectrum bandwidth MHz) Sanyo developed system code synchronization Allows direct primary modulation (FSK data analog signals. Data transfer maximum rate 256kbps made (when built-in used) Low-voltage operation (2.7 power dissipation mode) Small package: SSOP30
Package Dimensions
unit: 4182-SSOP30
[LV2700V]
Functions
Block] Spectrum spreader Crystal oscillator circuit code generator sequence) sequence code length (511, 255, 127, chips) 9.83 Band limiting filter (LPF) data transmission Block] Spectrum despreader Synchronization supplementation protection code generator sequence)
SANYO: SSOP30
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
90298RM (OT) 5651-1/20
LV2700V
Specifications
Maximum Ratings 25°C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol Topr Tstg Conditions Ratings +125 Unit
Operating Conditions 25°C
Parameter Recommended supply voltage Allowable voltage range Operating frequency range Symbol VCCop Conditions Ratings Unit
Electrical Characteristics 25°C, MHz, kHz, Vp-p
Parameter Symbol ICCOTX ICCORX VOTX VOTX TXVCC RFVCC RXVCC Applied resistor SW2: MHz, SW2: MHz, Conditions Ratings Unit
Quiescent current Block] Modulated signal voltage output voltage Spread bandwidth Block] Input sensitivity High level Demodulated output Demodulated output Total harmonic distortion Signal-to-noise ratio [CMOS-Level Interface] Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Input high-level current Input low-level current Input amplitude Crystal oscillator frequency conditions Input capacitance level
19.7
Vp-p
VSRX VORX1H VORX1L VORX2
output output output output output, filter
mVrms
XOSC
Pins Pins Pins Pins Pins Pins VCOIN XIN, XOUT RFIN, XIN, VCOIN
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Block Diagram LV2700V
Synchronization control
Strong field detector
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LV2700V Test Circuit
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LV2700V Functions
RFVCC voltage(V) function block power supply Equivalent circuit
REXT
Connection external capacitor resistor used internal amplifier
RFIN
input
RFGND
block ground
ANTDUMP
Output voltage used under strong reception conditions prevent saturation amplifier. Voltage variability range: about
RXVCC
Reception block power supply Connect capacitor between limiter reference terminal demodulated data waveshaping terminal.
CEXT
RXOUT
Demodulated data output (CMOS output.)
LOCK
Outputs high level when code synchronization established. (This CMOS-level output.)
RXAOUT
Demodulated analog output
Continued next page.
5651-5/20
LV2700V
Continued from preceding page.
voltage(V) function Through selection 150kHz LPF. through becomes when this input HIGH, normally (Low). code selection These pins select code-length types. code length reset Equivalent circuit
FILOFF
High
TX/RX
Send/receive mode selection. High: Transmission Low: Reception CMOS block power supply Transmission data input (CMOS levels). apply analog signals this pin.
DATAIN
DATAOUT
1Vp-p
Transmission data output. output signal band limited 300kHz voltage limited Vp-p. CMOS block ground
DGND 1/2VCC
Input 9.8304MHz reference oscillator inverter. Output 9.8304MHz reference oscillator inverter. resistor about between XOUT.
XOUT
1/2VCC
TXLPF
Connection 9.8MHz loop filter used transmission.
Continued next page.
5651-6/20
LV2700V
Continued next page.
voltage(V) function Equivalent circuit
LPFIN
Demodulated signal input (loop filter output) used reception. Connect external bias resistor.
RXPDOUT
buffer output. Connect external lowpass filter between pins required.
RXLPF
Connection 236MHz loop filter used reception.
LPFOUT
Control input 236MHz VCO. LV2700V includes switch selecting loop filter depending mode (transmission reception).
Transmission power supply
VCOIN
Input output from 236MHz VCO. Minimum input level: about
AGND
Analog system ground
Spectrum spreader RFOUT Spread-spectrum output transmission mode)
5651-7/20
LV2700V Description Operation Application Information Principle Operation LV2700V transmission reception functions necessary carrying half-duplex communication using spread spectrum communication. spectrum spreading being done using direct sequence (DS) method which carrier wave multiplied code. code used spectrum spreading this time typical sequence code, possible select types code lengths from chips chips. Further, since clock generating code derived from carrier wave frequency division, system realized which carrier wave code synchronized phase thereby obtaining configuration with simplified synchronization system. Transmission Mode transmission block shown Fig.
Data input
Output
Fig. transmission block Code generation method (Pseudo-random Noise) code name suggests, pulse train which occurrence probabilities pseudo-random nature, required spectrum spreading direct spreading method. Although there many types code series, most typical among them, sequence code (maximum-length sequence being used LV2700V. generator sequence code configured using shift register feedback circuit. Fig. shows configuration code generator 15-chip type. LV2700V, possible select among types codes from chips chips. Although there several shift register feedback methods (called feedback taps) case sequence code length more than chips, LV2700V, only type feedback used each code length. actual positions feedback taps shown Table
Code
Fig. Code generator
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LV2700V Table Feedback position
Code length position
Modulation method (FM, FSK) modulation method using information signal that direct frequency modulation (FM) VCO. Specifically, frequency modulation carried adding signal loop filter PLL. This same case analog signals digital data. Consequently, lower limit frequency frequency modulation gets limited loop band width PLL. That lower limit frequency becomes lower loop bandwidth becomes narrower. case data, although necessary make lower limit frequency lower than that case using analog signals, possible sufficiently lower lower limit frequency adding circuit that modulates reference oscillator frequency. Reception Mode reception block shown Fig.
Data output
Input
Synchronization control
Fig. reception block
5651-9/20
LV2700V Code synchronization order obtain data demodulating signal that been spread spectrum modulated, necessary first unspread signal convert into narrow band signal. This unspreading operation made multiplying input high frequency signal with code manner similar spreading operation made transmitting side. code used this time should same code that used transmitting side. However, possible recover narrow band signal before spreading merely using same code. necessary phases codes transmitting receiving sides matched within chip. consider this from autocorrelation function. Fig. shows autocorrelation function code. identical codes taken, autocorrelation function obtained evaluating products with code kept fixed reference other code shifted chip time relative reference code, that each chips multiplied with corresponding chip same position products obtained. shown figure, autocorrelation function highly characteristic that shows meaningful output values only within limited range. Therefore, other words, correlation value will always when there phase difference more than chip, value becomes maximum when codes have same phase. Consequently, process synchronization consists making phase receiving side code phase transmitting side code that correlation value between transmitting side receiving side codes becomes maximum. general, process establishing code synchronization considered consist stages firstly initial process which phase receiving side code made within chip transmitting side code which autocorrelation output appears, thereafter process obtaining best synchronization point while maintaining level synchronization obtained earlier that autocorrelation function value becomes maximum. first these process stages called initial acquisition second stage process called synchronization maintenance tracking control.
Autocorrelation function
Reference
Fig. Autocorrelation function
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LV2700V Initial acquisition LV2700V, initial acquisition done sliding correlation. Sliding correlation method obtaining correlation shifting, small amounts time, phase receiving side code relative transmitting side code. clock receiving side code generator being generated frequency division output similar transmitting side. Therefore, frequency difference caused between clocks sending receiving side slightly shifting free running frequency from carrier wave frequency, thereby carrying required sliding. this case, since speed sliding proportional amount this frequency shift, making amount frequency shift smaller causes time required initial capture become longer. Fig. shows time between peaks autocorrelation function value, etc., during sliding process.
code length msec chip µsec chip
Here, Frequency Carrier frequency Frequency division factor from output clock.
Fig. sliding time Next, consider process achieving initial acquisition. sliding process, output unspreading unit will still spread spectrum signal during period which correlation output zero. Further, since carrier wave component suppressed spread wave, does operate effectively does locked, hence sliding continued with remaining free running frequency condition. Next, timing which valid autocorrelation output appears, since continuous carrier wave component appears unspread output, operates correctly thereby achieving phase synchronization with carrier wave. result, output changes from free running frequency carrier wave frequency thereby making difference transmitting side receiving side clock frequencies zero, sliding stop point initial acquisition process gets completed.
5651-11/20
LV2700V Optimal control (tracking control) After initial acquisition completed, code synchronization condition maintained PLL. This because, LV2700V, since system configuration adopted that maintains phase synchronization between carrier wave clock, code synchronization maintained long locked carrier wave. However, since position synchronization point within chip range definite, control circuit provided track best synchronization point. Fig. shows block diagram optimal control circuit. this optimal control circuit, three codes delayed successively chip used code unspreading successively. other words, these correspond reference phase early phase late phase Next, correlation output obtained each code envelope detector circuit. These correlation outputs successively compared phase code controlled that correlation output reference phase larger than correlation values other codes. example, when codes positions shown Fig. since correlation value larger than that reference phase code controlled gradually delaying until finally position point which value autocorrelation function becomes maximum. Since this optimal control operation being carried continuously, synchronization condition maintained always best position even when reception condition varies large amounts.
Input
Sync detector
Control circuit
Fig. Optimal control circuit
After optimal control operation
Fig.
5651-12/20
LV2700V Demodulation code reference phase described above used unspreading unit signals. Further, last stage unspreading unit carries operation only above synchronization maintenance also functions demodulator that data signal obtained loop filter. However, since possible loop bandwidth sufficiently narrow because setting initial acquisition time response characteristics, component cannot sufficiently suppressed loop filter. Therefore, 150kHz provided demodulator output thereby removing leakage components code thus improving ratio. ratio further improved limiting demodulation bandwidth, necessary another LPF. Application Information Operating Mode Selection selection transmission mode reception mode follows input method applying voltage power supply terminal. Note that power supply bias circuit circuit block dedicated mode automatically made during mode thereby saving power dissipation.
Mode High Power supply terminal setting method Voltages applied power supply terminals. voltage applied power supply terminals except
Block Since LV2700V carries direct signal processing without converting frequency, possible configure transmitting receiving system with minimum external components. standard operating frequency been selected that used such systems using weak radio waves. addition, combining with up-converter down-converter that frequency becomes MHz, possible this even bands such GHz, etc. LV2700V amplifier input block, hence possible obtain input sensitivity about -100dBm using external amplifier about Further, necessary place latter stage antenna thereby removing components outside band interest thus improving interference characteristics input sensitivity. Mode output adjusted circuit frequency that times reference oscillator frequency, that MHz. reference oscillator circuit configured inverter using quartz oscillator element 9.8304 MHz. Also, phase comparator uses EX-OR gate carries comparison operation reference frequency. Further, since clock code generator generated frequency division output frequency becomes equal reference frequency. Mode reception mode, input signal will reference signal PLL. Therefore, under no-signal condition, will free running state. phase comparator carries phase comparison using analog mixer circuit. using circuit configuration which there frequency divider between phase comparator, loop gain made large thereby increasing input sensitivity itself. clock generated frequency dividing output similar that transmission mode.
5651-13/20
LV2700V Modulation When input signal analog signal, modulation modulation when input signal digital signal. However, modulation method common both, modulating signal applied analog signal control terminal PLL. Data Input data input dedicated data input terminal. This signal passed through limiter amplifier output output connected series circuit which loop filter terminal. Analog Input Since input dedicated data, cannot used analog inputs. Connect analog input signals series circuit Demodulation reception mode, demodulated signal obtained from loop filter terminal output after passing through buffer amplifier output order take demodulated signal without affecting loop filter constants. However, explained earlier, since possible make loop bandwidth sufficiently narrow setting time response characteristics synchronization initial acquisition process, possible sufficiently suppress component output loop filter terminal. Therefore, incorporated remove component included demodulated signal. However, since fundamental frequency becomes less than when code length becomes longer than chips, possible sufficiently suppress components built-in filter. Hence, when using code lengths more than chips, between fundamental frequency each code length given table below. Since these frequencies become fundamental frequencies leakage component, that sufficient attenuation this frequency. Further, these values also become maximum data transfer rates during data transmission. However, when built-in used, maximum rate will limited less than kbps.
Code length Fundamental frequency
Clock frequency Note: Fundamental frequency code length Analog Output analog output obtained Data Output data output which open drain output. order suppress output noise under nomodulation conditions, hysteresis provided connecting feedback resistor about between Care should taken because effective sensitivity becomes lower feedback resistor hysteresis made lower than
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LV2700V Method biasing necessary bias value equal reference bias amplifier through built-in LPF. reference bias built-in amplifier provided resistance divider consisting resistors, bias will about when power supply voltage result, although possible bias using bias resistors, recommended connect feedback resistor between (see Fig. Using this biasing method, possible apply same bias internal bias voltage times without being affected variations power supply voltage resistance values.
Fig. Miscellaneous information LOCKDET This output goes high level when code synchronization achieved. However, since LOCKDET sensitivity lower than synchronization sensitivity, near input sensitivity limit, even when demodulated output being made, LOCKDET output sometimes remain level. Treat this merely simple carrier detection signal. ANTDUMP This output proportional input level. However, since input dynamic range about output range variation about narrow, this output suitable signal meter. major application saturation prevention circuit amplifier under strong radio signal inputs. lock time reception about time switching power, about when there change from no-signal condition signal input condition. Recommended Components
Recommended component Resonator Variable coil Type 234.74MF10T115 LFB30N12B0236B024 CS-5N (SA-1100) Manufacturer Murata Mfg. Co., Ltd. Murata Mfg. Co., Ltd. Sumida Electric
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LV2700V
Input sensitivity
chips Data pattern chips @peak chips Data pattern chips -100 kbps
Data rate (kbps) characteristics output
chips -100 kHz, fdev
Input voltage (dBm@peak) Anti-interference characteristics
Peak power ratio (dB) Input voltage (dBm@peak) Frequency dependence anti-interference characteristics
Signal noise (dBV)
Peak voltage ratio
Input voltage (dBm@peak) control characteristics
Oscillator frequency (MHz)
Peak power ratio
Interference wave frequency carrier frequency (MHz) frequency divider input sensitivity
Mode input
Control voltage output
Input level (dBm)
Input frequency (MHz)
input power (dBm@peak)
Control sensitivity (MHz/V) 5651-16/20
Peak power ratio (dB)
illa
LV2700V
Lock output, control voltage
Lock output
150kHz Frequency characteristics
control voltage
control voltage
15chips
Input power (dBm@peak) 300kHz frequency characteristics
Lock output Relative level (dB)
Input frequency (kHz) output input
Output (dBm@peak)
Relative level (dB)
Input frequency (kHz) output power supply voltage dependence
input (dBm) Power supply current
Power supply voltage
Power supply current drain (mA)
output (dBm@peak)
Power supply voltage
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LV2700V Sample Application Circuit (Transmission side)
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LV2700V Sample Application Circuit (Reception side)
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LV2700V
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products described contained herein fall under strategic products (including services) controlled under Foreign Exchange Foreign Trade Control Japan, such products must exported without obtaining export license from Ministry International Trade Industry accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information September, 1998. Specifications information herein subject change without notice. 5651-20/20

Bi-CMOS LV2700V Spread Spectrum Communications Overview

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