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Intel Flash Memory Chip Scale Package User's Guide
Complete Reference Guide
1999
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life-saving, life-sustaining applications. Intel make changes specifications product descriptions time, without notice. Contact your local Intel sales office distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O.Box 5937 Denver, 80217-9808 call 1-800-548-4725 visit Intel's site http://www.intel.com
COPYRIGHT INTEL CORPORATION, 1999
*Other brands names property their respective owners.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CONTENTS
CHIP SCALE PACKAGING Applications PACKAGE ASSEMBLY PROCESS FLOW Product/Assembly Process Flow µBGA* Package Process Flow Description Easy Intel® Stacked-CSP Process Flow PACKAGE INFORMATION µBGA Package µBGA Package Drawing Dimensions Intel Stacked-CSP Intel Stacked-CSP Drawing Dimensions Easy Package Easy Package Drawing Dimensions Construction Material Sets SHIPPING MEDIA, HANDLING, DEVICE MARKINGS Shipping Media Overview 4.1.1 Shipping Media Selection Shipping Media 4.2.1 Tape Reel 4.2.2 JEDEC Trays 4.2.3 Electrical Samples 4.2.4 Shipping Media Orientation Shipping Media Socket Ordering Information 4.3.1 Ordering Information Device Markings Shipping Labels 4.4.1 Device Markings 4.4.2 Shipping Labels Handling Floor Life 4.5.1 Handling 4.5.2 Floor Life MANUFACTURING CONSIDERATIONS Process Design Guidelines 5.2.1 Escape Routing 5.2.2 Keep-out zones 5.2.3 Land Styles 5.2.4 Line widths Spaces 5.2.5 Vias Land Pads 5.2.6 Surface Finishes 5.2.7 Technologies 5.2.8 Multi-Site Layout Files
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Package Board Assembly Process 5.3.1 Solder Paste 5.3.2 Solder Stencils 5.3.3 Placement Alignment 5.3.4 Solder Reflow 5.3.5 Double-Sided Process 5.3.6 Cleaning 5.3.7 Inspection 5.3.8 Rework 5.3.9 Flux Only Attachment 5.3.10 Reballing 5.3.11 Test Accessories Programming Considerations 5.4.1 On-Board Programming (OBP) 5.4.2 Off-Board Programmers (OFBP) 5.4.3 Intel® Flash Memory Programmer 5.4.4 Distributors Value-Added Programming Service 5.4.5 Independent Programming Services
TOOLS SOFTWARE SUPPORT Tools Software Support Overview Tools Intel® Flash Memory Software Support Information QUALITY RELIABILITY ENGINEERING PACKAGE CERTIFICATION Introduction Quality/Reliability Verification Infant Mortality Summary High-Voltage Dynamic Lifetest High Temperature Storage (Bake) Package Pre-Conditioning Moisture Sensitivity Level Testing Temperature Cycle Steam (Autoclave) 7.10 Temperature Humidity Bias Test (85/85) 7.11 Solder Joint Reliability 7.12 Package Assembly Data 7.13 Bend/Push Test Data 7.14 Twist Test
APPENDIX FLASH SOLUTIONS DIVERSE APPLICATIONS Abstract General Application Values Handheld Application Values Embedded Application Values Package Solutions Handheld Applications Package Solutions Embedded Applications Easy Design/Cost Considerations Easy Surface Mount Technology Considerations Easy Reliability Considerations Conclusion References
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
APPENDIX CHIP SCALE REWORK USING SOLDER PASTE FLUX Chip scale rework compared magnification Future trends Rework Removal parts rework preparation Solder paste deposition Replacing Component Component placement Reflow CSP/MicroBGA Re-apply CSP-using flux Flux advances/techniques rework Conclusion APPENDIX SUCCESSFUL SOLUTIONS From Board design Solder paste printing Pick place, reflow Reflow, inspection rework Reliability Conclusion References APPENDIX SURFACE TENSION SELF-CENTERING BGAS APPENDIX SOLDER STENCIL PROCESS REFINEMENT µBGA ASSEMBLY APPENDIX SPECIFYING ATTACHMENT SITE FINISH BOARDS USING FINE-PITCH µBGA DEVICES APPENDIX ADVANCED FLASH MEMORY PACKAGES DRIVE INNOVATION
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
ACKNOWLEDGEMENTS
Intel would like thank following companies contributing content this document: Air-Vac Engineering Company, Inc. Progress Avenue Seymour, 06483 (203) 888-9900 www.air-vac-eng.com Jabil Circuits, Inc. Great Oaks Blvd. Jose, 95119 (408) 361-3200 www.jabil.com Merix Corporation 1521 Poplar Lane 3000 Forest Grove, 97116 (503) 359-9300 www.merix.com Plus, Inc. 5403-F Scotts Valley Drive Scotts Valley, 95066 (831) 438-6116 www.smtplus.com Tessera, Inc. 3099 Orchard Drive Jose, 95134 (408) 894-0700 www.tessera.com Xetel Corporation 2105 Gracy Farms Lane Austin, 78758 (512) 435-1000 www.xetel.com International, Inc. 1530 O'Brien Drive Menlo Park, 94025 (800) 776-1778 www.okinternational.com Johnson Matthey Advanced Circuits, 6442 City West Parkway Suite Eden Prairie, 55344 (612) 988-8700 www.jmei.com
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CHIP SCALE PACKAGING Introduction
Intel Flash Memory Chip Scale Package (CSP) User's Guide created review aspects CSPs location. Intel Flash Memory User's Guide designed easy-to-use reference source that covers wide variety different aspects using Intel® CSPs. These aspects include Intel introduced different types CSPs recent years, what makes them different, what types manufacturing design consideration should take into account prior selecting choice. Since introduction CSPs only short years ago, they have become biggest packaging trends recent history. There currently over different types CSPs available numbers increasing almost daily. CSPs evolving rapidly, that time read this guide, there will probably package information design considerations take into account. Intel attempted include much possible this guide cover many different areas such package information, application considerations, design, manufacturing tips tools. However, since CSPs continually evolving, contents this guide will continue evolve. Therefore, until versions this guide printed, package information manufacturing considerations will continue updated this guide Intel Flash Memory User's Guide begins explaining about various applications some CSPs more beneficial than others depending application. Other chapters cover such topics assembly flow diagrams package attributes Materials, packaging dimensions shipping media handling Printed Circuit Board (PCB) design considerations (trace/space, via, etc.) assembly manufacturing process recommendations manufacturing support tools Intel's quality criteria will also find full reference material (appendices) located back section this guide. Much this reference material contained various application notes technical papers that cover wide range topics including:
CHIP SCALE PACKAGING
Solutions Diverse Applications on-board programming rework (Solder paste/flux) surface tension self-centering CSPs solder stencils process refinements surface finishes Successful Solutions (additional design manufacturing considerations)
Applications
Intel provides full range Chip Scale Packages (CSP) your specific application. Each application packaging requirements that vary from smallest possible size, reliability, longterm footprint/size compatibility, unit cost, total cost, ease use. choice will vary depending which packaging requirements most important your application.
technical paper titled Solutions Diverse Applications located appendix section back this guide additional details different CSPs preferred different types applications. your application requires smallest possible package, µBGA* package (Figure 1-1) Intel® Stacked-CSP (Figure 1-2) best package choice your design. smallest size highest reliability, µBGA package remains best single-die your design. applications that flash SRAM, Intel Stacked-CSP adds value integrating Flash SRAM stacking both individual into package. This unique packaging approach provides ultimate size reduction eliminating component from board. These CSPs were designed meet demands handheld applications such cellular phones, pagers, personal digital assistants (PDA) Global Positioning Systems (GPS) units. Figure 1-1. µBGA* Package
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CHIP SCALE PACKAGING
Figure Easy Package routing using conventional technology. addition, large eutectic solder ball diameter size rigid laminate substrate package design allows excellent solder joint reliability over wide temperature range. While offering larger ball pitch compared other CSPs, Easy package maintains size benefits, measuring about half size TSOP equivalent package. Different markets require different packages. Intel provides full range CSPs best your specific application requirement.
Figure 1-2. Intel® Stacked-CSP Package
Other embedded applications such networking, automotive, set-top boxes, tele/data communications, measurement equipment products have different packaging requirements. While size still important factor these applications, lowest total cost (such manufacturing) long-term size/footprint compatibility highly valued. Easy package (Figure 1-3) package choice these types applications. Easy package relaxed 1.0-mm ball pitch that allows easy Package Highlights: µBGA Package Smallest single package Excellent moisture performance Solder joint reliability
Features: µBGA* Package:
Intel Stacked-CSP Combines Flash SRAM Approximately percent area reduction
Benefits:
Easy Long-term size/footprint compatibility Lowest total cost
Chip-size package 1.0-mm maximum package height Flexible polyimide tape elastomer package construction Combines Flash SRAM into package Available 16-Mbit flash/2-Mbit SRAM 32-Mbit flash/4-Mbit SRAM Uniform package size Thick laminate substrate Large eutectic solder balls 1.0-mm ball pitch
Best space-constrained board designs Allows low-profile application requirements Provides excellent long-term reliability over wide range field conditions Provides dual component functionality into single package Ideally suited wireless applications
Intel® Stacked-CSP:
Easy Package:
Provides easy upgrades density increases shrinks without need redesign Improves solder joint reliability Provides additional solder joint reliability Cost savings percent compared other fine pitch CSPs Maximum drill size 0.018" Maximum trace/space width 0.008" Provides easy routing
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE ASSEMBLY PROCESS FLOW
Product/Assembly Process Flow
cross-sectional diagrams illustrated below (Figures 2-1, 2-3) show various materials used manufacture packages. Figure 2-1. Cross-Sectional Diagram µBGA* Package
PACKAGE ASSEMBLY PROCESS FLOW
This section outlines manufacturing process flows (see Figures 2-4, 2-6). Following each step process flow brief description. Figure 2-4. µBGA* Package Manufacturing Flow
Figure 2-2. Easy Package
Figure 2-3. Intel® Stacked-CSP
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE ASSEMBLY PROCESS FLOW
Test µBGA packages processed through standard Intel tests. Ball Inspect Combines various ball inspection parameters utilizing laser-based inspection techniques. Inspections include ball count diameter, coplanarity, package height, length, width. Pack µBGA packages then packed into required shipping media such tape reel JEDEC trays with appropriate shipping material shipped.
µBGA Package Process Flow Description
Wafers µBGA package fabricated using standard Intel fabrication processes. Sort Standard Intel wafer level electrical tests. Elastomer Application Elastomer material applied polyimide interconnect tape, which provides base attached. elastomer modules material which decouples polyimide interconnect tape. Bond previously sawed attached elastomer tape. Ultrasonic Lead Bond lead beams, which part tape, thermosonically bonded bond pads die. Elastomer Fill Additional elastomer applied which encapsulates lead beams forms protective, compliant barrier entire µBGA package. Solder Ball Attach Eutectic solder balls (63/37 SnPb) then attached µBGA package. Mark Laser mark then performed µBGA package. Singulate µBGA packages then removed from tape strip individually singulated into JEDEC trays.
Easy Intel Stacked Process Flow
Easy Intel Stacked-CSP process flow very similar µBGA package. different process steps (Figures 2-6) explained below. Attach Epoxy Application Epoxy material applied substrate which provides base attached. Attach Silicon sawed from wafer attached epoxy substrate material. Wire Bond (Thermosonic) Traditional wire bonding attaches gold wires substrate pads. Mold Plastic encapsulation material formed around substrate/die shape final package.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Figure 2-5. Easy Package Manufacturing Flow
PACKAGE ASSEMBLY PROCESS FLOW
Figure 2-6. Intel® Stacked-CSP Manufacturing Flow
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE ASSEMBLY PROCESS FLOW
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE INFORMATION
NOTE: Please refer Web-based mechanical Spec detailed package dimensions This section reviews specific information such various construction, material sets, attributes, dimensional examples. also explains construction various mechanical samples referred Silicon Daisy Chain (SDC) samples used mechanical/process equipment set-up evaluation.
PACKAGE INFORMATION
silicon material during temperature variations, thus providing excellent reliability moisture performance (IPC level Figure 3-1. µBGA* Package
µBGA Package
µBGA package true chip size package. Because this, actual package dimensions dependent size silicon die. This section will show general package dimensions µBGA package. Please refer mechanical specification document Intel's site, contact your Intel representative latest, complete package dimensions, pinouts, schematics. µBGA package (Figure 3-1) 0.75-mm 0.5-mm ball pitch package takes full advantage reduction silicon size. This makes µBGA package smallest discrete Intel® Flash memory package. unique construction utilizes layer elastomer which decouples stresses caused coefficient thermal expansion (CTE) Table 3-1. Generic µBGA* Package Dimensions
Millimeters Symbol Package Height Ball Height Package Body Thickness Ball (Lead) Width (all 0.75-mm pitch) Ball (Lead) Width (all 0.50-mm pitch) Seating Plane Coplanarity Package Body Width Package Body Length Pitch Ball (Lead) Count Corner Ball Distance Along Corner Ball Distance Along 0.850 0.150 0.600 0.300 0.259 0.700 0.350 0.309 0.800 0.400 0.359 0.100 µBGA* Package Attributes Table 1.000 Notes 0.0335 0.0059 0.0236 0.0118 0.0102 0.0276 0.0138 0.0122 0.0315 0.0157 0.0141 0.0039 Inches 0.0394
Since size package equals size die, gets smaller fabrication lithography process reductions (die shrinks), does package. certain point, associated ball pitch will smaller well, order accommodate smaller size die. This eventually leads ball pitches small below. Currently majority µBGA packages 0.75-mm pitch. However, 0.5-mm pitch µBGA packages offer ultimate package size weight reduction will become package choice space constraint applications. industry moving quickly advanced Printed Circuit Board (PCB) technology will take full advantage µBGA packages 0.5-mm pitch below.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE INFORMATION
µBGA Package Drawing Dimensions
Figure 3-2. Example µBGA* Package Drawing Dimensions
NOTE:
µBGA package die-size dependent vary. Actual products vary with different levels matrix ball depopulation. Refer µBGA* Package Mechanical Shipping Media Specifications specific product/package dimensions/drawings pinouts Table 3-2. µBGA* Package Attributes Table
Ball pitch Square/ Rect. Package weight (mg) Matrix Actual ball count 6x10 5x11 SDCs2
µBGA* product name
GT28F008/800B3 0.75 GT28F016/160B3 0.75 GT28F160C3 GT28F320C3 GT28F160F3 G28F640J5 BG28F320D18 BG28FSDC Shipping Media Desiccant Pack1 0.75 0.75 0.75 0.75
7.910 7.286 7.286 8.000 7.670 7.520 6.794
6.500 6.964 10.850 10.240 16.370 13.420 7.530
1.330 1.018 1.018 0.625 1.214 1.135 0.897
1.375 1.607 3.550 3.245 5.935 2.960 2.765
µBGA products available Tape reel Trays µBGA products Level
NOTE: dimensions Desiccant Pack levels relate Moisture Sensitivity Levels, refer handling section this guide complete moisture level table. SDCs represent mechanical samples available various package size/type equivalents.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Intel Stacked-CSP
Another type gaining momentum industry "stacked" (Intel Stacked-CSP). These packages taking advantage multiple application requirements, such SRAM Flash, combining both into package (see Figure 3-3). However, instead placing individual side side (such multi-chip modules), Intel Stacked-CSP stacks each other maximum space savings advantage possible. Although package have larger ball pitch compared µBGA packages (0.8 0.75 mm), overall area Intel Stacked-CSP smaller than combined area separate components.
PACKAGE INFORMATION
Figure 3-3. Intel® Stacked-CSP
Intel Stacked-CSP Drawing Dimensions
Figure 3-4. Example Intel® Stacked-CSP Drawing Dimensions
NOTE:
Refer Intel Stacked-CSP Package Mechanical Shipping Media Specifications specific product/ package dimensions/drawings pinouts
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE INFORMATION
Millimeters 1.20 0.30 0.92 1.30 0.35 0.97 0.80 1.40 0.40 1.02 0.031 0.047 0.012 0.036 Inches 0.051 0.014 0.038 0.055 0.016 0.040 0.004 Intel® Stacked-CSP Attributes Table
Table 3-3.
Generic Intel® Stacked-CSP Dimensions
Package Height Ball Standoff Package Body Thickness Seating Plane Coplanarity Pitch Lead Count Package Body Width Package Body Length Corner First Bump Distance Along Corner First Bump Distance Along
Table 3-4.
Intel® Stacked-CSP Package Attributes Table
Square/ Rect.
Intel® Stacked-CSP product name RD28F1602C3 RD28F1604C3 RD28F3202C3 RD28F3204C3 Shipping Media Desiccant Pack
Package weight (mg) 180.3 231.6 227.8
Matrix (active)
SDCs2
10.00 12.00 12.00 12.00
8.00 8.00 8.00 8.00
1.20 1.20 1.20 1.20
0.60 1.60 1.60 1.60
products available Tape reel Trays Refer moisture barrier label specific level
NOTE: dimensions Desiccant Pack levels relate Moisture Sensitivity Levels, refer handling section this guide complete moisture level table. SDCs represent mechanical samples available various package size/type equivalents.
Easy Package
Easy package (Figure 3-5) designed flash memory package choice embedded applications. While offering larger ball pitch compared other CSPs, Easy package maintains size benefits, measuring about half size TSOP equivalent package. Another advantage Easy package constant package size/footprint respect memory density upgrades shrinks. element embedded applications need long product life cycles (5-7 years) that require same package size/footprint. only does package size/footprint need stay constant over time; will change result memory density upgrades process shrinks. This attribute very beneficial because many embedded applications increase memory density over time order incorporate additional functionality. Many embedded applications require high level reliability condition their environments. Easy been constructed specifi10
Figure 3-5. Easy Package
cally address these types requirements. Easy package construction incorporates many features that differentiate from other packages. Besides wider ball pitch previously discussed, Easy uses large diameter eutectic solder balls thick laminate rigid substrate. combination large solder balls thick laminate substrate provide very good reliability buffering maximizing separation between silicon surface minimize affects induced stresses.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Easy Package Drawing Dimensions
Figure 3-6. Easy Package Drawing Dimensions
PACKAGE INFORMATION
Table 3-5.
Easy Package Dimensions (all products)
Millimeters Symbol 0.250 0.715 0.330 9.900 0.780 0.430 0.845 0.530 1.200 0.0098 0.0281 0.0130 0.3898 0.5079 0.0307 0.0169 0.3937 0.5118 0.0394 0.100 1.400 2.900 1.500 3.000 1.600 3.100 0.0551 0.1142 0.0591 0.1181 0.0039 0.0630 0.1220 0.0333 0.0209 0.3976 0.5157 Notes Inches 0.0472
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner First Ball Along Corner First Ball Along
10.000 10.100 1.000
12.900 13.000 13.100
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
PACKAGE INFORMATION
Square/ Rect. Package weight (mg) 213.8 230.6 198.9 206.5 214.5 207.9 220.9 241.8 Matrix SDCs2 products available Tape reel Trays Refer Moisture barrier label specific level.
Table 3-6.
Easy Package Attributes Table
Easy product name RC28F800F3 RC28F160F3 RC28F800C3 RC28F160C3 RC28F320C3 RC28F320J3 RC28F640J3 RC28F128J3 Shipping Media Desiccant Pack
NOTE: dimensions Desiccant Pack levels relate Moisture Sensitivity Levels, refer handling section this guide complete moisture level table. SDCs represent mechanical samples available various package size/type equivalents.
Construction Material Sets
Table provides listing package construction material sets packages. Table 3-7.
Type Sq/Rect. Ball material Encapsulation material Attach material Substrate material Substrate trace material Substrate finish material Bond material Bond method (Cu) Copper Ultrasonic lead bond Elastomer Elastomer Polyimide tape (Cu) Copper (Au) Gold (Au) Gold wire Thermosonic Wire bond
Material Sets
µBGA* Package Easy 63/37 SnPb Epoxy mold compound Epoxy Laminate Intel® Stacked-CSP
Silicon Daisy Chain (SDC) Evaluation Units Intel also offers evaluation units that have been internally shorted together silicon) "daisy chain" pattern. This ensures that package's path complete through ball, substrate, lead beam bond wire, silicon, back down through separate path. These units useful set-up/ evaluation manufacturing equipment. Contact your Intel Representative more information.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Shipping Media Overview
NOTE:
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Shipping Media
Shipping media gaining more awareness from total cost manufacturing perspective. Tray tape/reel quality becomes essential small size CSPs order prevent misplacements other processing issues. Critical design tooling parameters like tray flatness media pocket tolerance improves device placement, throughput yields. Intel rigorous shipping media qualification process exceeds many industry design standards order ship CSPs with high level quality reliability. 4.2.1 Tape Reel CSPs shipped Tape Reel (T/R) utilize polycarbonate anti-static carrier tape Pressure Sensitive Adhesive (PSA) cover tape. CSPs have different quantity offerings: 2,000 Piece (Production) Piece (SDC samples) 2,000-piece quantity preferred high-volume method shipping CSPs from Intel customers. 100-piece quantity Silicon Daisy Chain (SDC) samples used mechanical system set-up evaluations. Refer Figures detailed carrier tape information. 4.2.2 JEDEC Trays CSPs shipped standard JEDEC trays generally offered stack multiples five full trays. Tray quantities vary depending type package being offered. Refer Figure specific tables detailed tray information. 4.2.3 Electrical Samples CSPs ordered samples two-piece Tapein-Tube shipping media. This approach consists standard two-piece carrier/PSA cover tape, which then placed into tube added protection. (See Figure Tape-in-Tube example.) utilizing cover tape, customer remove package peeling cover tape back re-use carrier/cover tape package housing required. Some electrical samples also offered piece Tape Reel. Consult your local Intel Sales Office Representative additional information.
Please refer Web-based Mechanical Shipping Media Specifications most up-to-date information 4.1.1 Shipping Media Selection industry moves into smaller packages with more features, shipping media constantly evolving well. Ideally, preferred type shipping media defined customer's optimized production process. recent trend programming flash memory onboard programming (OBP), which programs package after been placed PCB. benefits using that package remains original shipping media until placed assembly, therefore, eliminating extra handling processes which would normally occur during independent package off-board programming. consideration when choosing shipping media type programming method used. Off-board automated programming systems only certain types input/output media. important consider various media required programming and/or assembly processes. Both on-board off-board programming processes have their benefits, primary consideration when choosing which type shipping media comes down having good understanding your process requirements that quality ease-of-use optimized. Regardless means used programming, CSPs ships types shipping media, tape reel (T/R) JEDEC trays.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Figure 4-1. Carrier Tape Diagram
Table 4-1.
Carrier Tape Dimensions
µBGA* Package Carrier Tape Dimensions Single/ Double Sprocket Single Single
Pkg. Type 28F008S3 Other µBGA* Packages
Tape Size
1.65-1.85 1.65-1.85
3.9-4.1 3.9-4.1
11.9-12.1 11.9-12.1
0.27-0.29 0.32-0.34
11.9-12.3 23.9-24.3
Easy Package Carrier Tape Dimensions Pkg. Type Easy Products Tape Size 1.75 Single/ Double Sprocket Single 12.0 0.33 0.02 24.0 +0.3/-0.1
Intel® Stacked-CSP Carrier Tape Dimensions Pkg. Type 28F1602C3 28F1604C3 28F3202C3 28F3204C3 Tape Size 1.75 1.75 Single/ Double Sprocket Single Single 12.0 16.0 0.33 0.02 0.33 0.02 24.0 +0.3/-0.1 24.0 +0.3/-0.1
NOTE: dimensions
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Figure 4-2. Carrier Tape Reel Diagram
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Table 4-2.
Millimeters Maximum Minimum
Carrier Tape Reel Dimensions
20.2 16.0 20.2 30.4
Maximum
NOTE: Dimensions millimeters
Figure 4-3. Injection Molded Thin JEDEC Tray
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Columns Rows Pockets
Table 4-3.
Pkg. Type 28F008S3 28F016S3 28F800B3 28F008B3 28F160B3 28F016B3 28F160B3_A 28F016B3_A 28F160C3 28F320B3 28F320C3 28F320D18 28FSDC50 28F160F3 28F640J5 Pkg. Type products Pkg. Type 28F1602C3 28F1604C3 28F3202C3 28F3204C3
Injection Molded Thin JEDEC Tray Parameters
µBGA* Package Thin Tray Dimensions 17.246 12.052 12.390 13.386 18.9 16.129 12.128 11.532 12.522 13.462 19.380 15.367 17.043 12.4 9.220 12.420 13.919 13.640 10.9
15.7 12.95 11.85 18.9 13.386 19.30 20.00 14.40
12.15 9.00 19.380 14.70 14.70 14.70
12.4 15.30 11.00 12.4 25.121 16.80 11.90 11.90
10.00 10.20 10.9 13.640 13.90 13.70 15.30
Rows Rows
Columns Columns
Pockets Pockets
Easy Package Thin Tray Dimensions
Intel® Stacked-CSP Package Thin Tray Dimensions
NOTE: Dimensions millimeters
Figure Two-Piece Sample Tape-in-Tube
Package/Shipping Media Orientation
JEDEC Trays
4.2.4 Shipping Media Orientation shipping media orientation displayed figure below. Note that package/shipping media orientation referenced package mark. Tape/Reel, faces towards carrier tape sprocket holes (quadrant JEDEC trays, faces towards tray's chamfered corner side.
Carrier Tape
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
NOTE:
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Shipping Media Socket Ordering Information
Please refer Web-based Mechanical Shipping Media Specifications most up-to-date information Additional programming socket information found Electronic Tools Catalog (ETC) under sockets tool type 4.3.1 Ordering Information Shipping media off-board programming sockets purchased directly from manufacturers. These materials have been designed qualified Intel ensure optimal quality reliability same materials used internally testing shipping media. Many socket bases have been designed accommodate multiple package sizes replacing removable inserts. This programming socket design approach provides low-cost flexibility density upgrades and/ multiple package utilization. Refer Electronic Tools Catalog site above additional ordering information. following tables list various materials, manufacturer's part numbers, U.S. contact information. outside U.S., please consult manufacturer's nearest sales office.
NOTE:
Carrier Tape
Vendor: Contact 1-800-666-8273 µBGA* Packages Product 28F008S3 28F800B3 28F160B3 28F640J5 28F160B3_A 28F016B3_A 28F160C3 28F160C18 28F320D18 28F320C3 28F160F3 EASY Packages (all) 28F1602C3 28F1604C3 28F3202C3 28F3204C3 Part Number US035751 US040001 US038431 US039141 US044581
3M049281 3M051581 US046761 US045081 Easy Package US048641
Intel® Stacked-CSP Packages US048631 US048681
Cover Tape
Vendor: Contact 1-800-666-8273 Product 28F008S3 µBGA* Package other CSPs Part Number #2666 Cond. #2666 Cond.
hardware vendor remains solely responsible design, sale functionality product, including liability arising from product infringement product warranty.
Reels Pc.)
Vendor: Advantek Contact 1-612-938-6800 Product 28F008S3 µBGA Package other CSPs Part Number RD33704SW RD33708SW RD33708SW RD33716SW
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
JEDEC Thin Trays
Distributor: Alliance Electronics Contact 1-303-433-1648 Product 28F008S3 28F800B3 28F160B3 28F640J5 Part Number µBGA* Packages 21002-370 21002-373 21002-371 21002-372
Device Markings Shipping Labels
4.4.1 Device Markings packages laser marked. typical device mark shown Figure 4-5. Explanations markings follow: Line one: Marketing name. Represents memory density, configuration (x8/x16 00X/X00 respectively), product family/voltage. Line (µBGA package Easy BGA): First character represents type sample: Silicon Daisy Chain Engineering Mechanical Production (Last digit production year) Second character represents assembly site code. Third fourth represent serial number (01-ZZ). Fifth sixth represent work week code. Line (Intel Stacked-CSP only): Represents finish process order information. Line three four (Intel Stacked-CSP only): Represents SRAM assembly information. Figure 4-5. Device Marking Diagram
Vendor: Daiwon Contact (408) 562-6172 (USA) 82-347-794-2001 (Korea) 28F160B3_A 28F016B3_A 28F160C3 28F320C3 28F160C18 28F160F3 EASY Packages 28F1602C3 other Intel Stacked-CSP 12E-0607-C13
12E-0710-C13 12E-0706-C13 12E-0810-C13 Easy Packages 12B-1013-G13
Intel® Stacked-CSP Packages 12R-0810-213 12R-0812-213
Programming Sockets
Vendor: Yamaichi Contact 1-408-456-0797 Product 28F008S3 28F800B3 28F160B3 28F640J5 Part Number NP291-04002-G4-BF-P NP291-04812-G4-BF-P NP291-04808-G4-BF-P NP291-07210-G4-BF-P
Vendor: Texas Instruments Contact (508) 236-5216 28F160B3_A 28F016B3_A 28F160C3 28F320B3 28F320C3 28F160F3 Easy Packages 28F1602C3 28F1604C3 28F3202C3 28F3204C3 CBG048-035C13
CBG048-035B CBG060-044A Easy Packages CBG064-052A
Intel® Stacked-CSP Packages FBGA072-003A FBGA072-003B
4.4.2 Shipping Labels packages packed into trays, then sealed moisture barrier bags (MBB) with desiccant card desiccant bags, finally cardboard box. Labels placed individual cardboard which list product name, moisture level, number, other pertinent information (Figure 4-6). shipments samples shipped tape-intube, additional labels attached individual plastic reels tubes which provide same information labels. These provided added traceability during manufacturing process (Figure 4-7).
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CUST PROD: SUPPLIER: 04195 (M): (1P) IPN: G28F800B3T120 SPEC:
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Figure 4-6. Moisture Barrier (MBB) Label
(1B)
RW001104
(C): LEVEL
HOURS
SEAL DATE
08AUG97
(IT) LOT: T1234567
QTY: 2000
(9D) DATE: 9732
(IT) LOT:
QTY:
(9D) DATE:
Figure 4-7. Tube Tape Label
INTEL FPO# T1234567 SPEC: 2000
PRODUCT: G28F800B3T120
Handling Floor Life
4.5.1 Handling When manually automatically handling CSPs, like other semiconductor package, appropriate care handling precautions should addressed during manufacturing process. Although bent lead issues have been eliminated because nature packages, there still standard handling precautions that should addressed during various aspects manufacturing process. Standard manufacturing processes, which utilize automated pick place systems component transfer (off-board programming, placement systems, etc.) present additional risks concerns CSPs. with package, equipment set-up should verified excessive pick/place over-travel. However, manual handling practices vary widely within many manufacturing processes, leading additional risks process excursions. This majority handling precautions being discussed related manual handling process. 4.5.1.1 Manual Handling JEDEC Trays When handling CSPs JEDEC trays, always ensure cover tray attached. Avoid abrupt tray movement when cover tray removed eliminate possibility packages popping tray pockets.
Handling When manually handling CSPs, safe vacuum wands preferred, however, utilizing nonmetallic tweezers acceptable. using vacuum wand, preferred type battery powered vacuum wand that increases vacuum integrity reduces risk dropping package vacuum seal lack vacuum. Non-metallic tweezers should have flat contact area, avoid pointed type tweezers, which cause edge chips damage polyimide tape elastomer (µBGA package only). using non-metallic tweezers, contact sides package only, this simplifies placement avoids contact eutectic solder balls. After reflow, once µBGA package been mounted PCB, avoid depressing lifting package using excessive force. preferred method handling PCBs PCB's edge order minimize direct component contact. must reworked, standard rework station which equipped with automatic vacuum nozzle pickup which profiled lift component during liquid state solder paste/balls. rework station doesn't have this capability, always vacuum wand component pickup. Avoid using objects such screwdrivers other similar instruments devices during reflow/rework process. Design Considerations When designing PCB, avoid designs which require excessive contact component normal product handling practice, such installing connector reverse side where located. This usage model would require user depress directly package order insert connector.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
ASSEMBLED PHILIPPINES
SHIPPING MEDIA, HANDLING, DEVICE MARKINGS
Moisture Exposure Temp/Humidity Time 6962 85°C/85%RH 85°C/60%RH 30°C/60%RH 30°C/60%RH 30°C/60%RH 30°C/60%RH 30°C/60%RH
4.5.2 Floor Life Although Intel does specify maximum length time storage shelf life CSPs, current floor life varies depending type based moisture sensitivity rating IPC/JEDEC standard J-STD-020A. Generally, µBGA package level year MBB) Easy Table 4-4. Moisture Level Table
Level Description
Intel Stacked-CSP targeted level weeks MBB) better. However, each package qualified independently vary, manufacturing process constantly being improved levels subject change, therefore, always refer label exact moisture level described earlier this chapter.
Floor Life (Out Bag) Board Assembly Site Unlimited 30°C/85%RH Year 30°C/60%RH weeks 30°C/60%RH Week 30°C/60%RH 30°C/60%RH 30°C/60%RH 30°C/60%RH Time label (TOL)
Non-Moisture Sensitive Limited Moisture Sensitive Limited Moisture Sensitive Moisture Sensitive Highly Moisture Sensitive Extremely Moisture Sensitive Extremely Moisture Sensitive Bake Before
Bake 125°C hours before
NOTE: "Manufacturer's Exposure Time," compensation factor which accounts time after bake that component manufacturer requires process components prior seal, including factor distribution handling. Refer Joint IPC/JEDEC standard J-STD-020A additional information.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
MANUFACTURING CONSIDERATIONS
Process
Many factors contribute high yielding assembly process. focus areas their contributing factors highlighted Table 5-1. industry moves CSPs because many manufacturing benefits that tend produce higher assembly yields, such self-alignment characteristics lack coplanarity issues caused bend leads, focus shifts other areas optimize yields overall quality even further. This section reviews many design guidelines that help improve manufacturing process. However, also important understand design guidelines help improve CSP's solder joint reliability (SJR) quality extended life application's field. Chapter reviews Intel certifies their packages qualification process evolving order meet application's requirements. following design manufacturing guidelines have been together provide best known methods manufacturing while maintaining demands long-term application, quality reliability.
MANUFACTURING CONSIDERATIONS
signals from underneath package other components PCB. There many possible ways escape routing. This important since define signal trace space widths, sizes, number layers that used PCB-all which factors determining cost. Figure example escape routing diagram. Many escape routing files located Intel's Electronic Tools Catalog (ETC) downloadable Gerber files. Please refer going Intel's page 5.2.2 Keep-out zones Another design element keep-out zone area. This distance each side component nearest adjacent component board. This keep-out zone varies depending application generally much tighter handheld applications that require many components very small area. While system designers will often design keep-out zones anywhere from 0.100 0.050 inches embedded applications, many handheld applications trending toward 0.025 smaller. factor consider component will reworked needs replaced. Some Original Equipment Manufacturers (OEMs) require rework done using nozzle that isolates rework area specific component being reworked. Special consideration would required allow adequate area nozzle surround being reworked. Some rework manufacturers have designed custom rework nozzles that maintain very tight keep-out zones (see Electronic Tools Catalog [ETC] Web). Figure 5-1. Sample Escape Routing Diagram
Design Guidelines
There many factors consider when designing CSPs. factors initial decision which type selected application. This selection often based specific application's packaging values. Refer appendix technical paper titled, Solutions Diverse Applications appendix this guide. technology improving, just packaging technology improving. success customers providing packaging solution that compatible with today's technology. Intel asked customers what they needed CSP. customers told that they wanted packages costeffective easily integrated into today's manufacturing infrastructure. Easy package best choice embedded applications lowest cost conventional technology. Intel Stacked-CSP µBGA packages best choice space-constrained applications 5-mil spaces/traces, 0.020 inch pads. This fairly standard technology handheld applications, major driving factor choosing 0.75- 0.8-mm ball pitch. 5.2.1 Escape Routing efforts implementing packages PCB, design "escape routing." Escape routing basically determining route
5.2.3 Land Styles There basic designs land pads packages, Metal Defined style Solder Mask Defined style. Either type acceptable µBGA package. other packages, metal defined land pads recommended. Refer section 5.2.4 (PCB line widths spaces) design guidelines.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
MANUFACTURING CONSIDERATIONS
Table 5-1.
Essentials Assembly Quality
Uniform viscosity texture. Free from foreign material. Solder paste should used before expiration date. Shipment storage temperatures maintained proper temperature. Paste protected from drying solder stencil. Clean, flat, plated coated solder ball land area. Attachment surface must clean free solder mask residue. Tight tolerances usually required. packages self-center itself long major portion (more than percent) solder ball contact with solder paste covered land area board. Alignment marks (fiducials) helpful verifying correct placement parts. solder reflow profile will dependent design, thickness, type components, component density, recommended profile solder paste being used. reflow profile will need developed each type using various packages. Refer reflow profile solder reflow section this chapter.
Solder Paste Quality
Quality Placement Accuracy
Solder Reflow Profile
post-reflow solder profile tends slightly different between types land pads. Vern Solberg, Director Advanced Manufacturing Technology Tessera, Inc., noted following differences shape solder joint after reflow: Metal Defined style-This land pad, that free mask materials, promotes uniform tapered slope column profile solder ball shown below. Solder Mask Defined style-This approach promotes controlled collapse ball profile shown below. Figure 5-2. Post Reflow Solder Joint Profile
reductions, costs increase tighter design requirements. 0.5-mm pitch CSPs (Figure 5-5) design requirements become more demanding regards line widths spaces. Your specific finished tolerances vary depending requirements your application, abilities your manufacturing process. 5.2.5 Vias Land Pads When using multi-layer PCB, methods routing signals from package more vias drop signal another layer PCB, then route trace. Conventional technology uses mechanical drills accomplish this during manufacturing process. Vias that dropped other layers within ball grid array pattern referred interstitial vias. Generally, using conventional trace widths 0.005", fully populated ball grid array pattern greater than will require interstitial vias. Many CSPs have been designed with depopulated balls within array order allow single layer escape routing. Various drill sizes used create vias depending ball pitch (Figures 5-4). This significant factor when choosing best package your application because size requirements vias biggest factors contributing manufacturing cost PCB. While much industry moved conventional drill sizes 0.014" 0.010", many manufacturers still drill sizes large 0.018". While Easy package drill 0.018" vias, µBGA package Intel Stacked-CSP packages generally 0.010" drilled vias. ball pitch package gets smaller, cost manufacturing increases eventually types manufacturing, such microvia High Density Interconnect (HDI) will required. example, CSPs with ball pitch generally require this type technology interstitial vias.
preferred land style Metal Defined design since allows maximum flexibility designer, less stress points introduced solder joint solder mask. 5.2.4 Line Widths Spaces line widths spaces will vary depending pitch being used. Generally, conventional technology allows 5-mil line width spacing CSPs with ball pitches down 0.75 Refer Figures various design guidelines lines spaces CSPs. discussed chapter ball pitches smaller order take full advantage package size
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Recommended Style: Metal Defined Land Pads
Land Size Solder Mask Opening Metal Mask Clearance Max. Trace Width Typical Spaces
MANUFACTURING CONSIDERATIONS
Figure 5-3. Design Guidelines 0.75 mm-µBGA*, Intel® Stacked-CSP, Easy Packages
µBGA* Package, Intel® Stacked-CSP Easy Design Guidelines
Feature
0.75-mm µBGA* 0.30 (0.012) 0.431 (0.018) 0.050 (0.002) 0.127 (0.005) 0.160 (0.00625) 0.51 (0.020) 0.25 (0.010)
0.8-mm 1.0-mm Easy Intel® Stacked- 0.30 (0.012) 0.431 (0.018) 0.050 (0.002) 0.127 (0.005) 0.187 (0.0073) 0.510 (0.020) 0.25 (0.010) 0.30 (0.012) 0.431 (0.018) 0.050 (0.002) 0.233 (0.009) 0.233 (0.009) .711 (0.028) 0.457 (0.018)
Land Size Solder Mask Opening Metal Mask Clearance (Min) Max. Trace Width Typical Spaces Max. Capture Max. Drill Size
Max. Capture Max. Drill Size
Land Solder Mask
dimensions (inches)
Figure 5-4. Design Guidelines 0.5-mm µBGA* Packages
0.5-mm µBGA* Package Design Guidelines
Recommended Style: Metal Defined Land Pads
Land Size Solder Mask Opening
Feature
Typical Trace Width
0.5-mm µBGA* 0.279 (0.011) 0.356 (0.014) 0.1016 (0.004) 0.0737 (0.0029) 0.1016 (0.004)
Land Size Solder Mask Opening Typical Trace Width
Reduce Trace Width Between Land Pads
Trace Layer Typical Micro (Via-in-Pad) Size Land Solder Mask
Reduce Trace Width Between Land Pads Typical Micro (Via-in-Pad) Size
dimensions (inches)
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MANUFACTURING CONSIDERATIONS
Generally, handheld applications thinner PCBs than embedded applications. However, pitch decreases, diameter decrease accordingly. This presents design considerations when requires less than 0.010" vias. current technology mechanical drilling reaches cost capability cliff vias requiring less than 0.010" holes. Newer substrate technologies buildup multilayer boards with microvia order achieve these tighter pitch parameters. last categories Table specific high-density interconnect PCBs basis technology. many cases, additional costs associated with advanced technologies offset reduction metal layers size. Smaller pitch packages will beneficial customers require most advanced space saving/weight saving devices. Some Intel's products offered 0.5-mm pitch µBGA packages. 5.2.8 Multi-Site Layout Files Multi-site layouts (also referred flex-layouts) available from Intel variety flash memory components (see Figure 5-5). Multi-site layouts land designs that allow user flexibility either Small Outline Package (TSOP/ SSOP) package same land layout. These useful plans phasein package their production line. Multi-site layouts also make troubleshooting prototype PCBs easier allowing test point access array. However, there other tools that provide prototype test point access well CSP. Refer "Signal Access Tools CSPs" located Electronic Tools Catalog, Test accessories category additional information. Multi-site layout files also available Electronic Tools Catalog
5.2.6 Surface Finishes There variety surface finishes commonly available. factor selecting acceptable surface finish ensure that land pads have "uniform" coating. Irregular surface plating, uneven solder paste thickness crowning solder plating reduce overall surface mount yields. Bare Copper with Organic Solderability Preservative (OSP) coating, electroless nickel/immersion gold, electroplated nickel/ gold finishes have shown provide acceptable land surface. electroplated nickel/gold finish chosen, gold thickness must less than micro inches prevent embrittlement finished solder joint. type surface finish that should avoided referred dry-film process. This because copper undercut effect caused during film removal prevents optimal sidewall wetting during reflow process. more details Surface Finishes, Appendix, Tessera Application Note Specifying Attachment Site Finish Boards Using Fine-Pitch µBGA* Devices. 5.2.7 Technologies Many advanced technologies quickly emerging. most promising technologies tend fall into category called micro-via High Density Interconnect (HDI), where very small vias used selectively drop signal another layer PCB, then route signals other components PCB. been defined using blind vias measuring less than 0.006" (0.15 diameter 0.014" (0.35 smaller diameter pad. Some micro-via technologies being explored laser drilled, photo-defined, plasma-etched vias. Some studies have been done that categorize various technologies (see Table 5-2).
Table 5-2.
Typical Design Rules PCBs
Conventional 0.012 0.006 0.007 0.018 0.028 Advanced 0.012 0.004 0.004 0.014 0.022 Leading Edge 0.006 0.003 0.003 0.009 0.016 0.004 0.011 MOST MANY ~65% State 0.0055 0.002 0.002 0.006 0.014 0.002 0.008
Feature (inch) Contact Diameter Line Width Spacing Width Drill Diameter Drill Capture Microvia Diameter Microvia Capture Availability (worldwide)
(Source: TechLead Corp.)
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Figure 5-5. Sample Multi-Site Layout Diagram
MANUFACTURING CONSIDERATIONS
Thickness stencils usually 0.10-mm 0.15-mm (0.004" 0.006") range. actual thickness your stencil also dependent other surface mount devices PCB. paste materials tend when properly environmentally controlled. squeegee durometer harder should used. blade angle speed must fine-tuned ensure even paste transfer. inspection stenciled board recommended before placing parts proper stencil application most important factor with regards reflow yields further process. additional details, Appendix Solder Stencil Process Refinement µBGA* Assembly. 5.3.3 Placement Alignment pick place accuracy governs package placement rotational (theta) alignment. This equipment/process dependent. Slightly misaligned parts (less than percent center) will automatically self-align during reflow (see Figure 5-7). Grossly misaligned packages (greater than percent center) should removed prior reflow they develop electrical shorts, result solder bridges, they subjected reflow. More information self-alignment feature available Appendix Surface Tension Self Centering BGAs. There popular methods package alignment using machine vision: Package silhouette-the vision system locates package outline Ball recognition-Some vision systems directly locate solder ball array pattern Both methods acceptable placement. ball recognition type alignment tends more accurate, also slower since more complex vision processing required pick place machine. package silhouette method allows pick place system faster, generally less accurate. Both methods acceptable, have been successfully demonstrated major pick place equipment vendors, contract assembly houses. 5.3.4 Solder Reflow There special requirements necessary when reflowing components. with components, important that profiles checked board designs. addition, there multiple packages board, profile should checked different locations board. Component temperatures vary because surrounding components, location part board, package densities. maximize self-alignment effect CSPs (see Figure 5-7), recommended that maximum reflow temperature specified solder paste exceeded.
Package Board Assembly Process
5.3.1 Solder Paste quality paste print important factor producing high-yield assemblies. paste vehicle providing flux solder alloy necessary reliable repeatable assembly process. residue, no-clean solder paste with Sn63/Pb37 commonly used mounting CSPs, however water soluble flux materials widely used well. Typically choice solder paste determines profile reflow parameters. Most paste manufacturers provide suggested thermal profile their products should referenced prior manufacturing. Special specific solder pastes being marketed paste vendors that exhibit minimized voiding solder joint. Intel experienced excellent surface mount results using residue, clean solder paste. 5.3.2 Solder Stencils stencil thickness, well etched pattern geometry, determines precise volume solder paste deposited onto device land pattern. Stencil alignment accuracy consistent solder volume transfer critical uniform reflow-solder processing. Stencils usually made brass stainless steel, with stainless steel being more durable. stencil with either round aperture, square hole with tapered openings recommended applications. addition, aperture should trapezoidal ensure uniform release solder paste reduce smearing. Refer Figure solder stencil design guidelines.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
MANUFACTURING CONSIDERATIONS
Figure 5-6. Solder Stencil Diagram
Solder Stencil Design
Solder Stencil process keys achieving defect rate Stainless steel, laser/chemical etch, electropolished 0.005 Thickness Trapezoidal apertures 0.5-mm 0.75-mm 0.8-mm 1.0-mm Easy µBGA* µBGA Intel® StackedBGA 0.279 (0.011) 0.30 (0.012) 0.127 (0.005) 0.33 (0.013) 0.356 (0.014) 0.127 (0.005) 0.33 (0.013) 0.356 (0.014) 0.127 (0.005) 0.33 (0.013) 0.356 (0.014) 0.127 (0.005)
Feature
stencil aperture Bottom stencil aperture Stencil thickness
dimensions (inches)
Production rework profiles Intel Flash CSPs same other leaded Intel® Flash memory small outline packages (TSOP, SSOP). reflow profile guidelines based temperature actual solder ball land solder joint location. actual temperature solder joint often different than temperature settings reflow/ rework system location system thermocouple/RTD placement used monitor temperature. Specific production reflow rework systems vary depending manufacturer model number. Therefore, system specific profiles should established using thermocouples actual solder joint locations characterized using reflow guidelines below (see Figure 5-8). maximum temperature most CSPs subjected 240°C less than seconds. Intel tested qualified CSPs maximum three reflow operations. This allows reflow operation side (assuming double-sided PCB), rework operation necessary.
Zones Preheat Pre-Reflow Reflow Cool Down Characteristic Description
Figure 5-7. Package Self-Alignment Solder Reflow
Before Reflow
During Reflow
After Reflow
Windows/Limits 1-3°C/second 100-140°C 120-170°C Seconds 45-120 Seconds 205-225°C C/second
Initial heating lead/component Peak temperature Dryout solder paste activation Soak Time Time above 183°C Peak component body temperature Cooling rate
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Figure 5-8. Typical IR/Convection Reflow Profile (Ball location)
MANUFACTURING CONSIDERATIONS
sometimes been shown collection point outside contamination board surface. Because there many different types no-clean solder pastes available, application specific evaluations should performed remaining residue still needs removed from boards final application.
NOTE:
µBGA package only: post assembly cleaning will done, some chemicals attack elastomer package body. Known problem chemicals Terpene TCE. materials have shown problem. there question regarding other chemical interactions, please contact Intel Technical Support Line. 5.3.7 Inspection Inspection CSPs typically accomplished using transmission type X-ray equipment. most cases, percent inspection performed. Typically, X-ray inspection used establish process parameters, then monitor production equipment process. Transmission X-ray detect bridging, shorts, opens, solder voids. photo below shows results typical transmission X-ray. There many different types X-ray inspection equipment available functionality varies. X-ray inspection system features range from manual automated inspection. Different systems also provide single multiple dimensional inspection capabilities.
5.3.5 Double-Sided Process double-sided mounting reflow operation successfully been demonstrated, required special processes. Follow process above each side PCB. example, solder paste applied side PCB, units placed PCB, then solder reflow operation performed. turned over, process repeated. figure below shows cross sectional view double-sided using µBGA packages.
Photo: Courtesy Xetel Corporation
Photo: Courtesy Xetel Corporation
5.3.6 Cleaning residue, no-clean solder paste used, cleaning required, little effect CSPs. With elimination containing materials, most companies moving no-clean aqueous flux-based system. clean" fluxes solders simply mean that there harmful residues left board that will cause corrosion damage components left board. This residue
Another "quick" inspect proper package alignment after reflow process, fiducial marks that printed PCB. This common practice world. preferred method design fiducial alignment marks metal layer PCB. next example, signal traces were designed used package alignment simply covering traces with solder mask specific locations.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
MANUFACTURING CONSIDERATIONS
5.3.9 Flux Only Attachment solder paste recommended best package attachment results. However, fluxonly attachment been common practice packages during component rework. However, there factors that need considered prior using this method. Since flux-only attachment application reduces amount solder within solder joint, stand-off reduced, solder joint reliability compromised. Each manufacturer must evaluate flux-only solder paste application determine feasibility which process use. additional information rework, refer appendix, Rework Using Solder Paste Flux. 5.3.10 Reballing Reballing CSPs recommended production applications. This primarily variation techniques used when removing excess solder (redressing) from bottom side after been removed from PCB. Excessive heat during redress process damage CSP. However, when properly controlled, reballing successfully done. This necessary process commonly used during failure analysis process, especially balls must re-attached order verify proper programming flash device completed. Special reball fixtures tools have been designed simplify help control this process. additional information, refer test accessories category 5.3.11 Test Accessories Many test accessories have been developed system designer during development prototype stage product development cycle. such debug tool developed Signal Access Tool* (SAT). Signal Access Tool (Figure 5-9) designed allow test point access input/ output signals routing test points around perimeter while maintaining required keep-out zones (the required distance adjacent component PCB). Signal Access Tool only designed maintain minimal keep-out zones 0.025", also footprint compatible with there need redesign PCB. MicroGrippers designed connect devices with lead pitches small 0.012" using wire diameters 0.003". thin body design insulated wire tips allow side-by-side placement multiple MicroGrippers test/debug using logic analyzers oscilloscopes.
NOTE: Solder Mask removed traces alignment
explained "alignment" section this document, CSPs will self align land using surface tension during solder reflow process. Because this, very unlikely that will misaligned "just little." misalignment does occur, likely entire row. Because this, possible gross visual alignment check after reflow. fiducial marks also useful manually placing units rework process. 5.3.8 Rework Rework equipment continued progress rapidly address CSPs. Many manufacturers single rework station incorporate multiple rework process steps, such component removal, site redress, solder paste/flux application, alignment, component placement reflow. advancement beam-splitting imaging alignment/placement other areas such characterizing storing individual component reflow profiles greatly simplified rework process. With direction CSPs allowing more functionality/features smaller products, areas concern thermal separation adjoining components during rework process. Some manufacturers have addressed this concern designing nozzles which maintain keep-out zone area around rework component thermally isolate adjacent components during reflow process. Original Equipment Manufacturers have differing requirements when comes solder paste flux only applications during rework process. those require solder paste, micro-stencils squeegees have been developed correspond with multiple existing sizes ball array footprints. These micro-stencils aligned using same beamsplitting imaging component placement. Micro-squeegees allow simple, uniform solder paste coverage across micro-stencil. additional information rework, refer appendix, Rework Using Solder Paste Flux.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
additional information, refer test accessories category Figure 5-9. Signal Access Tool*
MANUFACTURING CONSIDERATIONS
View
Side View
Signal Access Tool µBGA* Package
Programming Considerations
There many ways program Intel flash CSPs. Traditional programming methods have mainly been off-board programming (OFBP) where individual flash components have been programmed prior being attached PCB. Another method recently being used on-board programming (OBP) where flash component programmed after being attached PCB. There benefits tradeoffs associated with each type programming approach ultimate decision question which approach provides most value OEM's manufacturing process. Some factors consider include cost implementation, maintenance/tech support, product flexibility, ease/speed code changes impact process throughput time, etc. 5.4.1 On-Board Programming (OBP) There several methods select from. Traditional Automatic-Test-Equipment (ATE) bed-of-nail approaches generally practical because there
generally test point access balls once attached PCB. method that gaining momentum IEEE 1149.1 (JTAG) Test Access Port program flash memory. This programming method requires only four signal connections JTAG compliant processor. Please work with your company's design, software manufacturing engineers determine which method best fits your application requirements. Intel offers following application notes provide technical details about various methods: AP-624 Introduction On-Board Programming with Intel Flash Memory, Order Number: 292179 AP-629 Simplify Manufacturing Using Automatic-Test-Equipment On-Board Programming, Order Number: 292185 AP-630 Designing On-Board Programming Using IEEE 1149.1 (JTAG) Access Port, Order Number: 292186 Intel application notes available Intel Flash Memory Programming Tools page also refer many other programming tools Electronic Tools Catalog same address above. technologies create opportunities innovative engineers approaches traditional programming challenges. Intel third-party vendors developed literature guide titled, Flash Memory Advanced Programming Handling which provides information about various on-board-programming techniques handling solutions. contains application notes providing technical details required implement manufacturing environment. available through Intel Literature Centers United States Swindon, order number 297787 (U.S. 800-548-4725 +1-708-296-9333 from overseas. Swindon +44(0)1793-431155). Intel encourages you, after reviewing information, contact vendors listed kit. They willing help solve unique flash memory programming handling challenges your leading-edge products. 5.4.2 Off-Board Programmers (OFBP) Off-board programming (OFBP) widely used there many different programming manufacturers available. There many different types OFBP systems ranging from totally automated concurrent, multiple-site systems manual gang, single multiple-site systems. Intel works closely with programming system manufacturers ensure programmer support available flash memory products product introductions. find more about Intel programming advantage complete listing sockets,
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
MANUFACTURING CONSIDERATIONS
adapters device programmers that support Intel flash memory CSPs please programming tools site Electronic Tools Catalog (ETC) available Intel 5.4.3 Intel® Flash Memory Programmer Intel® Flash Memory Programmer enables system designers program erase Intel® Flash memory devices. Intel Flash Memory Programmer designed engineers want evaluate flash products. work with leading companies ensure software hardware available your designing requirements 5.4.4 Distributors Value-Added Programming Service Intel works with variety distributors provide value-added programming services Intel flash memory components. this programming method appeals your needs please refer Electronic Tools Catalog (ETC) available Intel 5.4.5 Independent Programming Services Intel works with variety independent programming services provide value-added programming service Intel flash memory components. this programming method appeals your needs please refer Electronic Tools Catalog (ETC) available Intel
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
TOOLS SOFTWARE SUPPORT
Tools Software Support Overview
Today's competitive flash memory market demands more than just best products successful. Development tools software that help design your product using Intel® Flash Memory products part your success. Using Intel Flash Memory Tools Software reduce your product development time saves money getting your product market faster. Tools Software described everything that help design Intel Flash Memory "silicon" products your application. Intel® Flash Memory Tools Software found Flash Tools Software page Electronic Tools Catalog (Figure 6-1) Electronic Tools Catalog alone over tools from more than companies that provide solutions during definition, design, prototype, production stages your product development cycle. These tools were developed based customer requests industry demands. Here some examples Intel Flash Memory Tools Software:
TOOLS SOFTWARE SUPPORT
Programmer-Evaluated Programmer-Gang Programmer-Handler Programmer-In-Circuit Programming Solution-Automatic Test Equipment Programming Solution-JTAG Programming Socket/Breadboard Adapters Sockets Programming media services Distributors) Programming media services Tape Reel Services Tape Reel handlers Lead Inspection Equipment Rework Equipment SIMMs/DIMMs Test Accessories Example: examples mentioned above different Webbased tool categories. Each tool category contains additional tools information. example, last category Electronic Tools Catalog "Test Accessories." Here breakdown tool description different types tools will find "Test Accessories" category: Description: Test accessories include variety test debug tools usually used prototype production stage product development. These tools range from vacuum wands handling procedures test clip access fixtures Intel's flash memory packages. Individual tools included "Test Accessories" category: Emulator/Test Flex Probes Microgripper* (SAT/SOP test clips) Signal Access Tools (SAT) µBGA, Easy BGA, Intel Stacked-CSP packages Reballing Fixtures Reball Preforms Powered Vacuum Wand Manual Handling/Programming Process Specification TSOP Precision Vacuum Wand TSOP Test Clip also order Intel® Flash Memory Tools Guide that reviews Intel's flash memory tools available explains each tool used (Figure 6-2). This guide people require hard-copy guide review tools. order copy Intel Flash Memory Tools Guide, order direct contact Intel Literature Center (see contact information this chapter) Order Number: 298000.
Tools
Intel Flash Memory Products Family Intel® Product Selector SOFTWAREBuilder On-line Utilities Documentation Packaging Technology Programming Tools Electronic Tools Catalog (ETC) Definition Design Tools (Electronic Tools Catalog): Modeling/Simulation Emulator Component Flexible Layout File Escape routing files Schematic Symbol Files Software-Media/File Managers Software-Templates Software-Utilities Prototyping Production Tools (Electronic Tools Catalog): PCB-Contract Manufacturers Programmers-Concurrent Programmer-Engineering
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
TOOLS SOFTWARE SUPPORT
Figure 6-1. Intel® Tools Software Page
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Intel Flash Memory Software
Intel's software engineers have worked hard develop complete, flexible software solutions don't have years, OEMs around world have been taking advantage this resource, bringing innovative products market faster with less development effort than ever before. matter what your application Intel Flash memory products are, chances solution already exists help take work integrating flash into your next design. Intel® Flash Memory SOFTWAREBuilder utility provides many different software solutions that incorporated into your product design. Intel Flash Memory SOFTWAREBuilder found Tool Software page. been designed help learn more about software solutions that serve companion Intel's broad line flash memory components. example Intel's software products Intel® Persistent Storage Manager (IPSM) software which simplifies your design combining nonvolatile memory functions into single chip. solution enables combination executable code, registry back-up, file storage single Intel Flash memory product. This optimization reduces power consumption, component count, inventory costs, board costs, manufacturing costs. same time, delivers increased system reliability valuable user storage, while opening application possibilities. Another example Intel® Flash Data Integrator (IFDI). Many system designers interested using flash memory store system user data, well embedded code storage. using single, highdensity, NOR-based flash memory device both directly execute code store data, applications benefit eliminating need separate datastorage memory device, like EEPROM batterybacked SRAM. This saves system cost, power consumption, board space. Using flash memory, which already system, data storage fraction cost EEPROM battery-backed SRAM. Intel's Flash Data Integrator software fully tested, debugged, Intel-supported data storage manager real-time embedded applications, saving many man-months software engineering effort.
TOOLS SOFTWARE SUPPORT
Figure 6-2. Intel® Flash Memory Tools Guide
support information 24-hours day. You'll have access technical data such datasheets application notes, development tools software, well latest product news industry trends. Access World Wide your design needs. Application Notes/Briefs Papers Datasheets Product Introductions Design Builders Product Line Cards Development Tools Product Overviews Software Manuals Reference Designs News Highlights Technical Overviews Flash Memory Development Tools Software Home Page: Innovative, high-quality development tools assist decreasing your product development cycles, lowering development/product costs improving product capabilities. Intel years worked closely with leading industry hardware software vendors ensure that high-quality tools need available when need them. Whether programmers, software, pre-silicon software models, sockets adapters, automation equipment, test accessories, design files other product, they here ready your use.
Support Information
obtain more information Intel Flash Memory Tools Software, refer following: World Wide Home Page: http://www.intel.com INTEL Flash Memory Home Page: Intel's presence World Wide provides designers on-line access latest product
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
TOOLS SOFTWARE SUPPORT
Intel Literature Centers US/Canada (800) 548-4725 Outside U.S. (303) 297-7763 Flash Memory Databook: Intel® Flash Memory Tools Guide: Order #210830 Order #298000
When integrating flash memory into your system designs, look Intel's full range flash memory tools software give your development schedule boost. You'll find everything need solve design problems, simplify development process improve product capabilities Tools Software site. Intel General Information/Technical Hotline Personalized help regarding Intel® product application information. Canada: 5:00 a.m. 5:00 p.m. PST.) US/Canada (800) 628-8686 (916) 356-3104 Outside Contact your local Intel Distributor Intel Sales Office
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Introduction
QUALITY RELIABILITY ENGINEERING PACKAGE CERTIFICATION
QUALITY RELIABILITY ENGINEERING PACKAGE CERTIFICATION
Intel's packaging silicon certification methodology been refined over many technology generations proven track record delivering high quality reliability. While Intel continuously improving they certify package technologies, including knowledge-based certification methodology utilizing conditions, Intel continues certify flash products packages stringent traditional certification standards that have been industry years. This chapter reviews many package certification tests perform contains brief description each. Although these individual tests vary depending packages certification methodology, they typical Intel's certification tests. Contact your local Intel sales office representative obtain specific product/package certification data.
above stress tests conducted units that completed full manufacturing flow. cases, failure defined failure meet datasheet parameter. Stress test readouts electrical test endpoints done same equipment used electrical test commercial product manufacturing. Stresses with endpoints other than electrical test have explanations endpoints stress descriptions.
Infant Mortality Summary
Infant mortality evaluation (IME) data used predict product early life failure rate. data also used determine required burn-in time. Burn-in used production needed ensure that early life failure rate goals met. units functionally exercised predetermined voltage elevated ambient temperature +125°C hours. During test memory sequentially addressed outputs exercised, monitored loaded. checkerboard data pattern used simulate random patterns expected during actual use. Then units used infant mortality evaluation subjected Intel specification testing. Table 7-1.
Quality/Reliability Verification
This chapter designed provide detailed description methods used verify that CSPs meet exceed Intel's package certification requirements. reliability package generally defined probability that device will perform intended function under specified operating conditions throughout life. determine device's reliability, Intel subjects sample lots package variety stress tests order meet Intel's production qualification quality reliability requirements. Most evaluations performed certification included following: Infant Mortality 6.5V/+125°C Pre-conditioning CSAM, Visual High Voltage Dynamic Life Test (HVELT) +125°C, High Temperature Storage (Bake) +140°C Temperature Cycle (T/C after pre-conditioning) Steam (autoclave) +121°C, atm, 100%RH Temperature Humidity Bias Test (85/85) after pre-conditioning Solder Joint Reliability (opens/shorts test) Bend/Push Test 1-mm deflection (opens/shorts test) Twist Test deflection (opens/shorts test)
Infant Mortality Evaluation +125°C/V
Hours Hours Hours
7.4. High-Voltage Dynamic Lifetest
This test used accelerate oxide breakdown failures. test set-up identical used Infant Mortality Evaluation. This data with voltage acceleration factor accelerated bias voltages used calculate failure rate. Table 7-2.
High-Voltage Dynamic Lifetest +125°C
Hours Hours 1,000 Hours
High Temperature Storage (Bake)
+140°C bake, with applied voltage, performed determine effect high temperature storage without electrical bias. bake evaluation accelerates failure mechanisms such single charge loss, bond degradation, process wear-out mechanisms such ionic contamination. This stress also checks contact integrity. test conducted conformance with specification Mil-Std-883C method 1008.2.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
QUALITY RELIABILITY ENGINEERING PACKAGE CERTIFICATION
1,000 Hours
Table 7-3. High Temperature Storage +140°C
Hours Hours Hours
Package Pre-Conditioning
Package pre-conditioning performed simulate shipping, storage, surface mount reflow conditions. Each unit exposed temperature humidity simulate storage (duration exposure dependent package type). Finally, each unit through pass, reflow. After test been completed, each device electrically checked ensure that degradation functionality occurred. devices exposed this flow prior both temperature cycling temperature humidity testing. Figure 7-1. Package Pre-Conditioning Flow
Moisture Sensitivity Level Testing
addition electrical testing, sample parts tested before after pre-conditioning using visual acoustic miroscopy determine package cracking voiding occurred during simulated board mounting process. Each package tested various moisture sensitivity levels determine long package moisture barrier when 30c/60% environment. Flow doing pre-conditioning: Electrical Test CSAM Visual Stress (Bake-Temperature cycle cycles- Unbiased Temp. Humidity Soak-IR reflow) Visual CSAM Electrical Test
Temperature Cycle
Temperature cycling performed evaluate mechanical integrity device when exposed temperature extremes. Mechanical failure mechanisms such package cracking, cracking, thin film cracking, bond wire lifting, attach problems accelerated this stress. Temperature cycling also checks changes electrical characteristics mechanical displacement rupture conductors insulating materials. Other effects include delamination finishes degradation package hermeticity. this stress, devices alternately exposed cold temperature conditions. example temperature cycle condition performed unit(s) would exposed specified time then transferred temperature specified time. Heating cooling done convection.
Steam (Autoclave)
steam stress accelerates moisture penetration through packaging material surface die. objective test accelerate problems found very moist environments. Failure mechanisms typically seen from this stress include corrosion, passivation defects, leakage contamination. test chamber maintained temperature +130°C absolute pressure atmospheres.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Table 7-4. Steam
Hours
QUALITY RELIABILITY ENGINEERING PACKAGE CERTIFICATION
Table 7-5.
Hours Hours
Temperature Humidity Bias (85/85)
Hours 1,000 Hours
7.10
Temperature Humidity Bias Test (85/85)
7.11
Solder Joint Reliability
This high-temperature/high-humidity stress used evaluate reliability non-hermetic devices humid environments. units biased with maximum voltage within operating range applied alternate pins while maintaining minimum overall power dissipation, +85°C ambient with percent relative humidity. contamination present, combine with moisture form electrolyte. Typical failure mechanisms from this stress include electrolytic corrosion metal contamination induced threshold shifts moisture. Table 7-6. Solder Joint Reliability
Solder joint reliability testing performed soldering CSPs FR-4 boards thermal cycling units. units used silicon daisy chain configured die, failure criteria resistive (500) open leads determined continuous monitoring.
7.12
Package Assembly Data
following data example in-process monitors (µBGA package) used during assembly process. Data from lots used qualification testing.
40-Ball µBGA* Package Criteria Cycles Cycles Cycles 1,000 Cycles
Table 7-7.
Package Dimensions
Test Item Criteria max. 0.988 min. 0.888 min. 0.18 0.075 0.35 0.025 7.43 0.05 5.69 0.05 0.75 0.05 1.090 0.075 1.345 0.075 Sample Size Average Measurement 0.922 0.220 0.697 0.349 7.416 5.666 0.747 41.08 1.074 1.326 Standard Deviation 0.020 0.011 0.007 0.012 0.016 0.010 0.009 0.014 0.020
Total Height Stand Package Body Thickness Ball Diameter Package Body Length Package Body Width Ball Pitch Coplanarity Corner Ball (S1) Corner Ball (S2)
Table 7-8.
Process Lead Bond Attach Ball Attach Marking
Process Monitor
Test Item Initial Bond Pull Inspection Ball Shear Permanency Criteria min. 7.0g Bubble min. 200g defects Reject/ Accept 0/2,280 0/240 0/250 0/10 Average Measurement 14.16 Pass 366.14 Pass Standard Deviation 1.24 51.15
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
QUALITY RELIABILITY ENGINEERING PACKAGE CERTIFICATION
7.13
Bend/Push Test Data
This test designed evaluate solder joint reliability CSPs after they have been mounted board subjected bending stresses. board pushed down times opposite sides close proximity unit. board turned-over stress repeated times again. This considered cycle.
7.14
Twist Test
purpose this test determine package integrity after repeated bends. unit mounted coupon that 1.5" mils thick. Each group boards twisted 100,000 times either then electrically tested opens.
Table 7-9.
Bend/Push Test
1-mm Deflection (Open/Shorts Test)
Cycles
Cycles
Cycles
Cycles
Table 7-10. Twist Test
100,000 Twists Degrees Degrees
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
APPENDIX FLASH SOLUTIONS DIVERSE APPLICATIONS
James Malatesta Bauer Intel Corporation, Folsom, California
FLASH SOLUTIONS DIVERSE APPLICATIONS
Abstract
Over past several years, there been major transition Chip Scale Packages (CSPs) driven primarily consumer handheld applications that require smallest form factor packages. Today's flash memory market consists variety applications requirements. There variety applications that flash memory. There been ongoing debate industry about which package, technology will "win." reality that certain package technologies better suited specific applications than others. Therefore, choose best package, important understand needs application. While small size continued main thrust rapid acceptance CSPs, other applications within industry have been able take full advantage wave some tradeoffs associated with packages. This paper will discuss attributes some applications that flash memory, look package solutions that best meet needs these applications.
groups applications share many same package values, importance these values differ significantly. Handheld applications value smallest possible size advantage, while embedded applications, primary value achieving lowest total cost long-term size/footprint compatibility. Therefore, makes sense provide different types packages based value sets different applications.
Handheld Application Values
Handheld applications consist small products that demand increasing functionality while decreasing size product. These products generally have shorter life cycles (12-18 months) where they redesigned incorporate latest technologies innovations order compete their respective marketplace. They frequently incorporate advanced leading-edge Printed Circuit Board (PCB) technology order much functionality into smallest possible area. handheld applications, package size generally highest-ranking package values. Some examples handheld market include telecommunications devices such cellular phones, pagers, personal digital assistants (PDA) Global Positioning Systems (GPS) units.
Embedded Application Values
Embedded applications typically other applications aside from handheld products. While size still important factor many embedded applications, lowest total cost long-term size/footprint compatibility tend highest packaging values. Embedded applications tends have much longer life cycles than handheld applications (5-7 years 12-18 months respectively). Therefore, using package that doesn't change size pinout density upgrades process changes over life product very desirable. majority these applications also more conventional (lower-cost) technology
General Application Values
Each application packaging requirements, values. While these values vary depending application, packaging values shown Table A-1. Each packaging value require variation package order make optimal that value possible. Most today's applications seem fall into distinctive areas, handheld embedded. While both Table A-1. Packaging Values Table
Packaging value name Size Packaging value description
Overall package size includes height, width, length. Another consideration package size amount actual real estate (total area) package consumes PCB. Primarily based solder joint reliability when mounted various other use-condition stresses. Ability package maintain same size footprint (ball array pattern/pinout) over time while actual silicon size increase memory density and/or decreases result process change (die shrink). Overall handling ease package including moisture levels, manual/automated handling, placement/process rework ease. Individual cost die/package. Total cost usage. Includes items such PCB, surface mount process, programming, rework costs, etc.
Reliability Long-term size/footprint compatibility Ease Package Cost Total cost
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
FLASH SOLUTIONS DIVERSE APPLICATIONS
other types mature manufacturing processes. Examples these applications include Industrial Controllers, Network Products, Instrumentation, Automotive, Telecommunication Systems.
Package Solutions Handheld Applications
Handheld applications value smallest size lightest weight packages available order shrink size product. Mobile phones with smallest size, lightest weight, most features marketplace. meet these goals, design engineers looking smallest size lightest weight packages. Some manufacturers have chosen offer packages that change with size die, referred true chip-size packages. example this type package µBGA* package (see Figure A-1). Figure A-1. µBGA* Package
This package takes advantage ever-changing size flash memory silicon (die). When silicon manufacturing process changes, silicon size decreases shrinks. example, when fabrication lithography decreases from 0.4- 0.25-micron trace width below, package size weight also decrease. Since size package equals size die, gets smaller, does package. certain point, associated ball pitch will smaller well, order accommodate smaller size die. This will eventually lead ball pitches small below. Figure A-2. Process Migration
Another advantages µBGA package unique construction utilizing layer elastomer which decouples stresses caused coefficient thermal expansion (CTE) silicon material during temperature variations, thus providing excellent reliability. This elastomer layer also provides increased mechanical reliability well. This package passed 100,000 cycles degree twist testing inch inch, 0.010 inch thick test coupon. This added mechanical reliability important handheld products because sometimes mobile phones dropped, left inside vehicle less than ideal conditions. Other fine-pitch ball grid array packages defined molded plastic encapsulated packages with ball pitch being less than Since this type package fully encapsulated, maintain size/footprint regardless amount shrinks. However, this approach limit package size reduction benefits. Since some CSPs change size internal gets smaller process changes, definition evolved into near-die-size package with pitch smaller."1 Another type gaining momentum industry "Stacked" CSP. These packages taking advantage multiple application requirements, such SRAM Flash, combining both into package (see Figure A-3). Figure A-3. Intel® Stacked-CSP Package
However, instead placing individual side side (such multi-chip modules), Intel® StackedCSP stacks each other maximum space savings advantage possible. Although package have larger ball pitch compared µBGA packages (0.8 0.75 mm), overall area Intel Stacked-CSP smaller than combined area separate components. Most CSPs market today have chosen ball pitch less than wide. When ball pitch becomes less than wide, manufacturing process becomes more demanding regards routing design rules (PCB trace/space widths vias). shown Figure A-4, 0.75/0.8-mm pitch packages
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Figure A-4. National Technology Roadmap Electronic Interconnections 1997
FLASH SOLUTIONS DIVERSE APPLICATIONS
right edge conventional manufacturers capabilities.2 This issue handheld applications such mobile phones, because they tend thin (0.030 inch), leading-edge technology. These high-end, thin PCBs allow manufacturers fine pitch packages without adders.
Figure A-5. Microvia Sales
March 1999, Intel introduced volt Advanced+ Boot Block product 0.5-mm µBGA package. early user's 0.5-mm µBGA packages, XeTel Corporation, experienced very good assembly results with 0.5-mm package. first build, 0.062 inch thick, via-in-pad PCBs supplied MicroVia Inc., only 1/1,140 devices failed surface mount correctly. Three solder joints were involved failure, translating 58-PPMJ surface mount defect rate. This compares favorably typical TSOP surface mount defect rates 200-300 PPMJ. never ending quest smaller, lighter products, many mobile communications products rapidly implementing (High Density Interconnect) Microvia technology. Some analysts predict growth Microvia Motherboard Sales from $402M 1997 $1,048M 2002, with Personal communications being biggest driver.3 Figure A-5. This technology will enable even finer pitch 0.5-mm pitch components. 0.5-mm pitch could enable smaller chip sizes much percent equivalent 0.75-mm matrix package. Some OEMs (Original Equipment Manufacturers) view 0.5-mm pitch CSPs steppingstone more advanced packaging such Waferscale packaging.
Package Solutions Embedded Applications
Many advantages implementing CSPs have been documented throughout industry regards small package size higher assembly yields result self-alignment characteristics during reflow lack bend leads causing coplanarity issues. most part, embedded applications such Industrial Controllers, Network Products, Instrumentation, Automotive, Telecommunication Systems have been able take full advantage these benefits primarily because requirement advanced design rules longer life cycles products.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
FLASH SOLUTIONS DIVERSE APPLICATIONS
March 1999, Intel Corporation announced package offering, Easy package. EasyBGA package designed package choice wide variety applications. This package developed directly address longer product life cycle conventional technology diverse applications.
Easy Design/Cost Considerations
This package fixed package footprint package outline. Figure A-2. Figure A-6. Easy Package
Package size only consideration. design engineer also needs consider technology currently application, what routing requirement package has. Consider that most applications using drilled vias that greater than 0.010 inches. When this case, vias packages typically dropped outside array, vias array when larger pitch used. actual real estate consumed with surrounding similar that larger package, with wider pitch. some cases shown Figure A-8) inner balls cannot escape routed without least some small 0.010 inch vias. Figure A-8. Real Estate Comparison
0.75/0.8-mmPitch Pitch
0.35-mm Attachment Attachment Pads pads (.005 inch) Trace 0.127-mm (0.005 inch) Space Trace/Space (.025 inch) 0.635-mm (0.025 inch) Capture Pads capture pads (.014 inch) Drill 0.356-mm (0.014 inch) Holes Drill holes Balls unable routed Center balls unable with larger drills
lithography's change, package size will remain fixed, ensuring that products with long life cycles always same PCB. This package about half size widely used TSOP package, quite small µBGA package offering. Figure A-7. Easy package also maintains thin 1.2-mm height compatible with Card applications. Figure A-7. Package Size Comparison
routed with larger drills
1.0-mm Pitch Pitch 0.50-mm Attachment
Attachment Pads pads (.005 inch) Trace 0.127-mm (0.005 inch) Space Trace/Space 0.635-mm (0.025 (.025 inch) inch) Capture Pads capture pads 0.356-mm (0.014 Drill (.014 inch) inch) Holes holes Drill Balls routed balls routed
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
FLASH SOLUTIONS DIVERSE APPLICATIONS
costs also consideration. Many products are, will continue thicker PCBs. embedded applications, smaller drill sizes (typically 0.010") required vias array significantly increase costs higher Drill Aspect Ratio (DAR). determined dividing board thickness drill size. reason high cost higher DARs, twofold. One, smaller drills less efficient since less boards drilled time causing throughput time reduction. Also plating material does flow through narrow holes well, reducing yields. Example 18"x24" panel estimated using finer pitch 0.75/0.8-mm CSPs, also with 1.0-mm package. standard 0.062" thick PCB, finer pitch devices drive 6:1, potentially percent increase cost. Example Cost Estimate
Conventional Multilayer Cost:
Estimated Cost/Sq. Inch: $0.15-0.25 $0.30-0.45 $0.45-0.75 $0.75-1.25 Drill Aspect Ratio Adders: layers layers layers layers
Easy Reliability Considerations
required reliability application also dictate which packages considered. Reliability requirements vary widely depending type application, specific requirements manufacturer. Determining standard reliability tests, testing ranges, number cycles test daunting task. addition, many OEMs moving from Mil. Standard test requirements, more Model requirement that even include tests such twist, bend, drop. These tests tend more application specific, have much value industrial controller card that that times thick, rarely user There seems several temperature cycle ranges emerging de-facto standards. Some companies still testing +100 AT&T solder joint reliability range. During past year there seems shift +125°C 100°C) system reliability test criteria with minimum 1,000 cycles. Easy package designed meet exceed reliability needs wide variety applications. Easy package large 0.45-mm ball diameter size rigid laminate substrate increase board mounted reliability.
Premium
Conclusion
Different applications require different packages. important understand requirements each market choose package that best fits your specific application. CSPs such µBGA Intel Stacked-CSP packages ideal applications that require ultimate size, weight reliability. CSPs have, continue grow rapid rate applications such mobile phones, pages, units. CSPs have really taken diverse embedded applications such Industrial Controllers, Network Products, Instrumentation, Automotive, Telecom Systems, longer product life cycles, thicker conventional technology product. Easy package designed address specific needs these diverse embedded applications offering small form factor, easy upgrades, lowest possible implementation cost. These packages allow diverse applications enjoy manufacturing size benefits type package. more information Intel® Flash CSPs, please refer their page
Panel Cost with 0.8-mm/0.75-mm pitch devices: 18"x24" panel, 0.062" thick, layer, 0.005" trace/space, 0.010" drills $0.45/sq. inch $0.585 $0.585/ inch inches $254.48 Panel Cost with 1.0-mm pitch devices: 18"x24" panel, 0.062" thick, layer, 0.007" trace/space, 0.018" drills $0.45/sq. inch $0.45 $0.45/ inch inches $195.75
Easy Surface Mount Technology Considerations
relaxed 1.0-mm pitch also make difference ease assembly OEM's surface mount line. According Curtis Hart, chief technology officer XeTel Corporation, really easy. same processes, process controls, equipment that every 1.27-mm BGAs. However, CSPs 0.8-mm pitch below require careful evaluation stencil designs other process steps before production release."
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
FLASH SOLUTIONS DIVERSE APPLICATIONS
References
Sandra Winkler, "The Year Chip-Scale Package," Chip Scale Review, January 1999, National Technology Roadmap Electronic Interconnections 1997, Institute Interconnecting Packaging Electronic Circuits. Data provided Prismark Partners LLD.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
APPENDIX CHIP SCALE REWORK USING SOLDER PASTE FLUX
Paul Wood International, Yonkers,
CHIP SCALE REWORK USING SOLDER PASTE FLUX
Chip scale rework compared
components range from typically 15-mm 15-mm size 50-mm 50-mm square. This means magnification overall field view limited. typical maximum four-sided view 50-mm 50-mm size part viewed more than magnification, then component zoomed more than magnification. Some systems have diagonal overlay, which enhances corners part. This called corner overlay. left bottom right viewed magnification. This required rework overall size part generally more than 18-mm square extreme cases this 21-mm square). magnification When viewing component ball size much smaller than that component. Most common size balls 0.012" 0.030" 0.032" pitch. This requires higher magnification easy operator placement. higher magnification easier solder defects such poor solder paste deposition pads solder residue still left substrate. typically easy range work with magnifications parts size. only small size (TESSERA/Intel flash) chip being used, then 100x utilized. Future trends 20-mil pitch parts with 12-mil balls common such markets Japan where instance consumer market, products such camcorders push size weight products limits very quickly. typically 12-mm square, usually with perimeter ball pattern keeps technology simple. Higher CSPs being developed parts around 18-mm square with balls 20-mil pitch. industry generally quite ready produce finer tracks 3-mil track space reasonable costs multilayer construction layers just yet. Some parts future lean towards gold bump solid non-melt balls that paste will have used these parts.
taken rush process. removal with hasty removal time done easily many engineers think that saving secs removal going best process PCB. This case stressed high heat pulling PCB. Points remember: adhesion only 10-12-mil compared 30-mil size. PCBs should heated reflow secs (just because component can), this causes thermal stress multi-layer construction vias. going analyze part find what failure part PCB, interconnection, i.e., solder ball joint? general cycle time that have worked with successfully secs removal CSPs layer small circuit PCBs, such phone PCMCIA cards. Figure B-1. Figure B-1.
Time 01:00 02:00 02:40
130°C 191°C 240°C
T.C. 129°C 171°C 203°C
PreH 128°C 128°C 128°C
Rework
Removal parts rework part needs small amount heat remove from average PCB, care must
preparation removal solder done prepare land pads solder paste flux-only application. Figure B-2. solder removed then stencil will flush solder paste deposition cannot controlled. Although stencils used flux-only application, solder should removed provide flat land area surface. using blade remove solder from substrate controlled manner then process drawn which works well. iron used with various manufactures wick this disastrous, pads might removed unnecessarily. operator should have iron, which maintain temperature with overshoot regardless load. When temperature maintained next recommendations important cleanup.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CHIP SCALE REWORK USING SOLDER PASTE FLUX
Place wick with correct flux content, i.e., no-clean ideally, water soluble, onto area. Rest blade wick approximately secs smoke rising which good indicator solder wicking into wick. scrub wick around trying solder quickly, this will spread molten solder into vias. wick also useful stop operators from burning their hands. This damage difficult until part x-rayed. When much heat applied solder wick, plastic bobbin, which holds wick plastic melt, when this happens plastic from bobbin transferred wick. Then wick transfers plastic onto pad, during reflow solder paste there will appear void which seen x-ray. alternative wick desolder tool that sucks solder into catcher this also suitable alternative (various types available). Automatic desolder also available, much more expensive requires same type reworked high volume justify purchase. Figure B-2.
alignment easy. challenges past have been stencil flat PCB. stencil flat then even though stencil aligned paste deposition suspect. Steps successful stenciling. Have stencil made trapezoidal that paste release optimal. stencil trapezoidally etched then second application take place should area printed trapezoidal etch will just reform print allow second print take place. stencil where made with parallel side paste would squashed second application cause poor print, this would turn promote bridging small print case CSP/ MicroBGA parts. Step stencils rework machine lower stencil PCB. Figure B-3.
Solder paste deposition Reapplying solder paste pattern cannot done with pneumatic dispenser pitch accuracy tight. Automatic positive dispensement could possible controlled correctly. easiest most cost-effective solution single stencil designed pattern. Mini Micro stencil previously used stenciling cannot successfully used because alignment difficult eye, operator dependent. this type stencil used with rework machine align stencil with vision prism assembly then
Step Align stencil site flat patterns. Figure B-3. Step Lock stencil coplanar flat position lift vision alignment. Step When viewing stencil with prism system there many advantages over looking through stencil PCB. Generally stencil printing solder paste aperture smaller than that circuit board. When viewing from impossible align stencil spot middle fact stencil smaller than pad. avoid this with rework machine with prism vision. prism allow viewing from underside stencil relation during component placement. Figure B-4.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
Figure B-4.
CHIP SCALE REWORK USING SOLDER PASTE FLUX
Figure B-6. Trapezoidal etch seen print stencil Figures B-6.
Also when print done stencils have some paste residue left stencil, next print outline hole stencil seen alignment PCB. this done with standard Mini Micro stencil, cleaning would have done before print takes place. Step Raise stencil view print after manual squeegee print taken place, this carried with special blade made print wipe blade made same width print. Some more improvements also made blade. Figures B-6. Figure B-5.
These step etched blade promote paste roll bent angle make print take place recommended print angle degrees. Figures B-8. Figure B-7.
Figure B-8.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CHIP SCALE REWORK USING SOLDER PASTE FLUX
130°C 191°C 240°C T.C. 129°C 171°C 203°C PreH 128°C 128°C 128°C
Replacing Component
Component placement component placed should presented square pickup head picked centrally. This makes less work operator align part PCB, because part just picked then placement adjustments Theta would true. This same pick place machine this automatic placement machines square parts pickup head first before alignment. Once balls aligned pads, placement done either automatically controlled Z-axis movement manually. Figure B-9. placement weight should controlled, downward force. Most components printed with 5-mil paste thickness production same applies rework. Figure B-9.
Figure B-10.
Time 01:00 02:00 02:40
Preheat paste 130°C zone
Soak zone paste 160/170°C
Peak solder paste 203/205°C
Reflow CSP/MicroBGA When Reflowing Back using paste, correct preheat/ soak/ reflow/ cooling should take place good void free solder joint. Figure B-10. correct profile used then flux become trapped balls verified x-ray machine viewing joint seeing white spots joint. When using solder paste component will have same stand height production CSP, looking sideways through part between balls possible this. solder joint will also same volume production joint, this verified measuring joint size x-ray machine with joint size measuring tool. Typically 14-mil diameter joint when reflowed with using 12-mil ball.
Re-apply CSP-using flux Recently many users have tried using flux reflow CSPs back onto because they were unable good results with paste. However must consider many aspects before anyone states across board that flux rework. some applications this will fine others reliability product allow this take place. Issues consider: Strength joint/size joint. What does have withstand thermal cycling test? +125°C etc. 1,000 cycles. Stand-off height part from substrate. Cleaning under part difficult impossible when flux only used. Flux type used according customer specifications. Another consideration product: i.e., personal pager engine control plane. What value PCB? Does have elastomer layer between substrate? This will/may withstand cycle test better than without (such TESSERA design). Flux advances/techniques rework application flux operators always played large part yield. often operators will excessive amounts flux down which causes many other faults such flux filled vias which difficult clean manually automatically, flux surrounding adjacent components making difficult clean manually with spray cleaner, wrong type flux used, i.e., no-clean process, components moving pads excessive flux under part.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CHIP SCALE REWORK USING SOLDER PASTE FLUX
This controlled little better either using dispenser dispense controlled amount flux, which then brushed level area using brush small squeegee blade. using flux transfer system, which new, which gives controlled amount flux component. This been developed transfer flux part bottom solder ball only. plate step etched controlled depth area etched little bigger than component. flux then manually into plate handheld syringe. flux used none clean type. Then squeegee wiped across surface wipe surplus flux off. This then leaves controlled depth tack noclean flux. component then picked dipped into flux bath from pick-up head into flux this coats bottom one-third balls with flux. Then part simply aligned under prism alignment placed onto then reflowed. flux where needed during reflow solder joint. This stops flux residue from spreading over substrate, fact very hard flux residue. only evidence that part been reworked that stand-off height lower than normal. this substrate such memory where other chips same size mounted next each other height easily seen different. this were chip phone pager then uneducated person would know that part lower than normal. However joint smaller than that part back with solder paste. currently participating research project conjunction with University Salford (UK) industry partner investigate transfer quick efficient means flux deposition rework. believe there significant advantages over other methods, especially when dealing with fine pitches becoming common applications. Figures B-11, B-12 B-13. diagrams below detail basic methods: Stage Figure B-11.
Stage Figure B-12.
thickness flux dependent solder ball size. typically one-third thickness flux ball diameter. Component dipped into known depth flux paste. Stage Figure B-13.
Component withdrawn leaving deposit each solder ball. X-ray solder joint size flux verses paste Flash Memory microBGA. Figure B-14.
Component held vacuum then positioned above flux/paste.
Typical ball sizes when soldered with solder paste, using 5-mil stencil.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
CHIP SCALE REWORK USING SOLDER PASTE FLUX
Figure B-15.
Conclusion
method flux paste decision that taken process engineer factory, company. This based upon product reliability specifications, which only manufacturer decide. instance camcorder does throughout same stress reliability aircraft engine management system. Both methods reliable different standards need different considerations. Also consider future trends that gold bump non-melt solder balls become more common future. This paper designed help introduce process which used either paste flux depending requirements.
Typical size reflowed back with just flux gel/paste, 10-mil size x-ray.
INTEL® FLASH MEMORY CHIP SCALE PACKAGE USER'S GUIDE
APPENDIX SUCCESSFUL SOLUTIONS
Julian Partridge Curtis Hart XeTel Corp., Austin, Texas area-array component technology extended pitches below popular 1.27-mm Ball Grid Array standard, fine pitch BGAs Chip Scale Packages presenting design opportunities manufacturing challenges. While there many benefits integrating CSPs, they require careful consideration footprint layout narrow operating window many board assembly processes. Figure C-1. Cross-sections through 1.27-mm PBGA, 0.5-mm CSP. Shown identical magnifications.
SUCCESSFUL SOLUTIONS
Figure C-2. Alternative 0.5-mm pitch fan-outs with microvia-in-pad, soldermask defined pads without vias, etch-defined pads without vias (not recommended). SCALE.
Mask offset 0.04 offset 0.04
Mask Mask
Photovia Photovia
Trace
Exposed Exposed copper copper
Exposed copper shown Exposed copper shown
Board design
Typical PBGA board designs 1.27-mm pitch 0.64-mm diameter etch-defined pads, easily allowing 0.13-mm line/space standard interstitial vias with capture pads. Standard board
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