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Pentium® Processor/ 440LX AGPset Design Guide
April, 1998 297651-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document sale Intel products. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. *Third-party brands names property their respective owners. Pentium® Processor cartridge contain design defects errors known errata. 82443LX A.G.P. Controller 82371AB PCI-to-ISA/IDE Xcelerator contain design defects errors known errata. Current characterized errata available request. two-wire communication bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol SMBus bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect, 60056-7641 call 1-800-879-4683
COPYRIGHT INTEL CORPORATION, 1998 CG-041493
TABLE CONTENTS
CHAPTER INTRODUCTION Introduction Overview. References CHAPTER DESIGN FEATURES Design Features. Pentium® Processor Intel 440LX AGPset Xcelerator: PIIX4 CHAPTER 440LX PLATFORM REFERENCE DESIGN 440LX Platform Reference Design 440LX Reference Design 440LX Reference Design CHAPTER DESIGN RECOMMENDATIONS Design Recommendations General Design Recommendations. Pentium® Processor/440FX Pentium Processor/440LX Design Transition CHAPTER MOTHERBOARD LAYOUT ROUTING GUIDELINES Motherboard Layout Routing Guidelines Placement. Board Description Ball Grid Array (BGA) Component 5.3.1 Size 5.3.2 Vias. 5.3.3 Routing Routing Guidelines. 5.4.1 Host Layout Routing Guidelines 5.4.2 A.G.P. Layout Routing Guidelines 5-11 5.4.3 440LX Memory Subsystem Layout Routing Guidelines 5-13 5.4.4 Routing Guidelines 5-16 5.4.5 Decoupling Guidelines 440LX Platform 5-17
CONTENTS
CHAPTER DESIGN CHECKLISTS Design Checklists. Slot Checklist 6.1.1 Pentium Processor Errata 6.1.2 Slot Clocks 6.1.3 Slot Signals 6.1.4 Uni-Processor (UP) Slot Checklist 6.1.5 Dual-Processor (DP) Slot Checklist 6.1.6 Slot Decoupling Capacitance. 440LX AGPset Checklist 6.2.1 440LX AGPset Errata 6.2.2 440LX AGPset Voltage. 6.2.3 440LX AGPset GTL+ Interface. 6.2.4 440LX AGPset DRAM Interface 6.2.5 440LX AGPset Interface 6.2.6 440LX A.G.P. Interface. 6.2.7 440LX Miscellaneous Signals 6.2.8 82371AB (PIIX4) ISA/IDE Xcelerator. 6.2.9 82371AB (PIIX) Signals 6.2.10 82371AB (PIIX4) X-Bus Signals 6.2.11 Flash Signals Layout 6.2.12 82371AB (PIIX4) Signals. 6.2.13 82371AB (PIIX4) Interface. 6-10 6.2.14 82371AB (PIIX4) Power Management Interface 6-10 6.2.15 82093AA (IOAPIC) 6-11 6.2.16 Boot Block Flash Design Considerations: 6-11 6.2.17 Power RESET. 6-12 Software/BIOS 6-12 6.3.1 Design Considerations: 6-12 Thermals/Cooling Solutions 6-12 6.4.1 Design Considerations: 6-13 Mechanicals 6-13 6.5.1 Design Considerations 6-13 Layout checklist 6-13 6.6.1 Routing Board Fabrication 6-13 CHAPTER DEBUG RECOMMENDATIONS Debug Recommendations Slot Test Tools Debug/Simulation Tools 7.2.1 Logic Analyzer Interface (LAI) 7.2.2 In-Target Probe (ITP) 7.2.3 Functional Model (BFM) 7.2.4 IBIS Models 7.2.5 FLOTHERM* Model. Debug Features 7.3.1 Issue 7.3.2 Debug Logic Recommendations. 7.3.3 Debug Layout 7.3.4 Debug Procedures.
CONTENTS
APPENDIX 440LX SYSTEM PIIX4 Implementation .A-1 Motherboard Layout Guidelines.A-2 A.2.1 Data Signals Layout Guidelines .A-2 A.2.2 Power Distribution Layout Guidelines .A-4 A.2.3 Power Line Layout Topologies.A-5 A.2.4 Power Line Layout Topologies Which Recommended .A-7 Options Connector Cable Implementation .A-8 A.3.1 Recommended Options .A-8 A.3.2 Recommended Options.A-10 Implementation .A-10 A.4.1 Data Lines P+/P- Power lines .A-10 A.4.2 Motherboard Layout Options.A-10 A.4.3 Zero-Ohm Resistor Stuffing Option .A-11 A.4.4 Jumper Option .A-11 A.4.5 Overcurrent Protection Detection .A-12 BIOS Implementation .A-14 A.5.1 Systems/Motherboards WITHOUT Legacy Support.A-14 A.5.2 Systems/Motherboards WITH Legacy Support .A-15 A.5.3 START FRAME (SOF) Modify Register .A-16 PIIX4 USBCLK Guidelines.A-17 A.6.1 Frequency Tolerance .A-17 A.6.2 PIIX4 USBCLK Requirements.A-18 A.6.3 USBCLK Jitter.A-18 A.6.4 System Considerations .A-20 A.6.5 Clock Source Vendors .A-21 PIIX4 Design Checklist .A-22 A.7.1 Hardware Checklist .A-22 A.7.2 BIOS Implementation Checklist.A-23 Host Production Tester.A-24 Main Distributors.A-24
CONTENTS
APPENDIX LAYOUT CLARIFICATION Introduction.B-1 PIIX4 Implementation .B-1 B.2.1 Routing Guidelines .B-1 APPENDIX 82371AB PIIX4 INTERNAL Introduction. PIIX4 Module Implementation C.2.1 Registers RAM. C.2.2 Organization C.2.3 Access C.2.4 Time Keeping External Connections C.3.1 Crystal C.3.2 External Capacitor Values C.3.3 External Battery Connection Accuracy C.4.1 Voltage versus Accuracy C.4.2 External Capacitance Load versus Accuracy. C.4.3 PIIX4 Temperature versus Accuracy C.4.4 Crystal Temperature versus Accuracy Interrupts. C.5.1 Types Interrupts. C.5.2 Alarm Interrupt C.5.3 Periodic Interrupt C.5.4 Update Ended Interrupt. C.5.5 Interrupt Connections IRQ8# Usage Using Internal versus Using External Control Register Description. C.7.1 Control Register C.7.2 Control Register B.C-10 C.7.3 Control Register .C-11 C.7.4 Control Register .C-11 Real-Time Clock Configuration Register Description (RTCCFG) .C-12 C.8.1 RTCCFG-Real-Time Clock Configuration Register (Function .C-12 APPENDIX SYSTEM POWER CONTROL Desktop Power Environment Desktop Power Sequencing Model. Recovery from Mechanical Condition PIIX4 External Logic handle power loss condition
CONTENTS
APPENDIX SYSTEM MANAGEMENT (SMBUS) OVERVIEW SMBus Functional Description.E-1 SMBus Features.E-1 SMBus Command Protocols.E-1 Device Addresses.E-1 Start Stop Conditions.E-2 Data Validity .E-2 MAIN Differences Between SMBus .E-3 PIIX4 SMBus Implementation .E-4 E.8.1 PIIX4 SMBus Host Controller .E-4 E.8.2 PIIX4 SMBus Host Transaction.E-4 E.8.3 PIIX4 SMBus Slave Interface-Interrupts Resume Events .E-5 E.8.4 PIIX4 SMBus Frequency.E-6 E.8.5 PIIX4 SMBus Registers.E-6 Using Devices with SMBus Interface.E-7 E.9.1 devices communicating SMBus.E-7 E.9.2 devices communicating SMBus.E-8 E.9.3 PIIX4 SMBus Interface Connecting .E-8 APPENDIX SINGLE TERMINATION Intel 440LX Single Ended Termination Overview Intel 440LX Single Ended Termination Design Guidelines APPENDIX WAKE PENTIUM II/440LX SYSTEM Important Information Disclaimers. Scope. Overview System Requirements G.4.1 Motherboard G.4.2 G.4.3 Power Supply Unit Wake-on-LAN Definition. Connectors Cables. G.6.1 System Block Diagram G.6.2 Interconnect Cable Components G.6.3 PIIX4 Based System Implementation Electrical Characteristics Notes Related Documents. G.10 Detailed Header Cabling Harness Illustrations
CONTENTS
APPENDIX 82433LX APPLICATION NOTE #2-THERMAL DESIGN CONSIDERATIONS Introduction. H.1.1 Document Goals Importance Thermal Management. 82443LX Packaging Terminology Thermal Specifications H.4.1 Case Temperature H.4.2 Power Designing Thermal Performance H.5.1 Airflow Management Cooling Solutions. H.6.1 System Fans. H.6.2 Thermal Enhancements. H.6.3 Thermal Interface Management Heat-Sink Solutions. Measurements Thermal Specifications. H.7.1 Case Temperature Measurements H.7.2 LXPOWER Simulation Program.H-10 Conclusion.H-11 Heatsink Vendors .H-11 H.10 Reference Documents Information Sources .H-12
APPENDIX INTEL PENTIUM II/440LX SCHEMATICS Uni-Processor Systems. Dual-Processor System
viii
REVISION HISTORY
Revision Number Rev. April 1998
Date
Revision Status Original Release
Introduction
CHAPTER INTRODUCTION
Introduction
intent this document organize special design recommendations concerns that exist creating Pentium® processor/440LX AGPset based system. Likely design errors have been identified included here checklist format, section alleviate problems during debug phase. Some hints early debug problems also included section Design Features: items that Intel feels will allow capabilities Pentium processor Intel® 440LX AGPset fully utilized market segments which these products designed. Design Recommendations: items which Intel feels will provide flexibility cover broader range products within market segment. Design Checklists: items which have been found incorrect previous designs. These provided tool allow quick debug Pentium processor based systems. Design Considerations: items that should considered, applicable your design. Debug Recommendations: items that assist development Pentium processor, 440LX AGPset, products utilizing them.
Overview
different example designs provided this document: single Slot design (UP), twoway symmetric multiprocessor (referred 2-way this document) design. Both designs offer following features:
Full Support Pentium processor using Slot frequencies 440LX AGPset 82443LX PCI/A.G.P. Controller (PAC) 82371AB Xcelerator (PIIX4) Memory Interface: wide range DRAM support including 64-bit memory data interface plus bits DRAM 66-MHz SDRAM (Synchronous) Support 4-Mbit, 16-Mbit 64-Mbit DRAM Technologies
Integrated Controller Mode [0-4] Master support Mode [SW1-MW2] Ultra Mode [0-2] Integrated Universal Serial (USB) Controller with ports Integrated System Power Management Support On-board Floppy, Serial, Parallel Ports Add-in Slots ACPI Revision support addition, 2-way (DP) design has: Support Pentium processors Slot 1's), each with separate dedicated APIC device support interrupt support
Add-in Slots Specification Compliant A.G.P. Slot A.G.P. Interface Specification Compliant
INTRODUCTION
References
Pentium Family Developer's Manual (Order Number: 242693)
Pentium Processor BIOS Writer's Guide (Order Number: 649733) Intel Architecture MMXTechnology Developer's Guide (Order Number: 243006) AP-523 Pentium Processor Power Distribution Guidelines (Order Number: 242764)
AP-524 Pentium Processor GTL+ Layout Guidelines (Order Number: 242765) AP-525 Pentium Processor Thermal Design Guidelines (Order Number: 242766) Intel 440LX AGPset Data Sheet (Order Number: 290564) Intel 82371AB PIIX4 Data Sheet (Order Number 290562-001) Multi-Processor Specification (242016-004) Local Specification, Revision Universal Serial Specification, Revision Pentium Processor Enabling Technologies Supplier Guide, Revision later
Pentium Processor Data Sheet Processor Heat Sink Design Guidelines (Application Note #586), Revision later Processor Fan/Heat Sink Target Specification, Revision later Slot Test User's Guide, Revision later Interface Specification Compliance (www.agpforum.org) PC100 SDRAM Specification Version Clock 66-MHz 64/72-bit Unbuffered SDRAM DIMM 64/72-bit 3.3V Unbuffered DIMM DC-DC Converter Specification
Note: Pentium Processor Data Sheet Pentium Processor/Slot Data Sheet same document. reference questions regarding above listed documents, contact your local Intel Sales Office.
Design Features
CHAPTER DESIGN FEATURES
Design Features Pentium® Processor
Pentium® processor high-performance Intel Architecture processor which designed into products following market segments: Desktop Home Market Segment Desktop Corporate Market Segment Workstation Market Segment Server Market Segment Please contact your local Intel Field Sales representative assistance guidance your product definition process. They provide with Intel's Processor, AGPset System roadmaps above market segments. Also available system configuration recommendations target segments some above mentioned markets. applications hardware add-ins from third party vendors being developed that take advantage MMX(technology incorporated into Pentium processor. Please contact your local Intel Field Sales representative information IHV's ISV's utilizing Intel's technology.
DESIGN FEATURES
Support
Pentium Processor
Pentium® processor
Accelerated Graphics Port A.G.P. Compliant Graphics Device
440LX PCI/A.G.P. Controller
Memory 72-bit w/ECC
3.3V SDRAM Support
Slots
Local Memory
MHz/32-bit)
(Ultra DMA/33)
82371AB
324BGA
Buffers
SMBus
Slots
BIOS
IOAPIC
X-BUS
Figure 2-1. Intel Slot 1/440LX AGPset Reference Platform Block Diagram
Intel 440LX AGPset
440LX AGPset first generation desktop AGPset products designed Pentium processor. 440LX A.G.P. Controller (PAC) integrates Host-to-PCI bridge, optimized DRAM controller data path, Accelerated Graphics Port (A.G.P.) interface. A.G.P. high performance, component level interconnect, targeted graphics applications based upon performance enhancements PCI. subsystem portion 440LX platform based PIIX4, highly integrated version Intel's PCI-to-ISA bridge family. 440LX developed ultimate Pentium processor platform targeted emerging graphics multimedia applications. component includes following functions capabilities: Support single dual Pentium processor configurations 64-bit GTL+ based Host Interface 32-bit Host address Support 64/72-bit Main Memory Interface with optimized support SDRAM 32-bit Interface with integrated arbiter A.G.P. Interface with 133-MHz data transfer capability Extensive Data Buffering between interfaces high throughput concurrent operations
DESIGN FEATURES
Figure shows block diagram typical platform based 440LX AGPset. host interface supports Pentium processors MHz. physical interface design based GTL+ specification. provides optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies. provides interface operating MHz. This interface implementation compliant with Specification. first Intel product that introduces Accelerated Graphics Port interface. A.G.P. interface implementation based A.G.P. Specification 1.0. support 133-MHz data transfer rates. designed support PIIX4 bridge. PIIX4 highly integrated multifunctional component that supports following functions capabilities: compliant PCI-to-ISA Bridge with support 33-MHz operations Deep Green Desktop Power Management Support Enhanced controller 8259 Compatible Programmable Interrupt Controller System Timer functions Integrated controller with Ultra DMA/33 support host interface with support ports System Management (SMB) with support DIMM Serial Presence Detect Support external APIC component System Interface Pentium processor supports second level cache size 256K 512K. cache control logic provided Pentium processor. supports maximum 32-bit address 4-GB memory address space from processor perspective. provides control signals address paths transfers between processors' host bus, bus, Accelerated Graphics Port main memory. supports 4-deep in-order queue (i.e., provides support pipelining four outstanding transaction requests host bus). system concurrency requirements, along with support pipelining address requests from host bus, supports general request queuing three interfaces (Host, A.G.P. PCI). Host-to-PCI transfers, depending address space being accessed, address will either translated directly forwarded bus. access configuration space, processor cycle mapped configuration cycle. access memory space, processor address passed without modification bus, unless hits specific memory address range (later referenced A.G.P. Aperture Graphics Aperture) dedicated graphics memory address space. address will translated A.G.P. address remapping mechanism forwarded DRAM subsystem. Host cycles forwarded A.G.P. defined A.G.P. address map. also receives requests from A.G.P. initiators access main memory. target address within graphics aperture, then request translated into appropriate memory address. A.G.P. accesses destined graphics aperture snooped host because coherency aperture data maintained software. accesses aperture, from Host, A.G.P., translated using A.G.P. address remapping mechanism. DRAM Interface integrates main memory controller that supports 64/72-bit DRAM interface. DRAM controller supports following features:
DRAM type: Extended Data (EDO) Synchronous (SDRAM); DRAM controller optimized dual-bank SDRAM organization
DESIGN FEATURES Memory Size: Addressing Type: Memory Modules supported:
SDRAM: Mbytes Mbytes with eight memory rows EDO: Mbytes 1Gbyte with eight memory rows Symmetrical Asymmetrical addressing Single double density DIMMs
Configurable DRAM Interface: Configuration Large Memory Array Support DIMMs, DIMMs) Configuration Small Memory Array Support DIMMs) DRAM device technology: DRAM Speeds: Serial Presence Detect: Mbit, Mbit Mbit DRAM SDRAM 66-MHz parameters synchronous memory. SDRAM: Required EDO: Supported
provides optional data integrity features including (Error Checking) (Error Checking Correcting) memory array. Error Checking (EC) mode provides single multiple error detection. mode, provides error checking correction data during reads from DRAM. supports multiple-bit error detection single-bit error correction. Accelerated Graphics Port Interface 440LX first chip that supports A.G.P. interface; hence name change AGPset. A.G.P. implementation complies with Accelerated Graphics Port Specification 1.0. A.G.P. interface, must synchronously couple host bus. A.G.P. interface reach theoretical 532-Mbytes/sec transfer rate. Interface interface Local Specification Revision compliant (32-bit MHz) supports five external masters addition bridge (PIIX4). only supports synchronous coupling host bus. 440LX supports:
Mbytes Mbytes SDRAM Memory Configuration Mbytes Mbytes SDRAM supported Memory Configuration Gbyte memory achieved with Buffered DIMMs.
Read/Write Buffers implements sophisticated data buffering algorithm support required level concurrent operations provide adequate sustained bandwidth between DRAM subsystem other system interfaces (e.g. CPU, A.G.P. PCI). System Clocking operates host interface MHz, interface A.G.P. interface 66/133 MHz. Coupling between interfaces internal logic done synchronously. designed support host frequencies lower than MHz. uses external clock synthesizer which produces reference clocks host, A.G.P. interfaces. APIC APIC supports interrupts dual processor designs. Refer APIC datasheet more information. Dual Processor Schematics provided this document.
DESIGN FEATURES
Xcelerator: PIIX4
82371AB Xcelerator (PIIX4) multi-function device implementing PCI-toISA bridge function, function, Universal Serial host/hub function, Enhanced Power Management function. PCI-to-ISA bridge, PIIX4 integrates many common functions found ISA-based systems-a seven channel 82C371 Controller, 82C59 Interrupt Controllers, 82C54 Timer/Counter, Real Time Clock. addition compatible transfers, each channel supports Type transfers. 440LX/PIIX4 also contains full support PC/PCI protocol implementing based DMA. Interrupt Controller Edge Level sensitive programmable inputs fully supports external Advanced Programmable Interrupt Controller (APIC) Serial Interrupts. Chip select decoding provided BIOS, Real Time Clock, Keyboard Controller, external Microcontroller, well Programmable Chip Selects. PIIX4 provides full Plug Play compatibility. PIIX4 configured Subtractive Decode bridge Positive Decode bridge. PIIX4 supports four devices separate controllers. provides interface hard disks ROMs. PIIX4 supports PIO, BMIDE, Ultra DMA/33. PIIX4 contains Universal Serial (USB) Host Controller that Universal Host Controller Interface (UHCI 1.0) compliant. Host Controller's root programmable ports. PIIX4 supports Advanced Power Management, including full clock control, device management devices, suspend resume logic. fully supports operating system directed power management Advanced Configuration Power Interface (ACPI) specification 1.0. PIIX4 integrates both System Management (SMBus) host slave interface serial communication with other devices. more information PIIX4, refer PIIX4 Datasheet, Order Number 290562.
440LX Platform Reference Design
CHAPTER 440LX PLATFORM REFERENCE DESIGN
440LX Platform Reference Design 440LX Reference Design
This section describes 440LX Reference Design Schematics shown Appendix this document. Please read this section carefully observe design recommendations requirements. description each schematic page named logic block shown that page. numbers after schematic page name list page number single processor design (i.e. UP-x). Cover Sheet Block Diagram UP-1 UP-2 Cover Sheet shows Schematic page titles, page numbers disclaimers. This page shows block diagram 440LX system. Schematic page numbers each major components shown. Slot Connector (part UP-3 This page shows Slot Connector (part Shown this page supply, pullups IERR# TESTHI. SLP# connection comes directly from PIIX4. Intel recommends placing resistors signals. Primary Slot Connector (part UP-4 This page shows Slot Connector (part This page shows optional connections overriding from processor. This page also shows optional thermal sensor. Clock Synthesizer Connector UP-5 This page shows clock synthesizer components CK3D CKI/O. clock synthesizer components must meet host, other system clock requirements. Several vendors offer components that used this design. This page also shows Target Probe (ITP) Connector. connector recommended order Target Probe tool available from Intel other tool vendors Pentium processor based platform debug. Note: Some logic analyzer vendors also support connector. This connector optional. recommended design these headers into system initial system debug development, leave connector footprints unpopulated production. Component (Host DRAM Interfaces) UP-6 This page shows component, Host DRAM Interfaces. connects lower 32-bits address control signals, generates DRAM control signals memory interface. this design, configured interface "small" memory array. copies memory address signals provided this configuration. buffered copy provided each DIMM socket.
440LX PLATFORM REFERENCE DESIGN
Note:
series resistors required DRAM interface signals from array. jumper optional, needed initial debug. Component (PCI A.G.P. Interfaces) UP-7 This page shows component, A.G.P. Interfaces. Follow recommendations outlined A.G.P. Platform Design Guide, available A.G.P. Implementer's Forum site (http://www.agpforum.org). Note: must member A.G.P. Implementer's Forum download this document. Component (Memory Host Data Interfaces) UP-8 This page shows component, Memory Host Data Interfaces. GTL_REF signals also shown this page. Ideally, GTL_REF signals should decoupled separately, close possible component, this absolute requirement. optional 440LX platform. recommend that MECC[7:0] routed memory array, allow option either non-ECC DIMMs. DIMM Connectors UP-10 UP-11 These three pages show DRAM interface connections from DRAM array. This reference design uses memory configuration described 82443LX Datasheet. very important follow memory subsystem layout routing guidelines outlined this document. this memory design, using Memory Configuration MAA[13:0], RCSA[1:0], SRAS0, SCAS0, CDQA[7:0], WE0# connected furthest DIMM socket from this reference design, furthest DIMM socket DIMM #2). MAA[13:0], RCSA[3:2], SRAS1, SCAS1, CDQA[7:0], WE1# connected middle DIMM socket from this reference design, middle DIMM socket DIMM #1). MAB[13:0], RCSA[5:4], SRAS2, SCAS2, CDQA[7,6,4:2,0], CDQB[5,1], WE2# connected closest DIMM socket from this reference design, closest DIMM socket DIMM #0). ensure your 440LX memory array supports both DRAM SDRAM, 2-bank 4-bank, follow signal connection recommendations Intel SDRAM DIMM Specifications. PIIX4 Component UP-12 This page shows PIIX4 component. PIIX4 component connects bus, dual connectors, bus. This reference design supports subset power management features PIIX4. Refer Power Management section this document. PIIX4 Component UP-13 This page shows PIIX4 component Interrupts, USB, DMA, Power Management, XBus, GPIO interfaces. required power management features used. JP3: using external RTC, VBAT receive power from 3.3VSTBY (jumper 1-2), else, backup battery (jumper 2-3). SUSC# connected power connector, #14. VREF circuit provided ensure proper power sequencing. Ultra Component UP-14 This page shows Ultra component. optionally used. Infra Header Port also optional.
440LX PLATFORM REFERENCE DESIGN
A.G.P. Connector
UP-15
This page shows A.G.P. Connector. this design, A.G.P. INTA INTB connected directly INTA INTB. interrupt signals open-collector, pulled VCC3.3. Follow recommendations outlined A.G.P. Platform Design Guide, available A.G.P. Implementer's Forum site. Note: must member A.G.P. Implementer's Forum download this document. Connectors UP-16 UP-17 These pages show Connectors. this design, Connectors used. sure follow 440LX Interface Checklist this document. Connectors This page shows Connectors. Connectors UP-19 This page shows Connectors. special external logic required support Ultra DMA/33 hard drives. Headers UP-20 This page shows Headers. Note, voltage divider over current (OC) signals provide logic level transitions PIIX4. Flash BIOS Component UP-21 This page shows 28F002BC-T Flash BIOS component which provides Kbytes BIOS memory. jumper used provide option allowing BIOS programmed system BIOS upgrades and/or programming plug play information into Flash device. Note that Flash device required certain applications (motherboard devices such graphics, SCSI LAN). Parallel Port This page shows Parallel Port Interface. Serial Floppy This page shows Serial Ports Floppy Drive interfaces. Keyboard Mouse Connectors This page shows Keyboard Mouse interface. UP-25 this page shows voltage regulator modules (VRM) connector(s). modules provide VCCCORE voltage conversion Pentium processor. bottom this page shows voltage regulators, generating 1.5V GTL+ terminating voltage (VTT), other 2.5V regulator. generation circuit must able provide about amps current under worst case conditions. Note that amps current will normally supplied from linear regulator devices (about amps each), located each GTL+ traces. However, linear regulator device (supplying entire amps) used both ends GTL+ traces near each other. UP-24 UP-23 UP-22 UP-18
440LX PLATFORM REFERENCE DESIGN
Power Connectors Front Panel Jumpers
UP-26
This page shows system power connectors, hardware reset logic, standard chassis connectors hard disk, power LEDs, speaker output. Note: Header required Intel Boxed Pentium processor. GTL+ Termination Resistors UP-27 This page shows GTL+ termination resistors. components shown flat chip resistor array devices. These components available both devices package options. These devices have been chosen their small size reduce board space required. Discrete, resistor packages also used will require more board area. Each GTL+ signal that connects between slot connector should dual terminated insure most robust GTL+ signaling. Each GTL+ signal should routed using daisy chain methodology described GTL+ layout guidelines section this document. termination resistors each must located ends nets. Connect side resistor packs short trace possible before routing plane. plane inner layer, keep trace distance short possible placing between pins each resistor package. Where this possible, multiple vias plane each group signals. Please refer GTL+ Specification more complete details GTL+ signaling. Note: Appendix single termination designs. Pull-up Pull-down Resistors UP-28 UP-29 These pages show pull-up pull-down resistors signals, PIIX4, Slot 1(CMOS), ISA, A.G.P. signals. Also shown spare gates. De-coupling Capacitors UP-30 UP-31 UP-32 These pages show de-coupling capacitance used these schematics.
440LX Reference Design
This section describes 440LX Reference Design Schematics shown Appendix this document. Please read this section carefully observe design recommendations requirements. description each schematic page named logic block shown that page. numbers after schematic page name list page number dual processor design (DP-x). Cover Sheet Block Diagram DP-1 DP-2 Cover Sheet shows Schematic page titles, page numbers disclaimers. This page shows block diagram overview 440LX system design. Schematic page numbers each major schematics components shown. First Slot Connector (part DP-3 This page shows Slot Connector (part Shown this page supply. SLP# connection comes directly from PIIX4. Intel recommends placing resistors signals.
440LX PLATFORM REFERENCE DESIGN
First Slot Connector (part
DP-4
This page shows Slot Connector (part This page shows optional connections overriding from processor. This page also shows optional thermal sensor. A_SLOTOCC# used gate POWERGOOD signal processor. Second Slot Connector (part DP-5 This page shows Slot Connector (part Shown this page supply. SLP# connection comes directly from PIIX4. Intel recommends placing resistors signals. Second Slot Connector (part DP-6 This page shows Slot Connector (part This page shows optional connections overriding from processor. This page also shows optional thermal sensor. B_SLOTOCC# used gate POWERGOOD signal processor. Clock Synthesizer Connector DP-7 This page shows clock synthesizer components CK4D CKI/O. clock synthesizer components must meet host, other system clock requirements. Several vendors offer components that used this design. This page also shows Target Probe (ITP) Connector. connector recommended order Target Probe tool. This tool available from Intel other tool vendors Pentium processor based platform debug. Note: Some logic analyzer vendors also support connector. This connector optional. recommended design these headers into system initial system debug development, leave connector footprints unpopulated production. jumpers provided three different configurations-when processor first slot (second termination card), when processor second slot (first termination card) when both processors present. Component (Host DRAM Interfaces) DP-8 This page shows component, Host DRAM Interfaces. connects lower 32-bits address control signals, generates DRAM control signals memory interface. this design, configured interface "large" memory array. copies RAS#/CS# signals provided this configuration. There copy memory address bits down these must buffered. There copies memory address bits they must buffered. buffered copy provided each DIMM socket. Note: series resistors required DRAM interface signals from array. jumper optional, needed initial debug. Component (PCI A.G.P. Interfaces) DP-9 This page shows component, A.G.P. Interfaces. Follow recommendations outlined A.G.P. Platform Design Guide, available A.G.P. Implementer's Forum site (http://www.agpforum.org). Note: must member A.G.P. Implementer's Forum download this document. Component (Memory Host Data Interfaces) DP-10 This page shows component, Memory Host Data Interfaces. GTL_REF signals also shown this page. Ideally, GTL_REF signals should decoupled separately close possible component, this absolute requirement. optional 440LX platform. recommend that MECC[7:0] routed memory array, allow option either non-ECC DIMMs.
440LX PLATFORM REFERENCE DESIGN
DIMM Connectors
DP-11 DP-12 DP-13 DP-14
These four pages show DRAM interface connections from DRAM array. This reference design uses memory configuration described 82443LX Datasheet. very important follow memory subsystem layout routing guidelines outlined this document. this memory design, using Memory Configuration Copies RCSA#[7:0], CDQA[5]&[1], provided most heavily loaded control signals this array. buffered copy MAA[13:2] must each DIMM socket. MAA[1:0] MAB[1:0] copies first memory address signals. ensure your 440LX memory array supports both DRAM SDRAM, 2-bank 4-bank, follow signal connection recommendations Intel SDRAM DIMM Specifications. PIIX4 Component DP-15 This page shows PIIX4 component. PIIX4 component connects bus, dual connectors, bus. This reference design supports subset power management features PIIX4. Refer Power Management section this document. PIIX4 Component DP-16 This page shows PIIX4 component Interrupts, USB, DMA, Power Management, XBus, GPIO interfaces. required power management features used. JP3: using external RTC, VBAT receive power from 3.3VSTBY (jumper 1-2), otherwise, backup battery (jumper 2-3). SUSC connected power connector, #14. VREF circuit provided ensure proper power sequencing. APIC This page shows APIC component. Ultra Component DP-18 This page shows Ultra component. optionally used. Infra Header Port also optional. A.G.P. Connector DP-19 This page shows A.G.P. Connector. this design, A.G.P. INTA INTB connected directly INTA INTB. interrupt signals open-collector, pulled VCC3.3. Follow recommendations outlined A.G.P. Platform Design Guide, available A.G.P. Implementer's Forum site (http://www.agpforum.org). Note: must member A.G.P. Implementer's Forum download this document. Connectors DP-20 DP-21 These pages show Connectors. this design, Connectors used. sure follow 440LX Interface Checklist this document. Connectors This page shows Connectors. DP-22 DP-17
440LX PLATFORM REFERENCE DESIGN
Connectors
DP-23
This page shows Connectors. special external logic required support Ultra DMA/33 hard drives. Headers DP-24 This page shows Headers. Note: voltage divider over current (OC) signals provide logic level transitions PIIX4. Flash BIOS Component DP-25 This page shows 28F002BC-T Flash BIOS component which provides Kbytes BIOS memory. jumper used provide option allowing BIOS programmed system BIOS upgrades and/or programming plug plug information into Flash device. Note that Flash device required certain applications (motherboard devices such graphics, SCSI LAN). Parallel Port This page shows Parallel Port Interface. Serial Floppy This page shows Serial Ports Floppy Drive interfaces. Keyboard Mouse Connectors This page shows Keyboard Mouse interface. DP-29 this page shows voltage regulator modules (VRM) connector(s). modules provide VCCCORE voltage conversion Pentium processor. bottom this page shows voltage regulators. generates 1.5V GTL+ terminating voltage (VTT), while other 2.5V regulator. generation circuit must able provide about amps current under worst case conditions. Note that amps current will normally supplied from linear regulator devices (about amps each), located each GTL+ traces. However, linear regulator device (supplying entire amps) used both ends GTL+ traces near each other. Power Connectors Front Panel Jumpers DP-30 This page shows system power connectors, hardware reset logic, standard chassis connectors hard disk, power LEDs, speaker output. Note: Header required Intel Boxed Pentium processor. Pull-up Pull-down Resistors DP-31 DP-32 These pages show pull-up pull-down resistors signals, PIIX4, Slot 1(CMOS), ISA, A.G.P. signals. Also shown spare gates. De-coupling Capacitors DP-33 DP-34 DP-35 These pages show decoupling capacitance used these schematics. DP-28 DP-27 DP-26
Design Recommendations
CHAPTER DESIGN RECOMMENDATIONS
Design Recommendations
Voltage Definitions purposes this document following nominal voltage definitions used: 5.0V VCC3 3.3V VCCCORE Voltage dependent five setting VCCP Voltage dependent five setting VCC2.5 2.5V 1.5V VREF 1.0V AGPVREF 3.3V
General Design Recommendations
Intel recommends using industry standard programmable Voltage Regulator Module (VRM) installed header on-board programmable voltage regulator designed Pentium processors. Please DC-DC Converter Specification details Pentium processor regulator requirements. Systems should capable varying host processor core frequency ratio System Core Frequency Multiplier Configuration table Pentium Processor/Slot Data Sheet. Pentium processor uses following signals configure internal clock multiplier ratio: LINT[0]/INTR, IGNNE#, A20M#, LINT[1]/NMI. Follow recommendations this document ensure adequate hold times strapping signals. Ensure output strapping logic VCC2.5 logic level connection Slot connector. This accomplished using open-drain output driver with pull-up resistors VCC2.5. Design Flexible Motherboard table Pentium Processor/Slot Data Sheet. Also prepare additional thermal margin increases 1-5W higher performance otherwise enhanced processors. Motherboard designs targeted system integrators should design Boxed Pentium electrical, mechanical thermal specifications provided Boxed Pentium section Pentium Processor/Slot Data Sheet, most notably required power header fan/heatsink physical clearance motherboard. Motherboard designs should incorporate retention mechanism, retention mechanism attach mount heat sink support mounting holes keep areas Pentium processor Boxed Pentium processor.
DESIGN RECOMMENDATIONS
Pentium Processor/440FX Pentium Processor/440LX Design Transition
following list items should considered when Transitioning existing Pentium Processor Socket 8/440FX PCIset based system based Slot connector/440LX AGPset. 82450KX/GX PCIset designs supported Pentium processor. Pentium processor Slot connector different physical form factor than existing Pentium processor. Please Pentium Processor/Slot Data Sheet mechanical details ensure that mechanical keep areas observed mechanical interference occurs between Pentium processor your chassis. motherboard designs targeted with Boxed Pentium processor, ensure that fan/heatsink mechanical keep areas observed described Pentium Processor/Slot Data Sheet. Pentium processors will provided Single Edge Contact Cartridge (S.E.C. Cartridge) packaging technology. Slot connector requires mechanical support S.E.C. Cartridge heat sink. Intel enabled retention mechanism heat sink support retain S.E.C. Cartridge during shock vibration conditions. Proper mechanical support must provided S.E.C. Cartridge. Intel enabled solution requires mechanical keep areas bottom motherboard) retention mechanism, retention mechanism attach mount heat sink support. Refer Pentium Processor/Slot Data Sheet. Pentium processor physical form factor difference will cause different flow dynamics your chassis. Your thermal management solution should examined ensure that proper airflow Pentium processor cooling provided meet TPLATE specification provided Pentium Processor/Slot Data Sheet. Pentium processor utilizes VCCCORE 2.8V while existing Pentium processor VCCP 3.3V 200-MHz versions 3.1V 150-MHz version. Please ensure that your on-board regulator solution supports DC-DC Converter Specification voltage range Pentium processor current requirements. Designs utilizing solution should consult their regulator vendor determine these devices support higher current requirement Pentium processor requirements flexible motherboard documented Pentium Processor/Slot Data Sheet. Please note that solution will support future processors. Intel highly recommends five regulator. Slot defined additional VID[4] pin. regulator must provide between 2.8V able support Pentium processor future higher performance processors. Please Pentium Processor/Slot Data Sheet flexible motherboard VCCCORE current requirements. header three pins that redefined from header: VRM8.1 VRM8.0 VID4 Reserved IShare Reserved signal defined RESERVED Slot connector must no-connect. signal defined header. following list input signals required converted VCC2.5 logic levels going Slot connector: A20M#, IGNNE#, TDI, PWRGOOD, LINT[0]/INTR, LINT[1]/NMI, PREQ#, FLUSH#, SMI#, INIT#, STPCLK#, SLP#, TRST#. Intel recommends that open collector/drain driver used with pull-up VCC2.5 logic level conversion. pull-up resistor values should take into consideration recommendation section 7.3.1. following list open drain output signals must pulled VCC2.5 from Slot connector: FERR#, IERR#, THERMTRIP#, TDO. Unused outputs left no-connect. pull-up resistor values should take into consideration recommendation section 7.3.1.
DESIGN RECOMMENDATIONS
following open drain bi-directional signals must pulled VCC2.5 to/from Slot connector: PICD[1:0]#. Consider recommendation section 7.3.1. when choosing pull-up resistors. following clocks must VCC2.5 going Slot connector: PICCLK, BCLK TCK. Pentium processor port redefined (29) BCLK, previously defined GND. This clock should driven from separate host clock driver. existing Pentium processor provides support four processors. Slot 440LX AGPset only support maximum processors. Pentium processor only provides BREQ[1:0] connection host bus. TESTHI (pin A13) must pulled-up VCC2.5 kohm kohm). TESTHI Pentium processor previously required pulled-up directly VCCP through kohm resistor. Pentium processor requires high frequency decoupling motherboard, capacitors recommended. Pentium processor high frequency decoupling processor additional high frequency decoupling should required properly designed power delivery system. Please reference Pentium Processor/Slot Data Sheet recommendations requirements Slot connector. Pentium processor signal called SLP#. more advanced level power management desired, this signal connected from PIIX4 Slot this signal used, should pulled VCC2.5 with resistor. Slot connector signal called 100/66#. This signal must grounded Intel 440LX AGPset based motherboard. Slot connector reserved placement (Pin B15) thermal sensor future Pentium processors. These signals should left connect. Slot connector signal called SLOTOCC#, this similar function CPUPRES# existing Pentium processor, that ground Pentium processor. signal used inform motherboard logic that processor termination card present with GTL+ termination. presence core determined from signals, ones designates Core." Pentium processor GTL+ termination resistors processor. dual termination designs second termination resistors should placed motherboard. single termination designs reference appendix Dual-processor (DP) systems must have GTL+ termination's motherboard. terminator card required only single processor installed dual processor system. "GTL+" technology used signaling between Pentium processor 440LX AGPset. GTL+ Pentium processor synonymous. more information Pentium family developers manual (see figure below).
Pentium processor
Pentium processor
Pentium processor
PCIset PCIset
Figure 4-1. GTL+ Termination Locations
DESIGN RECOMMENDATIONS
Unlike requirements Boxed Pentium processor, motherboards designed with Boxed Pentium Processor should provide matched power header Boxed Pentium processor fan/heatsink power cable connector. Please consult Pentium Processor/Slot Data Sheet specifications power cable connector. power header must positioned within close proximity Slot connector. Pentium processor Boxed Pentium processor require mounting holes retention mechanism heat sink support. Please Pentium Processor/Slot Data Sheet. PIIX4 provides SMBus interface. provides configurable memory interface supports SDRAM. Please reference schematics Intel 440LX AGPset Data Sheet further details. PIIX4 provides additional power management signals. Please reference schematics details.
Motherboard Layout Routing Guidelines
CHAPTER MOTHERBOARD LAYOUT ROUTING GUIDELINES
Motherboard Layout Routing Guidelines
This section describes layout routing recommendations that should followed insure robust design. These guidelines should followed closely possible. deviations from guidelines listed here should simulated insure adequate margin still maintained design.
Placement
pins 440LX AGPset components have been assigned order simplify routing keep board reduce fabrication cost enabling 4-layer "UP" motherboard design. Figure shows signal quadrants 82443LX. component placement motherboard with this mind. This will simplify routing minimize number signals that cross. individual signals within respective groups have also been placed order simply route with only layers. complete list signals ball assignment found 82443LX Data Sheet.
Quadrant
Corner
GTL+ Quadrant
440LX View
A.G.P. Quadrant
DRAM Quadrant
Figure 5-1. Signal Quadrants
Examples proposed component placement single Pentium processor designs shown Figure both form factor design.
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Form Factor: placement layout Figure recommended single (UP) Pentium processor 440LX system design. example placement Figure shows slots, slots, DIMM sockets, A.G.P. connector. form factor design, A.G.P. compliant graphics device motherboard (device down option) A.G.P. connector (device option). trace length limitation between critical connections will addressed later this document. Figure reference only trade-off between number slots, number DIMM sockets, other motherboard peripherals needs evaluated each design.
Figure 5-2. Example Layout Pentium II/440LX Design
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Form Factor: placement layout below recommended single (UP) Pentium II/440LX system design. example placement below shows Slot connector, DIMM sockets, A.G.P. compliant device down. form factor design, A.G.P. compliant graphics device readily integrated motherboard (device down option). trace length limitation between critical connections will addressed later this document. figure below reference only trade-off between number DIMM socket, other motherboard peripherals need evaluated each design.
SDRAM DIMMs
CKBF
443LX
Pentium II/Slot Processor
Ports
PIIX4
PCI/ISA Riser Card
Figure 5-3. Example Placement Pentium processor/440LX Design
Note: also riser card.
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Board Description
single Pentium processor/440LX AGPset motherboard design, layer stack-up arrangement recommended. stack board shown Figure 5-4. impedance signal layers must between ohms. Lower trace impedance will reduce signal edge rates, reduce over undershoot, will create less crosstalk. Higher trace impedance will increase edge rates slightly decrease signal flight times.
Primary Signal Layer (1/2 cu.) mils mils mils PREPREG CORE PREPREG Ground Plane cu.) Power Plane cu.) Secondary Signal Layer (1/2 cu.) Total board width 62.6 mils
Figure 5-4. Four Layer Board Stack-up
Note that bottom routing layers specify However, after plating, traces will Please check with your vendor exact value insure that signal simulation performed.
Note:
thicker core helps reduce board warpage. Intel 440LX Uni-Processor reference design been successfully routed layer board. more signal layers necessary layer stack-up should used. designs layer stack-up recommended. examples shown below. first example signal layers, power plane ground plane. second example shows signal plane layers, power planes ground plane. second option makes easier accommodate power planes required 440LX design. layer stack-up used, route GTL+ signals inner layers. primary secondary signal layer used GTL+ signals where needed. inner layers (Figure 5-5) route orthogonally reduce crosstalk.
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Primary Signal Layer (1/2 cu.) mils mils PREPREG CORE PREPREG CORE PREPREG Ground Plane cu.) Inner Layer cu.) Inner Layer cu.) Power Plane cu.) Secondary Signal Layer (1/2 cu.) Total board width 62.4 mils
mils mils mils
Figure 5-5. Layer Board Stack-up with signal planes, power planes
Primary Signal Layer (1/2 cu.) mils mils PREPREG CORE PREPREG CORE PREPREG Ground Plane cu.) Inner Layer cu.) Power Plane cu.) Power Plane cu.) Secondary Signal Layer (1/2 cu.) Total board width 62.4 mils
Figure 5-6. Layer Board Stack-up with signal planes, power planes
mils mils mils
Additional guidelines board buildup, placement layout include:
Dual ended termination recommended GTL+ signals. termination resistor present Pentium processor, other termination resistors motherboard. single termination please appendix 6-layer dual processors design, termination required motherboard, each GTL+ terminated each Pentium processors. single Slot populated design, second Slot must populated with termination card. termination resistors GTL+ should ohms. board impedance should ohms 20%. FR-4 material should used board fabrication. ground plane should split. necessary, acceptable route signal power plane, only very short distance. Place vias decoupling capacitors close capacitor pads possible.
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Ball Grid Array (BGA) Component
This section addresses breakout PAC.
5.3.1 Size
contains rows balls. break from package route traces between pads achieve layer motherboard design. Figure shows routing examples ball pads. route traces between pads, traces spaces required size. route traces between pads, traces spacing used. Either size acceptable, size tradeoff should determined manufacture. larger trace widths desired, another alternative route within pads, then "neck larger trace widths once have cleared component area.
diameter mask diameter
SPACE
TRACE
diameter mask diameter
SPACE
TRACE
Figure 5-7. Routing Example Ball Pads
MOTHERBOARD LAYOUT ROUTING GUIDELINES
COMPONENT SIDE ROUTING ROWS BALL PADS
diameter diameter plated diameter mask diameter spacing traces
Figure 5-8. Routing Example
Using routing examples shown Figure Figure 5-8, first rows balls routed signal layer. inner rows must routed bottom side inner layers 6-layer board. result, vias required between pads. vias will discussed next section. NOTE: inner most balls figure above) power balls ground balls. These balls will require vias connect them their proper plane layer.
5.3.2 Vias
Figure shows connection between via. vias located between pads must covered with solder mask! This prevents solder from wicking vias pad. size recommended.
diameter solder ball
diameter diameter solder mask trace diameter plated
diameter
Typical Vias Drill Plate
Solder Mask must cover
NOTE:
Figure 5-9. Pads Vias
MOTHERBOARD LAYOUT ROUTING GUIDELINES
5.3.3 Routing
Figure 5-10 Figure 5-11 show routing example component solder sides layer board. first three rows routed component side, while inner three rows routed solder side. examples shows trace widths.
COMPONENT SIDE ROUTING ROWS BALL PADS
PITCH
diameter diameter plated diameter mask diameter SPACE TRACE
Figure 5-10. Component Side Routing Example
MOTHERBOARD LAYOUT ROUTING GUIDELINES
BACK SIDE ROUTING ROWS BALL PADS
PITCH
diameter diameter plated space
trace
Figure 5-11. Solder Side/Inner Layer Routing Example
Routing Guidelines
guidelines followed then imperative that simulate your design. guidelines followed, simulation still recommended. Contact your Intel Field Representative IBIS Models.
5.4.1 Host Layout Routing Guidelines
GTL+ routing guidelines were developed through simulation Pentium processor/440LX interconnect. Single Processor (UP) Layout Guidelines:
Slot connector beginning GTL+ termination stub: 1.5" max. GTL+ termination stub critical trace much beginning GTL+ termination stub: 1.5" max. single termination designs appendix
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Figure 5-12. "UP" Layout
Dual Processor Layout Guidelines:
Slot Slot max. Stub Length: 1.5" max.
Figure 5-13. "DP" Layout
5-10
MOTHERBOARD LAYOUT ROUTING GUIDELINES
5.4.2 A.G.P. Layout Routing Guidelines
definition A.G.P. Interface functionality (protocols, rules signaling mechanisms, well platform level aspects A.G.P. functionality), refer latest A.G.P. Interface Specification. This section describes 440LX platform recommendations A.G.P. interface. Refer Interface Specification revision more information. A.G.P. implementation compliant with Accelerated Graphics Port Interface Specification Rev. 1.0. supports only synchronous A.G.P. interface, coupling host frequency. A.G.P. interface reach theoretical 532-Mbytes/sec transfer rate. actual bandwidth will limited capability memory subsystem. Throughout this section term "data" refers AD[31:0], C/BE[3:0]# [7:0]. term "strobe" refers AD_STB[1:0] SB_STB.
Table 5-1A. Associated Data Strobe Associate Data AD[15:0] C/BE[1:0]# AD[31:16] C/BE[3:2]# SBA[7:0] AD_STB0 AD_STB1 SB_STB Strobe
A.G.P. Connector ("Up Option") Layout Guidelines: maximum line length dependent routing rules used motherboard. These routing rules were created give design freedom making tradeoffs between signal coupling (trace spacing) line lengths. These routing rules divided trace spacing. spacing, distance between traces (air gap) same width traces. spacing, distance between traces twice width traces.
Always Strobe Routing
A.G.P. Signal Bundle
A.G.P. Compliant Graphics Device
1.0"-4.5" (Data) Routing 4.5"-9.5" (Data) Routing
A.G.P. CONNECTOR
440LX PCI/A.G.P. Controller
Figure 5-14. A.G.P. Connector Layout Guidelines
trace lengths that between 1.0" 4.5", trace spacing recommended data lines. strobe requires trace spacing. This designs that require less than inches between A.G.P. connector A.G.P. target. Longer lines have more crosstalk. Therefore order maintain skew, longer line lengths require greater amount spacing between traces. line lengths greater than 4.5" less than 9.5", routing recommended data lines strobes. designs, line length mismatch must less than 0.5", strobe must longest signal group. Reduce line length mismatch insure added margin. order reduce trace trace coupling (crosstalk), separate traces much possible.
5-11
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Table 5-1B. Source Synchronous Routing Recommendations Width:Space Trace Line Length Line Length Matching
1:1(Data) (Strobe)
Data Strobe Data Strobe
1.0" line length 4.5" 1.0" line length 9.5"
-0.5", strobe longest trace -0.5", strobe longest trace
clock lines motherboard couple with other traces. recommended that clock spacing (air gap) least twice trace width other traces. also strongly recommended that clock spacing least four times trace width strobes. clock lines motherboard need simulated determine proper line length. motherboard needs designed characteristics clock driver that being used motherboard trace topology. These clocks need meet loading receiving device well add-in trace length. Additionally, control signals less than inches routed 1:1. Control signals (non-data signals) greater than inches should routed 1:2.
Table 5-1C. Control Signal Routing Recommendations Width:Space (1:4 Strobe) Board Motherboard Motherboard Motherboard Trace Control signals Control signals Clock Line Length 1.0" line length 8.5" 1.0" line length 10.0" Pull-up Stub Length 0.5" (Strobes 0.1") 0.5" (Strobes 0.1")
Some control signals require pull-up resistors placed motherboard. A.G.P. signals must pulled VCC3.3 using kohm kohm pull-up resistors (refer section 7.2.6 A.G.P. Signals Checklist). Pull-up resistors should discrete resistors, resistor packs will need longer stub lengths break timings. maximum stub length strobe trace inch. maximum stub trace length other traces 0.5." On-board A.G.P. Compliant Device ("Down Option") Layout Guidelines: Routing guidelines device `down' option very similar those when using connector.
Always Strobe Routing 1.0"-4.5" 1.5"(Data) Routing 1"-12" (Data) Routing
A.G.P. Compliant Graphics Device
440LX PCI/A.G.P. Controller
Figure 5-15. On-board A.G.P. Compliant Device Layout Guidelines
trace lengths that between 1.0" 4.5", trace spacing recommended data lines. strobe requires trace spacing. This designs that require less than inches between A.G.P. connector A.G.P. target. Longer lines have more crosstalk. Therefore order maintain skew, longer line lengths require greater amount spacing between traces. line lengths greater than 4.5" less than 9.5", routing recommended data lines strobes. designs, line length mismatch must less than 0.5", strobe must longest signal group.
5-12
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Table 5-1D. Source Synchronous Routing Recommendations Width:Space Trace Line Length Line Length Matching
1:1(Data) (Strobe)
Data Strobe Data Strobe
1.0" line length 4.5" 1.0" line length 12.0"
-0.5", strobe longest trace -0.5", strobe longest trace
clock lines motherboard couple with other traces. recommended that clock spacing (air gap) least twice trace width other traces. also strongly recommended that clock spacing least four times trace width strobes. clock lines motherboard need simulated determine proper line length. motherboard needs designed characteristics clock driver that being used motherboard trace topology. These clocks need meet loading receiving device well add-in trace length. Additionally, control signals less than inches routed 1:1. Control signals greater than inches should routed 1:2.
Table 5-1E. Control Signal Line Length Recommendations Width:Space Board Trace Line Length Pull-up Stub Length
(1:4 Strobe)
Motherboard Motherboard Motherboard
Control signals Control signals Clock
1.0" line length 8.5" 1.0" line length 12.5"
0.5" (Strobes 0.1") 0.5" (Strobes 0.1")
Some control signals require pull-up resistors installed motherboard. A.G.P. signals must pulled VCC3.3 using kohm kohm pull-up resistors (refer section 4.2.6 A.G.P. Signals Checklist). Pull-up resistors should discrete resistors, resistor packs will need longer stub lengths break timings. maximum stub length strobe trace 0.1". maximum stub trace length other traces 0.5."
5.4.3 440LX Memory Subsystem Layout Routing Guidelines
440LX integrates fully configurable main memory DRAM controller that supports 72-bit memory data interface (64-bit memory data plus bits). supports Extended Data (EDO) DRAM, Synchronous DRAM (SDRAM). generates Address Strobe/Chip Selects (RCSA# RCSB#), Column Address Strobe/Data Mask (CDQA# CDQB#), SCAS#, SRAS#, CKE, WE#, Memory Addresses (MA) DRAM array. CPU/PCI/A.G.P.-toDRAM cycles address data flows through PAC. generates data MECC buses writes accepts data these buses during reads. asserts ECCERR#, enabled, event single-bit correctable multi-bit uncorrectable error. 440LX DRAM interface operates synchronously clock. Fourteen memory address signals allow support wide variety DIMMs. Both symmetrical asymmetrical addressing supported. Eight RCS# lines permit maximum eight 64-bit wide rows DRAM. write operations less than quad word, will either perform byte-wise write (non protected configuration) read-modify-write cycle merging write data byte basis with previously read data (ECC configurations). supports DRAM 66-MHz SDRAM with CL3. Both single double-sided DIMMs supported.
5-13
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Possible DRAM system options supported 440LX AGPset include:
Table 5-2. Memory Types Supported 440LX DRAM Type: DRAM Module Type: DRAM Voltage: Number rows memory: DRAM Speed: DRAM Component Width: EDO, SDRAM 168-pin DIMM: 64-bit, 72-bit ECC, unbuffered 3.3V rows (Configuration #1), rows (Configuration #2). DRAM, 66-MHz SDRAM
following discussion term refers memory devices that simultaneously selected RCSA&B#/CS# signal. supports maximum rows memory configuration rows memory configuration supports "4-Clock 66-MHz 64/72-bit unbuffered SDRAM DIMM" Specification 64-bit 3.3V unbuffered DIMM" specification. your local Intel Field Sales Engineer these documents. Populating 440LX Memory Array:
DIMM sockets populated order. However, take advantage potentially faster timing, recommended populate sockets order. SDRAM DIMMs mixed within memory array. DRAM Timing register, which provides DRAM speed grade control entire memory array, must programmed timings slowest DRAMs installed.
440LX Memory Array Configurations:
Large Memory Array (Configuration Megabytes SDRAM/EDO Gigabyte Buffered Rows Small Memory Array (Configuration Megabytes SDRAM/EDO Rows
Each memory configuration offers different signals. This memory configuration selectable upon Boot/RESET strapping option signal (please refer signal description Intel 82443LX Data Sheet. Configuration Enables large memory arrays rows) with copies Address Strobe/Chip Selects (RCSAx# RCSBx#) extra copy Column Address Strobe/Data Mask (CDQB[5 most loaded CAS#/DQM signals when using DIMMs). Four SRAS#, SCAS# signals also provided. This configuration supports Single-Sided Double-Sided DIMMs, Single-Sided DIMMs. Configuration interface signals: memory configuration buffered copy MA[13:2] will DIMM sockets. MAA[1:0] will DIMM socket DIMM socket MAB[1:0] will DIMM socket DIMM socket CDQA[7:0]# will DIMM socket DIMM socket CDQA[7, 4-2, will DIMM socket DIMM socket CDQB[5&1]# will DIMM DIMM signal, provided PAC, buffered connected each DIMM socket. CMOS buffer provide copies signal. Four copies signal provided PAC, connected each DIMM socket.
5-14
MOTHERBOARD LAYOUT ROUTING GUIDELINES
RCSA&B[1:0]# RCSA&B[3:2]# RCSA&B[5:4]# RCSA&B[7:6]# SRAS0#/SCAS0# SRAS1#/SCAS1# SRAS2#/SCAS2# SRAS3#/SCAS3# CDQA[7:0]# CDQB[5&1]# MD[63:0] MECC[7:0] WE3# WE2# WE1# WE0# MAA[13:2] DIMM DIMM DIMM DIMM
FCT3245 MAB[1:0] MAA[1:0]
Figure 5-16. DIMM Sockets (Single Double Sided, Unbuffered)
Figure 5-16 shows typical 440LX memory array using Configuration maximum size this memory array using single sided DIMMs using SDRAM. supported using double sided buffered DIMMs.) Copies RCSA#[7:0], CDQA[5]&[1], provided most heavily loaded control signals this array. buffered copy MAA[13:2] must each DIMM socket. MAA[1:0] MAB[1:0] copies first memory address signals. Copies these signals needed ensure fast memory read burst rate. Layout Guidelines: Minimum trace length (from closest DIMM) 1.0". Maximum trace length (from furthest DIMM) 5.0". Critical Signals: CDQA[7:0]#: middle array. CDQB[5],[1]#: last DIMMs. MD[63:0]: middle array. MECC[7:0]: middle array. Configuration Enables small memory arrays rows) with copies Memory Address signals. Three SRAS#, SCAS# signals provided support DIMM sockets. This configuration supports Single-Sided Double-Sided DIMMs. Configuration interface signals: memory configuration connect MAB[13:0] DIMM socket closest PAC. Connect MAA[13:0] DIMM sockets external buffering needed memory control address signals. signal, provided PAC, buffered connected each DIMM socket. CMOS buffer provide copies signal. Three copies signal provided PAC, connected each DIMM socket.
5-15
MOTHERBOARD LAYOUT ROUTING GUIDELINES
RCSA[1:0]# RCSA[3:2]# RCSA[5:4]# SRAS0#/SCAS0# SRAS1#/SCAS1# SRAS2#/SCAS2# CDQA[7,6,4:2,0]# CDQB[5&1]# CDQA[5&1]# MECC[7:0] MD[63:0] WE2# WE1# WE0# DIMM DIMM DIMM
MAB[13:0] MAA[13:0]
Figure 5-17. DIMM Sockets (Single Double Sided, Unbuffered)
Figure 5-17 shows typical 440LX memory array using Configuration Connect MAB[13:0] closest DIMM socket PAC. Connect MAA[13:0] DIMM sockets external buffering needed memory control address signals. Layout Guidelines: Minimum trace length (from closest DIMM) 1.0." Maximum trace length (from furthest DIMM) 5.0". Critical Signals: CDQB[5],[1]#: Must routed closest DIMM, with MAB[13:0]. CDQA[7:0]#: Must between DIMMs MD[63:0]: Must from middle array. Termination: Series termination required DRAM interface signals 440LX memory array. Adding series termination cause difficulty routing memory array.
5.4.4 Routing Guidelines
440LX provides interface compliant with Local Specification 2.1. implementation optimized high-performance data streaming when acting either target initiator transaction. more information interface, please refer 82443LX Data Sheet. 440LX platform design basically same 440FX PCIset. 440LX supports masters (excluding PIIX4), support REQ# GNT# lines Connectors on-board Device). Thus system should only have "add-in" connectors. Because specifics layout, Figure 5-2, recommended that PIIX4 "END" bus, shown Figure 5-18. This insures proper "termination" signals. This recommended required.
5-16
MOTHERBOARD LAYOUT ROUTING GUIDELINES
440LX PCI/A.G.P. Controller
On-board Device
PiiX4
324BGA
Figure 5-18. layout guidelines
5.4.5 Decoupling Guidelines 440LX Platform
Decoupling capacitors should placed corners PAC. 0.01 recommended each corner. host, A.G.P., DRAM interface "break-out" from package four sides.
0.01
0.01
440LX PCI/A.G.P. Controller
0.01 0.01
Figure 5-19. Decoupling
Clock Routing Guidelines Pentium II/440LX platform will require different clock synthesizer different memory configurations. dual processor design with DIMM sockets, system will require clocks clocks, A.G.P., PAC, ITP), SDRAM clocks, clocks. single processor design with DIMM sockets, system will require clocks clock CPU, subsystem, PAC, ITP), SDRAM clocks, clocks. following figure table indicates relative skew requirement each clock. Each skew requirement require (from clock synthesizer chip), relative trace length motherboard, measurement point difference.
5-17
MOTHERBOARD LAYOUT ROUTING GUIDELINES
Symbol
Description Pentium II(HCLK) PAC(HCLK) skew PAC(HCLK) A.G.P. skew PAC(HCLK) PCI(PCLK) skew SDRAM(HCLK) PAC(HCLK) skew PAC(HCLK) APIC(PCLK) skew PCI(PCLK) PCI(PCLK) skew
(max) -250 (min) (max) -250 (min) (max) (min)
boards (max) (min) (max) (min) (max) (min) (max) (min)
2.5V 3.3V
Total (max) -250 (min) (max) -250 (min)
(max) -500 (min) (max) -500 (min) (max) -500 (min)
(max) (min) (max) -0.7 (min) (max) (min) (max) -2.0 (min)
(max) (min) (max) -500 (min)
(max) (min) (max) -1.5 (min)
Slot Slot Slot (Processor) Slot (Processor) APIC Clock Device DIMM Socket
Figure 5-20. Clock skew guidelines.
5-18
Design Checklists
CHAPTER DESIGN CHECKLISTS
Design Checklists
design checklist provides recommendations considerations Pentium processor/440LX system design. These provided tool allow quick debug 440LX systems. Design Considerations Pull-up pull-down values system dependent. appropriate value your system determined from AC/DC analysis pull-up voltage used, current drive capability output driver, input leakage current devices signal net, pull-up voltage tolerance, pull-up/pull-down resistor tolerance, input high/low voltage specifications input timing specifications rise time. analysis should done determine minimum maximum values that used individual signal.) simplified calculation pull-up value RMAX (VCCPU MIN) ILeakage RMIN (VCCPU MAX)
VccPU
RMAX ILeakage
VccPU
RMIN IOLMAX
Figure 6-1. Pull-up Resistor Calculation Variables
DESIGN CHECKLISTS
Slot Checklist
6.1.1 Pentium Processor Errata
Refer Pentium Processor Specification Update workarounds errata.
6.1.2 Slot Clocks Include circuit that provides ability host clock processor core speed ratio. Ensure clock driver into Slot connector 2.5V logic. uni-processor system (UP) with APIC, PICCLK must driven Slot connector, driven fast MHz. dual-processor (DP) system utilizing Intel's APIC (82093AA) maximum PICCLK frequency MHz. 6.1.3 Slot Signals Dual termination ohm) GTL+ recommended. IERR# output must pulled-up VCC2.5 (150 kohm) used system logic. These signals wire-ORed require external gate. They left no-connects they used. Please section 7.3.1. further information that affect these resistor values. FERR# output must pulled-up VCC2.5 (150 kohm) connected PIIX4. Please section 7.3.1 further information that affect these resistor values. PICD[1:0]# must have pull-ups VCC2.5 (even APIC being used). Please section 7.3.1 further information that affect these resistor values. SLP# input should pulled VCC2.5 (150 kohm). Please section 7.3.1 further information that affect this resistor value. Slot connector signal 100/66# must grounded Intel 440LX AGPset based motherboard. TESTIN# must pulled VCC2.5 kohm kohm). Slot connector reserved pins thermal sensor future Pentium processors. These signals should connects. sure Slot inputs being driven 3.3V logic. Logic translation 3.3V signals accomplished using open-drain buffers pulled-up VCC2.5 PWRGOOD input should driven from "AND" Power-Good signals from 3.3V VCCCORE supplies. output logic used drive PWRGOOD should 2.5V. VREF should generated Pentium processor. VREF locally generated processor. must have adequate bulk decoupling based reaction time regulator used create VTT. must provide current ramp 8A/µS. Maintain voltage tolerance defined Pentium Processor/Slot Data Sheet. Header used then refer DC-DC Converter Specification ensure that connections made properly. on-board voltage regulator used, VCCCORE must have adequate bulk decoupling based reaction time regulator used create VCCCORE. must provide current ramp 30A/µS while maintaining DC-DC Converter Specification. lines should have pull-up resistors them ONLY they required Voltage Regulator Module on-board regulator. signals used detect presence processor, pull-up required unless signals used other logic. lines only signals Slot connector that tolerant. reserved should connect.
DESIGN CHECKLISTS
(±5%) must provided Slot B109. This power connection used Pentium processor. required Slot tool required future Intel Boxed processors. JTAG port must properly terminated, even used. Debug Recommendation chapter this document. Pull down TRST# with resistor. pins Slot connector (pins B41, B61, B100) should connected system chassis ground through zero resistors. decision populate these resistors design dependent determined through empirical testing. current Pentium processor connects pins ground processor card, future processors utilize these pins suppression. Slot connectivity: Slot VCCCORE, VTT, VCC3.3, VCC, pins, connected VCCCORE, 1.5V, 3.3V, respectively.
VCCCORE B105 A102 A106 A110 A114 A118
DESIGN CHECKLISTS
VCC3.3 B113 B117 B121 VCC5 B109
TESTHI must pulled-up VCC2.5 with kohm resistor.
TESTHI
Reserved Pins must no-connects.
Reserved A113 A116 B112
Design Considerations:
regulators used, each bus, Intel recommends connecting regulator outputs together with wide trace that runs along same basic path GTL+ signals. aware potential cross talk signals. VREF should generated each AGPset component from this combined VTT. This simply recommendation minimize effects noise. AP-523 Pentium Processor Power Distribution Guidelines more information. single regulator used. system, maximum current 4.6A. This considers that some signals used 440LX AGPset only "single" termination resistor used (the processor card). power header Boxed Pentium processor fan/heatsink power cable should matched. Please consult Pentium Processor/Slot Data Sheet specifications power cable connector. power header must positioned within close proximity Slot connector. Slot connector signal SLOTOCC# (Pin B101) grounded Pentium processor. Using pull-up motherboard, this signal used inform motherboard logic that card present with GTL+ termination. presence core determined from signals, ones designates Core". SLOTOCC# tolerant.
6.1.4 Uni-Processor (UP) Slot Checklist uni-processor system must connect BREQ[0] Slot connector PAC's BREQ0# signal. This will assign agent processor. Leave BR[1] unconnected. uni-processor design GTL+ termination resistors ohm) recommended motherboard. single termination designs refer appendix
DESIGN CHECKLISTS
GTL+ termination decoupling required. Please AP-523 Pentium Processor Power Distribution Guidelines decoupling recommendations. FRCERR# left connect design: FRCERR#. board's termination resistor FRCERR# required since provided Pentium processor. Uni-Processor (UP) systems must connect PICCLK provide PICD[1:0]# pull-ups.
6.1.5 Dual-Processor (DP) Slot Checklist dual-processor system must cross connect BREQ[1:0] Slot connector PAC's BREQ0# signal, i.e. signal BREQ0# should tied BREQ1# other processor. This will assign agent respectively processors. Boot Strap Processor (BSP) will processor with highest agent "second" processor will BSP. appendix dual processor schematics, more details. Ensure specifications both Slot connector sites. on-board termination required. Termination resistors provided each Pentium processors. Dual Processor (DP) systems must incorporate APIC (82093AA PIIX4 based designs), connect PICCLK provide PICD[1:0]# pull-ups.
Design Considerations:
Each processor site isolated VCCCORE power plane. Contact your vendor availability VRMs with current sharing capabilities. Please DC-DC Converter Specification details. SLOTOCC# signal used block system from booting processors with GTL+ termination resistors present. Slot lines used determine non-functional processor core termination card present. Please Pentium Processor/Slot Data Sheet further information this signal.
6.1.6 Slot Decoupling Capacitance additional VCCCORE de-coupling high frequency bulk capacitance required properly designed Slot power delivery plane VRM. Please Pentium Processor/Slot Data Sheet details power plane length resistance requirements. designs utilizing local regulator motherboard, bulk decoupling required. This amount bulk decoupling depends regulator reaction time. Please contact your regulator vendor decoupling recommendations that will meet 8.1DC-DC Converter Specification.
Design Considerations:
many extra high frequency bulk decoupling capacitance sites will near processor slot ensure proper decoupling Slot connector. Decoupling capacitor traces should short wide possible.
DESIGN CHECKLISTS
440LX AGPset Checklist
6.2.1 440LX AGPset Errata Refer Intel 82443LX 82371AB PIIX4 specification updates work arounds errata. 6.2.2 440LX AGPset Voltage VCC3.3 component. Connect VCC3 pins VCC3.3. Pull REF5V through kohm resistor. A.G.P._REFV must VCC3.3, this achieved using voltage divider. Decouple GTL_REFV pin. 6.2.3 440LX AGPset GTL+ Interface dual termination design, on-board termination resistors required following signals: HD[63:0]#, A[31:3]#, HREQ[4:0]#, RS[2:0]#, HTRDY#, BREQ[0]#, BNR#, BPRI#, DBSY#, DEFER#, DRDY#, ADS#, HIT#, HITM#, HLOCK#, CPURST#. second termination resistors provided Pentium processor. single termination designs appendix design on-board termination resistors required following signals: HD[63:0]#, A[31:3]#, HREQ[4:0]#, RS[2:0]#, HTRDY#, BREQ[0]#, BNR#, BPRI#, DBSY#, DEFER#, DRDY#, ADS#, HIT#, HITM#, HLOCK#, CPURST#. second termination resistors provided second Pentium processor termination card. empty Slot connector allowed. following GTL+ signals Slot connector left connects both designs: HA[35:32], DEP[7:0], RSP#, RS#, AERR#, BERR#, AP[1:0]#, BPM[1:0]#, BP[3:2]#, BINIT#. On-board termination resistors required since they provided Pentium processor(s). 6.2.4 440LX AGPset DRAM Interface Externally buffer signal from DRAM array. CMOS buffer (74LVC245) should used. Route, mixed DRAM array, support both SDRAM, MAA12 (and MAB12 when using configuration from DIMM sockets support 64-Mbit SDRAM (BA1 signal) (A12 signal). Route MAA11 (and MAB11 when using configuration from DIMM sockets. SDRAM EDO. Route MAA13 (and MAB13 when using configuration from DIMM sockets. SDRAM EDO. When using memory configuration route buffered copy MAA[13:2] each DIMM socket. Copies MA[1:0] provided configuration. Route MAA[1:0] DIMM sockets MAB[1:0] other DIMM sockets. When using memory configuration route MAA[13:0], along with RCSA[1:0]#, CDQA[7:0]#, SRAS0#, SCAS0#, WE0#, furthest DIMM socket from PAC. Also route MAA[13:0] middle DIMM socket with RCSA[2:3]#, CDQA[7:0]#, SRAS1#, SCAS1#, WE1#. Route MAB[13:0] closest DIMM socket with RCSA[4:5]#, CDQA[7,6,4:2,0]#, CDQB[5,1]#, SRAS2#, SCAS2#, WE2#. series termination resistors required memory interface signals 440LX memory design.
DESIGN CHECKLISTS
Design Considerations:
Error Checking Correction (ECC) Error Checking (EC)-The 440LX supports either ECC, when using x72-bit memory devices. disable memory array.
6.2.5 440LX AGPset Interface kohm (approximate) pull-up resistors required PIRQ[A:D]#, FRAME#, TRDY#, STOP#, IRDY#, DEVSEL#, PLOCK#, PERR#, SERR#, CLOCKRUN, REQ64# ACK64. kohm (approximate) pull-up resistors independently bused required SDONE, SBO#, connectors. kohm (approximate) pull-down resistors independently bused (See Local Specification section 4.3.3 Pull-ups) required TRST# connectors. kohm (approximate) pull-up resistors required REQ[0:4]. These tolerant inputs PAC. kohm (approximate) pull-up resistors VCC3.3 required GNT[0:4]#, PHLDA# PHOLD#. GNT[0:4]# PHLDA# outputs from PAC.
Design Considerations:
440LX AGPset supports masters with REQ[4:0]# GNT[4:0]# pairs. supports loads. PIIX4 each represent load, other components soldered motherboard load each, each connector adds approximately loads. design using four slots will available loads. REQ[4:0]# GNT[4:0]# pairs used, simulation required ensure that Local Specification Rev. timings met.
6.2.6 440LX A.G.P. Interface A.G.P. interface designed 3.3V operating environment, both master target A.G.P. compliant devices must driven same supply line. following A.G.P. signals must have pull-up resistors, approximately kohm, VCC3.3: GFRAME#, GTRDY#, GIRDY#, GDEVSEL#, GSTOP#, GSERR#, GPERR#, GREQ#, GGNT#, SB_STB#, ADSTB-A, AD_STB-B, PIPE#. When interfacing with connector device that uses A.G.P. PIPE# SBA# signals then pull GPAR# 3.3V using kohm resistor. device uses GFRAME# then pull required. Pull-up RBF# VCC3 with kohm resistor using A.G.P. connector, A.G.P. compliant master motherboard tri-state RBF#. A.G.P. specification does require external termination resistors, signal integrity. Termination resistors added improve signal integrity provided that performance (timing) constraints still satisfied. A.G.P. interrupts shared with interrupts similar recommendations specification. example, system with slots A.G.P. slot, interrupts should connected such that each four INTA# lines connects unique input PIIX4. recommended that interrupts staggered. also recommended that each PIRQ programmed different IRQ, possible. this reference design, A.G.P. interrupts pulled 3.3V, buffer used isolate environment from A.G.P. bus. order minimize impact mismatch between motherboard add-in card, impedance strongly recommended. each component that requires A.G.P._VREF should generated locally from A.G.P. interface Vddq rail. Decouple VREF ground manage switching current.
DESIGN CHECKLISTS
6.2.7 440LX Miscellaneous Signals Route ECCERR# through open collector buffer EXTSMI# PIIX4, with kohm (approximate) pull-up 3V_STBY. WSC# left connect "UP" design. "DP" design, must connected APICACK2# signal IOAPIC with 8.2K (approximate) pull-up VCC3. CRESET# used control reset values A20M#, IGNNE#, LINT[1:0] determine ratio core frequency. This signal delayed provide BCLK hold requirement. additional delay logic required. Pull TESTIN# VCC3 with 8.2K (approximate) pull-up resistor. 6.2.8 82371AB (PIIX4) ISA/IDE Xcelerator Place kohm kohm pull-ups VCC3.3 INTR, NMI, IGNNE# signals. These open drain outputs PIIX4 connect core frequency ratio strapping logic. Place kohm pull-ups VCC2.5 SMI#, STPCLK# signals they directly connected Slot connector. These open drain outputs PIIX4. 6.2.9 82371AB (PIIX) Signals Place kohm pull-up IOCHCK# VCC3.3. Place kohm pull-ups IRQx, SD[15:0], MEMR#, MEMW#, IOR# IOW# VCC3.3. Place kohm pull-down DRQx. Place kohm pull-up RFRESH#, IOCHRDY, SMEMR#, MASTER# SMEMW# VCC3.3. Pull-ups pull-downs signals routed processor Slot section this chapter. PIIX4 will support maximum slots. 6.2.10 82371AB (PIIX4) X-Bus Signals XOE# XDIR# connected Ultra device. schematics that this document FDC37C932FR Ultra device. XOE# connected ROMCS# XDIR# connected ROMOE#. system using this Super device should same layout. 6.2.11 Flash Signals Layout adding switch write protection, switch instead VCC. Connect 2-Mbit devices anticipating Intel SmartVoltage boot block flash memory family future. inversion 1-Mbit devices inversion 2-Mbit devices differentiate between recovery normal modes. 0.01 µf-0.1 ceramic capacitor connected between each GND, between GND. These high frequency, inherently inductance capacitors should placed close possible package leads.
DESIGN CHECKLISTS
6.2.12 82371AB (PIIX4) Signals signals P0+, P0-, P1+, require kohm pull-down resistor PIIX4 outputs. PIIX4 provides ports. unused port must still terminated with kohm pulldown resistors both P+/P- data lines. Clock, MHz, with duty cycle better than 40/60% goes into (CLK48) PIIX4. PIIX4 does support 24-MHz clock rate. series termination resistors required Px+/Px- lines should placed close possible PIIX4. capacitors ground required Px+/Px- lines. capacitors must placed PIIX4 side ohm) series termination resistors close possible PIIX4. Intel recommends ferrite beads bypass capacitors VSS, power ground lines. These recommended purposes. Note:
more information signals Layout Guidelines Appendix
Driver
Motherboard Trace
Driver
Motherboard Trace Connector
PIIX4
Transmission Line
Figure 6-2. Data Signals
Twisted Pair Cable
Design Considerations:
Clock device Clock synthesizer vendors offer devices with 48-MHz outputs with controllers. These preferred over older clock synthesizer devices which 12-MHz outputs. Frequency tolerance must less than equal ±2500 ppm. Cycle-to-Cycle Clock Jitter must less than equal ±500
DESIGN CHECKLISTS
6.2.13 82371AB (PIIX4) Interface PIORDY# SIORDY# must have kohm (approximate) pull-up resistors VCC. PDDREQ SDDREQ require kohm (approximate) pull-down resistor VCC. IDEACTP# IDEACTS# each need kohm (approximate) pull-up resistor VCC. signals running connectors (except PIORDY#/SIORDY#) require (approximate) series terminating resistors. connectors (CSEL) requires pull-down resistor. state cable select determines master/slave configuration hard drive. There internal pull down PDD7 SDD7 PIIX4. ATA-3 specification suggest kohm pull-down section 4.3.1. Devices shall have pull-up resistor DD7. recommended that host have kohm pull-down resistor PDD7 SDD7 allow host recognize absence device power-up. intended that this recommendation become mandatory next revision standard. 6.2.14 82371AB (PIIX4) Power Management Interface EXTSMI# connected ECC_ERR PAC, pulled 3V_STBY with kohm (approximate) resistor. following signals supported Pentium II/440LX/PIIX4 platform left connect: SUSA#, SUSB#, CPU_STP#, PCI_STP#, SUS_STAT[1:2]#, SUSCLK control supply trickle current, SUSC# should connected pin#14 power supply inverter. PWRBT# connected soft-switch button front panel external de-bounce circuitry. RSMRST# powered from volt stand-by) power supply through delay Schmitt trigger. delay circuit provides necessary delay RSMRST#. Connect SMBCLK, SMBDATA kohm (approximate) pull-up resistors 3V_STBY, route DIMM sockets A.G.P. connector. SMBALERT# connected 3V_STBY with kohm (approximate) resistor. connected modem used). should pulled-up 3V_STBY with kohm (approximate) pull-up resistor it's used. note after this section. BATLOW# used battery monitoring logic needs 8.2K pull-up (approximate) resistor 3V_STBY used. used monitoring logic needs 8.2k pull-up (approximate) resistor 3V_STBY used. When used thermal protection mode, THRM# must pulled-up core power plane with kohm resistor. Note:
will cause problem PIIX4 systems until July 1998. Mobile systems will converted PIIX4E this time (for throttling). desktop systems that submitted WHQL after July 1998 will pass ACPI unless they connect event other than that generated. Design Consideration: following should considered when implementing RESET BUTTON desktop based systems. system reset button typically been connected indirectly PWROK input PIIX4. This technique will reset suspend well logic, which includes Host Slave controllers. reset hardware suspend well, reset button should connected RSMRST# input
6-10
DESIGN CHECKLISTS
PIIX4. Assertion RSMRST#, reset button, will result complete system reset. RSMRST# assertion will cause SUS[A-C]# assert which results deassertion PWROK SUS[A-C]# controls power supply PS-ON control signal. deassertion PWROK will cause PIIX4 assert PCIRST#, RSTDRV, CPURST.
6.2.15 82093AA (IOAPIC) APIC required "DP" system optional "UP" system. APIC device. pins must connected Pins power, pins ground pins. APICCLK-May 2.5V, 3.3V levels. shared with Slot PICCLK then must 2.5V. maximum frequency MHz, minimum MHz. APICACK2# (pin 8)-This connected WSC# signal.
Design Considerations:
CLK-Is compatible with 3.3V input levels. typically connected clocks that maximum frequency MHz, minimum MHz. Support-The option route through IOAPIC recommended depending intended platform. Alarm Interrupt-When IOAPIC enabled, IRQ8# output signal PIIX4 reflects state IRQ8. IRQ8# resides PIIX4 suspend well connects INTIN8 IOAPIC. system SOFF state, PIIX4 will continue drive IRQ8 IOAPIC which could damage IOAPIC powered. this reason 74LVC125 buffer included schematics isolate IOAPIC's INTIN8 signal from PIIX4's IRQ8# signal when system suspended. System Timer Interrupt-When IOAPIC enabled, PIIX4 IRQ0 output signal reflects state system timer interrupt. This signal should connected INTIN2 IOAPIC (note that schematics only show pull-up this signal). Interrupts-The IRQ9OUT# output signal PIIX4 reflects state internally generated IRQ9 interrupt. interrupts hardwired IRQ9 PIIX4. ACPI compliance, this signal must connected IOAPIC (note that schematics leave this signal connect). There different routing options: INTIN9: IRQ9OUT# connected INTIN9 IOAPIC. ACPI BIOS will report that uses IRQ9 both APIC enabled platforms. However, this solution IRQ9 must left unconnected. This could create legacy incompatibility with cards that must only IRQ9. Note that this conflict exists enabled systems. PIIX4 automatically masks IRQ9 when SCI_EN set. INTIN20 INTIN22 other available interrupts): IRQ9OUT# connected available IOAPIC interrupt. This solution eliminates IRQ9 legacy conflict described INTIN9 routing option. However, this routing option creates issue. ACPI BIOS needs report which interrupt used generate SCI. enabled (like Memphis) platform would PIIX4 internal IRQ9. APIC enabled (like platform would INTIN20, example. ACPI BIOS telling which use, BIOS does know which will load. platform only supports APIC enabled (NT-only) there issue since BIOS will just report IRQ20. platform needs support both APIC operating systems Memphis), BIOS will require setup screen option that selects between APIC (IRQ20) (IRQ9) BIOS properly report which interrupt assigned SCI.
6.2.16 Boot Block Flash Design Considerations:
Intel recommends 2-Mbit Boot Block device BIOS non-volatile storage. Many designers finding difficult keep amount BIOS code small enough into 1-Mbit Flash. Legacy support keyboards requires additional code size support.
6-11
DESIGN CHECKLISTS
6.2.17 Power RESET connect PWRGOOD logic directly board. Route through Schmitt trigger device square-off maintain signal integrity system. Incorporate PWRGOOD output into power reset logic.
Software/BIOS
Please Pentium Processor BIOS Writer's Guide details regarding following responsibilities BIOS. Pentium processor cache must initialized enabled BIOS. STPCLK# feature must enabled EBL_Power_On systems utilizing STPCLK# place processor into power mode. BIOS must load BIOS Update Pentium processor early possible POST. BIOS update signature mechanism verify that processor accepted BIOS update. recommended that BIOS implement minimum update interface allow BIOS Update stored BIOS updated. Intel-defined update APIs, recommended that full INT15h interface implemented. calling utility test tool available this interface. Please contact your local Intel Field Sales representative copy. Before starting Flash update routine, MTRRs disable caching, only allow mode. This prevents WBINVD instruction from writing stale data Flash memory. Leave MTRR un-programmed; they reserved operating system use.
6.3.1 Design Considerations:
systems support both current Pentium processor future processors highly recommended that storage space more) BIOS Updates provided. This will allow manufacturing flexibility install either Pentium processor future Intel Pentium processors, BIOS detects processor loads correct BIOS Update. systems recommended that storage more) BIOS Updates reserved case where different Pentium processors installed. This allows support different Pentium processors.
Thermals/Cooling Solutions
Provide adequate heatsink ventilation ensure that Pentium processor TPLATE specification documented Pentium Processor/Slot Data Sheet met. Refer Pentium Processor/Slot Data Sheet AP-525 Pentium Processor Thermal Design Guidelines thermal design information. Provide adequate ventilation, Pentium Boxed processor ensure that intake temperature fan/heatsink less than maximum allowable preheat temperature (TPH) system maximum ambient temperature, measured 0.3" above center fan. Pentium Processor/Slot Data Sheet Specification. Verify that major components have proper airflow.
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DESIGN CHECKLISTS
6.4.1 Design Considerations:
Make sure flow from processor obstructed (e.g., cards, etc.). There should nothing between processor intake that preheat flowing into fan/heatsink. Eliminate recirculation paths when using system fan. Monitor flow through Power Supply Unit (PSU)/system fan. Check maximum ambient operation temperature system.
Mechanicals
physical space requirements Pentium processor heatsink must met. Refer Pentium Processor/Slot Data Sheet details. Boxed Pentium processor: physical space requirements Boxed Pentium processor fan/heatsink must met. Please Pentium Processor/Slot Data Sheet details.
6.5.1 Design Considerations
Pentium processor retention mechanism, retention mechanism attach mount heatsink support optional support structure retaining Pentium processor cartridge system during shock vibration situations. Meet motherboard keep zones mounting hole requirements. Please Pentium Processor/Slot Data Sheet details. Boxed Pentium processor requires implementation heatsink support holes heatsink support structure defined Pentium Processor/Slot Data Sheet order properly support Boxed Pentium processor fan/heatsink.
Layout checklist
6.6.1 Routing Board Fabrication exact value series resistor dependent board layout should determined through simulation measurement. skew between HCLK loads must less than -250 (follow skew layout recommendations this document, simulate). skew between PCLKs must less than difference between rising edges HCLK PCLK must between Refer chapter this document board stack-up, layout routing recommendations. trace length recommendations host traces must compensated allow trace lengths Pentium processor. Pentium processor trace lengths provided Pentium Processor Card IBIS Models. Please contact your local Field Sales representative copy model. Make characteristic impedance GTL+ between ohm. Intel qualified Slot connector vendor. header Support: Make sure that VCCCORE trace/power plane sufficient ensure VCCCORE meets specification. Please Pentium Processor/Slot Data Sheet trace/power plane resistance length requirements. Route with least (1.25 wide trace. Isolate VREF traces minimize chance crosstalk. Route VCCCORE from voltage regulator Slot "island" opposed trace. Make decoupling capacitor traces short wide possible.
6-13
Debug Recommendations
CHAPTER DEBUG RECOMMENDATIONS
Debug Recommendations
This section provides tool information, logic suggestions, technical support options summary problems which have been found associated with system debug. Although comprehensive scope, recommendations included preclude unnecessary expenditures time effort during early stages debug. While methodologies suggested those which Intel believes most likely successful, they substitute correct design practices they substitute other Intel references.
Slot Test Tools
Slot Test Kit, available '96, consists following test tools: Slot Electrical/Mechanical/Thermal (EMT) Test Tool, which provides mechanical, thermal voltage transient testing capabilities. Slot Continuity Test Tool (CTT), which provides continuity testing capabilities Slot connector. Please Slot Test User's Guide more information these tools.
Debug/Simulation Tools
7.2.1 Logic Analyzer Interface (LAI)
Logic analyzer interface modules provide connect your logic analyzer signals Pentium processor system bus. available vendors: Hewlett-Packard their HP-16500B* series logic analyzers. Please contact your local Intel Field Sales representative learn procedure obtain this equipment. This product purchased directly from Hewlett-Packard. Tektronix their DAS/NT* DAS/XP* series logic analyzers. Please contact your local Field Sales representative availability LAI562T interface module from Intel. DAS* software available directly from Tektronix. Please contact your local Intel Field Sales representative complete proper non-disclosure agreement required receive LAI.
7.2.2 In-Target Probe (ITP)
ITP562 provides software debug capability allowing setting/clearing hardware/software breakpoints, assembly/disassembly code, display/modification processor register set, display/modification system memory, display/modification space includes macro language custom debug procedure creation, etc. Contact your local Intel Field Sales representative availability, proper software license agreement non-disclosure agreement required receive ITP.
DEBUG RECOMMENDATIONS
7.2.3 Functional Model (BFM)
functional model Pentium processor host available from third party vendors requires special non-disclosure agreement. Please contact your local Intel Field Sales representative information functional model vendors complete appropriate non-disclosure agreements.
7.2.4 IBIS Models
IBIS Models available from Intel for: Pentium processor 440LX AGPset PIIX4 Xcelerator Please contact your local Intel Field Sales representative copy these models complete appropriate non-disclosure agreements.
7.2.5 FLOTHERM* Model
FLOTHERM Model available Pentium processor. Please contact your local Intel Field Sales representative copy this model complete appropriate non-disclosure agreements.
Debug Features
features mentioned this section debug purposes only initial prototype systems. They required production level systems. Some these features desirable test functions incorporate onto production boards. These features required allow test equipment connections debugging purposes.
7.3.1 Issue
LAI562 integration tool been designed such that extra load will presented CMOS signals connected Slot connector. following list signals affected: PREQ#, TCK, TDI, TDO, TMS, TRST#, INIT#, FLUSH#, STPCLK#, PICCLK, PICD[1:0]#, LINT[0]/INTR, LINT[1]/NMI, IERR#, SMI#, PWRGOOD, THERMTRIP#, SLP#, FERR#, IGNNE# A20M#.
DEBUG RECOMMENDATIONS
following circuit describes CMOS probe signals LAI562:
From Target VREF
Vtt_CMOS 1.04V
Figure 7-1. Probe Input Circuit
extra loading LAI562 requires stronger pull-up values target system. However, current limitations some signal drivers, this stronger value feasible. Calculation correct pull-up resistor value each CMOS signals should include load analysis based pull-up voltage, pull-up voltage tolerance, pull-up resistor tolerance, specifications, driver current rating, input current leakage, input timings, etc. resulting values conflict. result extra loading following compromise pull-ups VCC2.5 recommended. actual value required your system vary depending logic connected drive strength signal Slot connector. Inputs Slot connector from ITP562 Port: PREQ# TRST# 150-330 150-330 150-330 (approximately) pull-down recommended, pull-up used) 150-330 150-220 150-220 150-330 150-330
Inputs Slot connector from PIIX4: STPCLK# SMI# SLP# IERR# FERR# PWRGOOD INIT#
Outputs from Slot connector:
THERMTRIP# 150-220 Inputs Slot connector, from system logic (assuming driver):
DEBUG RECOMMENDATIONS
LINT[0]/INTR 150-330 LINT[1]/NMI 150-330 IGNNE# A20M# PICD[0]# PICD[1]# FLUSH# 150-330 150-330
Bi-directional signal to/from Slot connector:
Inputs Slot connector, only pullup:
7.3.2 Debug Logic Recommendations
Debug Recommendations intended assist development Pentium processor systems products utilizing following strongly recommended early prototype designs only. When debugging provide push button reset circuit. rely power-on reset from power supply. push-button reset usually results more repeatable results when debugging initialization problems because when resets system does clear discrete devices within chips. Therefore increasing probability chips booting with same initialization issue. Include Pentium processor debug port connector. Integration tools chapter Pentium Processor/Slot Data Sheet schematics signal checklist. sure proper 0.050" .100" (1.27 spacing connector. Provide capability measure processor's case temperature (Tplate) ensure that maximum temperature specification Pentium Processor/Slot Data Sheet violated. Place style similar) coaxial connector power plane between Header on-board voltage regulator Slot connector that power plane noise monitored systems. cable needed connect oscilloscope also. This footprint should only populated during design evaluation. ITP562 requires complete boundary scan chain. system, recommended place jumpers motherboard allow boundary scan chain bypass Slot connector with termination card. Debug Considerations:
technology drives lower power modes, VCCCORE current demand becomes very small. This sometimes cause regulator regulation. Place pads load resistance VCCCORE regulator event regulator cannot function with extremely current. After meeting guidelines Pentium Processor/Slot Data Sheet, many extra high frequency bulk decoupling capacitance sites will near processor slot. Intel recommends using industry standard Voltage Regulator Modules designed Pentium processor. modules designed Pentium processor utilizing voltage should also work initial Pentium processor samples early debug. However, these previous modules support future processors Slot Pentium processor module specification does meet maximum current requirements Pentium processor. Note: There Header pinout change required support designed with Slot back-up plan, have buffered crystal oscillator method processor clock distribution. This will useful case there jitter specification issues number components containing internal PLLs processor card.
DEBUG RECOMMENDATIONS Special Function Pins: VID[4:0] TYPE: Open ground-short FUNCTION: Voltage pins (VID[4:0]). These pins used vary voltage point converter that supplies power processor. NUMBERS: A121, B119, A119, A120, B120
Provide jumpers shown Figure 7-2, resistors. This allows changing voltage part.
Note:
Some modules able support pull-up resistors shown Figure 7-2. Contact your vendors understand their pull-up requirements.
Figure 7-2. Circuit
7.3.3 Debug Layout close attention keep zones Logic Analyzer Interface (LAI) described Integration Tools section Pentium Processor/Slot Data Sheet. These keep zones required ensure that installed within system.
Design Considerations:
Plan much space possible Pentium processor. This will allow additional cooling other requirements early Pentium processors.
7.3.4 Debug Procedures
When using ITP562 In-Target Probe Pentium processor, common error that boundary scan chain order ITP562.INI input file correct. Please check file ensure that scan chain connections your motherboard match order provided. This file needs change based what components boundary scan chain. systems, processor with PREQ0# PRDY0# considered processor even isn't first chain. noise limit speed cause functional problems. speed change from 1250 using keyword, TCLK "value," [Debug Port] section ITP562.INI file. Refer HELP menu "Changing TCLK Signal Frequency" valid values. there difficulties initializing ITP562 slow TCK.
DEBUG RECOMMENDATIONS macros available 440LX AGPset assist debugging your system. number macros provided. Some macros utilities read/write configuration register, macro display POST codes stop specified code, macros dump PIIX4 register sets well processor specific registers. Contact local Intel Field Sales representative copy these utilities. each processor should have pull-up. PICD0# PICD1# should each have pull-up (IERR# might asserted during APIC/MP message generation insufficient pull-up used.). Watch incorrect clock voltages. BCLK, TCK, PICCLK VCC2.5 signals. PICCLK must driven even APIC used. APIC executes initialization even uni-processor system. APIC disabled BIOS initial debug clearing APIC base (0x1Bh). sure boundary scan chains properly reset using TRST# each device debug port chain. Global Descriptor Table (GDT) must aligned. must located DWORD boundary, else setting branching will cause SHUTDOWN transaction. "pins" command used check reset configuration states. aware, however, that observing state during reset will reveal anything about stability timing configuration signals around reset edge. expect following Pentium processor activity after reset: BNR# stops toggling approximately million BCLKs after deassertion RESET#, BIST configured run. BIST configured run, BNR# will continue toggle until BIST completion. After BNR# stops toggling, PICD[1:0]# signals begin initialization determine bootstrap processor. single processor boot, 21-cycle short messages transmitted APIC. (Refer Pentium Family Developer's Manual, Vol. III.) following fields expected others "don't care." Please note that PICD[1:0]# active electrical levels will complement numbers presented here. Interrupt Vector 0x4N first cycle 0x1N second cycle. Where processor number D3-D0 1111 (all including self shorthand) Trigger Mode (edge) Level (deasserted) Delivery Mode (fixed)
440LX System
APPENDIX 440LX SYSTEM
PIIX4 Implementation
PIIX4 contains Universal Serial (USB) Host Controller which moves data between main system memory devices USB. host controller also includes root with ports. This permits connection peripherals devices directly PIIX4. PIIX4 Host Controller completely supports standard Universal Host Controller Interface (UHCI) takes advantage UHCI software drivers. PIIX4 fully supports Specification, Revision 1.0. PIIX4 supports both full speed speed signaling: Mbps Mbps, differentiate between full speed speed devices connected ports. electrical requirements motherboard design are:
rise fall times Mbps data signals (rise time/fall time) 100% 110% crossover voltage should between volts. rise fall times Mbps data signal (rise time/fall time) 100% 120% crossover voltage should between volts. signal impedance full speed differential signal. Single-ended zero state ports when function attached. minimum supply current each port. voltage supplied host 4.65V 5.25V.
440LX SYSTEM
Motherboard Layout Guidelines
goal following routing guidelines minimize effects ringing, crosstalk, radiation data signal lines. very important ensure that high frequency system signals couple signals radiate cable. This done carefully matching motherboard circuitry impedance that twisted pair cable, controlling signal rise fall times, careful routing signals motherboard.
A.2.1 Data Signals Layout Guidelines
Following general guidelines interface:
unused port should terminated with pull-down resistors both P+/P- data lines. series resistors should placed close possible PIIX4 inch). These series resistors there source termination reflected signal. capacitors must placed close PIIX4 possible PIIX4 side series resistors data lines (P0±, P1±). These caps there signal quality (rise/fall time) help minimize radiation. kohm pull-down resistors should placed side series resistors data lines (P0±, P1±), REQUIRED signal termination specification. length stub should short possible. trace impedance P0±, signals should ground) each signal impedance ohms between differential signal pairs match twisted pair cable impedance. Note that twisted pair characteristic impedance series impedance both wires, resulting individual wire presenting impedance. trace impedance controlled carefully selecting trace width, trace distance from power ground planes, physical proximity nearby traces. data lines must routed `critical signals' (i.e., hand routing preferred). P+/P- signal pair must routed together parallel with other signal traces minimize crosstalk. Doubling space from P+/P- signal pair adjacent signal traces will help prevent crosstalk. worry about crosstalk between P+/P- signal traces. P+/P- signal traces must also same length. This will minimize effect common mode current EMI. (Common mode current caused differential signals whose currents perfectly matched.)
Figure illustrates recommended signals schematic:
440LX SYSTEM
Driver
Motherboard Trace Motherboard Trace Connector
Driver
PIIX4
Transmission Line
Figure A-1. Data Signals
Twisted Pair Cable
Figure A-1b illustrates possible configuration having transmission trace. system designer responsible ensuring that particular configuration meets their requirements.
Figure A-1b. Possible Trace
440LX SYSTEM
results from Figure A-1b are:
Impedance `Z0' 45.4 Line Delay 160.2 Capacitance Inductance 53.9 Trace Height
A.2.2 Power Distribution Layout Guidelines
Following general guidelines power line ground line:
power lines should bypassed with tantalum capacitor depended layout topologies. should placed between fuse ferrite bead VCC. tantalum capacitors should have dissipation factor allow decoupling higher frequencies. Please refer section A.2.3 recommended topologies. Ferrite beads (and optional bypass capacitors) recommended each VSS, power ground lines, minimize radiation. They should placed close possible connector. recommended value ferrite beads MHz. important connect bypass capacitors chassis ground they used. capacitor values should between 0.01 0.10 Voltage divider circuits should used drive status power line OC[1:0]# inputs. OC[1:0]# signals 3.3V inputs have leakage current maximum recommended value (maximum) resistors 470K kohms. 0.001 0.01 capacitor noise filtering. These resistors should placed motherboard riser card option used connectors. PolySwitch fuses, standard fuses, some type solid state switch should used each power line overcurrent protection. spec requires that current limited units load unit each port. However, circuit protector must chosen that will trip power dynamic attach transient current. reasonable value trip current 1.5A 2.0A, exceed Table A-1. Electrical Characteristics Parameter Supply Voltage (Powered Host) Supply Current (Powered Host)
NOTE: minimum supply voltage 4.65V port after voltage drop power line connector. voltage drop power line consists trace resistance, resistance fuse, resistance ferrite beads yielding total voltage drop about lowest transient voltage (AC) that appear host 4.20V. supply current cannot exceed 5.0A. recommended trip current (minimum) 1.5A-2.0A. recommended time trip minimum solid state switch circuit power dynamic attach transient current.
Symbol
4.65
5.25
Unit
Notes
Figure illustrates recommended power line ground circuit:
440LX SYSTEM
Vbus (5V)
Fuse
Ferrite Bead
Port
Optional
OC0#
Chassis Ground
0.001
Ferrite Bead
Port
Chassis Ground
Figure A-2. Power Line VBUS Ground Line
A.2.3 Power Line Layout Topologies
following power line layout topologies typical those found platforms. system designers need carefully evaluate each recommended topology choose appropriate meet voltage drop droop requirements.
A.2.3.1 Option Optimal Design-Implemented
Figure represents optimal design downstream power connection. drop minimized through separate fuses ferrite beads. Each port dedicated bulk capacitance. When plug occurs port effect second port minimized because form three-way capacitive divider. port ferrite beads also have small resistance, that resistance acts inrush current limiter. Note that recommended value tantalum capacitors represent motherboard capacitance. also important that located within inch connectors.
Fuses Ferrite Beads
Port Power Supply 5V±5%
Port
Figure A-3. Best Downstream Power Connection
440LX SYSTEM
A.2.3.2 Option Effective Design-Recommended
Figure less expensive still effective implementation power output stage. principal difference that port capacitors fuses shared. increased compensate need carry twice current then voltage drop through this output circuit remains same. Droop voltage response will quite good Figure A-3, because must both supply current both peripheral alread
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