VOLT BULK ERASE FLASH MEMORY 28F010 28F020 (x8) Flash Electr
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VOLT BULK ERASE FLASH MEMORY
28F010 28F020 (x8)
Flash Electrical Chip-Erase 1-Mbit: Second Typical Chip-Erase 2-Mbit: Second Typical Chip-Erase Quick-Pulse Programming Algorithm Typical Byte-Program 1-Mbit: Second Chip-Program 2-Mbit: Second Chip-Program 100,000 Erase/Program Cycles High-Performance Read Maximum Access Time CMOS Power Consumption Typical Active Current Typical Standby Current Watts Data Retention Power Integrated Program/Erase Stop Timer
Command Register Architecture Microprocessor/Microcontroller Compatible Write Interface Noise Immunity Features ±10% Tolerance Maximum Latch-Up Immunity through Processing ETOXNonvolatile Flash Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience JEDEC-Standard Pinouts 32-Pin Plastic 32-Lead PLCC 32-Lead TSOP
(See Packaging Spec., Order #231369)
Extended Temperature Options
Intel® Volt Bulk Erase CMOS flash memory offers most cost-effective reliable alternative read/write random access nonvolatile memory. 28F010 28F020 electrical chip-erasure reprogramming familiar EPROM technology. Memory contents rewritten: test socket; PROM-programmer socket; on-board during subassembly test; in-system during final test; in-system after sale. 28F010 28F020 increase memory flexibility, while contributing time cost savings. 28F010 1024 kilobit nonvolatile memory organized 131,072 bytes eight bits. Similarly, 28F020 2048 kilobit nonvolatile memory organized 262,144 bytes eight bits. Both devices offered 32-pin plastic 32-lead PLCC TSOP packages. assignments conform JEDEC standards byte-wide EPROMs. Extended erase program cycling capability designed into Intel® ETOX(EPROM Tunnel Oxide) process technology. Advanced oxide processing, optimized tunneling structure, lower electric field combine extend reliable cycling beyond that traditional EEPROMs. With 12.0 supply, 28F010 28F020 perform 100,000 erase program cycles-well within time limits quickpulse programming quick-erase algorithms. Intel 28F010 28F020 employ advanced CMOS circuitry systems requiring high-performance access speeds, power consumption, immunity noise. access time provides zero waitstate performance wide range microprocessors microcontrollers. Maximum standby current translates into power savings when device deselected. Finally, highest degree latch-up protection achieved through Intel's unique processing. Prevention latch-up provided stresses address data pins, from With Intel ETOX process technology base, 28F010 28F020 build years EPROM experience yield highest levels quality, reliability, cost-effectiveness.
December 1998
Order Number: 290663-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. 28F010 28F020 contain design defects errors known errata which cause products deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 5937 Denver, 8021-9808 call 1-800-548-4725 visit Intel's website http://www.intel.com Copyright Intel Corporation 1996, 1997, 1998. Third-party brands names property their respective owners.
28F010/28F020
CONTENTS
PAGE PAGE Characteristics-28F020-TTL/NMOS Compatible-Commercial Products Characteristics-28F010-CMOS Compatible-Commercial Products Characteristics-28F020-CMOS Compatible-Commercial Products Characteristics-28F010-TTL/NMO Compatible-Extended Temperature Products Characteristics-28F020-TTL/NMO Compatible-Extended Temperature Products 4.10 Characteristics-28F010-CMOS Compatible-Extended Temperature Products 4.11 Characteristics-28F020-CMOS Compatible-Extended Temperature Products 4.12 Operation-Commercial Extended Temperature Products 4.13 Characteristics-28F020-Read Only Operations-Commercial Extended Temperature Products 4.14 Characteristics-28F010- Write/Erase/Program Only Operation- Commercial Extended Temperature Products 4.15 Characteristics-28F020- Write/Erase/Program Only Operation- Commercial Extended Temperature Products 4.16 CE#-Controlled Write-Commercial Extended Temperature 4.17 Controlled Writes-Commercial Extended Temperature Products 4.18 Erase Programming Performance ORDERING INFORMATION ADDITIONAL INFORMATION.
APPLICATIONS. PRINCIPLES OPERATION. Integrated Stop Timer Write Protection 2.2.1 Operations 2.2.1.1 Read 2.2.1.2 Output Disable 2.2.1.3 Standby. 2.2.1.4 Intelligent Identifier Operation. 2.2.1.5 Write. 2.2.2 Command Definitions. 2.2.2.1 Read Command 2.2.2.2 Intelligent Identifier Command 2.2.2.3 Set-Up Erase/Erase Commands 2.2.2.4 Erase Verify Command 2.2.2.5 Set-Up Program/Program Commands. 2.2.2.6 Program Verify Command 2.2.2.7 Reset Command 2.2.3 Extended Erase/Program Cycling 2.2.4 Quick-Pulse Programming Algorithm 2.2.5 Quick-Erase Algorithm DESIGN CONSIDERATIONS Two-Line Output Control. Power Supply Decoupling. Trace Printed Circuit Boards Power-Up/Down Protection. Volt Bulk Erase Power Dissipation. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Operating Conditions Capacitance. Characteristics-28F010-TTL/NMOS Compatible-Commercial Products
28F010/28F020
REVISION HISTORY
Description
Number -001
This document combines datasheets 28F010 (order 290207) 28F020 (order 290245), bulk erase devices.
APPLICATIONS
Intel 28F010 28F020 flash memories provide nonvolatility along with capability perform over 100,000 electrical chip-erasure/ reprogram cycles. These features make 28F010 28F020 innovative alternative disk, EEPROM, battery-backed static RAM. Where periodic updates code data tables required, 28F010 28F020 reprogrammability nonvolatility make them obvious ideal replacements EPROM. Primary applications operating systems stored flash eliminate slow disk-to-DRAM download process. This results dramatic enhancement performance substantial reduction power consumption-a consideration particularly important portable equipment. Flash memory increases flexibility with electrical chip erasure in-system update capability operating systems application code. With updatable code, system manufacturers easily accommodate last-minute changes revisions made. diskless workstations terminals, network traffic reduces minimum systems instant-on. Reliability exceeds that electromechanical media. Often these environments, power interruptions force extended re-boot periods networked terminals. This mishap longer issue boot code, operating systems, communication protocols primary applications flash resident each terminal. embedded systems that rely dynamic RAM/disk main system memory nonvolatile backup storage, 28F010 28F020 flash memories offer solid state alternative minimal form factor. 28F010 28F020 provide higher performance, lower power consumption, instant-on capability, allows "eXecute place" (XIP) memory hierarchy code data table reading. Additionally, flash memory more rugged reliable harsh environments where extreme temperatures shock cause disk-based systems fail. need code updates pervades phases system's life-from prototyping system manufacture after sale service. electrical chip-erasure reprogramming ability 28F010 28F020 allow in-circuit alterability; this eliminates unnecessary handling less reliable
28F010/28F020
socketed connections, while adding greater test, manufacture, update flexibility. Material labor costs associated with code changes increases higher levels system integration-the most costly being code updates after sale. Code "bugs," desire augment system functionality, prompt after sale code updates. Field revisions EPROM-based code requires removal EPROM components entire boards. With 28F010 28F020, code updates implemented locally edge connector, remotely over communication link. systems currently using high-density static RAM/battery configuration data accumulation, flash memory's inherent nonvolatility eliminates need battery backup. concern battery failure longer exists, important consideration portable equipment medical instruments, both requiring continuous performance. addition, flash memory offers considerable cost advantage over static RAM. Flash memory's electrical chip erasure, byte programmability complete nonvolatility well with data accumulation recording needs. Electrical chip-erasure gives designer "blank slate" which record data. Data periodically off-loaded analysis flash memory erased producing "blank slate." high degree on-chip feature integration simplifies memory-to-processor interfacing. Figure depicts 28F020s tied 80C186 system bus. 228F010 28F020 architecture minimize interface circuitry needed complete incircuit updates memory contents. outstanding feature TSOP (Thin Small Outline Package) thickness. TSOP particularly suited portable equipment applications requiring large amounts flash memory. With cost-effective in-system reprogramming, extended cycling capability, true nonvolatility, 28F010 28F020 offer advantages alternatives: EPROMs, EEPROMs, battery backed static RAM, disk. EPROM-compatible read specifications, straightforward interfacing, incircuit alterability offers designers unlimited flexibility meet high standards today's designs.
28F010/28F020
Erase Voltage Switch Array Source Input/Output Buffers State Control Command Register Integrated Stop Timer Voltage Switch Chip Enable Output Enable Logic Data Latch Address Latch Y-Decoder Y-Gating
X-Decoder
2,097,152 Cell Matrix
290207-1
Figure 28F020 Block Diagram
Table Description Symbol A0-A16 DQ0-DQ7 Type INPUT INPUT/OUTPUT Name Function INPUT INPUT INPUT
28F010/28F020
ADDRESS INPUTS memory addresses. Addresses internally latched during write cycle. 28F010: A[0-16], 28F020: A[0-17] DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data during memory read cycles. data pins active high float tri-state when chip deselected outputs disabled. Data internally latched during write cycle CHIP ENABLE: Activates device's control logic, input buffers, decoders sense amplifiers. active low; high deselects memory device reduces power consumption standby levels. OUTPUT ENABLE: Gates devices output through data buffers during read cycle. active low. WRITE ENABLE: Controls writes control register array. Write enable active low. Addresses latched falling edge data latched rising edge pulse. Note: With memory contents cannot altered.
ERASE/PROGRAM POWER SUPPLY writing command register, erasing entire array, programming bytes array. DEVICE POWER SUPPLY ±10%) GROUND INTERNAL CONNECTION device. driven left floating.
28F010/28F020
N28F010 32-LEAD PLCC 0.450" 0.550" VIEW 28F020 28F020
P28F010 32-LEAD PDIP 0.62" 1.64" VIEW
28F020
STANDARD PINOUT E28F010 32-LEAD TSOP 0.31" 0.72" VIEW
Figure 28F010/28F020 Configurations
80C186 System A1-A18 -DQ15 -DQ7 A0-A17 DQ0-DQ7 DQ0-DQ7 A0-A17 Address Decoded Chip Select BHE# 28F020 28F020
28F010/28F020
290207-4
Figure 28F020 80C186 System
PRINCIPLES OPERATION
Flash memory augments EPROM functionality with in-circuit electrical erasure reprogramming. Volt Bulk Erase introduces command register manage this functionality. command register allows for: 100% TTL-level control inputs; fixed power supplies during erasure programming; maximum EPROM compatibility. absence high voltage pin, Volt Bulk Erase read-only memory. Manipulation external memory control pins yields standard EPROM read, standby, output disable, intelligent identifier operations. same EPROM read, standby, output disable operations available when high voltage applied pin. addition, high voltage enables erasure programming device. functions associated with altering memory contents-intelligent identifier, erase, erase verify, program, program verify-are accessed command register.
Commands written register using standard microprocessor write timings. Register contents serve input internal state machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. With appropriate command written register, standard microprocessor read timings output array data, access intelligent identifier codes, output data erase program verification.
Integrated Stop Timer
Successive command write cycles define durations program erase operations; specifically, program erase time durations normally terminated associated Program Erase Verify commands. integrated stop timer provides simplified timing control over these operations; thus eliminating need maximum program/erase timing specifications. Programming erase pulse durations minimums only. When stop timer terminates program erase operation, device enters inactive state remains inactive until receiving appropriate Verify Reset command.
28F010/28F020
Table 28F010/28F020 Operations Mode Read Output Disable READ-ONLY Standby Intelligent Identifier (Mfr)(2) Intelligent Identifier (Device)(2) Read READ/WRITE Output Disable Standby(5) Write VPP(1) VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH VID(3) VID(3)
DQ0-DQ7 Data Tri-State Tri-State Data Data Data Out(4) Tri-State Tri-State Data In(6)
NOTES: Refer Characteristics. When VPPL memory contents read written erased. Manufacturer device codes also accessed command register write sequence. Refer Table other addresses low. intelligent identifier high voltage. Refer Characteristics. Read operations with VPPH access array data intelligent identifier codes. With high voltage, standby current equals (standby). Refer Table valid data-in during write operation. VIH.
Write Protection
2.2.1 2.2.1.1
OPERATIONS Read
command register only active when high voltage. Depending upon application, system designer choose make power supply switchable-available only when memory updates desired. When VPPL, contents register default Read command, making 28F010 28F020 readonly memories. this mode, memory contents cannot altered. system designer choose "hardwire" VPP, making high voltage supply constantly available. this case, command register functions inhibited whenever below write lockout voltage VLKO. (See Section 3.4, Power-Up/Down Protection.) 28F010 28F020 designed accommodate either design practice, encourage optimization processor memory interface. two-step program/erase write sequence command register provides additional software write protections.
28F010 28F020 have control functions, both which must logically active, obtain data outputs. Chip Enable (CE#) power control should used device selection. Output Enable (OE#) output control should used gate data from output pins, independent device selection. Refer read timing waveforms. When high (VPPH), read operation used access array data, output intelligent identifier codes, access data program/erase verification. When (VPPL), read operation only access array data. 2.2.1.2 Output Disable
With logic-high level (VIH), output from device disabled. Output pins placed highimpedance state.
2.2.1.3 2.2.1.4
28F010/28F020
2.2.1.5 Write
Standby
With logic-high level, standby operation disables most 28F010 28F020's circuitry substantially reduces device power consumption. outputs placed high-impedance state, independent signal. 28F010 28F020 deselected during erasure, programming, program/erase verification, device draws active current until operation terminated. Intelligent Identifier Operation
Device erasure programming accomplished command register, when high voltage applied pin. contents register serve input internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store command, along with address data information needed execute command. command register written bringing logic-low level (VIL), while low. Addresses latched falling edge WE#, while data latched rising edge pulse. Standard microprocessor write timings used. Refer Only Operations erase/programming waveforms specific timing parameters. 2.2.2 COMMAND DEFINITIONS
intelligent identifier operation outputs manufacturer code (89H) device code (B4H 28F010, 28F020). Programming equipment automatically matches device with proper erase programming algorithms. With logic level, raising high voltage (see Characteristics) activates operation. Data read from locations 0000H 0001H represent manufacturer's code device code, respectively. manufacturer device codes also read command register, instances where 28F010 28F020 erased reprogrammed target system. Following write command register, read from address location 0000H outputs manufacturer code (89H). read from address 0001H outputs device code (B4H 28F010, 28F020).
When voltage applied pin, contents command register default 00H, enabling read-only operations. Placing high voltage enables read/write operations. Device operations selected writing specific data patterns into command register. Table defines these 28F010/28F020 register commands.
28F010/28F020
Table Command Definitions First Cycle Cycles Req'd
Second Cycle Operation(1) Address(2) Data(3) Read Write Read Write Read Write
Command Read Memory Read Intelligent Identifier Codes(4) Set-Up Erase/Erase(5) Erase Verify(5) Set-Up Program/ Program(6) Program Verify(6) Reset(7)
Operation(1) Address(2) Write Write Write Write Write Write Write
Data(3)
NOTES: operations defined Table Identifier address: manufacturer code, device code. Erase Address: Address memory location read during erase verify. Program Address: Address memory location programmed. Addresses latched falling edge pulse. Identifier Data: Data read from location during device identification (Mfr 89H, Device (B4H 28F010, 28F020). Erase Verify Data: Data read from location during erase verify. Program Data: Data programmed location Data latched rising edge WE#. Program Verify Data: Data read from location during program verify. latched Program command. Following Read Intelligent command, read operations access manufacturer device codes. Figure illustrates 28F010/28F020 Quick-Erase Algorithm flowchart. Figure illustrates 28F010/28F020 Quick-Pulse Programming Algorithm flowchart. second cycle must followed desired command register write.
2.2.2.1
Read Command
While high, erasure programming, memory contents accessed Read command. read operation initiated writing into command register. Microprocessor read cycles retrieve array data. device remains enabled reads until command register contents altered. default contents register upon power-up 00H. This default value ensures that spurious alteration memory contents occurs during power transition. Where supply hardwired 28F010 28F020, device powers-up remains enabled reads until command register contents changed.
Refer Characteristics-Read-Only Operations waveforms specific timing parameters. 2.2.2.2 Intelligent Identifier Command
Flash memories intended applications where local alters memory contents. such, manufacturer device codes must accessible while device resides target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines desired system design practice.
28F010 28F020 contain intelligent identifier operation supplement traditional PROMprogramming methodology. operation initiated writing into command register. Following command Write, read cycle from address 0000H retrieves manufacturer code 89H. read cycle from address 0001H returns device code (B4H 28F010, 28F020). terminate operation, necessary write another valid command into register. 2.2.2.3 Set-Up Erase/Erase Commands
28F010/28F020
case where data read FFH, another erase operation performed. (Refer Section 2.2.2.3, Set-Up Erase/Erase Commands.) Verification then resumes from address last-verified byte. Once bytes array have been verified, erase step complete. device programmed. this point, verify operation terminated writing valid command (e.g., Program Set-Up) command register. Figure 28F010/28F020 Quick-Erase Algorithm flowchart, illustrates commands operations combined perform electrical erasure 28F010 28F020. Refer Only Operations waveforms specific timing parameters. 2.2.2.5 Set-Up Program/Program Commands
Set-Up Erase command-only operation that stages device electrical erasure bytes array. set-up erase operation performed writing command register. commence chip-erasure, Erase command (20H) must again written register. erase operation begins with rising edge pulse terminates with rising edge next pulse (i.e., Erase Verify command). This two-step sequence set-up followed execution ensures that memory contents accidentally erased. Also, chip-erasure only occur when high voltage applied pin. absence this high voltage, memory contents protected against erasure. Refer Only Operations waveforms specific timing parameters. 2.2.2.4 Erase Verify Command
Set-up program command-only operation that stages device byte programming. Writing into command register performs set-up operation. Once program set-up operation performed, next pulse causes transition active programming operation. Addresses internally latched falling edge pulse. Data internally latched rising edge pulse. rising edge also begins programming operation. programming operation terminates with next rising edge WE#, used write Program Verify command. Refer Only Operations Waveforms specific timing parameters. 2.2.2.6 Program Verify Command
Erase command erases bytes array parallel. After each erase operation, bytes must verified. erase verify operation initiated writing into command register. address byte verified must supplied latched falling edge pulse. register write terminates erase operation with rising edge pulse. Volt Bulk Erase applies internallygenerated margin voltage addressed byte. Reading from addressed byte indicates that bits byte erased. Erase Verify command must written command register prior each byte verification latch address. process continues each byte array until byte does return data, last address accessed.
Volt Bulk Erase programmed byte-bybyte basis. Byte programming occur sequentially random. Following each programming operation, byte just programmed must verified. program verify operation initiated writing into command register. register write terminates programming operation with rising edge pulse. program verify operation stages device verification byte last programmed. address information latched.
28F010/28F020
Volt Bulk Erase applies internallygenerated margin voltage byte. microprocessor read cycle outputs data. successful comparison between programmed byte true data means that byte successfully programmed. Programming then proceeds next desired byte location. Figure 28F010/28F020 Quick-Pulse Programming Algorithm flowchart, illustrates commands combined with operations perform byte programming. Refer Only Operations waveforms specific timing parameters. 2.2.2.7 Reset Command
quick- erase algorithms. Intel's algorithmic approach uses series operations (pulses), along with byte verification, completely reliably erase program device. 2.2.4 QUICK-PULSE PROGRAMMING ALGORITHM
Reset command provided means safely abort Erase Program command sequences. Following either Set-Up command (Erase Program) with consecutive writes will safely abort operation. Memory contents will altered. valid command must then written place device desired state. 2.2.3 EXTENDED ERASE/PROGRAM CYCLING
quick-pulse programming algorithm uses programming operations duration. Each operation followed byte verification determine when addressed byte been successfully programmed. algorithm allows programming operations byte, although most bytes verify first second operation. entire sequence programming byte verification performed with high voltage. Figure illustrates 28F010/28F020 Quick-Pulse Programming Algorithm flowchart. 2.2.5 QUICK-ERASE ALGORITHM
Intel's quick-erase algorithm yields fast reliable electrical erasure memory contents. algorithm employs closed-loop flow, similar quick-pulse programming algorithm, simultaneously remove charge from bits array. Erasure begins with read memory contents. Volt Bulk Erase erased when shipped from factory. Reading data from device would immediately followed device programming. devices being erased reprogrammed, uniform reliable erasure ensured first programming bits device their charged state (Data 00H). This accomplished, using quick-pulse programming algorithm, approximately seconds. Erase execution then continues with initial erase operation. Erase verification (data FFH) begins address 0000H continues through array last address, until data other than encountered. With each erase operation, increasing number bytes verify erased state. Erase efficiency improved storing address last byte verified register. Following next erase operation, verification starts that stored address location. Erasure typically occurs second. Figure illustrates 28F010/28F020 Quick-Erase Algorithm flowchart.
EEPROM cycling failures have always concerned users. high electrical field required thin oxide EEPROMs tunneling literally tear apart oxide defect regions. combat this, some suppliers have implemented redundancy schemes, reducing cycling failures insignificant levels. However, redundancy requires that cell size doubled-an expensive solution. Intel designed extended cycling capability into ETOX flash memory technology. Resulting improvements cycling reliability come without increasing memory cell size complexity. First, advanced tunnel oxide increases charge carrying ability ten-fold. Second, oxide area cell subjected tunneling electric field onetenth that common EEPROMs, minimizing probability oxide defects region. Finally, peak electric field during erasure approximately MV/cm lower than EEPROM. lower electric field greatly reduces oxide stress probability failure. Volt Bulk Erase capable 100,000 program/erase cycles. device programmed erased using Intel's quick-pulse programming
Start Programming Apply VPPH
28F010/28F020
Operation Standby
Command
Comments Wait Ramp VPPH(1)
PLSCNT
Initialize Pulse-Count Set-Up Program Program
Write Set-Up Program Write Program (A/D)
Write Write
Data Valid Address/Data Duration Program Operation (tWHWH1
Standby Time Write Program Verify Time Read Data from Device Verify Data PLSCNT =25? Increment Address Last Address? Write Read Apply VPPL Standby Write Read Standby Write Program Verify(2)
Data C0H; Stops Program Operations(3) tWHGL Read Byte Verify Programming
Stand-by
Read
Compare Data Output Data Expected
Data 00H, Resets Register Read Operations
Wait Ramp VPPL(1)
Apply VPPL Programming Completed
Program Error
0207_04
NOTES: Characteristics value VPPH VPPL. Program Verify only performed after byte programming. final read/compare performed (optional) after register written with Read command. Refer Principles Operation. CAUTION: algorithm must followed ensure proper reliable operation device.
Figure 28F010/28F020 Quick-Pulse Programming Algorithm
28F010/28F020
Start Erasure Operation Command Comments Entire Memory Must Before Erasure Quick-Pulse Programming Algorithm (Figure Standby Wait Ramp VPPH
Data 00H? Program Bytes Apply VPPH ADDR PLSCNT Write Erase Set-Up Write Erase Time Set-Up Erase Erase
Initialize Addresses Pulse-Count Write Write Stand-by Erase Verify Data Data Duration Erase Operation (tWHWH2 Addr Byte Verify; Data A0H; Stops Erase Operation(3) tWHGL Read Byte Verify Erasure
Write Erase Verify Time Read Data from Device Data FFH? Increment Addr Last Address? Write Read PLSCNT 1000?
Write
Standby Read
Standby
Compare Output Increment Pulse-Count
Write
Read
Data 00H, Resets Register Read Operations
Standby Apply VPPL Erasure Completed Apply VPPL
Wait Ramp VPPL
Erase Error
0207_05
NOTES: Characteristics value VPPH VPPL. Erase Verify performed only after chip-erasure. final read/compare performed (optional) after register written with Read command. Refer Principles Operation. CAUTION: algorithm must followed ensure proper reliable operation device.
Figure 28F010/28F020 Quick-Erase Algorithm
28F010/28F020
DESIGN CONSIDERATIONS Two-Line Output Control
Trace Printed Circuit Boards
Flash memories often used larger memory arrays. Intel provides read control inputs accommodate multiple memory connections. Twoline control provides for: lowest possible memory power dissipation and, complete assurance that output contention will occur. efficiently these control inputs, address decoder output should drive chip-enable, while system's read signal controls flash memories other parallel memories. This assures that only enabled memory devices have active outputs, while deselected devices maintain power standby condition.
Programming flash memories, while they reside target system, requires that printed circuit board designer attention power supply trace. supplies memory cell current programming. similar trace widths layout considerations given power bus. Adequate supply traces decoupling will decrease voltage spikes overshoots.
Power-Up/Down Protection
Volt Bulk Erase designed offer protection against accidental erasure programming during power transitions. Upon powerup, Volt Bulk Erase indifferent which power supply, VCC, powers first. Power supply sequencing required. Internal circuitry Volt Bulk Erase ensures that command register reset read mode power-up. system designer must guard against active writes voltages above VLKO when active. Since both must command write, driving either will inhibit writes. control register architecture provides added level protection since alteration memory contents only occurs after successful completion two-step command sequences.
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System designers interested three supply current (ICC) issues-standby, active, transient current peaks produced falling rising edges chipenable. capacitive inductive loads device outputs determine magnitudes these peaks. Two-line control proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have ceramic capacitor connected between VSS, between VSS. Place high-frequency, low-inherent inductance capacitors close possible devices. Also, every eight devices, electrolytic capacitor should placed array's power supply connection, between VSS. bulk capacitor will overcome voltage slumps caused printed circuit board trace inductance, will supply charge smaller capacitors needed.
Volt Bulk Erase Power Dissipation
When designing portable systems, designers must consider battery power consumption only during device operation, also data retention during system idle time. Flash nonvolatility increases usable battery life your system because Volt Bulk Erase does consume power retain code data when system off. Table illustrates power dissipated when updating Volt Bulk Erase.
28F010/28F020
Table Volt Bulk Erase Typical Update Power Dissipation(4) Notes Power Dissipation (Watt-Seconds) 28F010 28F020 0.34 0.37 1.05 0.171 0.136 0.478
Operation
Array Program/Program Verify Array Erase/Erase Verify Complete Cycle
NOTES: Formula calculate typical Program/Program Verify Power [VPP Bytes typical Prog Pulses (tWHWH1 IPP2 typical tWHGL IPP4 typical)] [VCC Bytes typical Prog Pulses (tWHWH1 ICC2 typical tWHGL ICC4 typical]. Formula calculate typical Erase/Erase Verify Power [VPP (VPP3 typical tERASE typical IPP5 typical tWHGL Bytes)] [VCC (ICC3 typical tERASE typical ICC5 typical tWHGL Bytes)]. Complete Cycle Array Preprogram Array Erase Program. "Typicals" guaranteed, based limited number samples from production lots.
28F010/28F020
NOTICE: This production datasheet. specifications subject change without notice.
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings*
Operating Temperature During Read. °C(1) During Erase/Program °C(1) Operating Temperature During Read. °C(2) During Erase/Program °C(2) Temperature Under Bias °C(1) Temperature Under Bias °C(2) Storage Temperature .-65 +125 Voltage with Respect Ground. -2.0 +7.0 V(3) Voltage with Respect Ground.-2.0 +13.5 V(3, Supply Voltage with Respect Ground During Erase/Program .-2.0 +14.0 V(3, Supply Voltage with Respect Ground. -2.0 +7.0 V(3) Output Short Circuit Current .100 mA(5)
*WARNING: Stressing device beyond Absolute Maximum Ratings cause permanent damage. These stress ratings only. Operation beyond Operating Conditions recommended extended exposure beyond Operating Conditions affect device reliability. NOTES: Operating Temperature commercial product defined this specification. Operating Temperature extended temperature products defined this specification. Minimum input voltage -0.5 During transitions, inputs undershoot -2.0 periods less than Maximum voltage output pins which overshoot periods less than Maximum voltage overshoot +14.0 periods less than Output shorted more than second. more than output shorted time. Testing Input/Output Waveform (Figure Testing Load Circuit (Figure testing characteristics.
Operating Conditions
Limits
Symbol
Parameter Operating Temperature(1) Operating Temperature(2) Supply Voltage (10%)(6) Supply Voltage (5%)(7)
4.50 4.75
5.50 5.25
Unit
Capacitance
Limits
Symbol COUT
Parameter Address/Control Capacitance Output Capacitance
Notes
Unit
Conditions VOUT
NOTE: Sampled, 100% tested.
28F010/28F020
Characteristics-28F010-TTL/NMOS Compatible Commercial Products
Limits
Test Conditions
Symbol ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1
Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current Read Current Standby Current
Notes
Typ(3)
±1.0
Unit
VOUT Max, MHz, Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
±10.0
IPP2 IPP3 IPP4 IPP5 VOH1
Programming Current Erase Current Program Verify Current Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage Intelligent Identifier Voltage
-0.5
0.45
VPPH Programming Progress VPPH Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
-2.5
11.50 13.00
Symbol VPPL VPPH VLKO
28F010/28F020
Characteristics-28F010-TTL/NMOS Compatible Commercial Products (Continued)
Limits Parameter Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage Notes 0.00 11.40 Typ(3) 12.60 Unit Test Conditions NOTE: Erase/Program Inhibited when VPPL
NOTES: Sampled, 100% tested. currents unless otherwise noted. Typical values 12.0 These currents valid product versions (packages speeds). 100% tested: characterization data available. "Typicals" guaranteed, based limited number samples from production lots.
28F010/28F020
Characteristics-28F020-TTL/NMOS Compatible Commercial Products
Limits
Test Conditions
Symbol ICCS ICC1
Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current
Notes
Typ(3)
±1.0
Unit
VOUT IOUT Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
ICC2 ICC3 ICC4 ICC5 IPPS IPP1
Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current Read Current, Current Standby Current
IPP2 IPP3 IPP4 IPP5
Programming Current Erase Current Program Verify Current Erase- Verify Current
VPPH Programming Progress VPPH VPPH Program Verify Progress VPPH Erase Verify Progress
Symbol VOH1 VPPL VPPH VLKO
28F010/28F020
Characteristics-29F020-TTL/NMOS Compatible Commercial Products (Continued)
Limits Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Intelligent Identifier Voltage Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage 0.00 11.40 11.50 13.00 12.60 Notes -0.5 Typ(3) 0.45 Unit NOTE: Erase/Program Inhibited when VPPL -2.5 Test Conditions
NOTES: currents unless otherwise noted. Typical values 12.0 These currents valid product versions (packages speeds). 100% tested: Characterization data available. "Typicals" guaranteed, based limited number samples from production lots.
28F010/28F020
Characteristics-28F010-CMOS Compatible Commercial Products
Limits
Test Conditions VOUT ±0.2 Max, MHz, Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
Symbol ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1
Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current Read Current, Current Standby Current
Notes
Typ(3)
±1.0
Unit
IPP2 IPP3 IPP4 IPP5 VOH1 VOH2 Programming Current Erase Current Program Verify Current Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage 0.85 -0.5 0.45
VPPH Programming Progress VPPH Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
-2.5 -100
Symbol VPPL VPPH VLKO
28F010/28F020
Characteristics-28F010-CMOS Compatible Commercial Products (Continued)
Limits Parameter Intelligent Identifier Voltage Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage 0.00 11.40 Notes 11.50 Typ(3) 13.00 12.60 Unit NOTE: Erase/Programs Inhibited when VPPL Test Conditions
NOTES: Refer Section 4.4.
Characteristics-28F020-CMOS Compatible Commercial Products
Limits Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current Notes Typ(3) ±1.0 Unit Test Conditions VOUT ±0.2 MHz, IOUT Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
Symbol ICCS ICC1
ICC2 ICC3 ICC4 ICC5 IPPS
Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current
28F010/28F020
Characteristics-28F020-CMOS Compatible Commercial Products (Continued)
Limits Parameter Read Current, Current Standby Current Notes Typ(3) Unit
Test Conditions VPPH Programming Progress VPPH Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
Symbol IPP1
IPP2 IPP3 IPP4 IPP5 VOH1 VOH2 VPPL VPPH VLKO Intelligent Identifier Voltage Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage 0.00 11.4 Programming Current Erase Current Program Verify Current Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage 0.85 11.5 13.00 12.60 -0.5 0.45
-2.5 -100
NOTE: Erase/Programs Inhibited when VPPL
Symbol ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1
28F010/28F020
Characteristics-28F010-TTL/NMOS Compatible Extended Temperature Products
Limits Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current Read Current Standby Current Notes Typ(3) ±1.0 ±10.0 Unit Test Conditions VOUT Max, MHz, Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress 13.00 -2.5 VPPH Programming Progress VPPH Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
IPP2 IPP3 IPP4 IPP5 VOH1
Programming Current Erase Current Program Verify Current Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage Intelligent Identifier Voltage
-0.5
0.45
11.50
28F010/28F020
Characteristics-28F010-TTL/NMOS Compatible Extended Temperature Products (Continued)
Limits
Test Conditions
Symbol VPPL VPPH VLKO
Parameter Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage
Notes
Typ(3)
12.60
Unit
NOTE: Erase/Program Inhibited when VPPL
0.00 11.40
NOTES: Refer Section 4.4.
Symbol ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1
28F010/28F020
Characteristics-28F020-TTL/NMOS Compatible Extended Temperature Products
Limits Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current Notes Typ(3) ±1.0 Unit Test Conditions VCC= VOUT IOUT Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current Read Current, Current Standby Current
IPP2 IPP3 IPP4 Programming Current Erase Current Program Verify Current
VPPH Programming Progress VPPH VPPH Program Verify Progress
28F010/28F020
Characteristics-TTL/NMOS Compatible Extended Temperature Products (Continued)
Limits
Unit -2.5 Test Conditions VPPH Erase Verify Progress NOTE: Erase/Program Inhibited when VPPL
Symbol IPP5 VOH1 VPPL VPPH VLKO
Parameter Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage Intelligent Identifier Voltage Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage
Notes
Typ(3)
0.45
-0.5
11.50 0.00 11.40 13.00 12.60
4.10
Symbol ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1
28F010/28F020
Characteristics-28F010-CMOS Compatible Extended Temperature Products
Limits Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current Programming Current Erase Current Program Verify Current Erase Verify Current Leakage Current Read Current, Current Standby Current Notes Typ(3) ±1.0 Unit Test Conditions VOUT ±0.2 Max, MHz, Programming Progress Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
IPP2 IPP3 IPP4 IPP5 VOH1 VOH2 Programming Current Erase Current Program Verify Current Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage 0.85 -0.5 0.45
VPPH Programming Progress VPPH Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
-2.5 -100
28F010/28F020
4.10
Characteristics-28F010-CMOS Compatible Extended Temperature Products (Continued)
Limits
Test Conditions NOTE: Erase/Programs Inhibited when VPPL
Symbol VPPL VPPH VLKO
Parameter Intelligent Identifier Voltage Intelligent Identifier Current during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage
Notes
11.50
Typ(3)
13.00
Unit
0.00 11.40
12.60
NOTE: Refer Section 4.4.
4.11
Characteristics-28F020-CMOS Compatible Extended Temperature Products
Limits
Symbol ICCS ICC1
Parameter Input Leakage Current Output Leakage Current Standby Current Active Read Current
Notes
Typ(3)
±1.0
Unit
Test Conditions VOUT ±0.2 IOUT Programming Progress Erasure Progress VPPH Program Verify Progress
ICC2 ICC3 ICC4
Programming Current Erase Current Program- Verify Current
4.11
Symbol ICC5 IPPS IPP1 IPP2 IPP3 IPP4 IPP5 VOH1 VOH2
28F010/28F020
Characteristics-28F020-CMOS Compatible Extended Temperature Products (Continued)
Limits Parameter Erase Verify Current Leakage Current Read Current, Current Standby Current Notes Typ(3) Unit Test Conditions VPPH Erase Verify Progress
Programming Current Erase Current Program Verify Current Erase Verify Current Input Voltage Input High Voltage Output Voltage Output High Voltage 0.85 Intelligent Identifier Voltage Intelligent Identifier Current 11.50 13.00 -0.5 0.45
VPPH Programming Progress VPPH Erasure Progress VPPH Program Verify Progress VPPH Erase Verify Progress
-2.5 -100
28F010/28F020
4.11
Characteristics-28F020-CMOS Compatible Extended Temperature Products (Continued)
Limits
Test Conditions NOTE: Erase/Programs Inhibited when VPPL 1.3V
Symbol VPPL VPPH VLKO
Parameter during Read-Only Operations during Read/Write Operations Erase/Write Lock Voltage
Notes
0.00 11.40
Typ(3)
12.60
Unit
NOTE: Refer Section 4.4.
Input 0.45
Test Points
Output
0207_06
1N914 Device Under Test
0207_07
test inputs driven (2.4 VTTL) Logic (0.45 VTTL) Logic "0". Input timing begins (2.0 VTTL) (0.8 VTTL). Output timing ends VIL. Input rise fall times (10% 90%)
Figure Testing Input/Output Waveform
Includes Capacitance
Figure Testing Load Circuit
4.12
Symbol tAVAV/tRC tELQV/tCE tGLQV/tOE tELQX/tLZ tEHQZ
28F010/28F020
Operations Commercial Extended Temperature Products
Versions Characteristic Read Cycle Time Access Time Notes 28F010-90(1) 28F010-120(1) 28F010-150(1) Unit
tAVQV/tACC Address Access Time Access Time Chip Disable Output High
tGLQX/tOLZ Output tGHQZ/tDF tWHGL Output Disable Output High Output Hold from Address, CE#, Change Write Recovery Time before Read
NOTES: Input/Output Waveform Testing Load Circuit testing characteristics. Sampled, 100% tested. Guaranteed design. Whichever occurs first.
28F010/28F020
4.13
Characteristics-28F020-Read Only Operations Commercial Extended Temperature Products
Versions 28F020-90(4) Notes
Unit
28F020-120(4) 28F020-150(4)
Symbol tAVAV/tRC
Characteristics Read Cycle Time
tELQV/tCE> Chip Enable Access Time tAVQV/tACC Address Access Time tGLQV/tOE tELQX/tLZ tEHQZ Output Enable Access Time Chip Enable Output Chip Disable Output High
tGLQX/tOLZ Output Enable Output tGHQZ/tDF tWHGL Output Disable Output High Output Hold from Address, CE#, Change Write Recovery Time before Read
NOTES: Whichever occurs first. Sampled, 100% tested. Guaranteed design. High Speed Testing Input/Output Waveform (Figure High Speed Testing Load Circuit (Figure testing characteristics. Testing Input/Output Waveform (Figure Testing Load Circuit (Figure testing characteristics.
28F010/28F020
290207-9
Figure Waveforms Read Operations
28F010/28F020
4.14
Only Operations(1) Commercial Extended Temperature Products
Versions 28F010-90(2) Notes 28F010-120(2) 28F010-150(2)
Unit
Symbol tAVAV/tWC tAVWL/tAS tWLAX/tAH
Characteristic Write Cycle Time Address Set-Up Time Address Hold Time
tDVWH/tDS
Data Set-Up Time
tWHDX/tDH tWHGL tGHWL tELWL/tCS tWHEH/tCH tWLWH/tWP
Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Chip Enable Set-Up Time before Write Chip Enable Hold Time Write Pulse Width
tWHWL/tWPH Write Pulse Width High tWHWH1 tWHWH2 tVPEL Duration Programming Operation Duration Erase Operation Set-Up Time Chip Enable
NOTES: Read timing characteristics during read/write operations same during read-only operations. Refer Characteristics Read-Only Operations. Input/Output Waveform Testing Load Circuit testing characteristics. Minimum specification extended temperature product. Guaranteed design. integrated stop timer terminates programming/erase operations, thus eliminating need maximum specification.
4.15
Symbol tAVAV/ tAVWL/ tWLAX/ tDVWH/ tWHDX/ tWHGL tGHWL tELWL/ tWHEH/ tWLWH/
28F010/28F020
Only Operations(1) Commercial Extended Temperature Products
Versions Characteristics Write Cycle Time Address Set-Up Time Address Hold Time Data Set-Up Time Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Chip Enable Set-Up Time before Write Chip Enable Hold Time Write Pulse Width Notes 28F020-90(4) 28F020-120(4) 28F020-150(4) Unit
tWHWL/ tWPH tWHWH1 tWHWH2 tVPEL
Write Pulse Width High Duration Programming Operation Duration Erase Operation Set-Up Time Chip Enable
NOTES: Read timing characteristics during read/write operations same during read-only operations. Refer Characteristics Read-Only Operations. Guaranteed design. integrated stop timer terminates programming/erase operations, thus eliminating need maximum specification. Testing Input/Output Waveform (Figure Testing Load Circuit (Figure testing characteristics. Minimum Specification Extended Temperature product.
28F010/28F020
290207-13
290207-15
Figure 28F010 Typical Programming Capability
Figure 28F010 Typical Erase Capability
290207-14
290207-16
Figure 28F010 Typical Program Time
Figure 28F010 Typical Erase Time
28F010/28F020
0245_13 0245_11
Figure 28F020 Typical Programming Capability
NOTE: Does include Pre-Erase Program.
Figure 28F020 Typical Erase Capability
0245_14
0245_12
NOTE: Does include Pre-Erase Program.
Figure 28F020 Typical Program Time
Figure 28F020 Typical Erase Time
28F010/28F020
290207-10
Figure Waveforms Programming Operations
28F010/28F020
290207-11
Figure Waveforms Erase Operations
28F010/28F020
4.16
CE#-Controlled Writes(1) Commercial Extended Temperature
Versions 28F010-90(2) Notes
Unit
28F010-120(2) 28F010-150(2)
Symbol tAVAV tAVEL tELAX
Characteristic Write Cycle Time Address Set-Up Time Address Hold Time
tDVEH
Data Set-Up Time
tEHDX tEHGL tGHWL tWLEL tEHWH tELEH
Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Write Enable Set-Up Time before Chip Enable Write Enable Hold Time Write Pulse Width
tEHEL tEHEH1 tEHEH2 tVPEL
Write Pulse Width High Duration Programming Operation Duration Erase Operation Set-Up Time Chip Enable
NOTES: Read timing characteristics during read/write operations same during read-only operations. Refer Characteristics Read-Only Operations. Input/Output Waveform Testing Load Circuit testing characteristics. Minimum specification extended temperature product. Guaranteed design. integrated stop timer terminates programming/erase operations, thus eliminating need maximum specification.
4.17
Symbol tAVAV tAVEL tELAX tDVEH tEHDX tEHGL tGHWL tWLEL tEHWH tELEH
28F010/28F020
Controlled Writes(1) Commercial Extended Temperature Products
Versions Characteristics Write Cycle Time Address Set-Up Time Address Hold Time Data Set-Up Time Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Write Enable Set-Up Time before Chip Enable Write Enable Hold Time Write Pulse Width Notes 28F020-90(4) 28F020-120(4) 28F020-150(4) Unit
tEHEL tEHEH1 tEHEH2 tVPEL
Write Pulse Width High Duration Prog. Operation Duration Erase Operation Set-Up Time Chip Enable
NOTES: Read timing characteristics during read/write operations same during read-only operations. Refer Characteristics Read-Only Operations. Guaranteed design. integrated stop timer terminates programming/erase operations, thus eliminating maximum specification. Testing Input/Output Waveform (Figure Testing Load Circuit (Figure testing characteristics. Minimum specification extended temperature product.
28F010/28F020
4.18
Erase Programming Performance
Parameter Notes Typical 28F010 28F020 28F010 12.5
Unit 28F020
Chip Erase Time Chip Program Time
NOTES: "Typicals" guaranteed, based samples from production lots. Data taken VPP. Minimum byte programming time excluding system overhead µsec µsec program µsec write recovery), while maximum µsec/byte µsec loops allowed algorithm). chip programming time specified lower than worst case allowed programming algorithm since most bytes program significantly faster than worst case byte. Excludes programming prior erasure. Excludes system level overhead.
290207-19
NOTE: Alternative CE#-Controlled Write Timings also apply erase operations.
Figure Alternate Waveforms Programming Operations
28F010/28F020
ORDERING INFORMATION
Operating Temperature Extended Temp Blank Commercial Temp Package 32-Pin PDIP 32-Lead PLCC 32-Lead TSOP Product Line Designator Intel Flash products Access Speed (ns)
Density Mbit
290207-20
VALID COMBINATIONS: E28F010-90 N28F010-90 E28F010-120 N28F010-120 E28F010-150 N28F010-150 TE28F010-90 TE28F010-120 TE28F010-150 TN28F010-90 TN28F010-120 TN28F010-150 N28F020-90 N28F020-120 N28F020-150 TN28F020-90 TN28F020-120 TN28F020-150
P28F010-90 P28F010-120 P28F010-150 TP28F010-90 TP28F010-120 TP28F010-150 P28F010-90 P28F010-120 P28F010-150
E28F020-90 E28F020-120 E28F020-150 TE28F020-90 TE28F020-120 TE28F020-150
ADDITIONAL INFORMATION
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