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Intel® 440GX AGPset

Design Guide Update

Intel® 440GX AGPset
Design Guide Update
May 1999
Order Number:
Intel® 82443GX
Design Guide Update
Intel® 82443GX
Contents
Revision History.............................................................. 4 Preface ..................................................................... 5 General Design Considerations .................................................. 7 Schematic, Layout and Routing Updates ........................................... 9 Documentation Changes...................................................... 10
Design Guide Update
Intel® 82443GX
Revision History
Rev. 001 Initial Release Draft / Changes Date May 1999
Design Guide Update
Intel® 82443GX
Preface
This document is an update to the specifications contained in the Intel® 440GX AGPset Design Guide Rev 1.0, March 1999, order number 290651-001. References may also be made to the following documents: the Intel® 440GX AGPset: 82443BX Host Bridge Controller data sheet, order number 290638-001, and the 82371AB (PIIX4) data sheet section of the Platform Components databook, order number 296467-009. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. This design guide is primarily targeted at the PC market segment and was first published in 1999. Those using this design guide should check for device availability before designing in any of the components included in this document
Nomenclature
General Design Considerations includes system level considerations that the system designer should account for when developing hardware or software products using the Intel® 82440GX AGPset. Schematic, Layout and Routing Updates include suggested changes to the current published schematics or layout, including typos, errors, or omissions from the current published documents. Documentation Changes include suggested changes to the current published design guide not including the above.
Design Guide Update
Intel® 82443GX
Summary Table of Changes
The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Intel® 440GX AGPset stepping. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations: Codes Used in Summary Table Doc: Shaded: Document change or update that will be implemented. This item is either new or modified from the previous version of the document.
Plans Doc Doc Doc Doc Doc
GENERAL DESIGN CONSIDERATIONS Implementing a RESET BUTTON for 440GX Based Systems PCIRST# Load Sensitivity on PIIX4 / PIIX4E SPD EEPROM Write Protection. Execute the WBINVD Instruction to Save Cache State to Memory Before Initiating an S2 or S3 Sleep State. SLP# Connectivity in Multi-processor Systems.
Plans Doc Doc
SCHEMATIC, LAYOUT AND ROUTING UPDATES Guidelines to minimize ESD events that may cause loss of CMOS contents is added. Correct Strapping for SMC FDC37C932FR Ultra IO device VBAT pin.
Plans
DOCUMENTATION CHANGES There are currently no known documentation changes.
Design Guide Update
Intel® 82443GX
General Design Considerations
1. Implementing a RESET BUTTON for Desktop Based Systems
The following should be considered when implementing a RESET BUTTON for 440GX based systems: The system reset button has typically been connected indirectly to the PWROK input of the PIIX4 / PIIX4E. This technique will not reset the suspend well logic, which includes the SMBus Host and Slave controllers. To reset the hardware in the suspend well, the reset button should be connected to the RSMRST# input of the PIIX4 / PIIX4E. Assertion of RSMRST#, via a reset button, will result in a complete system reset. RSMRST# assertion will cause SUSA-C# to assert which results in the deassertion of PWROK if SUSA-C# controls the power supply PS-ON control signal. The deassertion of PWROK will cause the PIIX4 / PIIX4E to assert PCIRST#, RSTDRV, and CPURST.
PCIRST# Load Sensitivity on PIIX4 / PIIX4E
A specific board sensitivity has been identified by PCD that may result in a low going glitch on a deasserted PCIRST# signal when it is lightly loaded. This glitch may occur as a result of VCC droop caused by simultaneous switching of most / all AD31:0 signals from 0 to 1. This glitch can in some designs be low enough (below 1.7V) to interfere with proper operation of the Host PCI Bridge Controller component. This sensitivity manifests itself on designs where PCIRST# is lightly loaded with less than approximately 50pF, or is not driving the entire PCI bus. Design features that could aggravate the problem are an inline active component on the PCIRST# signal, such as an AND gate or, lack of a series termination resistor on the PCIRST# signal at the PIIX4 or PIIX4E. There are several improvements that can be implemented individually or in any combination. First, a series termination resistor between 22 and 33 ohms placed close to the PIIX4 / PIIX4E will help reduce the glitch. Second, an external capacitor of approximately 47pF will help reduce the glitch. Third, if the design currently uses an in-line active gate / buffer on PCIRST# to drive the PCI bus, consider removal of this gate / buffer entirely. The PIIX4 / PIIX4E is designed to drive the entire PCI bus.
Design Guide Update
Intel® 82443GX
SPD EEPROM Write Protection
The PC SDRAM Unbuffered DIMM Specification, Rev 1.0, dated Feb 1998, shows pin 81 of the DIMM module is the WP (write protect) pin for the SPD EEPROM. The block diagrams show there is a 47K pull-down resistor tied to the WP pin. This allows the DIMM manufacturers to write SPD data to the EEPROM. An OEM may wish to use the SPD EEPROM to write information into the DIMMs at production for system level checkout to identify the DIMM installed as being shipped with the system. For this reason, the OEM may wish to include some logic to control the level on pin 81 of the DIMM modules so that after the DIMM is tagged, they can be write protected again. If this pin is pulled high on the motherboard, the DIMM SPD EEPROM is write protected. Pin 81 of the DIMM sockets on the 82440GX reference schematics are shown as "NC", no connects. If an OEM wishes to write protect the SDRAM SPD EEPROMS, then these pins should be pulled high.
Execute the WBINVD Instruction to Save Cache State to Memory Before Initiating an S2 or S3 Sleep State
If a system design requires that the hardware platform be capable of flushing the processor caches, then FLUSH# must be asserted a minimum of one BSCLCK before STPCLK#. Power management software should perform a WBINVD on each processor for the S2 and S3 sleep states. Flushing the cache on each processor is not necessary for the S1 sleep state.
SLP# Connectivity in Multi-processor Systems
For multi-processor systems using the PIIX4 / PIIX4E, the SLP# signal may be asserted to one of the processors before it is in a processor sleep state 3, and therefore not yet acknowledged. This could result in a wakeup problem. Specifically, For PIIX4 / PIIX4E based platforms, STPCLK# from the PIIX4E is connected to all processors, and SLP# from the PIIX4E is connected to all processors. The following sequence occurs: 1) 2) 3) 4) OS writes to PMCNTRL register PIIX4E asserts STPCLK#, then waits for Stop Grant The processor acknowledges with a Stop Grant Acknowledge PIIX4E asserts SLP# after receiving Stop Grant Acknowledge
Design Guide Update
Intel® 82443GX
Schematic, Layout and Routing Updates
Guidelines to Minimize ESD Events That May Cause Loss of CMOS Contents
Correct Strapping for SMC FDC37C932FR Ultra IO Device VBAT Pin
When the PIIX4 / PIIX4E internal RTC is used, the SMC Ultra IO device, FDC37C932FR, VBAT pin must be connected to ground through between a 1K and 0 ohm pull-down resistor.
Design Guide Update
Intel® 82443GX
Documentation Changes
There are currently no known documentation changes.
Design Guide Update
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