Design Guide Update Order Number: 290660-001 Intel® 824

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Design Guide Update Order Number: 290660-001 Intel® 824

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Intel® 440GX AGPset
Design Guide Update
Order Number:
290660-001
Intel® 82443GX
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® 440GX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. *Third-party brands names property their respective owners. Copyright Intel Corporation 1999
Design Guide Update
Intel® 82443GX
Contents
Revision History. Preface General Design Considerations Schematic, Layout Routing Updates Documentation Changes.
Design Guide Update
Intel® 82443GX
Revision History
Rev. Initial Release Draft/Changes Date
Design Guide Update
Intel® 82443GX
Preface
This document update specifications contained Intel® 440GX AGPset Design Guide 1.0, March 1999, order number 290651-001. References also made following documents: Intel® 440GX AGPset: 82443BX Host Bridge Controller data sheet, order number 290638-001, 82371AB (PIIX4) data sheet section Platform Components databook, order number 296467-009. intended hardware system manufacturers software developers applications, operating systems, tools. This design guide primarily targeted market segment first published 1999. Those using this design guide should check device availability before designing components included this document
Nomenclature
General Design Considerations includes system level considerations that system designer should account when developing hardware software products using Intel® 82440GX AGPset. Schematic, Layout Routing Updates include suggested changes current published schematics layout, including typos, errors, omissions from current published documents. Documentation Changes include suggested changes current published design guide including above.
Design Guide Update
Intel® 82443GX
Summary Table Changes
following table indicates Specification Changes, Errata, Specification Clarifications Documentation Changes, which apply listed Intel® 440GX AGPset stepping. Intel intends some errata future stepping component account other outstanding issues through documentation Specification Changes noted. This table uses following notations: Codes Used Summary Table Doc: Shaded: Document change update that will implemented. This item either modified from previous version document.
Plans
GENERAL DESIGN CONSIDERATIONS Implementing RESET BUTTON 440GX Based Systems PCIRST# Load Sensitivity PIIX4/PIIX4E EEPROM Write Protection. Execute WBINVD Instruction Save Cache State Memory Before Initiating Sleep State. SLP# Connectivity Multi-processor Systems.
Plans
SCHEMATIC, LAYOUT ROUTING UPDATES Guidelines minimize events that cause loss CMOS contents added. Correct Strapping FDC37C932FR Ultra device VBAT pin.
Plans
DOCUMENTATION CHANGES There currently known documentation changes.
Design Guide Update
Intel® 82443GX
General Design Considerations
Implementing RESET BUTTON Desktop Based Systems
following should considered when implementing RESET BUTTON 440GX based systems: system reset button typically been connected indirectly PWROK input PIIX4/PIIX4E. This technique will reset suspend well logic, which includes SMBus Host Slave controllers. reset hardware suspend well, reset button should connected RSMRST# input PIIX4/PIIX4E. Assertion RSMRST#, reset button, will result complete system reset. RSMRST# assertion will cause SUS[A-C]# assert which results deassertion PWROK SUS[A-C]# controls power supply PS-ON control signal. deassertion PWROK will cause PIIX4/PIIX4E assert PCIRST#, RSTDRV, CPURST.
PCIRST# Load Sensitivity PIIX4/PIIX4E
specific board sensitivity been identified that result going glitch deasserted PCIRST# signal when lightly loaded. This glitch occur result droop caused simultaneous switching most/all AD[31:0] signals from This glitch some designs enough (below 1.7V) interfere with proper operation Host Bridge Controller component. This sensitivity manifests itself designs where PCIRST# lightly loaded with less than approximately 50pF, driving entire bus. Design features that could aggravate problem are; inline active component PCIRST# signal, such gate lack series termination resistor PCIRST# signal PIIX4 PIIX4E. There several improvements that implemented individually combination. First, series termination resistor between ohms placed close PIIX4/PIIX4E will help reduce glitch. Second, external capacitor approximately 47pF will help reduce glitch. Third, design currently uses in-line active gate/buffer PCIRST# drive bus, consider removal this gate/buffer entirely. PIIX4/PIIX4E designed drive entire bus.
Design Guide Update
Intel® 82443GX
EEPROM Write Protection
SDRAM Unbuffered DIMM Specification, 1.0, dated 1998, shows DIMM module (write protect) EEPROM. block diagrams show there pull-down resistor tied pin. This allows DIMM manufacturers write data EEPROM. wish EEPROM write information into DIMMs production system level checkout identify DIMM installed being shipped with system. this reason, wish include some logic control level DIMM modules that after DIMM tagged, they write protected again. this pulled high motherboard, DIMM EEPROM write protected. DIMM sockets 82440GX reference schematics shown "NC", connects. wishes write protect SDRAM EEPROMS, then these pins should pulled high.
Execute WBINVD Instruction Save Cache State Memory Before Initiating Sleep State
system design requires that hardware platform capable flushing processor caches, then FLUSH# must asserted minimum BSCLCK before STPCLK#. Power management software should perform WBINVD each processor sleep states. Flushing cache each processor necessary sleep state.
SLP# Connectivity Multi-processor Systems
multi-processor systems using PIIX4/PIIX4E, SLP# signal asserted processors before processor sleep state therefore acknowledged. This could result wakeup problem. Specifically, PIIX4/PIIX4E based platforms, STPCLK# from PIIX4E connected processors, SLP# from PIIX4E connected processors. following sequence occurs: writes PMCNTRL register PIIX4E asserts STPCLK#, then waits Stop Grant processor acknowledges with Stop Grant Acknowledge PIIX4E asserts SLP# after receiving Stop Grant Acknowledge
While this sequence works uni-processor systems, processors into Processor Sleep State State during ACPI state. This means that SLP# signal must connected processor multi-processor systems. Note that disabling SLEEP_EN PIIX4E Processor Control register accecptable workaround this issue since this only controls SLP# assertion state, state.
Design Guide Update
Intel® 82443GX
Schematic, Layout Routing Updates
Guidelines Minimize Events That Cause Loss CMOS Contents
Recommendations Board Designs: Provide dielectric, monolithic, ceramic capacitor between VCCRTC PIIX4/PIIX4E ground plane. This capacitor's positive connection should stubbed trace must close possible PIIX4/PIIX4E. capacitor must further than inch from PIIX4/PIIX4E. stub required, should kept maximum length. ground connection should made through ground plane, with minimal trace between capacitor via. Place battery, series current limit resistor, common-cathode isolation diode very close PIIX4/PIIX4E. this possible, place common-cathode diode resistor close capacitor possible. place these components between capacitor PIIX4. battery placed remotely from PIIX4/PIIX4E. boards that have chassis-intrusion utilizing external logic powered VCCRTC pin, place inverters close common-cathode diode possible. this possible, keep trace near center board. Keep PIIX4/PIIX4E VCCRTC trace away from board edge. this trace must from opposite ends board, keep trace towards board center, away from board edge where people equipment that handle board could make contact. Recommendations Existing Board Designs: effectiveness adding capacitor, identified above, needs determined examining routing placement. example, placing capacitor from PIIX4 reduces effectiveness.
Correct Strapping FDC37C932FR Ultra Device VBAT
When PIIX4/PIIX4E internal used, Ultra device, FDC37C932FR, VBAT must connected ground through between pull-down resistor.
Design Guide Update
Intel® 82443GX
Documentation Changes
There currently known documentation changes.
Design Guide Update
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Design Guide Update Order Number: 290660-001 Intel® 824

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