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Intel® 440GX AGPset
Order Number: 290651-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Intel® 440GX AGPset contain design defects errors which cause products deviate from published specifications. Current characterized errata available request. two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol SMBus bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999 *Third-party brands names property their respective owners.
Intel® 440GX AGPset
Contents
Introduction .1-1 About This Design Guide .1-1 References.1-2 Intel® Pentium® Processor Intel® 440GX AGPset Overview .1-3 1.3.1 Intel® Pentium® Processor.1-3 1.3.2 Intel® 440GX AGPset .1-4 1.3.2.1 System Interface.1-5 1.3.2.2 DRAM Interface .1-5 1.3.2.3 Accelerated Graphics Port Interface.1-5 1.3.2.4 Interface.1-6 1.3.2.5 System Clocking .1-6 1.3.3 PCI-to-ISA/IDE Xcelerator (PIIX4E).1-6 1.3.3.1 Instrumentation .1-7 1.3.3.2 Remote Service Boot.1-7 1.3.3.3 Remote Wake-Up .1-8 1.3.3.4 Power Management.1-8 Design Recommendations.1-8 1.4.1 Voltage Definitions .1-8 1.4.2 General Design Recommendations .1-9 1.4.3 Transitioning from Intel" 440BX AGPset Intel" 440GX AGPset Design .1-9 Quadrant Assignment.2-1 Board Description .2-3 Routing Guidelines.2-5 2.3.1 GTL+ Description .2-6 2.3.2 GTL+ Layout Recommendations .2-6 2.3.3 Single Processor Design.2-6 2.3.3.1 Single Processor Network Topology Conditions.2-6 2.3.3.2 Single Processor Recommended Trace Lengths .2-7 2.3.4 Dual Processor Systems.2-8 2.3.4.1 Dual Processor Network Topology Conditions .2-8 2.3.4.2 Dual Processor Recommended Trace Lengths.2-8 2.3.5 Single Processor Systems-Single-End Termination (SET) .2-8 2.3.5.1 Network Topology Conditions .2-8 2.3.5.2 Trace Length Requirements .2-9 2.3.6 Additional Guidelines .2-10 2.3.6.1 Minimizing Crosstalk.2-10 2.3.6.2 Practical Considerations .2-10 2.3.7 Design Methodology .2-11 2.3.8 Performance Requirements .2-12 2.3.9 Topology Definition .2-13 2.3.10 Pre-Layout Simulation (Sensitivity Analysis).2-13 Placement Layout.2-14 Post-Layout Simulation .2-14 2.5.1 Crosstalk Multi-Bit Adjustment Factor .2-15
Motherboard Layout Routing Guidelines .2-1
Intel® 440GX AGPset
Validation .2-15 2.6.1 Flight Time Measurement .2-15 2.6.2 Signal Quality Measurement.2-16 Timing Analysis.2-17 Layout Routing Guidelines .2-19 2.8.1 Connector ("Up Option) Layout Guidelines .2-19 2.8.2 On-board Compliant Device ("Down" Option) Layout Guidelines .2-20 82443GX Memory Subsystem Layout Routing Guidelines.2-22 2.9.1 82443GX Memory Array Considerations.2-22 2.9.1.1 Matching Reference Planes .2-23 2.9.1.2 Adding Additional Decoupling Capacitor .2-23 2.9.1.3 Trace Width Trace Spacing .2-24 2.9.2 Memory Layout Routing Guidelines .2-24 2.9.3 DIMM Routing Guidelines FET].2-30 2.9.4 Routing Guidelines .2-30 2.9.5 Decoupling Guidelines: Intel® 440GX AGPset Platform .2-31 2.9.6 Intel® 440GX AGPset Clock Layout Recommendations.2-32 2.9.6.1 Clock Routing Spacing .2-32 2.9.6.2 System Clock Layout.2-32 2.9.6.3 Clock Layout.2-33 2.9.6.4 SDRAM Clock Layout.2-33 2.9.6.5 Clock Layout .2-34 Overview .3-1 Pull-up Pull-down Resistor Values.3-1 Intel® Pentium® Processor Checklist.3-2 3.3.1 Intel® Pentium® Processor .3-2 3.3.2 Intel® Pentium® Processor Clocks.3-5 3.3.3 Intel® Pentium® Processor Signals.3-5 3.3.4 Uni-Processor (UP) Slot Checklist .3-7 3.3.5 Dual-Processor (DP) Slot Checklist .3-7 3.3.6 Slot Decoupling Capacitors .3-7 3.3.7 Voltage Regulator Module, .3-7 Intel® 440GX AGPset Clocks.3-8 3.4.1 CK100 Clock Synthesizer.3-8 3.4.2 CKBF SDRAM Clock Buffer.3-9 3.4.3 GCKE DCLKWR Connection .3-9 82443GX Host Bridge .3-10 3.5.1 82443GX Interface.3-10 3.5.2 82443GX GTL+ Interface .3-12 3.5.3 82443GX Interface.3-12 3.5.4 82443GX Interface .3-13 Intel® 440GX AGPset Memory Interface .3-14 3.6.1 SDRAM Connections .3-14 3.6.2 DIMM Solution With Switches .3-15 3.6.3 Registered SDRAM .3-15
Design Checklist .3-1
Intel® 440GX AGPset
3.10 3.11 3.12 3.13
3.14 3.15 3.16 3.17 3.18
3.19
3.20 3.21 3.22 3.23
3.24
82371EB (PIIX4E).3-16 3.7.1 PIIX4E Connections.3-16 3.7.2 Routing Guidelines.3-20 3.7.2.1 Cabling.3-20 3.7.2.2 Motherboard .3-20 3.7.3 PIIX4E Power Ground Pins .3-22 Signals .3-22 Signals .3-23 X-Bus Signals.3-23 Interface.3-24 Interface .3-24 Flash Design .3-25 3.13.1 Dual-Footprint Flash Design .3-25 3.13.2 Flash Design Considerations .3-25 System Test Signals .3-28 Power Management Signals .3-28 3.15.1 Power Button Implementation.3-30 Miscellaneous .3-31 82093AA (IOAPIC).3-32 Manageability Devices .3-33 3.18.1 Max1617 Temperature Sensor .3-33 3.18.2 LM79 Microprocessor System Hardware Monitor .3-33 3.18.3 82558B Checklist .3-34 3.18.4 Wake (WOL) Header.3-35 Software/BIOS .3-35 3.19.1 Multi-processor BIOS .3-35 3.19.2 Design Considerations.3-36 Thermals Cooling Solutions .3-36 3.20.1 Design Considerations.3-36 Mechanicals .3-36 3.21.1 Design Considerations.3-37 Electricals.3-37 3.22.1 Design Considerations.3-37 Layout Checklist.3-38 3.23.1 Routing Board Fabrication .3-38 3.23.2 Design Consideration.3-38 Applications Add-in Hardware.3-38 3.24.1 Design Consideration.3-38 Slot Test Tools .4-1 Debug/Simulation Tools.4-1 4.2.1 Logic Analyzer Interface (LAI).4-1 4.2.2 In-Target Probe (ITP).4-1 4.2.3 Functional Model (BFM) .4-2 4.2.4 Buffer Models .4-2 4.2.5 FLOTHERM* Model .4-2
Debug Recommendations .4-1
Intel® 440GX AGPset
Debug Features .4-2 4.3.1 Intel® Pentium® Processor Issue .4-2 4.3.2 Debug Logic Recommendations.4-4 4.3.2.1 Debug Considerations .4-5 4.3.3 Debug Layout .4-5 4.3.3.1 Design Considerations .4-5 4.3.4 Debug Procedures .4-5 Processors .5-1 5.1.1 Voltage Regulator Modules .5-2 5.1.2 Voltage Regulator Control Silicon .5-2 Intel® 440GX AGPset .5-3 5.2.1 Clock Drivers .5-3 5.2.2 Power Management Components .5-3 5.2.3 Switches(4 DIMM/FET Design).5-3 Other Processor Components .5-4 5.3.1 Slot Connector .5-4 5.3.2 Mechanical Support .5-4 5.3.3 Heat sinks .5-4 5.3.4 Heat sink attachment: Rivscrews* associated tools.5-4 5.3.5 Thermal interface materials .5-4
Third-Party Vendor Information .5-1
Intel® 440GX AGPset Platform Reference Design
Intel® 440GX AGPset
Figures
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 Intel® Pentium® Processor Intel® 440GX AGPset System Block Diagram.1-4 Major Signal Sections (82443GX View).2-1 Example Placement Pentium® processor/ Intel® 440GX AGPset Design .2-2 Example Placement Intel® Pentium® processor Intel® 440GX Design.2-3 Four Layer Board Stack-up.2-4 Layer Board Stack-up With Signal Planes Power Planes.2-4 Layer Board Stack-up With Signal Planes Power Planes.2-5 Recommended Topology Single Processor Design .2-6 Solution Space Single Processor Design (Based Results Parametric Sweeps).2-7 Recommended Topology Dual Processor Design.2-8 Topology Single Processor Designs With Single-End Termination (SET).2-9 Solution Space Single Processor Designs With Single-End Termination (SET).2-9 GTL+ Design Process.2-12 Pre-layout simulation process.2-14 Connector Layout Guidelines .2-19 On-board Compliant Device Layout Guidelines .2-21 Switch Example.2-22 Registered SDRAM DIMM Example .2-23 Matching Reference Planes Adding Decoupling Capacitor .2-24 DIMMs (Single Double-Sided) .2-24 Motherboard Model-Data (MDxx), DIMMs.2-25 Motherboard Model-DQMA[0,2:4,6:7], DIMMs .2-26 Motherboard Model-DQM_A[1,5], DIMMs .2-26 Motherboard Model-DQM_A[1,5], DIMMs .2-26 Motherboard Model-DQM_B[1,5], DIMMs .2-27 Motherboard Model-CS_A#/CS_B#, DIMMs .2-27 Motherboard Model-SRAS_A#, DIMMs.2-27 Motherboard Model-Data (MDxx) Lines, DIMMs FET) .2-30 Layout Example .2-31 82443GX Decoupling.2-31 Clock Trace Spacing Guidelines.2-32 Clock Layout.2-34 Pull-up Resistor Example.3-2 GCKE DCLKWR Connections.3-9 Current Solution With Existing Switches .3-15 Series Resistor Placement Primary Connectors.3-21 Dual Footprint Flash Layouts .3-25 nterfacing Intel's Flash with PIIX4E Desktop .3-26 Interfacing Intel's Flash with PIIX4E Desktop .3-28 PWRGOOD PWROK Logic .3-29 Probe Input Circuit.4-3
Intel® 440GX AGPset
Tables
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 3-10 3-11 3-12 3-13 Recommended Trace Lengths Single Processor Design .2-7 Recommended Trace Lengths Dual Processor Designs2.2-8 Trace Length Requirements .2-9 Recommended System Flight Time Specs .2-13 System Timing Requirements Validating Setup/Hold Windows .2-16 Ringback Guidelines Intel® Pentium® Processor Edge Fingers .2-16 Intel® Pentium® Processor Inte®l 440GX AGPset System Timing Equations .2-17 Intel® Pentium® Processor Intel® 440GX AGPset System Timing Terms .2-17 Intel® Pentium® Processor Intel® 440GX AGPset Timing Specifications.2-18 Recommended System Timing Parameters.2-18 Recommended System Flight Time Specs .2-18 Data Associated Strobe .2-19 Source Synchronous Motherboard Recommendations .2-20 Control Signal Line Length Recommendations .2-20 Source Synchronous Motherboard Recommendations .2-21 Control Signal Line Length Recommendations .2-21 lines Reference Planes Routing .2-23 Switch Route Example .2-25 Motherboard Model: SRAS_B#, DIMMs .2-28 Motherboard Model: SCAS_A#, DIMMs .2-28 Motherboard Model: SCAS_B#, DIMMs .2-28 Motherboard Model: WE_A#, DIMMs .2-29 Motherboard Model: WE_B#, DIMMs .2-29 Motherboard Model: MA_A[14:0], DIMMs .2-29 Motherboard Model: MA_B[12,11,9:0]#, MA_B[14,13,10], DIMMs.2-30 Slot Connectivity .3-2 Power Definition .3-4 Processor Frequency Select.3-8 82443GX Connectivity .3-10 Strapping Options .3-13 SDRAM Connectivity .3-14 PIIX4E Connectivity .3-16 Series Termination.3-20 PIIX4E GND.3-22 Non-PIIX4E Signals .3-23 Non-PIIX4E Signals .3-23 Non-PIIX4E IDE.3-24 Flash Recommendations.3-27 Slot Connector .5-1 Retention Mechanism, Retention Mechanism Module Attach Sink Suppor .5-1 GTL+ Slot Terminator Cards .5-1 Voltage Regulator Modules .5-2 Voltage Regulator Control Silicon Vendors .5-2 Clock Driver Vendors.5-3 Power Management Component Vendors.5-3 Switch Vendors .5-3
viii
Intel® 440GX AGPset
Revision History
Date 3/99 Revision -001 Initial Release. Description
Intel® 440GX AGPset
Intel® 440GX AGPset
Introduction
Introduction
Introduction
This document provides design guidelines developing Intel® Pentium® processor Intel® 440GX AGPset based systems. Motherboard memory subsystem design guidelines covered. Special design recommendations concerns presented. Likely design issues have been identified included here checklist format alleviate problems during debug phase. reference board design presented:
Dual Processor (DP), DIMM design
These designs Intel® Pentium® processor Intel® 440GX AGPset consisting 82443GX Host Bridge 82371EB PIIX4E. Note: Intel® Pentium® processor installed Slot connector. Intel® Pentium® processor will also offered Intel boxed processor, intended system integrators build systems from motherboards other components. Some hints early debug problems also included.
About This This document intended hardware design engineers experienced design motherboards memory subsystem. This document organized follows: Chapter Introduction. This chapter provides overview features reference design. Chapter also provides general component overview Intel® Pentium® processor Intel 440GX AGPset. Wired Management Initiative also discussed which Intel® initiative improve manageability desktop, mobile, server systems. This chapter also provides design recommendations which Intel feels will provide flexibility cover broader range products within market segment. Chapter Motherboard Layout Routing Guidelines. This Chapter provides detailed layout, routing, placement guidelines motherboard memory subsystem. Design guidelines each (Host GTL+, PCI, DRAM, AGP) covered. This chapter provides details design methodology, Timing analysis, simulation, design validation. Chapter Design Checklist. This chapter provides design checklist that intended used when reviewing your Intel® 440GX AGPset design. checklist based Intel® 440GX AGPset reference design provided this Design Guide. Items which have been found incorrect previous designs provided tool allow quick debug Intel® Pentium® processor based systems. Chapter Debug Recommendations. This chapter presents debug recommendations that assist development Intel® Pentium® processor, Intel® 440GX AGPset, products utilizing them. This chapter also provides tool information, logic suggestions, technical support options, summary problems which have been found associated with system debug. Chapter Third Party Vendor Information. This chapter includes information regarding various third-party vendors provide products support Intel® 440GX AGPset. Appendix Intel® 440GX AGPset Reference Design Schematics. This appendix provides schematics used single processor dual processor reference designs.
Intel® 440GX AGPset
Introduction
References
Intel® Pentium® Processor Datasheet Intel® 440GX AGPset Datasheet (WWW; order number 290638) Intel 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (WWW; order number 290562) Intel Architecture Software Developer's Manual, Volume Basic Architecture (order number 243190) (order number 243191)
Intel Architecture Software Developer's Manual, Volume Instruction Reference Intel Architecture Software Developer's Manual, Volume System Programming Guide
(order number 243192)
Intel Architecture MMXTechnology Developer's Guide (order number 243006) AP-485 CPUID Application Note (WWW; order number 41618) AP-585 Layout Application Note (WWW; order number 243330) AP-586 Thermal Application Note (WWW; order number 243331) AP-587 Power Application Note (WWW; order number 243332) AP-589 (WWW; order number 243334) AP-524 Intel® Pentium® Processor GTL+ Layout Guidelines (order number 242765) AP-525 Intel® Pentium® Processor Thermal Design Guidelines (order number 242766) Multi-Processor Specification (order number 242016) Processor Fan/Heat Sink Target Specification, Revision later Slot Test User's Guide, Revision later Slot Processor Enabling Technologies Supplier Guide, Revision Local Specification, Revision Universal Serial Specification, Revision
Intel® 440GX AGPset
Introduction
Intel® Pentium® Processor Intel® 440GX AGPset Overview
following list features that Intel® Pentium® processor Intel® 440GX System will provide:
Full Support Intel® Pentium® processors, with system frequencies
Intel® 440GX AGPset
82443GX Host Bridge Controller (GX) 82371EB Accelerator (PIIX4E)
Memory Interface: wide range DRAM support including
64-bit memory data interface plus bits hardware scrubbing SDRAM (Synchronous) DRAM Support 16Mbit, 64Mbit, 128Mbit, 256Mbit DRAM Technologies
Add-in Slots
Specification Compliant
Slot:
Interface Specification Compliant 66/133 MHz, 3.3V device support
Integrated Controller with Ultra DMA/33 support
Mode transfers Master support
Integrated Universal Serial (USB) Controller with ports Integrated System Power Management Support On-board Floppy, Serial, Parallel Ports, Add-in slots APIC device support interrupt support
1.3.1
Intel® Pentium® Processor
Intel® Pentium® processor follow-on Intel® Pentium® processor. This high performance Intel Architecture processor offers features that designed into products following market segments: Desktop Home Market Segment Desktop Corporate Market Segment Workstation Market Segment Server Market Segment applications hardware add-ins from third party vendors being developed that take advantage MMXtechnology incorporated into Intel® Pentium® processor. Please contact your local Intel field sales representative information IHVs ISVs utilizing Intel's MMXtechnology.
Intel® 440GX AGPset
Introduction
Intel introduced Intel® Pentium® processor 350/100 400/100 speeds with cache versions.
1.3.2
Intel® 440GX AGPset
Intel® 440GX AGPset fourth generation chipset based Intel® Pentium®
processor architecture. been designed interface with Intel® Pentium® processor's system MHz. Along with Host-to-PCI bridge interface, 82443GX host bridge controller been optimized with SDRAM memory controller data path. 82443GX also features Accelerated Graphics Port (AGP) interface. 82443GX component includes following functions capabilities: Support single dual Intel® Pentium® processor configurations 64-bit GTL+ based system data Interface 32-bit system address support 64/72-bit main memory interface with optimized support SDRAM 32-bit interface with integrated arbiter interface with data transfer rate Extensive data buffering between interfaces high throughput concurrent operations
Figure 1-1. Intel® Pentium® Processor Intel® 440GX AGPset System Block Diagram
Pentium® Processor Video Camera Host Video Capture w/ECO Main Memory SDRAM Support Graphics Local Memory Encoder
Pentium® Processor
Graphics Device
82443GX Host Bridge
Display
Slots Primary (PCI
Video BIOS
System Mgnt (SM) Ports (Ultra DMA/33) 82371EB (PIIX4E) (PCI-to-ISA Bridge) System BIOS
sys_blk.vsd
APIC
Ports
Slots
Intel® 440GX AGPset
Introduction
Figure shows block diagram typical platform based Intel® 440GX AGPset. 82443GX system interface supports Intel Pentium® processors maximum frequency MHz. physical interface design based GTL+ specification compatible with Intel® 440GX AGPset solution. 82443GX provides optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies. 82443GX designed support PIIX4E bridge. PIIX4E highly integrated multifunctional component that supports following functions capabilities:
1.3.2.1
compliant PCI-to-ISA Bridge with support operations ACPI Desktop Power Management Support Enhanced controller standard interrupt controller timer functions Integrated controller with Ultra DMA/33 support host interface with support ports System Management (SMB) with support DIMM Serial Presence Detect Support external APIC component
System Interface
Intel® Pentium® processor supports second level cache size with ECC. cache control logic provided processor. 82443GX supports maximum address memory address space from processor perspective. 82443GX provides control signals address paths transfers between processors bus, bus, Accelerated Graphics Port main memory. 82443GX supports 4-deep in-order queue (i.e., provides support pipelining outstanding transaction requests system bus). system bus-to-PCI transfers, addresses either translated directly forwarded bus, depending address space being accessed. access configuration space, processor cycle mapped configuration space cycle. access memory space, processor address passed without modification bus. Certain memory address range (later referred document Graphics Aperture) dedicated graphics memory address space. this space portion mapped main DRAM, then address will translated address remapping mechanism request forwarded DRAM subsystem. portion graphics aperture mapped corresponding system cycles that that range forwarded without translation. Other system cycles forwarded defined address map.
1.3.2.2
DRAM Interface
82443GX integrates main memory controller that supports 64/72-bit DRAM interface which operates MHz. integrated DRAM controller features: supports doublesided DIMMs, 256M using 16Mbit technology, using 64Mbit technology, using 128M 256M technology, copies MAxx provided optimized timing, with hardware scrubbing.
1.3.2.3
Accelerated Graphics Port Interface
82443GX supports interface. interface reach maximum theoretical ~532 Mbytes/sec transfer rate.
Intel® 440GX AGPset
Introduction
1.3.2.4
Interface
82443GX interface Revision compliant supports five external masters addition bridge (PIIX4E).
1.3.2.5
System Clocking
82443GX operates system interface MHz, 66/133 MHz. 443GX clocking scheme uses external clock synthesizer which produces reference clocks system interfaces. 82443GX produces single SDRAM clock output which clock buffer support DIMMs.
1.3.3
PCI-to-ISA/IDE Xcelerator (PIIX4E)
PCI-to-ISA/IDE Xcelerator (PIIX4E) multi-function device implementing PCI-toISA bridge function, function, Universal Serial host/hub function, Enhanced Power Management function. PCI-to-ISA bridge, PIIX4E integrates many common functions found ISA-based systems; seven channel Controller, 82C59 Interrupt Controllers, 8254 Timer/Counter, Real Time Clock. addition Compatible transfers, each channel also supports Type transfers. PIIX4E contains full support both PC/PCI Distributed protocols implementing based DMA. Interrupt Controller Edge Level sensitive programmable inputs fully supports external Advanced Programmable Interrupt Controller (APIC) Serial Interrupts. Chip select decoding provided BIOS, Real Time Clock, Keyboard Controller, second external Microcontroller, well Programmable Chip Selects. PIIX4E provides full Plug Play compatibility. PIIX4E configured Subtractive Decode bridge Positive Decode bridge. PIIX4E supports connectors four devices providing interface IDE/EIDE hard disks ROMs. four devices supported Master mode. PIIX4E contains support "Ultra DMA/33" synchronous compatible devices. PIIX4E contains Universal Serial (USB) Host Controller that Universal Host Controller Interface (UHCI) compatible. Host Controller's root programmable ports. PIIX4E supports Enhanced Power Management, including full Clock Control, Device Management devices, Suspend Resume logic with Power Suspend, Suspend Suspend Disk. fully supports Operating System Directed Power Management Advanced Configuration Power Interface (ACPI) specification. PIIX4E integrates both System Management (SMBus) Host Slave interface serial communication with other devices. more information PIIX4E, please refer thePIIX4 datasheet.
1.3.4 Wired Management Initiative
Wired Management (WfM) Intel initiative improve manageability desktop, server systems. goal reduce Total Cost Ownership (TCO) through improved manageability following four technology areas:
Instrumentation Remote Service Boot Remote Wake-Up Power Management
Intel® 440GX AGPset
Introduction
Manageability features each these four technology areas combine form Wired Management Baseline Specification. copy Wired Management Baseline Specification obtained from:
on-line Design Guide available
Future versions specification, which preserve today's investments, will available this site.
1.3.3.1
Instrumentation
component's instrumentation consists code that maintains attributes with up-to-the-minute values adjusts component's operational characteristics based these values. providing instrumentation, platform provides accurate data management applications, those applications make best decisions managing system product. 1.1a Baseline requires that compliant desktop mobile platforms utilize Version 2.00 Management Interface (MI) Component Interface (CI) application programming interfaces host v2.00 Service Provider, defined DMTF. Intel's Service Provider Software Development (SDK) provides Service Provider binaries that support Version 2.00. This available
Intel's LANDesk© Client Manager product includes Service Provider component instrumentation. Information regarding this product found
Baseline Instrumentation specification identifies specific standard groups, including event generation groups, that must instrumented Baseline-compliant platform. This reference design provides support SMBIOS revision specification which along with appropriate component instrumentation will supply some required data specified groups. This reference design also provides additional optional instrumentation hardware support with LM79 Maxim MAX1617 components.
1.3.3.2
Remote Service Boot
Baseline specifies protocols which client requests downloads executable image from server minimum requirements client execution environment when downloaded image executed. Baseline specification includes APIs particular network controller used. code supporting Preboot eXecution Environment (PXE) network controller provided EtherExpress© PRO/100 adapters Option ROM. implementation options available: with Option Wake Header Motherboard implementation. second option, Preboot execution environment network controller code must incorporated into system BIOS. addition, BIOS must provide _SYSID_ _UUID_ data structures. details BIOS requirements obtained from Intel site.
Intel® 440GX AGPset
Introduction
1.3.3.3
Remote Wake-Up
supports reduced power state, must possible bring system fully powered state which management interfaces available. Typically, adapter recognizes special packet signal wake system. This reference design utilizes Wake (WOL) Header provide standby power interface wake signal. physical connection motherboard Cable provided with design kit. Header Recommendations document
system BIOS must enable wake event provide wake status. details BIOS requirements obtained from Intel Corporation site:
1.3.3.4
Power Management
Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, Mechanical Off. Soft usually provided user accessible switch that will send soft request system. PIIX4 provides power button input this purpose implementation details described schematics. second optional "override" switch located less obvious place removal power cord) stops current flow forcing platform into mechanical state without consent. Note that second "override" switch required legal reasons some jurisdictions (for example, some European countries). BIOS support power management requirement either through revision ACPI revision specifications. This reference design's BIOS implementation incorporates both interfaces. PIIX4 provides hardware level register support both ACPI specifications. Intel's site additional information:
1.4.1
Design Recommendations
Voltage Definitions
purposes this document following nominal voltage definitions used: Vcc3.3 VccCORE Vcc2.5 VREF 5.0V 3.3V Voltage dependent five setting 2.5V 1.5V 1.0V
Intel® 440GX AGPset
Introduction
1.4.2
General Design Recommendations
Intel recommends using industry standard programmable Voltage Regulator Module (VRM) installed header onboard programmable voltage regulator designed Intel® Pentium® processors. Systems should capable varying system processor core frequency ratio System Core Frequency Multiplier Configuration table Intel® Pentium® processor datasheet. Intel® Pentium® processor uses following signals configure internal clock multiplier ratio: LINT[0]/INTR, IGNNE#, A20M#, LINT[1]/NMI. Follow recommendations this document ensure that adequate hold times strapping signals. Ensure output strapping logic Vcc2.5 logic level connection Slot connector. This accomplished using open-drain output driver with pullups Vcc2.5. Please prepare additional thermal margin increases 1-5W higher performance otherwise enhanced processor. Motherboard designs targeted system integrators should design Boxed Intel® Pentium® processor electrical, mechanical thermal specifications provided Intel® Pentium® processor datasheet, most notably required power header, fan/heatsink physical clearance motherboard. Motherboard designs should incorporate retention mechanism, retention mechanism attach mount heatsink support mounting holes keep areas Intel® Pentium® processor boxed Intel® Pentium® processor.
1.4.3
Transitioning from Intel® 440BX AGPset Intel® 440GX AGPset Design
82443GX supports using 128M 256M memory technology. design guidelines MAA14 MAB14 same MAA-13 MAB-13 82443BX. Intel® 440GX AGPset supports system SDRAM Memory only. There DIMM support with Intel 440GX AGPset.
Intel® 440GX AGPset
Introduction
1-10
Intel® 440GX AGPset
Motherboard Design
Motherboard Layout Routing Guidelines
Motherboard Layout Routing Guidelines
This chapter describes layout routing recommendations insure robust design. Follow these guidelines closely possible. deviations from guidelines listed here should simulated insure adequate margin still maintained design
Quadrant Assignment
Intel assigned pins 82443GX simplify routing keep board fabrication costs down, permitting motherboard routed 4-layers. Figure shows signal quadrants 82443GX. component placement motherboard should done with this general flow mind. This simplifies routing minimizes number signals which must cross. individual signals within respective groups have also been optimized routed using only layers. Note: Intel® 82443GX AGPset Datasheet contains complete list signals Ball assignments.
Figure 2-1. Major Signal Sections (82443GX View)
Quadrant Corner
GTL+ Quadrant
Quadrant
SDRAM Quadrant
v001
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Figure Figure show proposed component placement single processor both form factor designs. Form Factor: placement layout below recommended single (UP) Intel® Pentium® processor Intel® 440GX AGPset system design. example placement below shows slots, slots, DIMM sockets, connector. form factor design, compliant graphics device either motherboard (device down option), connector option). trace length limitation between critical connections will addressed later this document. figure below reference only trade-off between number slots, number DIMM socket, other motherboard peripherals need evaluated each design. Figure 2-2. Example Placement Pentium® processor/Intel® 440GX AGPset Design
Ports
PCI0
AGP/PCI1 Pentium Slot
Host Interface Interface 82443GX Interface CKBF
SDRAM Interface
CK100
SDRAM DIMMs PIIX4E
v002
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Form Factor: placement layout below recommended single (UP) Intel Pentium® processor Intel® 440GX AGPset system design. example placement below shows Slot connector, DIMM sockets, compliant device down. form factor design, compliant graphics device readily integrated motherboard (device down option). trace length limitation between critical connections will addressed later this document. Figure reference only trade-off between number DIMM sockets, other motherboard peripherals need evaluated each design. Figure 2-3. Example Placement Intel® Pentium® processor Intel® 440GX Design
SDRAM DIMMs CK100
SDRAM Interface CKBF 82443GX
Interface Interface
Host Interface
Pentium Slot
PIIX4E
PCI0/ISA Riser
Board Description
single processor Intel® 440GX AGPset motherboard design, layer stack-up arrangement recommended. stack board shown Figure 2-4. impedance signal layers between ohms. Lower trace impedance will reduce signal edge rates, over undershoot, have less cross-talk than higher trace impedance. Higher trace impedance will increase edge rates slightly decrease signal flight times.
Intel® 440GX AGPset
Ports
v003
Motherboard Layout Routing Guidelines
Figure 2-4. Four Layer Board Stack-up
ohms
Primary Signal Layer (1/2 cu.) mils mils mils
PREPREG CORE PREPREG
Ground Plane cu.) Power Plane Secondary Signal Layer (1/2
ohms
Total board thickness 62.6
Note:
bottom routing layers specify However, time board plated, traces will about Check with your fabrication vendor exact value insure that signal simulation accounts this value. thicker core help reduce board warpage issues. dual processor Intel® 440GX AGPset design, layer stack-up recommended. examples shown below. Figure signal plane layers power plane layers. Figure shows signal plane layers power plane layers. second option makes easier accommodate power planes required Intel® 440GX AGPset design. layer stack-up used, then recommended route most GTL+ signals inner layers. primary secondary signal layer used GTL+ signals where needed. Routes inner layers should orthogonal reduce crosstalk between layers.
Note:
Figure 2-5. Layer Board Stack-up With Signal Planes Power Planes
Primary Signal Layer (1/2 cu.) mils mils
ohms
ohms
PREPREG CORE PREPREG CORE PREPREG
Ground Plane cu.) Inner Layer cu.) Inner Layer Power Plane Secondary Signal Layer (1/2
mils mils mils
ohms
Total board thickness 62.4
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Figure 2-6. Layer Board Stack-up With Signal Planes Power Planes
ohms
Primary Signal Layer (1/2 cu.) mils mils
PREPREG CORE PREPREG CORE PREPREG
Ground Plane cu.) Inner Layer cu.) Power Plane Power Plane Secondary Signal Layer (1/2
ohms
mils mils mils
ohms
Total board thickness 62.4
Additional guidelines board buildup, placement layout include:
4-layer single processor design, double ended termination recommended GTL+
signals. termination resistor present processor substrate, other termination resistor needed motherboard. possible single-ended termination, trace lengths tightly controlled 1.5" minimum 4.0" maximum.
6-layer dual processor design, termination required motherboard GTL+
signals, each GTL+ terminated each processor. single Slot populated design, second Slot must populated with termination card.
termination resistors GTL+ should ohms. board impedance should between ohms ohms ±20%) FR-4 material should used board fabrication. ground plane should split ground plane layer. signal must routed short distance power plane, then should routed plane, ground plane.
Keep vias decoupling capacitors close capacitor pads possible.
Routing Guidelines
This section lists guidelines followed when routing signal traces board design. order which signals routed first last will vary from designer designer. Some designers prefer routing clock signals first, while others prefer routing high speed signals first. Either order used, long guidelines listed here followed. guidelines listed here followed, very important that your design simulated, especially GTL+ signals. Even when guidelines followed, still good idea simulate many signals possible proper signal integrity, flight time cross talk.
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.3.1
GTL+ Description
GTL+ electrical technology used Intel® Pentium® processor Intel® Pentium® processor system bus. GTL+ output swing, incident wave switching, opendrain with external pull-up resistors that provide both high logic level termination bus. complete GTL+ specification contained Pentium processor databook. specification defines:
Termination voltage, Termination resistance, Maximum output voltage, VOL, output current, Output driver edge rate when driving GTL+ reference load Receiver high voltage level, Receiver reference voltage, VREF, function termination voltage Receiver ringback tolerance
Refer GTL+ layout Guidelines Pentium® Processor Intel® 440GX AGPset more details.
2.3.2
GTL+ Layout Recommendations
This section contains layout recommendations GTL+ signals. layout recommendations derived from pre-layout simulations that Intel using methodology described Section 2.3.7, "Design Methodology" page 2-11. Results from pre-layout simulations included this section. Intel® Pentium® Processor Specification Update workarounds errata that present particular stepping processor used.
2.3.3
2.3.3.1
Single Processor Design
Single Processor Network Topology Conditions
recommended topology single processor systems shown Figure 2-7. addition termination resistor Pentium processor substrate, termination resistor placed system board. recommended value termination resistor
Figure 2-7. Recommended Topology Single Processor Design Slot Intel® 440GX AGPset
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.3.3.2
Single Processor Recommended Trace Lengths
Single processor trace length recommendations summarized Table 2-1. recommended lengths derived from parametric sweeps Monte Carlo analysis described following section.
Table 2-1. Recommended Trace Lengths Single Processor Design
Trace Minimum Length 1.50" 0.00" 0.00" Maximum Length 6.75" 1.50" 2.50"
NOTE: Refer Intel® Pentium® Processor Specification Update (order number 243337); Specifically, erratum #42: workaround L1=4.5".
Intel strongly recommends running analog simulations using available buffer models together with layout information extracted from your specific design. Simulation will confirm that design adheres guidelines. Figure 2-8. Solution Space Single Processor Design (Based Results Parametric Sweeps)
[in] PASS FAIL [in]
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.3.4
2.3.4.1
Dual Processor Systems
Dual Processor Network Topology Conditions
Figure 2-9. Recommended Topology Dual Processor Design Intel® 440GX AGPset Slot
Slot
Maximum Length 1.50" 4.00" 1.00", greater than 5.00"
2.3.4.2
Dual Processor Recommended Trace Lengths
recommended trace lengths dual processor designs summarized Table 2-2. Intel's simulations have shown that desirable control amount imbalance network meet ringback specifications Intel® Pentium® processor when Intel® 440GX AGPset drives. This control reflected recommendations Table 2-2.
Table 2-2. Recommended Trace Lengths Dual Processor Designs2
Trace
Minimum Length 0.50" 1.50" 1.00", L4+L5 must least 4.00"
NOTES: interchangeable possible find working solutions outside recommendations Table 2-2, solution space plot show. Intel strongly recommends that traces that fall outside recommended lengths simulated ensure they meeting timing signal quality specs.
2.3.5
2.3.5.1
Single Processor Systems-Single-End Termination (SET)
Network Topology Conditions
Removal termination resistors from system board reduce system cost, expense increased ringing reduced solution space. Intel simulated this topology, known single termination (SET), found that work. However, topology some limitations which discussed below.
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
topology, only termination Intel® Pentium® processor substrate. There termination present other network. lack termination, exhibits much more ringback than dual terminated topology. Extra care required simulations make sure that ringback specs under worst case signal quality conditions. addition, since there only pull-up resistor rising edge response substantially degraded when using slow corner buffers. This effect manifests itself degraded flight time, which results reduced maximum trace length that meets timing requirements. This loss design flexibility must carefully weighed against cost savings from removing resistors. Figure 2-10. Topology Single Processor Designs With Single-End Termination (SET) Intel® 440GX AGPset
Slot
2.3.5.2
Trace Length Requirements
Intel performed sensitivity analysis topology. required trace lengths operation with topology based sensitivity analysis results, listed Table 2-3. Intel's simulations were performed assuming four layer system board, that traces used microstrip propagation velocity range. slower propagation stripline transmission line structures included recommendations Table 2-3.
Table 2-3. Trace Length Requirements
Trace Minimum Length 1.50" Maximum Length 4.00"
Figure 2-11. Solution Space Single Processor Designs With Single-End Termination (SET)
SUBSTRATE TRACE LENGTH [IN] [in]
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.3.6
2.3.6.1
Additional Guidelines
Minimizing Crosstalk
following general rules will minimize impact crosstalk high speed GTL+ design:
Maximize space between traces. Maintain minimum 0.010" between traces wherever
possible. necessary tighter spacings when routing between component pins.
Avoid parallelism between signals adjacent layers. Since GTL+ slow signal swing technology, important isolate GTL+ signals from
other signals least 0.025". This will avoid coupling from signals that have larger voltage swings, such PCI.
Select board stack-up that minimizes coupling between adjacent signals. Route GTL+ address, data control signals separate groups minimize crosstalk
between groups. Pentium processor uses split transaction bus. given clock cycle, address lines corresponding control lines could driven different agent than data lines their corresponding control lines.
2.3.6.2
Practical Considerations Distribute with wide trace. 0.050" minimum trace recommended minimize
losses. Route trace components system bus. sure include decoupling capacitors. Guidelines distribution decoupling contained Intel® Pentium® Processor Power Distribution Guidelines.
Place resistor divider pairs VREF generation Intel® 440GX AGPset component.
VREF generation needed processor(s). VREF generated locally processor. sure include decoupling capacitors. Guidelines VREF distribution decoupling contained Intel® Pentium® Processor Power Distribution Guidelines.
There GTL+ signals that driven more than agent simultaneously. These
signals require extra attention during layout validation portions design. When signal asserted (driven low) agents same clock edge, falling wave fronts will meet some point bus. This create large undershoot, followed ringback which violate ringback specifications. This "wired-OR" situation should simulated following signals: AERR#, BERR#, BINIT#, BNR#, HIT#, HITM#.
Lossless simulations overstate amount ringing GTL+ signals. Lossy simulations
help make your results less pessimistic ringing problem. Intel found resistivity copper printed circuit board signal layers higher than value 0.662 -mil2/in that been published annealed copper. Intel recommends using value -mil2/in lossy simulations.
Higher values tend increase amount ringback rising edge, while smaller
values tend increase amount ringback falling edge. necessary budget variation your simulations comprehend expected manufacturing variation. least slower. Therefore, only necessary ensure that minimum flight time when network driven fast buffer models. least faster. only necessary ensure that maximum flight time when network driven slow buffer models, long ringback problems exist.
Buffer models fast corner correspond minimum Tco. Slow corner buffers will
Buffer models slow corner correspond maximum Tco. Fast corner buffers will
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Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.3.7
Design Methodology
Intel recommends using following design methodology when designing systems based Intel® Pentium® processors Intel® 440GX AGPset. methodology evolved from Intel's experience developing validating high speed GTL+ designs Intel® Pentium® Intel® Pentium® processors. methodology provides step-by-step process which summarized Figure 2-12. process begins with initial timing analysis topology definition. Timing topology recommendations included this section. heart methodology structured around extensive simulations analysis prior board layout. This represents significant departure from traditional design methods. pre-layout simulations provide detailed picture working "solution space" design. basing board layout guidelines solution space, need iterate between layout post-layout simulation minimized. methodology includes specific recommendations analytical techniques simulation conditions. Following layout, simulation with extracted design database used verify that design meets flight time signal quality requirements prior building hardware. Finally, validation verifies that system meets timing signal quality requirements with actual hardware.
Intel® 440GX AGPset
2-11
Motherboard Layout Routing Guidelines
Figure 2-12. GTL+ Design Process Establish System Performance Requirements (Timing Analysis)
Define Topologies
Perform Pre-Layout Simulations (Sensitivity Analysis)
Define Routing Rules
Place Route Board
Perform Post-Layout Simulations (Verification)
Meet Requirements?
Validate Design
2.3.8
Performance Requirements
Prior performing interconnect simulations, establish minimum maximum flight time requirements. Setup hold requirements determine flight time bounds host bus. system contains multiple paths which must considered:
Intel® Pentium® processor driving AGPset component AGPset component driving Intel® Pentium® processor Intel® Pentium® processor driving Intel® Pentium® processor
(dual processor systems only)
2-12
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Section 2.7, "Timing Analysis" page 2-17 describes timing analysis host more detail. Table provides recommended flight time specifications single dual Intel® Pentium® processor systems. Flight times measured Intel® Pentium® processor edge fingers. Pentium® Processor Developer's Manual (order number 243502), Chapter "GTL+ Interface Specifications", information GTL+ timing measurements signal quality specifications. Table 2-4. Recommended System Flight Time Specs
Driver Intel Pentium processor Intel 440GX AGPset Intel Pentium processor
Receiver AGPset Intel Pentium processor Intel Pentium processor
Tflight,min [ns] 0.36 0.37 1.23
Tflight,max [ns] 2.13 1.76 2.39
2.3.9
Topology Definition
GTL+ sensitive transmission line stubs, which result ringing rising edge caused high impedance output buffer high state. GTL+ signals should connected daisy chain, keeping transmission line stubs Intel® 440GX AGPset under inches. Intel® Pentium® processors should placed properly terminate GTL+ signals. single Intel® Pentium® processor design, Intel recommends that termination resistors placed other (AGPset) bus. This provides most robust signal integrity characteristics maximizes range trace lengths that will meet flight time requirements. recommended termination resistor value dual Intel® Pentium® processor based designs, termination card must placed unused slot when only processor populated. This necessary ensure that signal integrity requirements met. Refer Slot Termination Card Design Guidelines details.
2.3.10
Pre-Layout Simulation (Sensitivity Analysis)
After initial timing analysis been completed, simulations should performed determine bounds system layout. layout recommendations Section "Debug Recommendations" page based results pre-layout simulations conducted Intel. GTL+ interconnect simulations using transmission line models recommended determine signal quality flight times proposed layouts. Recommended parameter values obtained your supplier's specific capabilities known. corner values should comprehend full range manufacturing variation. Intel® Pentium® processor models include buffer models, core package parasitics, substrate trace length, impedance velocity. Intel® 440GX AGPset models include buffers package traces. Termination resistors should controlled within
2.3.11 Simulation Methodology
Pre-layout simulation allows system "solution space" that meets flight time signal quality requirements understood before routing undertaken. Determining layout restrictions prior physical design removes iteration cycles between layout post layout simulation, shown Figure 2-13.
Intel® 440GX AGPset
2-13
Motherboard Layout Routing Guidelines
methodology that Intel recommends known "Sensitivity Analysis". sensitivity analysis, interconnect parameters varied understand they affect system timing signal integrity. Sensitivity analysis further broken into types analysis, parametric sweeps Monte Carlo analysis, which described below. Figure 2-13. Pre-layout simulation process
Interconnect Simulations (Transmission-Line)
1.75v 1.75v 1.75v 1.75v
1.25v
1.25v
1.25v
1.25v
0.75v
0.75v
0.75v
0.75v
0.25v 0.00ns 20.00ns 40.00ns OTHERS 82440FXPIN KLAMATH2PIN KLAMATH2 0.00ns +0.000v xdelta 0.000ns KLAMATH1PIN NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH1 TRACKING: KLAMATH1 KLAMATH1
0.25v 0.00ns 20.00ns 40.00ns OTHERS 82440FXPIN KLAMATH2PIN KLAMATH2 0.00ns +0.000v xdelta 0.000ns KLAMATH1PIN NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH2 TRACKING: KLAMATH1 KLAMATH1
0.25v 0.00ns 20.00ns 40.00ns OTHERS 82440FXPIN KLAMATH2PIN KLAMATH2 0.00ns +0.000v xdelta 0.000ns KLAMATH1PIN NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH1 TRACKING: KLAMATH1 KLAMATH1
0.25v 0.00ns 20.00ns 40.00ns OTHERS 82440FXPIN KLAMATH2PIN KLAMATH2 0.00ns +0.000v xdelta 0.000ns KLAMATH1PIN NET: SLOWDPNM_LS_12_6, DRIVER: KLAMATH2 TRACKING: KLAMATH1 KLAMATH1
Sensitivity Analyses
Performance function Length (flight time, signal quality, etc.)
IGHT
silicon slow board)
Monte Carlo (pass/fail function length)
(fast silic
inch inche inch inche 1.75 3.25 4.75 6.25 7.75 9.25 10.75 11.5 1.75 3.25 4.75 6.25 7.75 9.25 10.75 11.5
ches inches ches inches
PCard 82440FX Separation Distance (in)
ratio
atio ista
rati stan
Solution Space
PCard#1 82440FX Separation Distance (in)
1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 5.75
Placement Layout
Once pre-layout simulation completed, route board using solution space resulting from sensitivity analysis.
Post-Layout Simulation
Following layout, extract traces simulations verify that layout meets timing noise requirements. small amount trace "tuning" required, experience Intel shown that sensitivity analysis dramatically reduces amount tuning required. post layout simulations should take into account expected variation interconnect parameters. timing simulations, VREF both Intel® Pentium® processor Intel® 440GX AGPset components. Flight times measured from Pentium processor edge fingers other system components standard flight time method.
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Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.5.1
Crosstalk Multi-Bit Adjustment Factor
Coupled lines should included post-layout simulations. flight times listed Table apply single simulations only. They include allowance crosstalk. Crosstalk effects accounted for, part multi-bit timing adjustment factor, Tadj, that defined Table 2-8. recommended timing budget includes adjustment factor. caution applying Tadj coupled simulations. This adjustment factor encompasses other effects besides board coupling, such processor package crosstalk, ground return inductances. general, additional delay introduced coupled simulations should less than
2.6.1
Validation
Flight Time Measurement
timings Intel® Pentium® processor specified processor edge fingers. systems, processor edges fingers readily accessible. most cases, measurements must taken system board solder connection Slot connector. effectively correlate delay measurements values Pentium processor edge fingers, Slot connector delay must incorporated. Flight time defined difference between delay signal input receiving agent (measured VREF), delay output driving agent when driving GTL+ reference load. However, driver delay into reference load readily available, thus making flight time measurement unfeasible. There three options dealing with this limitation:
first option subtract delay driver system environment Slot
connection board) from delay receiver. Such measurement will introduce uncertainty into measurement differences between driver delay reference system loads. simulations indicate that your design margin flight time specifications, this approach will allow verify that design robust.
second option subtract simulated reference delay from delay receiver.
limitation this option that there more uncertainty between actual driver delay results from simulation. This approach less accurate that first option.
final option simply measured delay from driver receiver (Tmeasured)
validate that system meets setup hold requirements. this approach, driver delay flight time must within "valid window" setup hold. timing requirements satisfying valid window shown below.
Intel® 440GX AGPset
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Motherboard Layout Routing Guidelines
Table 2-5. System Timing Requirements Validating Setup/Hold Windows
Driver Pentium® processor Receiver AGPset Equation
Tmeasured Thold Tskew ,CLK Tskew ,PCB Tclk ,max
Tmeasured Tcycle Tskew,CLK Tskew, Tjit Tadj Tclk ,min
AGPset
Pentium® processor
Tmeasured Thold Tskew ,CLK Tskew ,PCB Tclk ,min
Tmeasured Tcycle Tskew ,CLK Tskew Tjit Tadj Tclk ,max
Pentium® processor
Pentium® processor
Tmeasured Thold Tskew ,CLK Tskew
Tmeasured Tcycle Tskew ,CLK Tskew, Tjit Tadj
2.6.2
Signal Quality Measurement
Signal integrity specified processor core, which accessible. Intel found that there substantial miscorrelation between ringback edge finger versus core. miscorrelation creates instances where signal fails satisfy ringback requirements edge finger, passes ringback specification core. this reason, signal integrity specified core. Ringback guidelines supplied edge finger, shown Table 2-6. measurement edge finger that violates guidelines should simulated verify that meets specification core.
Table 2-6. Ringback Guidelines Intel® Pentium® Processor Edge Fingers
Edge Rising Falling Guideline Processor Edge Finger 1.29V 0.71V Spec Processor Core 1.12V1 0.88V
NOTE: Ringback specifications follow methodology described Intel® Pentium® Processor MHz, MHz, Datasheet.
2-16
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Timing Analysis
determine available flight time window perform initial timing analysis. Analysis setup hold conditions will determine minimum maximum flight time bounds host bus. following equations establish system flight time limits.
Table 2-7. Intel® Pentium® Processor Inte®l 440GX AGPset System Timing Equations
Driver Pentium® processor Receiver AGPset Equation
Tflight ,min Thold Tco,min Tskew ,CLK Tskew Tclk ,max
Tflight ,max Tcycle ,max Tskew ,CLK Tskew ,PCB Tjit Tadj Tclk ,min
AGPset
Pentium® processor
Tflight ,min Thold Tco,min Tskew ,CLK Tskew ,PCB Tclk ,min
Tflight ,max Tcycle Tco,max Tskew ,CLK Tskew ,PCB Tjit Tadj Tclk ,max
Pentium® processor
Pentium® processor
Tflight ,min Thold Tco,min Tskew ,CLK Tskew ,PCB
Tflight ,max Tcycle ,max Tskew,CLK Tskew Tjit Tadj
terms used equations described Table 2-8. Table 2-8. Intel® Pentium® Processor Intel® 440GX AGPset System Timing Terms
Term Tcycle Tflight,min Tflight,max Tco,max Tco,min Tskew,CLK Tskew,PCB Tjit Tadj Description System cycle time. Defined reciprocal frequency Minimum system flight time. Flight time defined Section "Debug Recommendations" page 4-1. Maximum system flight time. Flight time defined Section "Debug Recommendations" page 4-1. Maximum driver delay from input clock output data. Minimum driver delay from input clock output data. Minimum setup time. Defined time which input data must valid prior input clock. Minimum hold time. Defined time which input data must remain valid after input clock. Clock generator skew. Defined maximum delay variation between output clock signals from system clock generator. skew. Defined maximum delay variation between clock signals system board variation Intel® 440GX AGPset loading variation. Clock jitter. Defined maximum edge edge variation given clock signal. Multi-bit timing adjustment factor. This term accounts additional delay that occurs network when multiple data bits switch same cycle. adjustment factor includes such mechanisms package crosstalk, high inductance current return paths, simultaneous switching noise. Minimum clock substrate delay. Defined minimum adjustment factor that accounts delay clock trace Pentium processor substrate. Minimum clock substrate delay. Defined maximum adjustment factor that accounts delay clock trace Pentium processor substrate.
Tclk,min Tclk,max
Intel® 440GX AGPset
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Motherboard Layout Routing Guidelines
Notice that timing equations include extra term account delay routing BCLK trace processor substrate from processor edge fingers processor core. Adding BCLK adjustment timing calculations between processor chipset guarantees host clock synchronization between AGPset processor core. minimum maximum values this term contained Table 2-9. Component timings Intel® Pentium® processor Intel® 440GX AGPset contained Table 2-10. timing specifications contained Intel® Pentium® processor Intel® 440GX AGPset Datasheets. These timing reference only. Table 2-9. Intel® Pentium® Processor Intel® 440GX AGPset Timing Specifications
Timing Term Tco,max [ns] Tco,min [ns] [ns] [ns] Tclk,min [ns] Tclk,max [ns] Intel® Pentium® Processor 4.66 0.71 1.97 1.61 0.77 0.84 Intel® 440GX AGPset 4.45 0.80 3.00 -0.10 applicable applicable
Recommended values system timings contained Table 2-10. Skew jitter values clock generator device come from CK97 clock driver specification. skew spec based results extensive simulations Intel. Tadj value based Intel's experience with systems that Intel® Pentium® processor Intel® Pentium® processor. Table 2-10. Recommended System Timing Parameters
Timing Term Tskew,CLK [ns] Tskew,PCB [ns] Tjit [ns] Tadj [ns] Value 0.18 0.15 0.25 0.40
flight time requirements that result from using component timing specifications recommended system timings summarized Table 2-11. component values should verified against current specifications before proceeding with analysis. Table 2-11. Recommended System Flight Time Specs
Driver Intel® Pentium® processor AGPset Intel® Pentium® processor AGPset Intel® Pentium® processor Intel® Pentium® processor Receiver Tflight,min 0.36 0.37 1.23 Tflight,max 2.13 1.76 2.39
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Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Layout Routing Guidelines
definition Interface functionality (protocols, rules signaling mechanisms, well platform level aspects functionality), refer latest Interface Specification Platform Design Guide. These documents focus only specific Intel® 440GX AGPset platform recommendations interface. this document term "data" refers AD[31:0], C/BE[3:0]# SAB[7:0]. term "strobe" refers AD_STB[1:0] SB_STB. When term data used, referring three groups data seen Table 2-12. When term strobe used referring three strobes relates data associated group.
Table 2-12. Data Associated Strobe
Data AD[15:0] C/BE[1:0]# AD[31:16] C/BE[3:2]# SBA[7:0] Associated Strobe AD_STB0 AD_STB1 SB_STB
2.8.1
Connector ("Up Option) Layout Guidelines
maximum line length dependent routing rules used motherboard. These routing rules were created give freedom designs making trade-offs between signal coupling (trace spacing) line lengths. These routing rules divided trace spacing. spacing, distance between traces (air gap) same -width trace. spacing, distance between traces twice width trace.
Figure 2-14. Connector Layout Guidelines Always Strobe Routing Compliant Graphics Device Signal Bundle 1.0" 4.5" (Data) Routing 4.5" 9.5" (Data) Routing Connector trace lengths that between inch inches, trace spacing recommended data lines. strobe requires trace spacing. This designs that require less than inches between connector target. Longer lines have more crosstalk. Therefore, maintain skew, longer line lengths require greater amount spacing between traces. line lengths greater than 4.5" less than 9.5", routing recommended data lines well strobes. designs, line length mismatch must less than 0.5" strobe must longest signal group.
82443GX
Intel® 440GX AGPset
2-19
Motherboard Layout Routing Guidelines
always best reduce line length mismatch wherever possible insure added margin. also best separate traces much possible reduce amount trace trace coupling. Table 2-13. Source Synchronous Motherboard Recommendations
Width:Space (Data) (Strobe) Trace Data Strobe Data Strobe Line Length line length line length Line Length Matching -0.5 strobe longest trace -0.5 strobe longest trace
clock lines motherboard couple with other traces. recommended that clock spacing (air gap) least times trace width other traces. also strongly recommended that clock spacing least four times trace width strobes. clock lines motherboard need simulated determine their proper line length. motherboard needs designed type clock driver that being used motherboard trace topology. These clocks need meet loading receiving device well add-in trace length. Additionally, control signals less than inches routed 1:1, while control signals greater than inches should routed 1:2. Table 2-14. Control Signal Line Length Recommendations
Width:Space (1:4 Strobe) Board Motherboard Motherboard Motherboard Trace Control signals Control signals Clock Line Length line length line length 10.0 Pull-up Stub Length (Strobes 0.1in) (Strobes 0.1in)
Some control signals require pull-up resistors installed motherboard. signals must pulled VCC3.3 using 8.2K pull-up resistors (refer Section 3.5.1, "82443GX Interface" page 3-10). Pull-up resistors should discrete resistors, resistor packs will need longer stub lengths break timing. stub these pull-up resistors needs controlled. maximum stub length strobe trace inch. maximum stub trace length other traces inch.
2.8.2
On-board Compliant Device ("Down" Option) Layout Guidelines
Routing guidelines device `down' option very similar those when device `up'. Some modifications need made when placing graphics device motherboard, various trace spacing.
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Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Figure 2-15. On-board Compliant Device Layout Guidelines
Always Strobe Routing Compliant Graphics Device 1.0" 4.5" (Data) Routing (Data) Routing 82443GX
trace lengths that between inch inches, trace spacing recommended data lines. strobe requires trace spacing. This designs that require less than inches between device target. Longer lines have more crosstalk. Therefore, maintain skew, longer line lengths require greater amount spacing between traces. line lengths greater than 4.5" less than 12.0", routing recommended data lines strobes. designs, line length mismatch must less than 0.5" strobe must longest signal group. cases best reduce line length mismatch wherever possible insure added margin. also best separate traces much possible reduce amount trace trace coupling. Table 2-15. Source Synchronous Motherboard Recommendations
Width:Space 1:1(Data) (Strobe) Trace Data Strobe Data Strobe Line Length line length line length 12.0 Line Length Matching -0.5 strobe longest trace -0.5 strobe longest trace
clock lines motherboard couple with other traces. recommended that clock spacing (air gap) least times trace width other traces. also strongly recommended that clock spacing least four times trace width strobes. clock lines motherboard need simulated determine their proper line length. motherboard needs designed type clock driver that being used motherboard trace topology. These clocks need meet loading receiving device well add-in trace length. Additionally, control signals less than inches routed 1:1, while control signals greater than inches should routed 1:2. Table 2-16. Control Signal Line Length Recommendations
Width:Space (1:4 Strobe) Board Motherboard Motherboard Motherboard Trace Control signals Control signals Clock Line Length line length line length 12.5 Pull-up Stub Length (Strobes 0.1in) (Strobes 0.1in)
Intel® 440GX AGPset
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Motherboard Layout Routing Guidelines
Some control signals require pull-up resistors installed motherboard. signals must pulled VCC3.3 using 8.2K pull-up resistors (refer Section 3.5.1, "82443GX Interface" page 3-10). Pull-up resistors should discrete resistors, resistor packs will need longer stub lengths break timing. stub these pull-up resistors needs controlled. maximum stub length strobe trace inch. maximum stub trace length other traces inch. Note: Under certain layouts, crosstalk ground bounce observed AD_STB signals interface. Although Intel observed system failures this issue, have improved noise margin enhancing buffers 82443GX. designs, additional margin obtained following these layout guidelines.
2.9.1
82443GX Memory Subsystem Layout Routing Guidelines
82443GX Memory Array Considerations
Designing reliable high performance memory system will challenging. Careful consideration motherboard routing stackup topologies, DIMM topology, impedance, trace lengths must taken into account. 82443GX when configured with double-sided DIMMs have heavy loading. offset heavy loading lines, switch recommended reduce loading memory driving 82443GX, vice versa. alternative NO-FET solution also provided this solution more strict routing restrictions.
Figure 2-16. Switch Example 82443GX MECCs DIMM[1:0]
DIMM[3:2]
build large capacity DIMMs (i.e., using present technology, SDRAM devices must used. loading control lines (MA/GXx, CS#, DQM, etc.) twice loading device. DIMM which "registers" these control lines must produced meet timings (note that must added registered DIMM additional jitter must factored into overall timing analysis). Electrical, thermal layout topologies these registered DIMMs founded following address:
2-22
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Figure 2-17. Registered SDRAM DIMM Example
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
Register
Register
Data
Control
Clock
There also "population" rules which need observed. properly adjust memory timings operation, asked user populate motherboard starting with DIMM located furthest from 82443GX.
2.9.1.1
Matching Reference Planes
Providing good return path currents induced power ground planes critical reducing signal noise. best provide inductance return path "match" motherboard reference planes given signal. example, routed next ground plane. "match" reference planes, should routed Motherboard such that closest motherboard ground plane. Routing memory signals this manner will provide best possible path return currents.
Table 2-17. lines Reference Planes Routing
Memory Data Line MD0,MD1,MD2,MD3, MD4, MD7, MD11, MD14, MD15, MD16, MD17, MD19, MD20, MD21, MD22, MD23, MD27, MD28, MD29, MD31, MD33, MD36, MD37, MD38, MD40, MD41, MD42, MD43, MD45, MD48, MD49, MD52, MD53,MD55, MD56, MD61, MD62, MD63, MECC[6:0] MD5, MD6, MD8, MD9, MD10, MD12, MD13, MD18, MD24, MD25, MD26, MD30, MD32, MD34, MD35, MD39, MD46, MD47, MD50, MD51, MD54, MD59, MD60, MECC7 3.3v layer 3.3v power plane layer plane 82443GX Reference Layer Motherboard Reference Plane
2.9.1.2
Adding Additional Decoupling Capacitor
Another provide inductance path return currents provide additional decoupling capacitors next signal vias. possible route lines single layer. result, some lines will transition between signal layers through vias. return currents associated with these signals also require inductance path between ground. This inductance path provided decoupling capacitors between ground. These decoupling capacitors should placed close possible signal vias.
Intel® 440GX AGPset
SDRAM
2-23
Motherboard Layout Routing Guidelines
Figure 2-18. Matching Reference Planes Adding Decoupling Capacitor
2.9.1.3
Trace Width Trace Spacing
minimize crosstalk, trace width trace spacing routing (e.g., mils mils mils mils) should used memory interface signals.
2.9.2
Memory Layout Routing Guidelines
Figure 2-19. DIMMs (Single Double-Sided)
CS_A[7:6]#,CS_B[7:6]# CS_A[5:4]#,CS_B[5:4]# CS_A[3:2]#,CS_B[3:2]# CS_A[1:0]#,CS_B[1:0]#
Group
Group
SRAS_A# SRAS_B# SCAS_A# SCAS_B# DQM_A[1,5] DQM_A[7,6,4:2,0] DQM_B[1,5] WE_A# WE_B#
MAA[14:0] MAB[12, 9:0]#, MAB[14, 13,10] MD[63:0]
16212
FENA MECC[7:0]
16212
DIMM_CLK[3:0] DIMM_CLK[7:4] DIMM_CLK[11:8] DIMM_CLK[15:12] SMB_CLK SMB_DATA
Layout Guidelines: signals require careful routing both trace lengths
2-24
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
Table 2-18. Switch Route Example
1.1" 2.0" 0.6" 0.3" 1.0" 0.7" 0.6"
82443GX
v004
Figure 2-20. Motherboard Model-Data (MDxx), DIMMs 0.7" 2.4" 82443GX
Switch 16212
0.4" 0.6"
0.3" 1.0"
1.1" 2.0"
0.4" 0.6"
DIMM Module
DIMM Module
DIMM Module
Intel® 440GX AGPset
DIMM Module
2-25
Motherboard Layout Routing Guidelines
Figure 2-21. Motherboard Model-DQMA[0,2:4,6:7], DIMMs 1.0" 3.25" 82443GX 0.4" 0.6" 0.4" 0.6" 0.4" 0.6"
DIMM Module
DIMM Module
DIMM Module
Figure 2-22. Motherboard Model-DQM_A[1,5], DIMMs 1.0" 3.25" 82443GX 0.4" 0.6"
DIMM Module
Figure 2-23. Motherboard Model-DQM_A[1,5], DIMMs 1.0" 3.25" 82443GX 0.4" 0.6"
DIMM Module
2-26
Intel® 440GX AGPset
DIMM Module
DIMM Module
DIMM Module
Motherboard Layout Routing Guidelines
Figure 2-24. Motherboard Model-DQM_B[1,5], DIMMs 1.0" 3.25" 82443GX 0.4" 0.6"
DIMM Module
Figure 2-25. Motherboard Model-CS_A#/CS_B#, DIMMs 1.0" 4.0" 82443GX DIMM Module
Figure 2-26. Motherboard Model-SRAS_A#, DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
Intel® 440GX AGPset
DIMM Module
DIMM Module
2-27
Motherboard Layout Routing Guidelines
Table 2-19. Motherboard Model: SRAS_B#, DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
Table 2-20. Motherboard Model: SCAS_A#, DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
Table 2-21. Motherboard Model: SCAS_B#, DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
2-28
Intel® 440GX AGPset
DIMM Module
DIMM Module
DIMM Module
Motherboard Layout Routing Guidelines
Table 2-22. Motherboard Model: WE_A#, DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
Table 2-23. Motherboard Model: WE_B#, DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
Table 2-24. Motherboard Model: MA_A[14:0], DIMMs 1.0" 3.0" 82443GX 0.4" 0.6"
DIMM Module
Intel® 440GX AGPset
DIMM Module
DIMM Module
DIMM Module
2-29
Motherboard Layout Routing Guidelines
Table 2-25. Motherboard Model: MA_B[12,11,9:0]#, MA_B[14,13,10], DIMMs VCC3 1.0" 3.0" 82443GX 0.4" 0.6" DIMM Module DIMM Module stub pullup/pulldown line: 0.2" MAB12# 0.5" MAB[11,9]# (only applies straps)
2.9.3
DIMM Routing Guidelines FET]
Figure 2-27. Motherboard Model-Data (MDxx) Lines, DIMMs FET) 82443GX 0.4" 0.2" 0.2" 0.4"
DIMM Module
DIMM Module
DIMM Module
NOTE: Route using trace spacing. Route outer layers. Trace impedance 60-80 ohms. Trace velocity 1.6-2.2 ns/ft
2.9.4
Routing Guidelines
82443GX provides interface that compliant with Local Specification. implementation optimized high-performance data streaming when 82443GX acting either target initiator bus. more information interface, refer Intel® 440GX AGPset Datasheet. Intel® 440GX AGPset design basically same Intel® 440BX AGPset. Intel® 440GX AGPset supports masters (excluding Intel® 440GX AGPset PIIX4E), support PREQ# PGNT# lines.
2-30
Intel® 440GX AGPset
DIMM Module
Motherboard Layout Routing Guidelines
Because specifics layout, recommended that PIIX4E component "END" bus, shown Figure 2-28. This insures proper "termination" signals. Figure 2-28. Layout Example
82443GX
PIIX4E
2.9.5
Decoupling Guidelines: Intel® 440GX AGPset Platform
Decoupling caps should placed corners 443GX(BGA Package). minimum four 0.1uF four 0.01 recommended. system bus, AGP, PCI, DRAM interface "break-out" from package four sides. Additional caps will also help reduce cross-talk.
Figure 2-29. 82443GX Decoupling
0.1uF 0.01uF
0.1uF 0.01uF
82443GX
Host Bridge Controller
0.1uF 0.01uF 0.1uF 0.01uF
v006 Note: There other discrete components VTT, Voltages that must also considered when routing around 82443GX.
Intel® 440GX AGPset
2-31
Motherboard Layout Routing Guidelines
2.9.6
2.9.6.1
Intel® 440GX AGPset Clock Layout Recommendations
Clock Routing Spacing
Intel® Pentium® processor Intel® 440GX AGPset platform requires clock synthesizer supplying system clocks, clocks, APIC clocks, clocks. These clocks supplied CK100 clock synthesizer defined CK97 clock/driver specification. SDRAM DIMM clocks generated from controlled clock buffer (CKBF) which produces DIMM clock outputs from single DCLK output provided 82443GX. minimize impact crosstalk, minimum 0.014" spacing should maintained between clock traces other traces. minimum spacing 0.018" recommended serpentines.
Figure 2-30. Clock Trace Spacing Guidelines
0.014" 0.018" Clock
Trace length 3.25" 4.00" 1.0" 1.0" 1.0" 9.0" 12.0" 13.0" Substrate 3.25"
2.9.6.2
System Clock Layout
System clock nets should routed point-to-point connections with series resistor that placed close output pins clock driver possible (<0.5"). system, clock skew between 82443GX processor reduced tying clock driver pins together clock chip driving processor 82443GX from this with resistor driver each. Trace lengths still match specs defined below. Layout guidelines: Match trace lengths longest trace.
Clock chip Processor Clock chip 82443GX Clock chip
2-32
Intel® 440GX AGPset
Motherboard Layout Routing Guidelines
2.9.6.3
Clock Layout
clock nets should routed point-to-point connections with series resistor that placed close output pins clock driver possible (<0.5"). Layout guidelines: Match trace lengths longest trace.
Clock chip connector Clock chip PIIX4E Clock chip -440GX Trace length 4.8" 7.3" 7.3" 1.0" 1.0" 1.0" 12.5" 15.0" 15.0" Substrate 2.5"
2.9.6.4
SDRAM Clock Layout
Series Termination: series termination required SDRAM clocks between CKBF DIMMs. DCLKO (between 82443GX CKBF), termination resistors required: series resistor located driver, series resistor located receiver. Layout guidelines:
440GX CKBF (DLKO) CKBF DIMM (SDRAM Clocks) CKBF 82443GX (DCLKWR) Trace Length A+2.5" 1.0" 1.0" 3.5"5.5" 10.0" 3.0" 20pF
Note:
single clock output from CKBF used drive DCLKWR 82443GX. single clock should "T"d close possible 82443GX. additional capacitive load 20pF also required. capacitor should also located close 82443GX possible. 82443GX does have internal connection AB22. Existing designs connected DCLKWR AB22 nets motherboard. Since 82443GX does have internal connection AB22, will cause slightly reduced load capacitance net. avoid additional clock skew existing designs, discrete capacitor larger than 20pF capacitor recommended required.
Intel® 440GX AGPset
2-33
Motherboard Layout Routing Guidelines
2.9.6.5
Clock Layout
Series Termination: series termination should used clocks. Layout guidelines: feedback clock trace length equals standard clock motherboard trace length plus card trace length.
Figure 2-31. Clock Layout
22ohm GCLKOUT 22ohm AGPCLK
GCLKIN
resistor connector resistor 82443GX (feedback)
Trace Length 3.3"
0.5" 0.5"
15.3"
Card Trace Length ~3.3"
Note:
driver. signal splits 82443GX, each half trace goes through resistor, then their respective loads. graphics chip down motherboard, trace length graphics chip feedback trace length 82443GX will both same length.
2-34
Intel® 440GX AGPset
Design Checklist
Design Checklist
Design Checklist
Overview
following checklist intended used schematic reviews Intel® 440GX AGPset desktop designs. does represent only design system, provides recommendations based Intel® 440GX AGPset reference platform.
Pull-up Pull-down Resistor Values
Pull-up pull-down values system dependent. appropriate value your system determined from AC/DC analysis pull-up voltage used, current drive capability output driver, input leakage currents devices signal net, pull-up voltage tolerance, pull-up/pull-down resistor tolerance, input high/low voltage specifications, input timing specifications rise time), etc. Analysis should done determine minimum/maximum values that used individual signal. Engineering judgment should used determine optimal value. This determination include cost concerns, commonality considerations, manufacturing issues, specifications other considerations. simplistic calculation pull-up value
RMAX (VccPU MIN) ILeakage RMIN (VccPU MAX)
Since ILeakage normally very small, RMAX meaningful. RMAX also determined maximum allowable rise time. following calculation allows maximum allowable rise time, total load capacitance circuit, including input capacitance devices driven, output capacitance driver, line capacitance. This calculation yields largest pull-up resistor allowable meet rise time simplistic calculation pull-up value is:=
RMAX (VIH VccPU MIN)
Intel® 440GX AGPset
Design Checklist
Figure 3-1. Pull-up Resistor Example
VccPU
RMAX ILeakage
VccPU
RMIN IOLMAX
3.3.1
Intel® Pentium® Processor Checklist
Intel® Pentium® Processor
Table 3-1. Slot Connectivity (Sheet
Processor Connection Connected CK100. series resistor MAB#12. pull-up 3.3V CK100. connect between CPUs (Logic provided detect frequency match). A[35:32]#, A[31:3] A20M# ADS# AERR# AP[1:0]# BCLK BERR# BINIT# BNR# BP[3:2]# BPM[1:0] BPRI# BREQ[1:0]# D[63:0]# Leave connect A[31:3]# 82443GX. pull-up 2.5V. Connect 82443GX; Connect CPUs 82443GX Leave Leave Connect CK100. series resistor. Leave Leave Connect 82443GX; Connect CPUs 82443GX Leave Leave Connect 82443GX; Connect CPUs 82443GX. Connect BREQ0# 82443GX. Leave BREQ1# Connect BREQ0# each BREQ1# other. Connect these 82443GX. Connect 82443GX; Connect CPUs 82443GX.
100/66#
Intel® 440GX AGPset
Design Checklist
Table 3-1. Slot Connectivity (Sheet
Processor DBSY# DEFER# DEP[7:0] DRDY# FERR# FLUSH# FRCERR# HIT# HITM# IERR# IGNNE# INIT# LINT[1:0] LOCK# PICCLK PICD[1:0] PRDY# PREQ# PWRGOOD REQ[4:0]# RESET# RS[2:0]# RSP# SLOTOCC# SLP# Connection Connect 82443GX; Connect CPUs 82443GX. Connect 82443GX; Connect CPUs 82443GX. connect. Connect 82443GX; Connect CPUs 82443GX. Connect GND. Connect PIIX4E, pull-up 2.5V. Connect CPUs PIIX4E, pull-up 2.5V. pull-up 2.5V. Connect CPUs pull-up. Leave Connect between CPUs 82443GX. Connect between CPUs 82443GX. Leave pull-up 2.5V. Connected frequency strapping circuit. Connect CPUs, frequency strapping unit, pull-up 2.5V. Connect PIIX4E, pull-up 2.5V. Connect CPUs PIIX4E, pull-up 2.5V. pull-up 2.5V. Connect CPUs pullup 2.5V. Connect 82443GX; Connect CPUs 82443GX. Connect CK100. series resistor. pull-up 2.5V. Connect CPUs IOAPIC pull-up 2.5V. series resistor ITP. Connected ITP. pull-up 2.5V. Requires pull-up 2.5V. Connect between CPUs. Connect 82443GX; Connect CPUs 82443GX. Connect 82443GX, series resistor ITP. Connect CPUs with series resistor. Leave Connect 82443GX; Connect CPUs 82443GX. Leave GND. Part PWRGD logic, 8.2K pull-up 3.3V. pull-up 2.5V. Connect PIIX4E. Connect CPUs PIIX4E with pull-up 2.5V. Connect PIIX4E, pull-up 2.5V. SMI# Connect CPUs jumper APC_SMI# PX4_SMI# IOAPIC). pull-up 2.5V. Connect PIIX4E, pull-up 2.5V. Connect CPUs PIIX4E, pull-up. pull-up 2.5V. series resistor ITP. Separate series resistors then hooked together ITP. pull-up 2.5V.
STPCLK#
Intel® 440GX AGPset
Design Checklist
Table 3-1. Slot Connectivity (Sheet
Processor TESTHI THERMTRIP# TRDY# TRST# VID[4:0] Connection Connected ITP. pull-up 2.5V. Connected jumpers between signals. schematics details. Connected ITP. pull-up 2.5V. Connected jumpers between signals. schematics details. 4.7K pull-up 2.5V. Connect CPUs 4.7K pull-up 2.5V. used. pull-up 2.5V used. Connect CPUs pull-up 2.5V. pull-up 2.5V. series resistor ITP. Separate series resistors then hooked together ITP. pull-up 2.5V. Connect 82443GX. Connect CPUs 82443GX. Connect ITP. pull-down. Connect CPUs pull-down. 8.2K pull-up default use. Optional override could used. Also connect optional LM79.
Table 3-2. Power Definition
A102 A106 A110 A114 A118 VccCORE B105 (1.5V) VCC3 (3.3V) B113 B117 B121 Reserved (NC) A113 A116 B112 (5V) B109
Intel® 440GX AGPset
Design Checklist
3.3.2
Intel® Pentium® Processor Clocks
Include circuit system clock core frequency ratio processor. ratio
should configurable opposed hard wired. frequency select straps will latched rising edge CRESET#.
CRESET# used selection signal muxing A20M#, IGNNE#, INTR, with
processor bus/core frequency selection jumpers. `244 buffer maybe used mux. outputs `244 device open collector buffers voltage translation CPU. reference board schematics specific implementation.
PICCLK must driven clock even APIC being used. This clock
high 33.3 system. system utilizing Intel's APIC (82093AA) maximum PICCLK frequency 16.666 MHz.
3.3.3
Intel® Pentium® Processor Signals
Dual termination ohm) GTL+ required trace length restrictions
(single-ended termination) environment cannot met.
THERMTRIP# must pulled-up Vcc2.5 (150 ohm) used system logic.
signal wire-OR'ed does require external gate. left used. Debug Recommendations further information that affect resistor values. PIIX4E. reference schematics uses ohms. Debug Recommendations further information that affect these resistor values.
FERR# output must pulled Vcc2.5 (150 ohm) connected PICD[1:0]# must have pull-ups Vcc2.5 even APIC being used.
Debug Recommendations further information that affect these resistor values.
CMOS inputs should pulled Vcc2.5 (150 ohm). Debug
Recommendations further information that affect these resistor values.
sure Slot inputs being driven 3.3V logic. Logic translation 3.3V
signals accomplished using open-drain drivers pulled-up Vcc2.5.
PWRGOOD input should driven appropriate level from active-high "AND"
Power-Good signals from 3.3V VccCORE supplies. output logic used drive PWRGOOD should Vcc2.5 level processor.
VREF should generated Intel® Pentium® processor. VREF locally generated
processor card.
must have adequate bulk decoupling based reaction time regulator used
generate Vtt. must provide current ramp 8A/uS while maintaining voltage tolerance defined Intel® Pentium® Processor datasheet.
on-board voltage regulator used instead VRM, VccCORE must have adequate bulk
decoupling based reaction time regulator used generate VccCORE. must provide current ramp 30A/uS while maintaining DC-DC Converter Specification. Regulator Module board regulator that have chosen. pull-up voltage used should regulator input voltage 12V). However, used, resistor divider should utilized lower signal CMOS/TTL levels. signals used detect presence processor core. pull-up required unless signals
lines should have pull-up resistors ONLY they required Voltage
Intel® 440GX AGPset
Design Checklist
used other logic requiring CMOS/TTL logic levels. lines Slot connector tolerant.
(±5%) should provided Slot signal B109. This power connection
used Intel® Pentium® processor. required Slot tool required future Boxed processors. Recommendations further information that affect these resistor values.
JTAG port must properly terminated even used. Debug pins Slot connector (pins B41, B61, B100) should connected
system chassis ground through zero resistors. determination install these resistors design dependent determined through empirical methods.
TRST# must driven during reset components with TRST# pins. Connecting
pull-down resistor TRST# will accomplish reset port.
regulators used, each bus, Intel recommends connecting
regulator outputs together with wide trace that runs along same basic path GTL+ signals (beware crosstalk). VREF should generated each AGPset component from this combined VTT. This simply recommendation minimize effects noise. AP-523 Intel® Pentium® Processor Power Distribution Guidelines more information.
single regulator used. system simplistic calculation maximum Motherboards planning support Boxed Intel® Pentium® processor must provide
worst case current 5.0A. This takes into consideration that some signals used Intel® 440GX AGPset.
matched power header Boxed Intel® Pentium® processor fan/heatsink power cable connector. power header must positioned within close proximity Slot connector. presence core determined from combination non-zero signals, (all ones designates Core") state SLOTOCC# low.
Slot connector signal SLOTOCC# (Pin B101) ground Slot processor. ITPREQ[1:0]#, ITPRDY[1:0]# individually hooked either CPU. .inf file
must match connections.
DBRESET (ITP Reset signal) requires pull-up VCC3.
Intel® 440GX AGPset
Design Checklist
3.3.4
Uni-Processor (UP) Slot Checklist
system must connect BREQ0# Slot connector 82443GX's BREQ0#
signal. This will assign agent processor. BREQ1# Slot connector left connect.
design, GTL+ termination resistors ohm) recommended
motherboard (dual ended termination). second terminations provided Intel® Pentium® processor. Single ended termination (processor termination only) achieved provided trace lengths adhere very restrictive lengths given layout guidelines.
FRCERR# left connect design. board termination resistors
required since they provided Intel® Pentium® processor.
3.3.5
Dual-Processor (DP) Slot Checklist
system must cross connect BREQ[1:0]# Slot connector 82443GX's
BREQ0# signal, i.e. BREQ0# should tied BREQ1# other processor.
onboard termination required because termination provided Intel® Pentium®
processor.
FRCERR# left connect design mode supported.
board termination resistors required since they provided Intel® Pentium® processors.
Each processor site should have isolated VccCORE power plane. Contact your vendor
availability VRMs with current sharing capabilities desired.
SLOTOCC# signal used block system from booting sets GTL+
termination resistors present. Slot lines from each connectors used determine non-functional processor core terminator card present.
IOAPIC clock distributed CPUs through series resistors.
3.3.6
Slot Decoupling Capacitors
Additional VccCORE decoupling capacitance, high frequency bulk, required
properly designed Slot power delivery plane VRM. designs utilizing local regulator motherboard, adequate bulk decoupling required. This bulk decoupling dependent upon regulator reaction time. Contact your regulator vendor bulk decoupling recommendations that will meet DC-DC Converter Specification.
Decoupling capacitor traces should short wide possible.
3.3.7
Voltage Regulator Module,
formerly reserved pin, 12VIN. formerly reserved pin, 5VIN. ISHARE used design using same manufacturer's share current
load between VRMs.
modified from provide future processors. (voltage identification) pins from processor will determine VccCORE output
VRM.
Intel® 440GX AGPset
Design Checklist
3.4.1
Intel® 440GX AGPset Clocks
CK100 Clock Synthesizer
system clock which provides processor Intel® 440GX AGPset,
clocks APIC must +2.5V.
implemented clock chip, when strapped low, provides spread spectrum
modulation effect which help reduce EMI. modulation will "down spread" only, meaning that nominal 100/66 frequencies will modulated 0.25% 0.5% below 100/66. While this help testing, performance will impacted. Check with your clock vendor availability this feature.
pins CK100 used select special functionality using 8.2K pull-ups
Table 3-3. Processor Frequency Select
SEL100/66# SEL1 SEL0 Function Tri-state Test Mode Active 66MHz Active 100MHz
Unused clocks should terminated ground with resistors. series resistors recommended CPU, PCI, IOAPIC clock outputs. system, clock skew between 82443GX reduced tying
clock driver pins together clock chip driving 82443GX from this with resistor driver each.
pull-ups VCC3.3 recommended PCI_STP#, CPU_STP#, PWRDWN#.
supported, connecting these signals PIIX4E required. reset, SUSA# (connected PWRDWN#) asserted, which causes clock outputs stop. This cause problems with when connected. Zero stuffing options used select functionality.
Check with your clock vendor reference schematics special layout decoupling
considerations. reference schematics implement filter supply pins reduce noise.
Intel® 440GX AGPset
Design Checklist
3.4.2
CKBF SDRAM Clock Buffer
4.7K pull-up VCC3.3 needed enable buffer. Note that DCLKRD been changed connect (NC). DCLKRD functionality
been combined with DCLKWR. desire remove trace going DCLKRD pin, capacitor value should adjusted compensate capacitance change.
interface provided which allows BIOS disable unused SDRAM clocks
reduce power consumption. recommended that BIOS disable unused clocks.
series termination required SDRAM clocks between CKBF DIMMs. DCLKO from 82443GX CKBF should have series resistor placed
82443GX, series resistor placed CKBF. This been shown simulations improve signal integrity this signal.
Check with your clock vendor reference schematics special layout decoupling
considerations. reference schematics implement filter supply pins reduce noise.
3.4.3
GCKE DCLKWR Connection
diagram below implementation 16-bit flip-flop generation
DIMMs.
GCKE trace length from 82443GX flip-flop recommended
MAX. trace lengths from flip-flop DIMMS recommended Figure 3-2. GCKE DCLKWR Connections
CKBF
DCLKWR (AB22) GCKE
27pF
82443GX
20pF
Clock signals back into 82443GX D-FF must `T'-off with equal trace length close possible 82443GX D-FF. capacitors must placed close node where clock signals `T'-ed. capacitor values shown.
74LVCH16374
CKE7 1D3, CKE6 1D5, CKE5 1D7, CKE4 2D1, CKE3 2D3, CKE2 2D5, CKE1 2D7, CKE0
v007
NOTES: above circuitry only applies unbuffer DIMMS. GCKE needs disabled register DIMMS. AB22 been changed connect (NC), 82443GX does have internal connection AB22. Existing designs connected DCLKWR AB22 nets motherboard. Since 82443GX does have internal connection AB22, will cause slightly reduced load capacitance net. avoid additional clock skew existing designs, discrete capacitor larger than 20pF capacitor recommended required.
Intel® 440GX AGPset
Design Checklist
3.5.1
82443GX Host Bridge
82443GX Interface
Table 3-4. 82443GX Connectivity (Sheet
SIGNAL AD#[31:0] ADS# AGPREF BNR# BPRI# BREQ0# GXPWROK C/BE[3:0]# FENA GCKE Connected bus. Connected CPUs. Connected VCC3.3. performed voltage divider. Connected CPUs. Connected CPUs. Connected CPUs. Connected PIIX4E PWROK pin. Connected bus. 4DIMM Design: Connected FET-switches enable pin. GCKE needs disabled register DIMMS. GCKE unless connected SN74ALVCH16374 16-bit flip-flop. reference schematics details. connected PIIX4E, pull down through resistor both 82443GX PIIX4E. Connected CPUs (240 series resistor). pull-up 3.3V. Controls strapping signals. Connect DIMMs; each Connect CSA[7:6]# DIMM Connect DIMMs; each Connect CSB[7:6]# DIMM Connected CPUs. Connected CKBF. series resistor placed next 443GX series resistor placed next CKBF. Driven single clock from CKBF. Clock section Connected CPUs. 2.7K pull-up Connected bus. Connected DIMMs. DIMM: Connected DIMM2 DIMM3. 2.7K pull-up Connected bus. Connected connector. Connected GCLKOUT through resistor. Connected connector through series resistor. CONNECTION
CLKRUN# CPURST# CRESET# CSA[5:0]# CSA[7:6]# CSB[5:0]# CSB[7:6]# DBSY#, DRDY# DCLKO DCLKWR, AB22 (NC) DEFER# DEVSEL# DQMA[7:0] DQMB5, DQMB1 FRAME# GAD[31:0], BE[3:0]# GCLKIN GCLKOUT
Intel® 440GX AGPset
3-10
Design Checklist
Table 3-4. 82443GX Connectivity (Sheet
SIGNAL GADSTBA, GADSTBB, GDEVSEL#, GFRAME#, GGNT#, GIRDY#, GREQ#, GSTOP#, GTRDY#, GPAR GTLREFA, GTLREFB HA[31:3]# HCLKIN HD[63:0]# HIT#, HITM# HLOCK# HREQ[4:0]# HTRDY# IRDY# MAA[14:0] MAB[14, 10], MAB[11, 9:0]# MD[63:0], MECC[7:0] PCIRST# PCLKIN PGNT[4:0]# PHLDA# PHOLD# PIPE# PLOCK# PREQ[4:0]# RBF# REFVCC5 RS[2:0]# SBA[7:0] SBSTB SCAS[B:A]# SERR# SRAS[B:A]# ST[2:0] STOP# SUSTAT# TESTIN# CONNECTION
8.2K pull-ups 3.3V. Connected connector.
100K pull-down required. Connect connector. buffer voltage reference input (1.0V vtt) Connected CPUs. Connected CK100 through series resistor. Connected CPUs. Connected CPUs. Connected CPUs. Connected CPUs. Connected CPUs. 2.7K pull-up Connected bus. Connected DIMM0 DIMM1. Connected DIMM2 DIMM3. Connected each DIMM. Switch Design: Connected switches. Connected bus. Connected PIIX4E, connector, connectors. Connected CK100 through series resistor. 8.2K pull-ups 3.3V. Connected connectors. 8.2K pull-up 3.3V. Connected PIIX4E. 8.2K pull-up 3.3V. Connected PIIX4E. 8.2K pull-ups 3.3V. Connected connector. 2.7K pull-up Connected connectors. 2.7K pull-ups Connected connectors (except PREQ4#). 8.2K pull-up 3.3V. Connected connector. reference voltage tolerant buffers. Connected CPUs. Connected connector. 8.2K pull-up 3.3V. Connected connector. Each connected DIMMs. 2.7K pull-up Connected bus. Each connected DIMMs. Connected connector. 2.7K pull-up Connected bus. pull-up 3.3V. Connect PIIX4E implementation. 8.2K pull-up 3.3V which removed validation permits.
Intel® 440GX AGPset
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Design Checklist
Table 3-4. 82443GX Connectivity (Sheet
SIGNAL TRDY# VTTA, VTTB WE[B:A]# WSC# CONNECTION 2.7K pull-up Connected bus. threshold voltage early clamps. Each connected DIMMs. Leave Connected IOAPIC. pull-up resistor needed.
GTLREFx pins driven from independent voltage dividers which GTLREFx pins
VTT*2/3 using resistor ratio.
82443GX GTL_REF[B:A] pins should adequately decoupled. 82443GX component 3.3V component. pins labeled should connected
VCC3.3.
VDD_AGP pins have been changed pins. VSSA been changed VSS. 82443GX REFVCC5 connected same power sequencing circuit used
PIIX4E. PIIX4E section further information sharing this circuit.
82443GX AGPREF required VCC3.3, this performed
voltage divider.
82443GX GX_PWROK connected PIIX4E PWROK pin. series resistors GCLKOUT GCLKIN should placed next driver
GCLKOUT.
CRESET# used control reset values A20M#, IGNNE#, LINT[1:0]
determine ratio core frequencies. This signal delayed provide BCLK hold requirement. pull-up 3.3V recommended.
TESTIN# should pulled VCC3.3 with 8.2K resistor. internal pull-up
prove sufficient, however first boards should include external pull-up safe.
3.5.2
82443GX GTL+ Interface
Intel® 440GX AGPset does support entire Intel® Pentium® processor GTL+
bus. design, board termination resistors recommended following signals: HD[63:0]#, A[31:3]#, HREQ[4:0]#, RS[2:0]#, HTRDY#, BREQ[0]#, BNR#, BPRI#, DBSY#, DEFER#, DRDY#, ADS#, HIT#, HITM#, HLOCK#, CPURST#. second terminations provided Intel® Pentium® processor.
Intel® 440GX AGPset does support entire Intel® Pentium® processor GTL+
bus. design, board termination resistors required following signals: HD[63:0]#, A[31:3]#, HREQ[4:0]#, RS[2:0]#, HTRDY#, BREQ[0]#, BNR#, BPRI#, DBSY#, DEFER#, DRDY#, ADS#, HIT#, HITM#, HLOCK#, CPURST#. second terminations provided second Intel® Pentium® processor terminator card. empty Slot connector allowed.
3.5.3
82443GX Interface
boundary scan supported motherboard: (See Specification
Section 4.3.3 more information)
Intel® 440GX AGPset
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Design Checklist
(connector (connector should independently bussed pulled with (approximate) resistors. TRST# (connector (connector should independently bussed pulled down with (approximate) resistors. (connector should left open.
3.5.4
82443GX Interface
following will help reduce AGPREF margin needed when data being written read
interface. only resistors AGPREF voltage divider 82443GX boards. This will limit AGPREF margin needed 100mV below Vcc. resistors used, AGPREF margin needed would 160mV. Have least" spacing around Strobe decrease crosstalk inductive coupling from adjacent signals. This could reduce crosstalk much 100-300 interface designed 3.3V operating environment, both master target compliant devices must driven same supply line. external termination signal quality required spec., added improve signal integrity provided timing constraints still satisfied. interrupts shared with interrupts similar recommendations spec. example, system with slots slot, interrupts should connected such that each four INTA# lines hooks unique input PIIX4E. recommended that interrupts staggered. also recommended that each PIRQ programmed different possible. requirement motherboard designer properly interface interrupts bus. this reference design, interrupts pulled 3.3V, buffer used isolate environment from bus. minimize impact mismatch between motherboard add-in card, board impedance ohms strongly recommended. each component that requires AGP_Vref should generated locally from interface Vddq rail.
Table 3-5. Strapping Options
Signal MAB9# MAB11# MAB12# Description Signals Order Queue Depth Host Frequency Register PMCR[1] MGXCFG[2] NGXCFG[13] Pulled Enabled (Default) Non-Pipelined Reserved Pulled Disabled Maximum Queue Depth Enabled (Default) 100MHz (Default)
NOTES: MAB[9]# connected internal pull-down resistors. MAB[12:11] connected internal pull-up resistors. Note that strapping signals driven 82443GX during reset sequence. Proper strapping must used define logical values these signals. Default values provided internal pull-up pull-down resistors overridden external resistor. When disabled, signals tri-stated isolated. They need external pull-up resistors. signals PIPE#, SBA[7:0], RBF#, ST[2:0], GADSTBA, GADSTBB, SBSTB, GFRAME#, GIRDY#, GTRDY#, GSTOP#, GDEVSEL#, GREQ#, GGNT#, GAD[31:0], FC/BE[3:0]#, GPAR. When disabled, AGP_Vref ground.
Intel® 440GX AGPset
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Design Checklist
3.6.1
Intel® 440GX AGPset Memory Interface
SDRAM Connections
Table 3-6. SDRAM Connectivity
82443GX Pins/Connection CKBF buffer outputs DCLK[x:y] CS_A[7:0]# CS_B[7:0]# MAx[9:0]#, MAx10 MAx11# Max12# MAA13#, MAB13 MAA14, MAB14 MDx[63:0] (from FET) MD[63:0] FET) MECC[7:0] Strap SMBus individual Address SMBDATA SMBCLK SCASx# SRASx# WEx# DIMM Pins CK[3:0] DCLKs DIMM) S#[1:0] DIMM) S#[3:2] DIMM) A[10:0] DQ[63:0] CB[7:0] SA[2:0] CAS# RAS# WE0# Clock Chip Select Chip Select Address Address Address Address Address Address Data Error Checking Correction SMBus Address SMBus Data SMBus Clock SDRAM Column Address Select SDRAM Address Select Write Enable Function
NOTES: Some ranges above dependent which DIMM being reviewed. indicate signal copies. MAAxx address lines need routed DIMM sockets closest 82443GX. MABxx# will routed DIMM sockets furthest from 82443GX. Selected MABxx# lines will also require strapping options properly configure 82443GX. either no-FET solution. solution will require 56-pin switch multiplexers. most common switches available family. no-FET solution must adhere strict no-FET design layout guidelines. MECC lines require routing load balancing. Copies SRAS#, SCAS#, should evenly distributed throughout memory array. MABxx# pins (except MAB10, MAB13, MAB14) inverted signal integrity reasons. MAB10, MAB13, MAB14 inverted maintain correct SDRAM commands. Series termination resistors required motherboard DIMM signals (MD, DQM, etc.). SDRAM Serial Presence Detect Data Structure specification information EEPROM register contents. SDRAM Unbuffered DIMM Specification, 1.0, dated 1998, shows DIMM module (write protect) EEPROM. block diagrams show there pulldown resistor tied pin. This allows DIMM manufacturers write data EEPROM. wish EEPROM write information into DIMMs production system level checkout identify DIMM installed being shipped with system. this reason, wish include some logic control level DIMM modules that after DIMM tagged, they write protected again. this pulled high motherboard, DIMM EEPROM write protected. DIMM sockets 82443GX dual processor reference schematics currently shows "NC", connects. wishes write protect SDRAM EEPROMS, then these pins should pulled high.
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Design Checklist
3.6.2
DIMM Solution With Switches
With existing 64Mbit technology, support servers
workstations must have double sided DIMMs.
pull-down resistors each second inputs (1A2, 2A2, etc.)
recommended switches (500 ohms recommended based simulation) prevent direct short ground while switching. Figure 3-3. Current Solution With Existing Switches
0-71
82443GX
0-71 0-71
FENA
v009.vsd
lines through switch. current switch Pericom PI5C16212A, package type A56. third-party vendor
list more switch vendors.
functional units part requires devices motherboard.
3.6.3
Registered SDRAM
There power thermal considerations registered DIMMs. design going
support registered DIMMs, DIMM spacing need evaluated based mechanical cooling issues.
REGE, DIMMs needs pull-up enable registered DIMMs. Data lines directly connected SDRAM components, while address control
signals registered. clock signal routed SDRAM devices.
Access registered DIMMs requires additional clock leadoff latency, programmable
82443GX.
Intel® 440GX AGPset
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Design Checklist
3.7.1
82371EB (PIIX4E)
PIIX4E Connections
Table 3-7. PIIX4E Connectivity (Sheet
Signal Names 48MHz A20GATE A20M# AD[31:0] APICACK# GPO12 APICCS# GPO13 APICREQ# GPO15 BALE BATLOW# GPI9 BIOSCS# C/BE#[3:0] CLOCKRUN# CONFIG1 CONFIG2 CPURST CPU_STP# GPO17 DACK#[7:0] DEVSEL# DREQ[7:0] EXTSMI# FERR# FRAME# GNT[C:A]# GPO[11:9] GPI1 GPI[x:y] (Unused) GPO[x:y] (Unused) IDSEL IGNNE# INIT# INTR Connection Connect CK100 through series resistor. Connected SIO. 8.2K pull-up VCC3. Part CPU/bus frequency circuit. 2.7K pull-up VCC3. Connect slots 82443GX. Connect slots. Leave Connect IOAPIC. Leave Connected IOAPIC. 8.2K pull-up VCC3. 8.2K pull-up VCC3. Connected IOAPIC. Connect slots. 8.2K pull-up 3VSB BATLOW# used. Connect Flash. Connect slots 82443GX. pull-down. 8.2K pull-up 3VSB. 8.2K pull-down. Leave connect, connected CK100 with pull-up 3VSB. Connect slots. DACK#[3:0] also connect SIO. 2.7K pull-up pull-up Connect between 82443GX, slots, PIIX4E. Connected slots. 5.6K pull-down. Connected LM79. 8.2K pull-up 3VSB. Connect between CPUs. pull-up 2.5V. 2.7K pull-up pull-up Connect between 82443GX, slots, PIIX4E. connect. Used PCI_PME. 8.2K pull-up 3VSB. Pull-up 3VSB also required when using this pin. 2.7K pull-up VCC3. connect. resistor AD18. Part CPU/bus frequency circuit. 2.7K pull-up VCC3. Connected CPUs. pull-up 2.5V. Part CPU/bus frequency circuit. 2.7K pull-up VCC3. Connected IOAPIC.
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Design Checklist
Table 3-7. PIIX4E Connectivity (Sheet
Signal Names IOCHCK# IOCHRDY IOCS16# IOR# IOW# IRDY# IRQ0 GPO14 IRQ8# IRQ[1,3:7] IRQ[15:14] IRQ[9:12] KBCCS# GPO26 LA[17:23] GPI10 MCCS# MEMCS16# MEMR#, MEMW# PCICLK PCIRST# PCI_STP# GPO18 PCS1# PCS3# PDA[2:0] PDD[15:0] PDDACK# PDIOR# PDIOW# PDREQ PGCS#0 PGCS#1 Connection Connected slots. 4.7K pull-up VCC. Connected slots Ultra I/O. pull-up VCC. Connected slots. pull-up VCC. Connected slots, Ultra I/O, LM79. 8.2K pull-up VCC. Connected slots, Ultra I/O, LM79. 8.2K pull-up VCC. 2.7K pull-up pull-up Connect between 82443GX, slots, PIIX4E. connect. Connected INTIN2 IOAPIC. 8.2K pull-up 3VSB. Connected IOAPIC through tri-state buffer. 8.2K pull-up VCC. Connected slots Ultra I/O. Connected IOAPIC. Connected slots, Ultra I/O, IDE. 8.2K pull-up VCC. Connected IOAPIC. Connected slots, Ultra I/O. 8.2K pull-up VCC. Connected IOAPIC. Connect. Connected slots. 8.2K pull-up VCC. 8.2K pull-down used. Connect wake Header used. connect. Connected slots. pull-up VCC. Connected slots Flash. 8.2K pull-up VCC. Connected IOAPIC. Part CPU/bus frequency circuit. 2.7K pull-up Driven overcurrent detection voltage divider. Connect CK100. Connect slots 82443GX. Connect CK100. Connect AGP, PCI, 82443GX. connect, connected CK100 with pull-up 3VSB. Connected connector through series resistor. Connected connector through series resistor. Connected connector through series resistors. Connected connector through series resistors. recommended that PDD[7] have pull-down resistor. Connected connector through series resistor. Connected connector through series resistor. Connected connector through series resistor. Connected through series resistor. 5.6K pull-down PIIX4E side series resistor. connect. 8.2K pull-up VCC3. Connected LM79.
Intel® 440GX AGPset
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Design Checklist
Table 3-7. PIIX4E Connectivity (Sheet
Signal Names PHLD# PHLDA# PIORDY Connection Connected 82443GX. 8.2K pull-up VCC3. Connected 82443GX. 8.2K pull-up VCC3. Connected through series resistor. pull-up PIIX4E side series resistor. 2.7K pull-up pull-up Connect between 443GX, slots, PIIX4E. PIRQ[A:B]# also AGP. PIRQ[A:D]# connected IOAPIC. From power button circuitry. Connect 82443GX power logic. 8.2K pull-up VCC3. Connect SIO. Connected slots. pull-up VCC. 8.2K pull-up VCC3. Connect corresponding REQ[3:0]# signals Host Bridge(443GX) connectors. 8.2K-ohm pull-up VCC. Connected connector AGP_PME# (pin A48). 8.2K pull-up 3VSB. From connector buffer/delay circuitry. Connect Ultra I/O, slots, (through Schmitt trigger). connect. connect. Connect crystal. Connect crystal. Connected slots, Ultra I/O, Flash, LM79. 8.2K pull-up VCC. Connected IOAPIC. Connect slots. Connected connector through series resistor. Connected connector through series resistor. Connected slots, Ultra I/O, LM79. 8.2K pull-up VCC. Connected IOAPIC. Connected connector through series resistors. Connected connector through series resistor. Connected connector through series resistors. recommended that PDD[7] have pull-down resistor. Connected connector through series resistor. Connected connector through series resistor. Connected through series resistor. 5.6K pull-down PIIX4E side series resistor. 2.7K pull-up VCC3. 2.7K pull-up pull-up Connect between 82443GX, slots, PIIX4E. Connected through series resistor. pull-up PIIX4E side series resistor. Connected CPUs. pull-up 2.5V. Connect MAX1617. 8.2K pull-up 3VSB.
PIRQ[D:A]# PWRBT# PWROK RCIN# REFRESH# REQ[C:A]# GPI[4:2] REQ[3:0]# GPI12 RSMRST# RSTDRV RTCALE GPO25 RTCCS# GPO24 RTCX1 RTCX2 SA[0:19] SBHE# SCS1# SCS3# SD[0:15] SDA[2:0] SDDACK# SDD[15:0] SDIOR# SDIOW# SDREQ SERIRQ GPI7 SERR# SIORDY SLP# SMBALERT# GPI11
Intel® 440GX AGPset
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Design Checklist
Table 3-7. PIIX4E Connectivity (Sheet
Signal Names SMBCLK, SMBDATA SMEMR#, SMEMW# SMI# SPKR STOP# STPCLK# SUSA# SUSB# GPO15 SUSC# GPO16 SUSCLK SUS_STAT[2:1]# GPO[21:20] SYSCLK TEST# THERM# GPI8 TRDY# USBPx+VBAT Connection Connect devices SMBus. 2.7K pull-up VCC3. This value need adjusted based loading. Connected slots. pull-up VCC. pull-up 2.5V. This open drain output from PIIX4E. Connected CPU. Connected IOAPIC. Connect speaker circuit. 2.7K pull-up pull-up Connect between 82443GX, slots, PIIX4E. Connected CPUs. pull-up 2.5V. This open drain output from PIIX4E. connect, connected CK100 power down control with pull-up VCC3. connect. Controls power supply. Connect Connect Connect LM79 slots. Connect slots. 8.2K pull-up 3VSB. Connected LM75. 8.2K pull-up VCC3. 2.7K pull-up pull-up Connect between 82443GX, slots, PIIX4E. 47pF ground with series resistor port. These should placed close possible PIIX4E. Connect battery circuit. Connect 82443GX power supply sequencing circuit. PIIX4E data sheet. Connect SIO. Connect SIO. Connected slots. pull-up VCC. connect.
VREF
XDIR# GPO22 XOE# GPO23) ZEROWS# GPO19
Intel® 440GX AGPset
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Design Checklist
3.7.2
Routing Guidelines
This section contains guidelines c
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