Specification Update April, 2000 Notice: Intel 82443GX AGPse
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Intel® 82443GX AGPset Specification Update
Specification Update
April, 2000
Notice: Intel 82443GX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update.
Order Number: 290643-003
Intel® 82443GX AGPset Specification Update
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Specification Update
Intel® 82443GX AGPset Specification Update
Contents
Revision History.4 Preface Specification Changes Errata Specification Clarifications.15 Documentation Changes
Specification Update
Intel® 82443GX AGPset Specification Update
Revision History
Rev. -001 -002 -003 Initial Release Added Specification Change Modify Memory Buffer Strength Terminology Register 69-6Eh. Added Specification Change Increase Supported Memory Configurations. Added Documentation Change Correction SERR# Type. Added Specification Clarification Multi-bit Memory Error Draft/Changes Date October 1998 November 1998 April 2000
Specification Update
Intel® 82443GX AGPset Specification Update
Preface
This document update specifications contained Intel 82443GX Intel 440GX AGPset: 82443GX Host Bridge/Controller Datasheet, -001. intended hardware system manufacturers. contains Specification Changes, Errata, Specification Clarifications, Documentation Changes.
Nomenclature
Specification Changes modifications current published specifications. These changes will incorporated next release specifications. Errata design defects errors. Errata cause Intel 82443GX AGPset, behavior deviate from published specifications. Hardware software designed used with given stepping must assume that errata documented that stepping present devices. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications.
Component Identification Programming Interface
Intel 82443GX AGPset identified following register contents:
Stepping Vendor 8086h
Device
Revision Number
71A9/71A2h
NOTES: Vendor corresponds bits 15-0 Vendor Register located offset 00-01h function configuration space. Device corresponds bits 15-0 Device Register located offset 02-03h function configuration space. Revision Number correspond bits Revision Register located offset function configuration space.
Specification Update
Intel® 82443GX AGPset Specification Update
Component Marking Information
Intel 82443GX AGPset identified following component markings:
Stepping SL2TF SL2VJ S-Spec Marking FW82443GX Q633ES FW82443GX Q634ES FW82443GX SL2TF FW82443GX SL2VJ Notes Engineering Sample, Test Engineering Sample, Test 443GX Production ASSY 443GX Production ASSY
Specification Update
Intel® 82443GX AGPset Specification Update
Summary Table Changes
following table indicates Specification Changes, Errata, Specification Clarifications Documentation Changes which apply listed Intel 82443GX AGPset steppings. Intel intends some errata future stepping component account other outstanding issues through documentation Specification Changes noted. This table uses following notations: Codes Used Summary Table Doc: Fix: Fixed: NoFix Erratum, Specification Change Clarification that applies this stepping. Document change update that will implemented. This erratum intended fixed future stepping component. This erratum been previously fixed. There plans this erratum.
mark) (Blank Box): This erratum fixed listed stepping specification change does apply listed stepping. Shaded: This item either modified from previous version document.
PLANS
SPECIFICATION CHANGES Modify Abort Disable Test Mode Configuration Bits Register [30:29] Modify MD[63:0] [Control2] MECC [7:0] [Control bits Register CACCh [20,17] Non-Supported SDRAM Memory Configuration Modify Input/Output Data Mask A/B-Side Data Buffer Strength Programming Register CA-CCh [6:2] Modify Memory Buffer Strength Terminology Register 69-6Eh Incease Supported Memory Configurations
PLANS SDRAM Suspend Refresh
ERRATA
Specification Update
Intel® 82443GX AGPset Specification Update
PLANS
SPECIFICATION CLARIFICATIONS Function with Registered DMMs Memory Initialization with Enabled Normal Refresh Enable DCLKO State During POS/STR Mulit-bit Memory Error Clarification
PLANS
DOCUMENTATION CHANGES Correction 82443GX Alphabetical List (Table 5-1) Correction SERR# Type
Specification Update
Intel® 82443GX AGPset Specification Update
Specification Changes
Modify Abort Disable Test Mode Configuration Bits Register [30:29]
Intel Reserved Register bits offset F4h, bits should normal operation.
Modify MD[63:0] [Control2] MECC [7:0] [Control bits Register CA-CCh [20,17]
Reserved programming bits register CA-CCh valid buffer programming options. These bits programming 100MHz 100MHz shown below:
Bits
Description
[63:0] [Control This enables 100Mhz buffers [63:0] [Control (Refer corresponding MBSC register programming details). 100MHz 100MHz
Bits
Description
MECC [7:0] [Control This enables either 100Mhz buffers MECC [7:0] [Control (Refer corresponding MBSC register programming details). 100MHz 100MHz
Non-Supported SDRAM Memory Configuration
memory configuration using SDRAM memory type 128Mbit 32Mx4 with rows columns supported Intel 82443GX AGPset. This support been removed because these SDRAM (13x10 128Mbit) devices planned production memory vendors.
Specification Update
Intel® 82443GX AGPset Specification Update
Modify Input/Output Data Mask A/B-Side Data Buffer Strength Programming Register CA-CCh [6:2]
Characterization Input/Output Data Mask A/B-Side Data buffers shown that actual buffers stronger than simulated buffer strengths. result, buffer strength settings recommended order improve system noise margin, shown below:
Bits
Description DQMA5. This enables 100MHz buffers DQMA5. 100MHz 100MHz
DQMA1. This enables 100MHz buffers DQMA1. 100MHz 100MHz This enables 100MHz buffers DQMB5. 100MHz 100MHz This enables 100MHz buffers DQMB1. 100MHz 100MHz This enables 100MHz buffers DQMA[7:6], DQMA[4:2],
DQMB5.
DQMB1.
DQMA[7:6,4:2,0]. DQMA[0].
100MHz 100MHz
Modify Memory Buffer Strength Terminology Register 69-6Eh.
Previous changes Register CA-CCh (for example, Specification Changes above) require similar changes Register 69-6Eh. result, Register 69-6Eh changes shown below. These changes match "100MHz "100MHz terminology found Register CA-CCh.
35:34
[63:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MD[63:0] path that connected DIMM2 DIMM3. buffer strength programmable based upon SDRAM load detected DIMM slots 2&3. This path enabled when FENA asserted (High) Intel® 82443GX AGPset.
DIMM non-FET Configuration: This field should programmed same value MD[63:0] Buffer Strength Control This buffer strength programmable based upon SDRAM load detected DIMM connectors.
Specification Update
Intel® 82443GX AGPset Specification Update
Buffer Strength Invalid setting
Value 33:32
Reserved only
[63:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MD[63:0] path that connected DIMM0 DIMM1. buffer strength programmable based upon SDRAM load detected DIMM slots 0&1. This path enabled when FENA de-asserted (Low) Intel® 82443GX AGPset.
DIMM non-FET Configurations: buffer strength programmable based upon SDRAM load detected DIMM connectors.
Value 31:30
Buffer Strength Invalid setting
Reserved only
MECC [7:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MECC[7:0] path that connected DIMM2 DIMM3 buffer strength programmable based upon SDRAM load detected DIMM slots 2&3. This path enabled when FENA asserted (High) Intel® 82443GX AGPset.
DIMM non-FET Configurations: This field should programmed same value MECC[7:0] Buffer Strength Control This buffer strength programmable based upon SDRAM load detected DIMM connectors.
Value 29:28
Buffer Strength Invalid setting
Reserved only
MECC [7:0] Buffer Strength Control DIMM Configuration: This field sets buffer strength MECC[7:0] path that connected DIMM0 DIMM1. buffer strength programmable based upon SDRAM load detected DIMM slots 0&1. This path enabled when FENA de-asserted (Low) Intel® 82443GX AGPset.
DIMM non-FET Configuration: buffer strength programmable based upon SDRAM load detected DIMM slots.
Specification Update
Intel® 82443GX AGPset Specification Update
Value 13:12 Buffer Strength Invalid setting
Reserved only
DQMA5 Buffer Strength This field sets buffer strength DQMA5 pins.
Value
Buffer Strength Invalid setting
Reserved only
11:10
DQMA1 Buffer Strength This field sets buffer strength DQMA1 pin.
Value
Buffer Strength Invalid setting
Reserved only
DQMB5 Buffer Strength This field sets buffer strength DQMB5 pin.
Value
Buffer Strength Invalid setting
Reserved only
DQMB1 Buffer Strength This field sets buffer strength DQMB1 pin.
Value
Buffer Strength Invalid setting
Reserved only
Specification Update
Intel® 82443GX AGPset Specification Update
DQMA[7:6,4:2,0] Buffer Strength This field sets buffer strength DQMA[7:6], DQMA[4:2], DQMA[0] pins.
Value
Buffer Strength Invalid setting
Reserved
Increase Supported Memory Configurations
Reference Intel® 440GX AGPset: 82443GX Host Bridge/Controller Datasheet, Order Number 290638-001, pages 4-17 4-18. 128Mbit technology 16MX8 components organized 32MX72 unbuffered DIMMs were tested Intel® 440GX AGPset validation platform passed tests. result, page 4-17 showing "Option" "SDRAM Component Type" Option changed follows: OPTION (128 SDRAM COMPONENT TYPE 16MX16, 16MX8, 16MX4
Also, Table 4-9, "Supported Memory Configurations", Technology 128Mb, bank section page 4-18 changed follows:
DRAM Attributes
DRAM DIMM
DRAM Addressing
DRAM Device
DRAM Size Banks row)
Type
Tech
Depth
Width
Rows
Cols
SDRAM
16Mb
128M
Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric Asymmetric
128MB 256MB 512MB
SDRAM
64Mb bank
SDRAM
128Mb bank
SDRAM
256Mb2 bank
Specification Update
Intel® 82443GX AGPset Specification Update
Errata
Problem:
SDRAM Suspend Refresh
This erratum occur Intel 440GX APGset chipset platforms that implement suspend Stop Clock (C3) states. Platforms that affected DIMM desktop platforms using GCKE. This platform requires Intel 440GX APGset memory controller stop normal refresh place SDRAM self-refresh mode before system transitions these states. selfrefresh trigger (SUSTAT1# signal asserted) occurs same time internally generated normal refresh request, 440GX generates incorrect GCKE CSAx#CSBx# signal sequence SDRAM. SDRAM placed self-refresh mode memory contents lost. DIMM desktop platforms affected. DIMM desktop platforms that GCKE also affected.
Implication:
observed effect erratum system hang, although data loss corruption theoretically possible.
Workaround: BIOS workaround: POS, POSCCL, POSCL, states workaround disables normal refresh prior entering these states before Intel® 82443GX AGPset automatically generates SDRAM self-refresh command. BIOS will re-enable normal refresh exit from these states. ACPI BIOS workaround (TBD): Status: Implement BIOS workaround.
Specification Update
Intel® 82443GX AGPset Specification Update
Specification Clarifications
Function with Registered DIMMs
stacking technology used registered DIMMs prohibits function. registered DIMMs, components stacked another. stacked components physically same row, logically separate rows. stacked components connect pins together, except pin, order address components different rows. Since pins components connected together, components logically different rows, function supported.
Memory Initialization with Enabled
82440GX ACPset systems using memory, memory must initialized with enabled (NBXCFG bits through bits errors received during initialization should ignored.
Normal Refresh Enable
When user performs soft reset, PIIX4 will drive SUS_STAT1# Intel® 82443GX AGPset. This will force Intel® 82443GX AGPset switch suspend refresh state. When BIOS attempts execute cycles DRAM, Intel® 82443GX AGPset will accept these cycles because believes that suspend state After coming reset software must Normal refresh enable (bit Power management control register Offset 7Ah) Intel® 82443GX AGPset before doing access memory.
DCLKO State During POS/STThe state DCLKO during POS/STR high low. result, designs implementing POS/STR should move CKBF component same VCC3 plane Intel® 82443GX AGPset component.
Multi-bit Memory Error Clarification
When Intel 440GX AGPset platform configured support, multi-bit uncorrectable memory error detected during memory read system device, SERR, SCI, will generated. This typically results NMI, however data still reach intended target before generated before interrupt handler service problem. This result data being returned target permanently stored, resulting system data corruption. This chipset architected designed ensure that targets protected from this corrupted data these situations.
Specification Update
Intel® 82443GX AGPset Specification Update
Documentation Changes
Correction 82443GX Alphabetical List (Table 5-1)
Table MAB14 incorrectly referenced AE22. correct location Intel® 82443GX AGPset AE23.
Correction SERR# Type
Table 2-4, page 2-5, Intel® 440GX AGPset: 82443GX Host Bridge/Controller Datasheet, Order Number 290638-001, shows SERR# type I/O. This correct. SERR# type
Specification Update
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