Design Guide Update Notice: Intel® 440LX AGPset contain design de

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Design Guide Update Notice: Intel® 440LX AGPset contain design de

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Pentium® Processor/ Intel® 440LX AGPset
Design Guide Update
Notice: Intel® 440LX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update. Order Number: 290642-002
Intel® 82443LX
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® 440LX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. *Third-party brands names property their respective owners. Copyright Intel Corporation 1998, 1999
Design Guide Update
Intel® 82443LX
Contents
Revision History. Preface General Design Considerations Schematic, Layout Routing Updates Documentation Changes.
Design Guide Update
Intel® 82443LX
Revision History
Rev. Initial Release Added General Design Consideration Draft/Changes Date August 1998
Design Guide Update
Intel® 82443LX
Preface
This document update specifications contained Intel® Pentium® processor/440LX AGPset Design Guide 1.0, April 1998, order number 297651-001. References also made following documents: Intel® 440LX AGPset: 82443LX (PAC) datasheet section, 82371AB (PIIX4) datasheet section Platform Components data book, order number 296467-009. intended hardware system manufacturers software developers applications, operating systems, tools. This design guide primarily targeted market segment first published 1998. Those using this design guide should check device availability before designing components included this document
Nomenclature
General Design Considerations includes system level considerations that system designer should account when developing hardware software products using Intel® 82440LX AGPset. Schematic, Layout Routing Updates include suggested changes current published schematics layout, including typos, errors, omissions from current published documents. Documentation Changes include suggested changes current published design guide including above.
Design Guide Update
Intel® 82443LX
Summary Table Changes
following table indicates Specification Changes, Errata, Specification Clarifications Documentation Changes, which apply listed Intel® 440LX AGPset stepping. Intel intends some errata future stepping component account other outstanding issues through documentation Specification Changes noted. This table uses following notations: Codes Used Summary Table Doc: Shaded: Document change update that will implemented. This item either modified from previous version document.
Plans
GENERAL DESIGN CONSIDERATIONS Implementing RESET BUTTON Desktop Based Systems SLP# Connectivity Multi-processor Systems
Plans
SCHEMATIC, LAYOUT ROUTING UPDATES Guidelines minimize events that cause loss CMOS contents. Correct Strapping FDC37C932FR Ultra device VBAT pin.
Plans
DOCUMENTATION CHANGES Section 6.2.18, Ultra Support
Design Guide Update
Intel® 82443LX
General Design Considerations
Implementing RESET BUTTON Desktop Based Systems
following should considered when implementing RESET BUTTON desktop-based systems: system reset button typically been connected indirectly PWROK input PiiX4/PiiX4E. This technique will reset suspend well logic, which includes SMBus Host Slave controllers. reset hardware suspend well, reset button should connected RSMRST# input PIIX4/PIIX4E. Assertion RSMRST#, reset button, will result complete system reset. RSMRST# assertion will cause SUS[A-C]# assert which results deassertion PWROK SUS[A-C]# controls power supply PS-ON control signal. deassertion PWROK will cause PIIX4/PIIX4E assert PCIRST#, RSTDRV, CPURST.
SLP# Connectivity Multi-processor Systems
multi-processor systems using PiiX4/PiiX4E, SLP# signal asserted processors before processor sleep state therefore acknowledged. This could result wakeup problem. Specifically, PiiX4/PiiX4E based platforms, STPCLK# from PiiX4E connected processors, SLP# from PiiX4E connected processors. following sequence occurs: writes PMCNTRL register PiiX4E asserts STPCLK#, then waits Stop Grant processor acknowledges with Stop Grant Acknowledge PiiX4E asserts SLP# after receiving Stop Grant Acknowledge
While this sequence works uni-processor systems, processors into Processor Sleep State State during ACPI state. This means that SLP# signal must connected processor multi-processor systems. Note that disabling SLEEP_EN PiiX4E Processor Control register accecptable workaround this issue since this only controls SLP# assertion state, state.
Design Guide Update
Intel® 82443LX
Schematic, Layout Routing Updates
Guidelines Minimize Events That Cause Loss CMOS Contents
Recommendations Board Designs: Provide dielectric, monolithic, ceramic capacitor between VCCRTC PIIX4/PIIX4E ground plane. This capacitor's positive connection should stubbed trace must close possible PIIX4/PIIX4E. capacitor must further than inch from PIIX4/PIIX4E. stub required, should kept maximum length. ground connection should made through ground plane, with minimal trace between capacitor via. Place battery, series current limit resistor, common-cathode isolation diode very close PIIX4/PIIX4E. this possible, place common-cathode diode resistor close capacitor possible. place these components between capacitor PIIX4. battery placed remotely from PIIX4/PIIX4E. boards that have chassis-intrusion utilizing external logic powered VCCRTC pin, place inverters close common-cathode diode possible. this possible, keep trace near center board. Keep PIIX4/PIIX4E VCCRTC trace away from board edge. this trace must from opposite ends board, keep trace towards board center, away from board edge where contact could made people equipment that handle board.
Recommendations Existing Board Designs: effectiveness adding capacitor, identified above, needs determined examining routing placement. example, placing capacitor from PiiX4 reduces effectiveness.
Correct Strapping FDC37C932FR Ultra Device VBAT
When PIIX4/PIIX4E internal used, Ultra device, FDC37C932FR, VBAT must connected ground through between pulldown resistor.
Design Guide Update
Intel® 82443LX
Documentation Changes
Design Checklist, section 6.2.18, Ultra Support
section will added section described below. "When PIIX4/PIIX4E internal used, ensure that VBAT Ultra device, FDC37C932FR, connected ground through between pulldown resistor. Consult your device vendor implementation guidelines this other devices."
Design Guide Update
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Design Guide Update Notice: Intel® 440LX AGPset contain design de

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