Specification Update Notice: Intel 82443BX AGPset contain design

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Specification Update Notice: Intel 82443BX AGPset contain design

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Intel® 440BX AGPset: 82443BX Host Bridge/Controller
Specification Update
Notice: Intel 82443BX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata documented this Specification Update. Document Number: 290639-006
Intel 82443BX
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel 82443BX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation www.intel.com call 1-800-548-4725 *Other names brands claimed property others. Copyright 1998-2001, Intel Corporation
Specification Update
Intel 82443BX
Contents
Revision History. Preface Specification Changes. Errata. Specification Clarifications Documentation Changes.
Specification Update
Intel 82443BX
Revision History
Rev. -001 -002 -003 -004 -005 -006 Initial Release Added Specification Changes Added Specification Changes Stepping Information Added Documentation Change Added Documentation Change Renumbered Specifiation Changes added Specification Changes 5B-12, Renumbered Errata added errata 1-9. Added Specification Clarifications 1-11. Renumbered Documentation Changes added Documentation Changes 1-2. Draft/Changes Date 1998 July 1998 October 1998 November 1998 April 1999
Specification Update
Intel 82443BX
Preface
This document update specifications contained documents listed following Affected Documents/Related Documents table. compilation device document errata specification clarifications changes, intended hardware system manufacturers software developers applications, operating system, tools. Information types defined Nomenclature section this document consolidated into this update document longer published other documents. This document also contain information that been previously published. Affected Documents/Related Documents
Document Title Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet 82443BX Host Bridge/Controller Electrical Thermal Timing Specification datasheet addendum Document Number 290633-001 273219-002
Nomenclature
Specification Changes modifications current published specifications. These changes will incorporated next release specifications. Errata design defects errors. Errata cause Intel® 82443BX, behavior deviate from published specifications. Hardware software designed used with given stepping must assume that errata documented that stepping present devices. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications.
Specification Update
Intel 82443BX
Component Identification Programming Interface
Intel® 82443BX identified following register contents:
Stepping Vendor 8086h 8086h 8086h 8086h 8086h Device 7190h/7192h 7190h/7192h 7190h/7192h 7190h/7192h 7190h/7192h Revision Number3 (note
NOTES: Vendor corresponds bits 15-0 Vendor Register located offset 00-01h function configuration space. Device corresponds bits 15-0 Device Register located offset 02-03h function configuration space. default value 7190h. When disabled, value 7192h. Revision Number corresponds bits Revision Register located offset function configuration space. step device never entered production. result step revision number remains 03h.
Component Marking Information
Intel 82443BX identified following component markings:
Stepping S-Spec Marking FW82443BX Q575ES FW82443BX Q575ES Q607ES-100 FW82443BX Q607ES-100 FW82443BX Q575ES Q608ES-66 FW82443BX Q608ES-66 FW82443BX Q578ES FW82443BX Q577ES FW82443BX Q579ES FW82443BX Q628ES Freq. 100/66 Notes Engineering Sample, Test Engineering Sample, Test Remarked Q575ES with Q607ES-100 Engineering Sample, Test Engineering Sample, Test Remarked Q575ES with Q608ES-66 Engineering Sample, Test Engineering Sample, Test Engineering Sample, Test Engineering Sample, Test with Burn-In Engineering Sample, Test
100/66 100/66 100/66 100/66
Specification Update
Intel 82443BX
Stepping
S-Spec
Marking FW82443BX Q629ES FW82443BX Q630ES
Freq. 100/66 100/66 100/66 100/66 100/66 100/66 100/66
Notes Engineering Sample, Test Engineering Sample, Test with Burn-In Full Production Flow 82443BX Production ASSY 82443BX Remnants 82443BX Production ASSY 82443BX Production ASSY 82443BX Remnants
SL2T5 SL2T6 SL2VH SL2VH
FW82443BX SL2T5 FW82443BX SL2T6 FW82443BX SL2VH FW82443BX SL2VH FW82443BX SL378
SL378
NOTES: Pound signs (######) used over "Q57ES" components instead "strike-through" lines that shown. Step SL2VH device never entered production never sampled customers. result, step S-Spec remains SL2VH.
Specification Update
Intel 82443BX
Summary Table Changes
following table indicates Specification Changes, Errata, Specification Clarifications Documentation Changes which apply listed Intel 82443BX steppings. Intel intends some errata future stepping component account other outstanding issues through documentation Specification Changes noted. This table uses following notations: Codes Used Summary Table Doc: Fix: Fixed: NoFix Erratum, Specification Change Clarification that applies this stepping. Document change update that will implemented. This erratum intended fixed future stepping component. This erratum been previously fixed. There plans this erratum.
mark) (Blank Box): This erratum fixed listed stepping specification change does apply listed stepping. Shaded: This item either modified from previous version document.
Number
Steppings
SPECIFICATION CHANGES
Configuration Register 50-53, Bits 13(1) Reads Outside Aperture(1) Memory Buffer Strength Control Register Memory Buffer Frequency Select Register Processor Lock Time Affects Intel® 82443BX DRAM Write Thermal Throttling Control Register DRAM Read Thermal Throttling Control Register Error Command Register Error Status Register DCLKRD (Pin AB22) Changed Connect(1) Reserved Straps MAB13 Polarity Change SERR# Target Abort(1) Abort Disable Test Mode Configuration Bits Selective Auto Precharge
Specification Update
Intel 82443BX
Number
Steppings
SPECIFICATION CHANGES
Memory Data Buffer Strength Programming Intel® 82443BX Host Bridge/Controller NAND Tree Testing GTL+Termination Voltage (Mobile Only) Undershoot Specification Changed -750 (Mobile Only)
NOTES: This specification change been incorporated into Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet, been removed from this document. Number Steppings Locked Cycle Retry Error Address Pointer Register Read/Write Cycles with Auto Precharge Enabled Global SMRAM Enable MAB11# during Command Memory Read Line Operation Snoop Ahead Power Dissipation Hard Reset Collision with Refresh IPDLT Setting SDRAM Suspend Refresh Refresh Collision with SUS_STAT# Assertion (EDO Memory) Plans ERRATA
Specification Update
Intel 82443BX
Number Normal Refresh Enable
SPECIFICATION CLARIFICATIONS
Function with Registered DIMMs Memory Initialization with Enabled DCLKO State during POS/STR DCLKRD Connected NAND Chain Modifying DRAM Configuration Registers during DRAM Cycles Side Band Addressing Signals Float before Enable 128-Mbit Technology SDRAM Memory HCLKIN Lead Time PCLKIN Timing MBSC Memory Buffer Strength Control Register (Device Address Offset 69-6Eh Multi-Bit Memory Error Clarification
Number
DOCUMENTATION CHANGES Correct Intel® 82443BX Simplified Block Diagram Note Table Page iii, Features List Changed
Specification Update
Intel 82443BX
Specification Changes
Configuration Register 50-53, Bits
This specification change been incorporated into Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet.
Reads Outside Aperture
This specification change been incorporated into Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet.
Memory Buffer Strength Control (MBSC) Register
following register definition B-0, steppings 82443BX. MBSCMemory Buffer Strength Control Register Address Offset: 69-6Eh Default Value: 000000000000h Access: Read/Write This register programs various DRAM interface signal buffer strengths, based non-mixed memory configurations DRAM type (EDO SDRAM), DRAM density (x8, x16, x32), DRAM technology Mb), rows populated. Note that DRAM only supported when used registered DIMMs.
47:40 39:38 Reserved
Description
MAA[13:0], WEA#, SRASA#, SCASA# Buffer Strengths. This field sets buffer strength MAA[13:0], WEA#, SRASA#, SCASA# pins. Value Buffer Strength Reserved Invalid setting
37:36
MAB[13:11, 9:0]# MAB10, WEB#, SRASB#, SCASB# Buffer Strengths. This field sets buffer strength MAB[13:11, 9:0]# MAB10, WEB#, SRASB#,SCASB# pins. Note: address's MAB[13:11, 9:0]# inverted copies MAA[13:0], with exception MAB10. Value Buffer Strength Reserved Invalid setting
Specification Update
Intel 82443BX
35:34 [63:0] Buffer Strength Control
Description
DIMM (FET) Configuration: This field sets buffer strength MD[63:0] path that connected DIMM2 DIMM3. buffer strength programmable based upon SDRAM load detected DIMM slots 2&3. This path enabled when FENA asserted (High) 443BX. DIMM DIMM FET)Configuration: This field should programmed same value MD[63:0] Buffer Strength Control This buffer strength programmable based upon SDRAM load detected DIMM connectors. Value 33:32 Buffer Strength Reserved Invalid setting Only
[63:0] Buffer Strength Control DIMM (FET) Configuration: This field sets buffer strength MD[63:0] path that connected DIMM0 DIMM1. buffer strength programmable based upon SDRAM load detected DIMM slots 0&1. This path enabled when FENA de-asserted (Low) 443BX. DIMM DIMM FET) Configuration: buffer strength programmable based upon SDRAM load detected DIMM connectors. Value Buffer Strength Reserved Invalid setting Only
31:30
MECC [7:0] Buffer Strength Control DIMM (FET) Configuration: This field sets buffer strength MECC[7:0] path that connected DIMM2 DIMM3 buffer strength programmable based upon SDRAM load detected DIMM slots 2&3. This path enabled when FENA asserted (High) 443BX. DIMM DIMM FET)Configuration: This field should programmed same value MECC[7:0] Buffer Strength Control This buffer strength programmable based upon SDRAM load detected DIMM connectors. Value Buffer Strength Reserved Invalid setting Only
29:28
MECC [7:0] Buffer Strength Control DIMM (FET) Configuration: This field sets buffer strength MECC[7:0] path that connected DIMM0 DIMM1. buffer strength programmable based upon SDRAM load detected DIMM slots 0&1. This path enabled when FENA de-asserted (High) 443BX. DIMM DIMM FET) Configuration: buffer strength programmable based upon SDRAM load detected DIMM slots. Value Buffer Strength Reserved Invalid setting Only
Specification Update
Intel 82443BX
27:26
Description CSB7#/CKE5 Buffer Strength. This field sets buffer strength CSB7#/CKE5 pins. Value Buffer Strength Reserved Invalid setting
25:24
CSA7#/CKE3 Buffer Strength. This field sets buffer strength CSA7#/CKE3 pins. Value Buffer Strength Reserved Invalid setting
23:22
CSB6#/CKE4 Buffer Strength. This field sets buffer strength CSB6#/CKE4 pins. Value Buffer Strength Reserved Invalid setting
21:20
CSA6#/CKE2 Buffer Strength. This field sets buffer strength CSA6#/CKE2pins. Value Buffer Strength Reserved Invalid setting
CSA5#/RASA5#, CSB5#/RASB5# Buffer Strength. This field sets buffer strength CSA5#/RASA5#, CSB5#/RASB5# pins. Value Buffer Strength
CSA4#/RASA4#, CSB4#/RASB4# Buffer Strength. This field sets buffer strength CSA4#/RASA4#, CSB4#/RASB4# pins. Value Buffer Strength
CSA3#/RASA3#, CSB3#/RASB3# Buffer Strength. This field sets buffer strength CSA3#/RASA3#, CSB3#/RASB3# pins. Value Buffer Strength
CSA2#/RASA2#, CSB2#/RASB2# Buffer Strength. This field sets buffer strength CSA2#/RASA2#, CSB2#/RASB2# pins. Value Buffer Strength
Specification Update
Intel 82443BX
Description CSA1#/RASA1#, CSB1#/RASB1# Buffer Strength. This field sets buffer strength CSA1#/RASA1#, CSB1#/RASB1# pins. Value Buffer Strength
CSA0#/RASA0#, CSB0#/RASB0# Buffer Strength. This field sets buffer strength CSA0#/RASA0#, CSB0#/RASB0# pins. Value Buffer Strength
13:12
DQMA5/CASA5# Buffer Strength. This field sets buffer strength DQMA5/CASA5# pins. Value Buffer Strength Reserved Invalid setting Only
11:10
DQMA1/CASA1# Buffer Strength. This field sets buffer strength DQMA1/CASA1# pin. Value Buffer Strength Reserved Invalid setting Only
DQMB5/CASB5# Buffer Strength. This field sets buffer strength DQMB5/CASB5# pin. Value Buffer Strength Reserved Invalid setting Only
DQMB1/CASB1# Buffer Strength. This field sets buffer strength DQMB1/CASB1# pin. Value Buffer Strength Reserved Invalid setting Only
Buffer Strength. This field sets buffer strength DQMA[7:6]/CASA[7:6]#, DQMA[4:2]/CASA[4:2]#, DQMA[0]/CASA[0]# pins. Value Buffer Strength Reserved Invalid setting
Specification Update
Intel 82443BX
Description CKE1/GCKE Buffer Strength. This field sets buffer strength CKE1 pin. Value Buffer Strength Reserved Invalid setting
CKE0/FENA Buffer Strength. This field sets buffer strength CKE0/FENA pin. Value Buffer Strength Reserved Invalid setting
Memory Buffer Frequency Select (MBFS) Register
following register definition B-0, steppings 82443BX. MBFSMemory Buffer Frequency Select Register Address Offset: Default Value: Access: CA-CCh 000000h Read/Write
settings this register enable buffers each following signal groups. example: Setting MBFS equal enables selection buffers (1x, MAA[13:0], WEA#, SRASA#, SCASA#. MBFS equals then buffers (1x, enabled MAA[13:0], WEA#, SRASA#, SCASA#. actual buffer strength (1x, determined settings MBSC register specific signal group.
Reserved MAA[13:0], WEA#, SRASA#, SCASA# (100 buffer select bit). This enables either buffers following signals: MAA[13:0], WEA#, SRASA#, SCASA#. Value Buffer Description
MAB[13:11, 9:0]# MAB10, WEB#, SRASB#, SCASB# (100 buffer select bit). This enables either buffers following signals: MAB[13:11, 9:0]# MAB10, WEB#, SRASB#, SCASB#. Note: address's MAB[13:11, 9:0]# inverted copies MAA[13:0], with exception MAB10. Value Buffer
Specification Update
Intel 82443BX
Description [63:0] (100 buffer select [Control 2]). This enables either buffers following signals: [63:0] [Control (Refer corresponding MBSC register programming details). Value Buffer
[63:0] (100 buffer select [Control 1]). This enables either buffers following signals: [63:0] [Control (Refer corresponding MBSC register programming details). Value Buffer
MECC [7:0] (100 buffer select [Control 2]). This enables either buffers following signals: MECC [7:0] [Control (Refer corresponding MBSC register programming details). Value Buffer
MECC [7:0] (100 buffer select [Control 1]). This enables either buffers following signals: MECC [7:0] [Control (Refer corresponding MBSC register programming details) Value Buffer
CSB7#/CKE5 (100 buffer select bit). This enables either buffers following signals: CSB7#/CKE5. Value Buffer
CSA7#/CKE3 (100 buffer select bit). This enables either buffers following signals: CSA7#/CKE3. Value Buffer
CSB6# CKE4 (100 buffer select bit). This enables either buffers following signals: CSB6# CKE4. Value Buffer
CSA6# CKE2 (100 buffer select bit). This enables either buffers following signals: CSA6# CKE2. Value Buffer
CSA5# RASA5#,CSB5# RASB5# (100 buffer select bit). This enables either buffers following signals: CSA5#/RASA5#, CSB5#/RASB5#. Value Buffer
Specification Update
Intel 82443BX
Description CSA4#/RASA4#, CSB4#/RASB4# (100 buffer select bit). This enables either buffers following signals: CSA4#/RASA4#, CSB4#/RASB4#. Value Buffer
CSA3#/RASA3#, CSB3#/RASB3# (100 buffer select bit). This enables either buffers following signals: CSA3#/RASA3#, CSB3#/RASB3#. Value Buffer
CSA2#/RASA2#, CSB2#/RASB2# (100 buffer select bit). This enables either buffers following signals: CSA2#/RASA2#, CSB2#/RASB2#. Value Buffer
CSA1#/RASA1#, CSB1#/RASB1# (100 buffer select bit). This enables either buffers following signals: CSA1#/RASA1#, CSB1#/RASB1#. Value Buffer
CSA0#/RASA0#, CSB0#/RASB0# (100 buffer select bit). This enables either buffers following signals: CSA0#/RASA0#, CSB0#/RASB0#. Value Buffer
DQMA5/CASA5# (100 buffer select bit). This enables either buffers following signals: DQMA5/CASA5#. Value Buffer
DQMA1/CASA1# (100 buffer select bit). This enables either buffers following signals: DQMA1/CASA1#. Value Buffer
DQMB5/CASB5# (100 buffer select bit). This enables either buffers following signals: DQMB5/CASB5#. Value Buffer
DQMB1/CASB1# (100 buffer select bit). This enables either buffers following signals: DQMB1/CASB1#. Value Buffer
Specification Update
Intel 82443BX
Description (100 buffer select bit). This enables either buffers following signals: DQMA[7:6]/CASA[7:6]#, DQMA[4:2]/CASA[4:2]#, DQMA[0]/CASA[0]#. Value Buffer
CKE1/GCKE (100 buffer select bit). This enables either buffers following signals: CKE1. Value Buffer
CKE0/FENA (100 buffer select bit). This enables either buffers following signals: CKE0/FENA. Value Buffer
Processor Lock Time Affects Intel 82443BX
82443BX requires minimum between deassertion CPU_STP# deassertion SUSTAT# processor exit. 82443BX requires minimum between deassertion CPU_STP# deassertion SUSTAT# cold boot.
DRAM Write Thermal Throttling Control Register
DRAM Write Throttling Control Register Offset: Default: Access: Size: E0h-E7h 0000_0000_0000_0000h Read/Write/Lock
DRAM Write Throttling Control register defines maximum sustained bandwidth writes DRAM which tolerated before throttling mechanism invoked. also specifies maximum DRAM write bandwidth that will permitted throttling mechanism. Both these bandwidths specified providing sampling period maximum number QWords which written sampling period. first bandwidth described specified Global DRAM Write Sampling Window (GDWSW) Global Threshold (GQT). Large values used GDWSW 1020 order allow short bursts writes peak bandwidth occur without invoking throttling. Once throttling mechanism invoked, QWords written DRAM counted during Throttle Monitoring Window (TMW), writes temporarily masked remainder number exceeds Throttle Maximum (TQM). Throttle Monitoring Window much smaller than Global Sampling window, programmable from 0-2048 clocks. This small window allows throttling implemented with minimal latency impact. This register also defines Throttle Time, which measured multiple Global DRAM Write Sampling Windows. Throttle Time amount time that throttling mechanism remains
Specification Update
Intel 82443BX effect after being triggered. Once throttle time expired, Intel 440BX AGPset returns GDWSW determine throttling must invoked again. locking mechanism included protect contents this register well DRAM read throttling control register described below.
Bits Description Throttle Lock (TLOCK). This secures DRAM throttling control registers. defaults `0', then once written configuration register bits E0h-E7h E8h-EFh (read throttle control) become read-only. Reserved Global DRAM Write Sampling Window (GDWSW). This eight value multiplied define length time milliseconds (0-1020) over which number QWords written counted. number written during this window exceeds Global Threshold defined below, then throttling mechanism will invoked limit DRAM writes lower bandwidth checked over smaller time windows. Global Threshold (GQT). twelve-bit value held this field multiplied arrive number that must written within Global DRAM Write Sampling Window order cause throttling mechanism invoked. Throttle Time (TT). This value provides multiplier between which specifies long throttling remains effect number Global DRAM Write Sampling Windows. example, GDWSW programmed 1000_0000b 01_0000b, then throttling will performed seconds once invoked (128 Throttle Monitoring Window (TMW). value this register padded with four specify window 0-2047 DRAM CLKs with clock granularity. While throttling mechanism invoked, DRAM writes monitored during this window-if number written during window reaches Throttle Maximum, then write requests blocked remainder window. Throttle QWord Maximum (TQM). Throttle QWord Maximum defines maximum number QWords between 0-1023 which permitted written DRAM within Throttle Monitoring Window while throttling mechanism effect. Reserved
62:46 45:38
37:26
25:20
19:13
12:3
DRAM Read Thermal Throttling Control Register
DRAM Read Throttling Control Register Offset: Default: Access: Size: E8h-EFh 0000_0000_0000_0000h Read/Write/Lock
DRAM Read Throttling Control register defines maximum sustained bandwidth reads DRAM which tolerated before throttling mechanism invoked. also specifies maximum DRAM read bandwidth that will permitted throttling mechanism. Both these bandwidths specified providing sampling period maximum number QWords which read sampling period. first bandwidth described specified Global DRAM Read Sampling Window (GDRSW) Global Read Threshold (GQRT). Large values used GDRSW ms-1020 order allow short bursts reads peak bandwidth occur without invoking throttling.
Specification Update
Intel 82443BX Once throttling mechanism invoked, Q-words read from DRAM counted during Read Throttle Monitoring Window (RTMW), traffic temporarily masked remainder RTMW number exceeds Read Throttle Maximum (RTQM). Read Throttle Monitoring Window much smaller than Global Sampling window, programmable from 0-2048 clocks. This small window allows throttling implemented with minimal latency impact. This register also defines Read Throttle Time, which measured multiple Global DRAM Read Sampling Windows. Read Throttle Time amount time that throttling mechanism remains effect after being triggered. Once read throttle time expired, returns GDRSW determine throttling must invoked again. contents this register protected making bits read-only once written Throttle Lock (bit config register E0-E7h).
Bits 63:46 45:38 Reserved
Description
Global DRAM Read Sampling Window (GDRSW). This eight value multiplied define length time milliseconds (0-1020) over which number QWords read from DRAM counted. number read during this window exceeds Global Threshold defined below, then throttling mechanism will invoked limit DRAM reads lower bandwidth checked over smaller time windows. Global Read Threshold (GRQT). twelve-bit value held this field multiplied arrive number that must written within Global DRAM Read Sampling Window order cause throttling mechanism invoked. Read Throttle Time (RTT). This value provides multiplier between which specifies long read throttling remains effect number Global DRAM Read Sampling Windows. example, GDRSW programmed 1000_0000b 01_0000b, then read throttling will performed seconds once invoked (128 Read Throttle Monitoring Window (RTMW). value this register padded with specify window 0-2047 DRAM CLKs with clock granularity. While throttling mechanism invoked, DRAM reads monitored during this window-if number read during window reaches Throttle Maximum, then Host read requests, well requests, blocked remainder window. Read Throttle QWord Maximum (RTQM). Read Throttle Q-word Maximum defines maximum number QWords between 0-1023 which permitted read from DRAM within Read Throttle Monitoring Window while throttling mechanism effect. Reserved
37:26
25:20
19:13
12:3
Specification Update
Intel 82443BX
Error Command Register
ERRCMDError Command Register This existing register. used enable SERR# generation when throttling conditions met. other fields remain unchanged. Address Offset: Default Value: Access: Size: Read/Write bits
This 8-bit register controls Intel 440BX AGPset responses various system errors. actual assertion SERR# enabled Command register.
Description SERR# Non-snoopable Access Outside Graphics Aperture. When this ERRSTS registers transitions from (during access address outside graphics aperture) then SERR# assertion event will generated. this then reporting this condition disabled. Default=1 SERR# Invalid DRAM Access. non-snoopable READ accesses locations outside graphics aperture outside main DRAM range (i.e., range above memory) invalid. Consider scenario when agent generates READ access using enhanced protocol, which 82443BX must accept without qualification from address decode logic since there protocol mechanism reject When this set, ERRSTS will SERR# will asserted these read accesses directed main memory aperture range. this then reporting this condition SERR# disabled. SERR# Access Invalid Graphics Aperture Translation Table Entry. When this 82443BX will ERRSTS assert SERR# following read write access invalid entry Graphics Aperture Translation Table residing main memory. this then reporting this condition SERR# disabled. SERR# Receiving Target Abort. When this 82443BX asserts SERR# upon receiving target abort either PCI0. When this 82443BX does assert SERR# upon receipt target abort. SERR# Detected Power Throttling Condition. When this 82443BX asserts SERR# when power throttling condition detected either read write function. When this 82443BX does assert SERR# power throttling. SERR# assertion mode. When this (default), SERR# asserted clock (standard mode). When this SERR# becomes level mode signal. Systems that connect SERR# EXTSMI# error reporting should this SERR# Receiving Multiple-Bit ECC/Parity Error. When this 82443BX asserts SERR# when detects multiple-bit error reported DRAM controller. systems supporting this must disabled. SERR# Receiving Single-bit Error. When this 82443BX asserts SERR# when detects single-bit error. systems that support this must disabled.
Specification Update
Intel 82443BX
Error Status Register
ERRSTSError Status Register This existing register which bits 12:11 used reflect when read write throttling conditions met. other fields remain unchanged. Address Offset: Default Value: Access: Size: 91-92h 0000h Read Only, Read/Write Clear bits
SERR# generated zero transition these flags enabled ERRCMD register).
15:13 Reserved. Read throttling condition. When this indicates that read throttling condition occurred. Software write clear this bit. Default=0 Write throttling condition. When this indicates that write throttling condition occurred. Software write clear this bit. Default=0 AGP. non-snoopable access outside Graphics Aperture. When this set, indicates that access occurred address that outside graphics aperture range. Software write clear this bit. Default=0 Invalid non-snoopable DRAM read access (R/WC). When this indicates that non-snoopable READ access attempted outside graphics aperture outside main memory (i.e., range above memory). Software must write clear this status bit. Access Invalid Graphics Aperture Translation Table Entry (AIGATT) (R\WC). When this indicates that invalid translation table entry returned response graphics aperture read write access. Software must write clear this bit. Multi-bit First Error (MBFRE) (RO). This field contains encoded value DRAM which first multi-bit error occurred. simple binary encoding used indicate containing multi-bit error: 000b indicates 001b through 111b indicating When error detected, this field updated set. This field will then locked further updates) until flag been reset. value this field undefined. Multiple-bit (uncorrectable) Error Flag (MEF) (R/WC). this memory data transfer uncorrectable error (i.e., multiple-bit error). When enabled, multiple error reported DRAM controller propagated SERR# pin, enabled ERRCMD register. BIOS write clear this unlock MBFRE field. Default value this zero. Single-bit First Error (SBFRE) (RO). This field contains encoded value DRAM which first single-bit error occurred. simple binary encoding used indicate containing single-bit error: 000b indicates 001b through 111b indicating When error detected, this field updated set. This field then locked further updates) until flag been reset. value this field undefined. Description
Specification Update
Intel 82443BX
Description Single-bit (correctable) Error Flag (SEF) (R/WC). this memory data transfer single-bit correctable error corrected data sent access. When enabled, single error reported propagated SERR# pin, enabled ERRCMD register. BIOS write clear this unlock SBFRE field.
DCLKRD (Pin AB22) Changed Connect
This specification change been incorporated into Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet.
Reserved Straps
MAB8# MAB13 have been defined "reserved" strapping options. function these straps currently undefined, reserved future use. These signals sampled during power reset. Internal pull down resistors default strap value `0'. Provisions should made motherboard external pull resistor option (i.e., resistor pads), resistor should populated.
MAB13 Polarity Change
step 82443BX, polarity B-copy memory address will changed from MAB13# MAB13 (see errata #5).
SERR# Target Abort
This specification change been incorporated into Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet.
Abort Disable Test Mode Configuration Bits
Intel Reserved Register bits offset F4h, bits should normal operation.
Selective Auto Precharge
inconsistent behavior selective auto precharge feature with different SDRAM components, this feature will removed from further revisions This specification change been incorporated into Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet Paging Policy register, Offset 78-79h should (default). Offset will become Intel Reserved location.
Memory Data Buffer Strength Programming
Characterization buffers shown that actual buffers stronger than simulated buffer strengths. result, buffer strength settings recommended order improve system noise margin.
Specification Update
Intel 82443BX
Intel® 82443BX Host Bridge/Controller NAND Tree Testing
This section provides information about NAND tree testability features Intel 82443BX. Test Mode Activation primary test mode enabled TESTIN# pin. enable NAND Tree primary test mode, TESTIN# input asserted 3-bit binary pattern presented PREQ[2:0]# input pins. Table shows PREQ[2:0]# signal encoding NAND tree test modes enabled TESTIN# pin. Table Primary Test Modes
PREQ[2:0]# Test Mode Enabled NANDtree NANDtree
Figure timing diagram shows sequence required enable primary test mode. Note that TESTIN# input acts latch enable, PREQ[2:0]# pins latch inputs. test mode decoded from output latch. Figure Waveform Primary Test Mode
50ns 100ns 150ns 200ns
Primary testmode activation without cold reset (toggling BXPWROK) DCLKWR BXPWROK PCIRST# TESTIN# PREQ[2:0]# Nandtree
Primary Test Mode
Nandtree
Specification Update
Intel 82443BX
Tester Power-Up Sequence
Figure shows typical power-up sequence 82443BX 256-pin tester. time PCIRST# TESTIN# must asserted. BXPWROK signal must also asserted indicate that cold reset progress. Once PCIRST# deasserted, fourth DCLKWR positive edge, TESTIN# also safely deasserted. PCIRST# TESTIN# should deassert same time because race condition prevents circuit from guaranteeing proper latching primary test modes. Figure Typical Power-Up Sequence
250ns 500ns 750ns 1000ns
Initial Powerup 256-pin DCLKW DCLKR GCLKI HCLKI PCLKI DCLKWR prds. BXPWRO DCLKWR PCIRST DCLKWR prds. TESTIN PREQ[2:0] Normal Operation
SUSTAT
suspend mode disabled long SUSTAT# remains deasserted Channel Enable
Primary Test Mode Async Tristate
Specification Update
Intel 82443BX
Primary Test Mode Details NANDtree
NANDtree test mode used board level connectivity test. main purpose detect connectivity shorts between adjacent pins check proper bonding between pads pins. help reduce board level test cost, NAND chain limited pins chain. This accomplished implementing separate NAND chains. conceptual diagram NANDtree shown Figure Figure NAND Chain Connectivity
Nand Chain 82443BX Inputs Outputs
HA21# HA6# SBA[7] SBA[6] SBA[5] SBA[4] HA4# SBA[3] SBA[2] AD21 SBA[1] SBA[0]
Specification Update
Intel 82443BX
example NANDtree test shown Figure first, input pins driven logic Next, each input driven logic sequence, that output pin, this case SBA[0], toggles. observing NANDtree output pin, detect shorted unconnected pins. Figure Waveform NAND Chain Test
500ns 1000ns
GGNT# GAD26 GAD24 CBE3# GAD30 GAD22 GAD20 GADSTB# GAD18 GSTOP# GAD28 CBE1# GAD12 GAD10 GAD8 GAD14 GAD6 GAD1 GAD4 GAD3 GAD2
Specification Update
Intel 82443BX
NAND chain assignments shown following tables. Table Signals Included NANDtree NANDtree
Signals BXPWROK PCIRST# TESTIN# Used cold reset Used cold warm reset Used enter NANDtree test modes Purpose
Table NANDtree Outputs
Signals SBA[0] SBA[1] SBA[2] SBA[3] SBA[4] SBA[5] SBA[6] SBA[7] NAND-Chain Output NAND-Chain Output NAND-Chain Output NAND-Chain Output NAND-Chain Output NAND-Chain Output NAND-Chain Output NAND-Chain Output Purpose
Legend Table When mode disabled, NANDtree chains also deactivated. When mode enabled, NAND chains active during NANDtree test mode. output NANDtree chains (when mode enabled) must always through chains respectively, before comes SBA[4] SBA[5]. mode MAB7# strap configuration controlling "mobile mode operation." When mode enabled lower order NAND tree chains paired groups also tested.
Specification Update
Intel 82443BX
Chain Name HA21# HA6# HA4# HA28# HA20# HA26# HA27# HA30# HA24# CPURST# HD32# HD33# HD37# HD434# HD40# HD36# HD35# HD44# HD34# HD47# HD42# HD38# HD51# HD49# HD54# HD48# HD45# HD59# HD39# HD53# HD60# HD55# HD63# HD41# Pad#
Chain Name HA15# HREQ0# HA18# HA23# HA31# BREQ0# HA10# HA22# HD1# HA11# HD2# HA29# HD4# HD0# HD3# HD8# HD5# HD9# HD6# HD7# HD10# HD12# HD14# HD15# HD17# HD11# HD18# HD13# HD20# HD16# HD21# HD19# HD22# HD25# Pad#
Chain Name GNT3# GNTO# AD19 AD17 AD11 C/BE2# AD15 STOP# DEVSEL# SERR# AD13 C/BEO# MD34 MD32 MD35 MD33 MD36 MD37 MD38 MD42 MD40 MD39 MD41 MD44 MD43 MD45 WEB# SCASA# Pad#
Chain Name AD30 AD24 TRDY# AD18 AD16 FRAME# IRDY# AD12 PLOCK# C/BE1# AD14 AD10 CLKRUN# WSC# SUSTAT# MD11 MD15 MD10 MECC0 Pad#
Specification Update
Intel 82443BX
Chain Name HD58# HD62# HD46# HD61# HD57# HD52# HD56# HD50# REQ1# REQ0# GNT2# PHOLD# AD31 AD29 AD25 GNTA4# AD27 AD23 AD21 Pad#
Chain Name HD23# HD26# HD29# HD27# HD31# HD29# HD24# HD30# GNT1# REQ4# PHLDA# REQ2# AD28 AD26 C/BE3# AD22 REQ3# AD20 PCLKIN Pad#
Chain Name DQMA4 MD46 MD47 SCASB# MAB0# MAB2# MAB4# MAB1# MAB5# MAB8# MAB9# MAB11# MAB12# MAB3# MAB13# MAB6# MAB7# MAB10 DCLKWR Pad#
Chain Name MD14 MECC1 MECC4 MD12 MECC5 WEA# MD13 DQMA0 CSA1# CSA2# CSA4# CSA3# SRASA# DQMA1 SCA5# CSA0# DQMA5 CKE0 SRASB# Pad#
Specification Update
Intel 82443BX
Chain Name DQMB1 DQMB5 CKE3 CKE2 CKE4 CSB1# CSB0# CSB2# CSB3# CSB5# DCLKO CSB4# Pad#
Chain Name MAA0 MAA2 MAA4 MAA6 MAA5 MAA8 MAA9 MAA1 MAA10 MAA3 MAA11 MAA12 CKE1 CKE5 MAA7 MAA13 DCLKRD* Pad#
*NOTE: Chain #A5, DCLKRD: This pad/pin part this chain stepping 82443BX. This pad/pin removed from chain stepping. This should only chain that fails 82443BX stepping 82443BX stepping NAND tree test used. pins tested after DCLKRD will give opposite data when testing 82443BX step device with 82443BX step NAND tree test. repair NAND tree test Chain #A5/#A9 (MMO enabled) 82443BX stepping, remove DCLCKRD from test invert expected data pins (MAA13, MAA7, CKE5, CKE1, MAA12, MAA11, MAA3, MAA10, MAA1, MAA9, MAA8, MAA5, MAA6, MAA4, MAA2, MAA0) which were tested following DCLKRD pin.
Specification Update
Intel 82443BX
Chain Name RBF# GREQ# PIPE# SB-STB GAD31 GAD29 GAD27 GAD23 GAD25 GAD17 GC/BE2# GFRAME# GTRDY# GAD21 GPAR GAD19 GAD15 GAD13 GDEVSEL# GAD11 GAD7 GC/BE0# GAD-STBA GAD5 GAD9 GAD0 Pad#
Chain Name GGNT# GCLKIN GAD26 GCLKO GAD24 GC/BE3# GAD30 GAD22 GAD20 GAD-STBB GAD16 GAD18 GSTOP# GIRDY# GAD28 GC/BE1# GAD12 GAD10 GAD8 GAD14 GAD6 GAD1 GAD4 GAD3 GAD2 Pad#
Specification Update
Intel 82443BX
Chain Name DQMA6 MECC2 DQMA7 MD50 MD48 MD49 MD51 MD59 MD52 MD53 MD54 MD55 MD57 MD58 MD56 MD61 MD62 MD63 CRESET# MD60 RS0# RS2# HREQ3# HREQ2# HREQ4# HREQ1# BPRI# BNR# HLOCK# HA5# HA14# HA13# ADS# HA16# HA19# HA25# Pad#
Chain Name Pad#
DQMA2 DQMA3 MECC7 MECC6 MECC3 MD16 MD17 MD18 MD19 MD21 MD20 MD22 MD23 MD24 MD25 MD27 MD28 MD29 MD26 MD31 MD30 RS1# HCLKIN HIT# DBSY# DEFER# HITM# DRDY# HTRDY# HA9# HA3# HA7# HA8# HA12# HA17#
Specification Update
Intel 82443BX Figure Waveform NANDtree Chain Pair
Nand Chain 82443BX Inputs Outputs
HA21# HA6# SBA[7] SBA[6] SBA[5] SBA[4] HA4# SBA[3] SBA[2] AD21 SBA[1] SBA[0]
Specification Update
Intel 82443BX
NANDtree
NANDtree test mode used test SBA[7:0] pins. These pins outputs during NANDtree test mode tested that mode. NANDtree test mode, SBA[7:0] signals become inputs CRESET# becomes output. Table NANDtree Outputs
Signals CRESET# Purpose NAND-Chain Output
Table NANDtree Chain
Chain Name SBA0 SBA1 SBA2 SBA3 SBA4 SBA6 SBA5 SBA7 Pad#
Specification Update
Intel 82443BX Figure Diagram NANDtree Test mode
Nandtree Test 82443BX Inputs SBA[0] SBA[1] Outputs
SBA[7]
CRESET#
GTL+Termination Voltage (Mobile Only)
values termination Voltage (mobile), VTTm have been changed 2.035 Table 82443BX Characteristics, 82443BX Host Bridge/Controller Electrical Thermal Timing Specification datasheet addendum.
Undershoot Specification Changed -750 (Mobile Only)
undershoot specification been changed -750 Table 82443BX Characteristics, Note 82443BX Host Bridge/Controller Electrical Thermal Timing Specification datasheet addendum. PIIX4/PIIX4E register CNTB-Count (Function address offset [10:6] (processor lock count bits) (processor lock resolution bit) control processor lock time resolution function. default value this register 00h. These bits must programmed insure 82443BX minimum time requirements between deassertion signals met.
Specification Update
Intel 82443BX
Errata
Problem:
Locked Cycle Retry
following sequence events following locked retry cycle DRAM result system failure. Scenario: Intel 440BX AGPset PIIX regime (i.e., PIIX4 pending cycle DRAM). processor issues locked read DRAM which results write back. Intel 440BX AGPset retries locked cycle DRAM (due pending cycle DRAM). Intel 440BX AGPset accepts write data write back cycle posts System fails Scenarios: Case master initiated cycle deferred. processor issues locked read DRAM which results write back. Intel 440BX AGPset retries locked cycle DRAM (due pending cycle DRAM). Intel 440BX AGPset accepts write data write back cycle posts System fails Case CPU1 performs locked cycle DRAM. CPU2 attempts execute locked cycle DRAM which results write back. Intel 440BX AGPset retries cycle from CPU2. Intel 440BX AGPset accepts write data write back cycle posts System fails
Implication: System failure occur. Workaround: workaround Configuration Register 0F4h, This will force continuously assert BPRI# when there pending cycle from PIIX DRAM workaround Assert BNR# whenever LOCK# asserted Status: Problem: This erratum intended fixed next stepping 82443BX.
Error Address Pointer Register
When error occurs, Error Address Pointer register, (80h) records address error. specified Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet, Intel 440BX AGPset should change register value error occurs. stepping, however, when error occurs, address first error overwritten.
Implication: register will retain address first error Workaround: None
Specification Update
Intel 82443BX Status: Problem: This erratum intended fixed next stepping 82443BX.
Read/Write Cycles with Auto Precharge Enabled
When Selective Auto Precharge enabled, Read Write cycles DRAM result data errors.
Implication: Incorrect data read from written DRAM. Workaround: Register disable selective auto precharge. Status: Problem: This erratum intended fixed next stepping 82443BX.
Global SMRAM Enable
Global SMRAM Enable, (PCI Config Register modified even when D_LCK (PCI Configuration Register set.
Implication: Software disable SMRAM space, even though D_LCK been set. Workaround: None Status: Problem: This erratum intended fixed next stepping 82443BX.
MA11 High during Command
According PC100 SDRAM Specification, during command SDRAM MA11 must low. 82443BX step drives MAB13# high, which connected MA11 SDRAM component.
Implication: Some SDRAM DIMMs properly initialized. Workaround: None Status: Problem: This erratum intended fixed next stepping 82443BX.
Memory Read Line
While process performing PCIx memory read line cycle, back-to-back snoop cycles occur which successfully completed. following initiated cycles response.
Implication: System will fail. Workaround: Configuration Register Status: This erratum intended fixed next stepping 82443BX.
Specification Update
Intel 82443BX
Problem:
Operation
used generate DRAM clock output stable over specified operating range.
Implication: This cause system failures when running MHz. Systems will operate normally MHz. Workaround: Screened components available. Reducing 3.3V power supply voltage also eliminate failures. Status: Problem: This erratum intended fixed next stepping 82443BX.
Snoop Ahead
following sequence events cause incorrect data transferred and/or system hang: PCIx device performs memory read multiple. first snoop PCIx read clean. second snoop PCIx read dirty, which requires writeback cycle. When second snoop begins, there outstanding write (CPU initiated) host (the data transferred yet). destination outstanding write data initiated must different than destination writeback caused second snoop cycle.
Implication: Incorrect data will transferred and/or system will hang. Workaround: Configuration Register Status: Problem: This erratum intended fixed stepping 82443BX.
Power Dissipation
Internal diodes that were connected incorrectly caused higher standby operating power step 82443BX.
Implication: Power dissipation step silicon will higher. Workaround: None. Status: Problem: This erratum intended fixed stepping 82443BX.
Hard Reset Collision with Refresh
During software generated hard reset, DRAM refresh cycle coincides with activation PCIRST#, system will hang.
Implication: system will hang. Workaround: system BIOS must disable refresh before generating reset sequence Status: This erratum will fixed stepping 82443BX. This erratum intended fixed stepping 82443BX.
Specification Update
Intel 82443BX Problem:
IPDLT Setting
System validation uncovered marginal internal timing path.
Implication: incorrect address driven DRAM bus, resulting memory data being fetched from wrong location. Workaround: IPDLT bits (register offset 76h, bits should (i.e., Status: BIOS workaround (configuration register change). This erratum intended fixed next stepping 82443BX.
Problem:
SDRAM Suspend Refresh
This erratum occur Intel 440BX AGPset platforms that implement suspend Stop Clock (C3) states. Platforms that affected include mobile SDRAM platforms using module MMconfig mode (single CKE) DIMM desktop platforms using GCKE. These platforms require Intel 440BX AGPset memory controller stop normal refresh place SDRAM self-refresh mode before system transitions these states. self-refresh trigger (SUSTAT1# signal asserted) occurs same time internally generated normal refresh request, Intel 440BX AGPset generates incorrect CKE# signal sequence SDRAM. SDRAM placed self-refresh mode memory contents lost. Mobile SDRAM platforms using normal mode (not MM-config) DIMM desktop platforms affected. DIMM desktop platforms that GCKE also affected.
Implication: observed effect erratum system hang, although data loss corruption theoretically possible. Workaround: BIOS workaround: POS, POSCCL, POSCL, states workaround disables normal refresh prior entering these states before 82443BX automatically generates SDRAM self-refresh command. BIOS will re-enabling normal refresh exit from these states. ACPI BIOS workaround (TBD): Status: Implement BIOS workaround. This erratum intended fixed next stepping 82443BX.
Specification Update
Intel 82443BX
Problem:
Refresh Collision with SUS_STAT# Assertion (EDO Memory)
entry POSCL system with memory, SUSSTAT1# asserted same time DRAM refresh cycle occurs normal refresh state machine left improper state. Refresh control transferred suspend refresh state machine which affected. When system resumes from STR, refresh control returned normal refresh state machine which improper state.
Implication: system will hang, typically with RAS# stuck high stuck low. During execution resume code, operation will continue until BIOS sets NREF_EN (82443BX, Device#0, Register Offset 7Ah, Workaround: BIOS workaround consisting aligning occurrence 82443BX north bridge refresh cycles away from transitions PIIX4 south bridge SUSCLK# (which controls assertion SUSSTAT#) available. Status: Implement BIOS workaround. This erratum intended fixed next stepping 82443BX.
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Intel 82443BX
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Intel 82443BX
Specification Clarifications
Normal Refresh Enable
When user performs soft reset, PIIX will drive SUSTAT# This will force switch suspend refresh state. When BIOS attempts execute cycles DRAM, will accept these cycles because believes that suspend state After coming reset software must normal refresh enable (bit power management control register Offset 7Ah) 82443BX before doing access memory.
Function with Registered DIMMs
stacking technology used registered DIMMs prohibits function. registered DIMMs, components stacked another. stacked components physically same row, logically separate rows. stacked components connect pins together, except pin, order address components different rows. Since pins components connected together, components logically different rows, function supported.
Memory Initialization with Enabled
Intel 440BX AGPset systems using memory, memory must initialized with enabled (NBXCFG bits through bits errors received during initialization should ignored.
DCLKO State during POS/STThe state DCLKO during POS/STR high low. result, mobile desktop designs implementing POS/STR should move CKBF component same VCC3 plane 82443BX component.
DCLKRD Connected NAND Chain
Even though DCLKRD (pin AB22) been changed connect (see Specification Change DCLKRD still routed internally part NAND chain.
Modifying DRAM Configuration Registers during DRAM Cycles
Modifying configuration registers that affect DRAM (SDRAM EDO) while DRAM cycles running cause system problems. DRAM configuration registers should completely initialized before running DRAM cycles.
Specification Update
Intel 82443BX
Side Band Addressing Signals Float before Enable
82443BX does have internal pull-ups SBA[7:0] signals. Some devices drive SBA[7:0] signals prior Enable enable bits being set. This cause failures Intel 440BX AGPset-based system. devices that drive SBA[7:0] prior enable bits being set, workaround required.
128-Mbit Technology SDRAM Memory
Reference Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet. following comments page 4-14, paragraph 4.3, DRAM Interface, after last sentence first paragraph: 128-Mbit technology SDRAM using 16MX8 devices have been tested Intel 82440BX AGPset System Validation (SV) platform using 82443BX stepping. This SDRAM memory configuration double-sided. Each SDRAM DIMM module therefore contained total memory. total four DIMM modules were available testing. There were detection sizing problems with this SDRAM memory array using 82443BX board 82443BX BIOS. Intel 440BX AGPset supports 128-Mbit technology SDRAM memory using 82443BX stepping described this paragraph. recommended that OEMs wishing 128-Mbit technology SDRAM perform validation using their BIOS their Intel 440BX AGPset systems.
HCLKIN Lead Time PCLKIN Timing
Reference 82443BX Host Bridge/Controller Electrical Thermal Specification datasheet addendum, Table Clock Timing; MHz. following table after symbol t34, HCLKIN Lead Time PCLKIN:
t34a
HCLKIN Lead Time PCLKIN config enabled)
MBSC Memory Buffer Strength Control Register (Device Address Offset 69-6Eh
Reference Section 3.3.20, MBSC Memory Buffer Strength Control Register (Device Address Offset 69-6Eh, Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet "NOTE" changed read: Note: Intel recommended settings this register 440BX/440GX 440BX/440GX BIOS specifications specification updates reflect validation Intel specific platforms memory. These register settings revised modified platforms memory combinations when functionality signal quality confirmed follow-up validation OEMs. choice buffer setting independent frequency. possible select memory buffer even though frequency (and vice versa).
Specification Update
Intel 82443BX These values used combination manipulated order obtain best characteristics platform level.
Multi-Bit Memory Error Clarification
When Intel 440BX AGPset platform configured support, multi-bit uncorrectable memory error detected during memory read system device, SERR, SCI, will generated. This typically results NMI, however data still reach intended target before generated before interrupt handler service problem. This result data being returned target permanently stored, resulting system data corruption. This chipset architected designed ensure that targets protected from this corrupted data these situations.
Specification Update
Intel 82443BX
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Specification Update
Intel 82443BX
Documentation Changes
Correct Intel 82443BX Simplified Block Diagram
82443BX Simplified Block Diagram, page Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet, replaced with following corrected diagram:
A[31:3]# ADS# BPRI# BNR# CPURST# DBSY# DEFER# HD[63:0]# HIT# HITM# HLOCK# HREQ[4:0]# HTRDY# DRDY# RS[2:0]# BREQ0# AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# DEVSEL# SERR# PLOCK# STOP# PHOLD# PHLDA# WSC# PREQ0# PREQ[4:1]# PGNT0# PGNT[4:1]# GAD[31:0] GC/BE[3:0]# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GPAR PIPE# SBA[7:0] RBF# ST[2:0] ADSTB_A ADSTB_B SBSTB Clocks, Reset, Test, Reference Misc.
Host Interface
Interface (PCI
RASA[5:0]#/CSA[5:0]# RASB[5:0]#/CSB[5:0]# CKE[3:2]/CSA[7:6]# CKE[5:4]/CSB[7:6]# CASA[7:0]#/DQMA[7:0] CASB[5,1]#/DQMB[5,1] GCKE/CKE1 SRAS[B,A]# CKE0/FENA SCAS[B,A]# MAA[13:0] MAB[13,12#,11#,10,9:0#] WEA# WEB# MD[63:0] MECC[7:0]
DRAM Interface
Interface
HCLKIN PCLKIN GTLREF[B:A] AGPREF VTT[B:A] REF5V PCIRST# CRESET# TESTIN# GCLKO GCLKIN DCLKO DCLKW
Power Mgnt
CLKRUN# SUSTAT# BXPWROK
BX_BLK
Specification Update
Intel 82443BX
Note Table
following added Note Table 3-1, 82443 Register Device (Sheet Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet: Missing leading values default value settings zeros. example, address offset 30-33h (reserved) shown with default value "00h". actual default value "00000000h". Another example address offset F2-F7h. default value this reserved register shown "0000F800h". actual default value "00000000F800h"."
Page iii, Features List, Changed
(See Specification Change above.) Integrated DRAM Controller section Intel 82443BX Features List page Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet changed follows: first item changed read: ".128-Mbit SDRAM technology supported stated paragraph page 4-14 this document. result, Mbytes Gbyte memory available depending system implementation." last item changed read: ".Enhanced SDRAM Open Page Architecture Support 16-, 64-, 128-Mbit SDRAM technology devices with page sizes."
Specification Update

Specification Update Notice: Intel 82443BX AGPset contain design

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