Pentium® OverDrive® PROCESSOR WITH MMXTECHNOLOGY Pentium PROCESSOR-BAS
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200-MHz Pentium® OverDrive® Processor with MMXTechnology upgrade 100/133/166-MHz Pentium Processor-Based Systems 180-MHz Pentium OverDrive Processor with Technology upgrade 90/120/150-MHz Pentium Processor-Based Systems upgrades 75-MHz Pentium Processor-Based Systems 150-MHz 166-MHz Pentium OverDrive Processor with Technology upgrade 100/133MHz Pentium Processor-Based Systems
Pentium® OverDrive® PROCESSOR WITH MMXTECHNOLOGY Pentium PROCESSOR-BASED SYSTEMS
Support MMXTechnology Powerful Processor Upgrades Upgradable Pentium® Processor-Based Systems Superscalar Architecture Enhanced pipelines Pipelined Integer Units Capable Instructions/Clock Pipelined Unit Pipelined Floating-Point Unit Separate Code Data Caches Deeper Write Buffers, "Pool" Configuration Enhanced Branch Prediction Virtual Mode Extensions 32-Bit with 64-Bit Data .35µM CMOS Silicon Technology
On-package Voltage Regulation Voltage Filtering Integrated Fan/Heatsink Thermal Solution Compatible with Installed Software Base MS-DOS*, Windows*, Windows Windows OS/2*, UNIX* Product Line Supports Socket Socket Designs SPGA Package Bus/Core Ratio, Hard-Bonded Modes Easy Installation Supports 66-MHz Speeds Single Volt Supply
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel. INTEL CORPORATION 1995 June 1997 Order Number: 290607-001
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Pentium® OverDrive® processor with MMXtechnology end-user, single chip, Pentium processor upgrade product. user able support Intel's technology increase performance their simply replacing existing 100, 120, 133, 150, 166-MHz Pentium processor with Pentium OverDrive processor with technology. Pentium OverDrive processor with technology provides performance needed today's mainstream desktop applications workstations. Pentium OverDrive processor with technology binary compatible with Pentium processor compatible with entire installed base applications MS-DOS*, Windows*, Windows Windows OS/2*, UNIX*. 200-MHz Pentium OverDrive processor with technology designed upgrade 100, 133, 166-MHz Pentium processor-based systems. most these systems sockets that allow easy user installation processor upgrade. 180/150-MHz Pentium OverDrive processor with technology designed upgrade 120, 150-MHz Pentium processor-based systems. 166-MHz Pentium OverDrive processor with technology designed upgrade 133-MHz Pentium processor-based systems. Pentium OverDrive processor with technology Pentium processor-based systems million transistors built Intel's advanced 0.35-micron silicon technology. Pentium OverDrive processor with technology equipped with high reliability, integrated fan/heatsinks.
Technical Product Notice Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium OverDrive processor with technology contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from: Intel Corporation P.O. 7641 Prospect 60056-7641 call 1-800-879-4683 visit Intel's website http://www.intel.com Copyright Intel Corporation 1996, 1997. Third-party brands names property their respective owners.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
CONTENTS
PAGE PAGE 3.7. On-Package Voltage Regulator.30 3.8. Cache Support.30 3.9. Code Prefetch Queue Branch Target Buffers 3.10. Buffers 3.11. Test Register Access 4.0. BIOS SOFTWARE.31 5.0. ELECTRICAL SPECIFICATIONS.31 5.1. Power Ground 5.2. Decoupling Recommendations.31 5.3. Other Connection Recommendations 5.4. Absolute Maximum Ratings.31 5.5. D.C. Specifications 5.6. A.C. Specifications 5.6.1. TABLES 50-MHZ BUS.34 5.6.2. TABLES 60-MHZ BUS.38 5.6.3. TABLES 66-MHZ BUS.42 5.6.4. TIMING WAVEFORMS 6.0. MECHANICAL SPECIFICATIONS 6.1. Package Dimensions.50 6.2. Spatial Requirements 6.3. Socket.53 6.3.1. SOCKET COMPATIBILITY 6.3.2. SOCKET PINOUT.53 6.3.3. SOCKET PINOUT.54 7.0. THERMAL SPECIFICATIONS 8.0. TESTABILITY 8.1. Introduction 8.2. Built Self Test (BIST) 8.3. Tri-State Test Mode.57
1.0. INTRODUCTION 1.1. Product Overview.5 1.2. Product Description 1.3. Purpose this Document 1.4. Compatibility Note 2.0. PINOUT DESCRIPTION.8 2.1. Pinout.8 2.2. Cross Reference 2.3. Quick Reference 2.4. Descriptions 2.4.1. INPUT PINS 2.4.2. OUTPUT PINS 2.4.3. INPUT/OUTPUT PINS 2.4.4. GROUPING ACCORDING FUNCTION 3.0. COMPONENT OPERATION.27 3.1. Core Ratio Higher Speed.27 3.2. Hardware Interface Differences 3.2.1. CPUTYP SIGNAL 3.3. Processor Initialization 3.3.1. POWER SPECIFICATION.27 3.3.2. TEST CONFIGURATION FEATURES (BIST, FRC, TRISTATE TEST MODE).28 3.3.3. INITIALIZATION WITH RESET, INIT BIST 3.4. Instruction Differences.28 3.4.1. MMXTECHNOLOGY EXTENSIONS INTEL ARCHITECTURE.28 3.4.2. RDPMC (READ PERFORMANCE MONITORING COUNTER) 3.5. CPUID 3.6. On-Package Fan/Heatsink
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
FIGURES Figure Pentium® OverDrive® Processor with MMXTechnology Block Diagram.6 Figure Pentium® OverDrive® Processor with MMXTechnology Features.7 Figure Pentium® OverDrive® Processor with MMXTechnology Upgrade Choices Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Top Side View Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Pin Side View Figure Pentium® OverDrive® Processor with MMXTechnology with Fan/Heatsink30 Figure Clock Waveform.46 Figure Valid Delay Timing Figure Float Delay Timing Figure Setup Hold Timing.47 Figure Reset Configuration Timing.48 Figure Test Timing.49 Figure Reset Configuration Timing.50 Figure Pentium® OverDrive® Processor with MMXTechnology Package Dimensions Figure Illustrates Physical Space Requirements Pentium® OverDrive® Processor with MMXTechnology.53 Figure Required Free Space from Sides SPGA Package.53 Figure 320-Pin Socket 5.54 Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Top Side View
Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Pin Side View.56
TABLES Table 320-Pin SPGA Cross Reference Name.11 Table Quick Reference Table Input Pins.22 Table Output Pins.24 Table Input/Output Pins.25 Table Interprocessor Pins.25 Table Functional Grouping Table Functional Groupings Supported Pentium® OverDrive® Processor with MMXTechnology Table Core/Bus Frequencies.27 Table Values Definition CPUID.29 Table Values Definition Processor Type Table Absolute Maximum Ratings without Fan/Heatsink Table Absolute Maximum Ratings Fan/Heatsink Only.32 Table 3.3V D.C. Specifications.33 Table 50-MHz A.C. Specifications Table 60-MHz A.C. Specifications Table 66-MHz A.C. Specifications Table Pentium® OverDrive® Processor with MMXTechnology Package Summary Table Package Dimensions.51 Table Design Considerations
1.0.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Pentium processor-based systems that compatible with Pentium OverDrive processor with technology must designed both original processor specifications Pentium OverDrive processor with technology specifications.
INTRODUCTION
This datasheet describes Intel's Pentium OverDrive processor with technology upgradable Pentium processor-based systems. Pentium OverDrive processor with technology currently includes upgrades 100, 120, 133, 150, 166-MHz Pentium processors. Technical descriptions other Pentium OverDrive processors available Intel OverDrive® Processors datasheet (Order #290436). This datasheet intended used conjunction with Pentium® Family User's Manual (Order #241428), which describes Pentium family architecture functionality. enhancements differences between Pentium OverDrive processor with technology original Pentium processor (i.e., 75/90/100/120/133/150/ 166-MHz Pentium processor 200/180/166-MHz Pentium OverDrive processor with technology) described this datasheet.
1.1.
Product Overview
Pentium OverDrive processor with technology, upgradable 100, 120, 150, 166-MHz Pentium systems, allows users upgrade more advanced Pentium processor technology adds Intel's technology. Figure contains block diagram Pentium OverDrive processor with technology. Figure lists some enhancements Pentium OverDrive processor with technology. Figure describes upgrade choices available existing Pentium processor system.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-1
Figure Pentium® OverDrive® Processor with MMXTechnology Block Diagram
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Based Advanced Pentium® Processor with MMXTechnology Superscalar Architecture Pipelined Floating-Point Unit Separate Code Data caches Data Address Parity Virtual Mode Extensions System Management Mode Fractional Operation 200, 180, 166-MHz Pentium OverDrive® Processors with Technology
.35µM
CMOS Silicon Technology Dynamic Branch prediction Improved Execution Time Writeback MESI Protocol Data Cache Cycle Pipelining Internal Parity Checking Performance Monitoring Execution Tracing Active Fan/Heatsink
100-MHz Pentium Processor-Based Systems SPGA Pinout On-package Voltage Regulation
290607-2
Figure Pentium® OverDrive® Processor with MMXTechnology Features
Current Processor 75-MHz Pentium Processor
Pentium® OverDrive® Processor with MMXTechnology Upgrade 150-MHz Pentium OverDrive Processor with Technology 180-MHz Pentium OverDrive Processor with Technology
90/120/150-MHz Pentium Processor
100/133/166-MHz Pentium Processor
166-MHz Pentium OverDrive Processor with Technology
290607-3
Figure Pentium® OverDrive® Processor with MMXTechnology Upgrade Choices
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
1.2.
Product Description
always load
Pentium OverDrive processor with technology comes 320-pin SPGA package drop-in replacement 100, 120, 133, 166-MHz Pentium processor. comes with on-package voltage regulation provide required volts core fan/heatsink complete thermal solution. internal core operates times speed system respective 200MHz 166-MHz Pentium OverDrive processor with technology. dual socket systems original processor must removed Pentium OverDrive processor with technology should installed secondary socket since does support dual processing.
depend states undefined bits when testing values defined register. Mask them when testing. depend states undefined bits when storing them memory another register. depend ability retain information written into undefined bits. When loading registers undefined bits zeros.
Never connect signals device pins marked "NC" "RES". pins Internal No-Connects. This means that connected processor internally. example; CPUTYP signal Pentium OverDrive processor with technology internally connected package pin. core internally tied VSS. package defined INC. external connections package will affect processor core because core physically disconnected from package pin.
1.3.
Purpose this Document
This document describes system architecture physical environment Pentium OverDrive processor with technology. also outlines differences between originally installed Pentium processor Pentium OverDrive processor with technology.
2.0. 1.4. Compatibility Note 2.1.
this document some register bits shown "Intel Reserved" (RES) some pins marked Connects" (NC) "Reserved" (RES). When reserved bits called out, treat them fully undefined. This essential software compatibility with current future processors. When marked "NC" "RES" important connect other signals such pins ensure proper operation. Intel strongly recommends following guidelines below:
PINOUT DESCRIPTION Pinout
Pentium OverDrive processor with technology 320-pin SPGA pinout designed installed into Socket Socket Section more details Socket Socket Figure Figure illustrations each side SPGA package.
IERR#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
PICD1 TMS# D/P#
PICCLK PICD0
PM0BP0
PM1BP1 MI/O#
AHOLD KEN#
STPC
CMC# PEN#
BOFF PHIT# B/WT INIT
IGNNE# SMI# INTR
HOLD
PHITM#
PBREQ# APCH
SMIACT#
BREQ
HLDA ADS# D/C# HIT# BE1# BE2# BE3# SCYC
RESET
HITM# BUSC BE0#
ADSC
EADS#
FLUSH#
290607-4
Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Top Side View
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 D/P# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 PICD1 TMS# VCC3 VCC3 VCC3 VCC3
VCC3 VCC3 VCC3 VCC3
VCC3 VCC3 VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC2
VCC2 VCC2
PICCLK PICD0
IERR# FERR#
CPUTYP TRST# VCC3 VCC3
PM0BP0
PM1BP1 MI/O#
VCC2
CACHE#
STPCLK#
AHOLD KEN#
EWBE#
BRDY#
VCC2
FRCMC#
BRDYC#
PEN# INIT
BOFF# WB/WT#
IGNNE# INTR SMI#
PHIT#
HOLD PRDY
VCC2
PHITM#
PBGNT#
APCHK# PBREQ# PCHK#
SMIACT#
LOCK# VCC3 VCC3 VCC3 VCC3 VCC3 RESET VCC2 VCC2 SCYC VCC2 BE7# BE5# VCC2 BE3# BE1# BE2# VCC2 VCC2 A20M# ADS# HIT# D/C# HLDA
BREQ
BE6#
BE4#
BE0# BUSCHK# HITM# W/R#
EADS#
ADSC# VCC5
VCC2
FLUSH#
VCC5
290607-5
Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Pin Side View
2.2.
Signal Signal
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Cross Reference
Table 320-Pin SPGA Cross Reference Name Address Location AL35 AM34 AK32 AN33 AL33 AM32 Signal Location AK30 AN31 AL31 AL29 AK28 AL27 Signal Data Location Signal Location Signal Location Signal Location Signal Location Location AK26 AL25 AK24 AL23 AK22 AL21 Signal Location AF34 AH36 AE33 AG35 AJ35 AH34 Signal Location AG33 AK36 AK34 AM36 AJ33
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Signal PEN# PM0/BP0 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT# Location AC05 AL03 AC35 AK20 AL17 AB34 AG03 AM06 AA05
Table 320-Pin SPGA Cross Reference Name (Continued) Control Signal A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# Location AK08 AJ05 AM02 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 APIC Signal PICCLK PICD0 [DPEN#] PICD1 [APICEN] Location Signal BRDYC# BREQ BUSCHK# CACHE# CPUTYP** D/C# D/P#* EADS# EWBE# FERR# Location AJ01 AL07 AK04 AE35 AM04 Signal FLUSH# FRCMC# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# Location AN07 AK06 AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04 Dual Processor Private Interface Signal PBGNT# PBREQ# PHIT# PHITM# Location AD04 AE03 AA03 AC03
Clock Control Signal BF1** STPCLK# Location AK18
NOTES: shaded definitions Pentium® OverDrive® processor with MMXtechnology dual processing pins supported Pentium OverDrive processor with technology Table D/P# signal 100, 120, 133, 150, 166-MHz Pentium processor always driven. indicates primary processor high indicates secondary processor driving bus. Pentium OverDrive processor with technology this defined internal connect. These signals internally connected Pentium OverDrive processor with technology pins. pins defined Internal No-Connects.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 320-Pin SPGA Cross Reference Name (Continued) NC/INC AJ15 AJ23 AL19 AN35 AN05 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ07 AJ09 AJ13 AJ17 AJ21 AJ25 AJ27 AJ31 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 VCC5 AN01 AN03 AM26 AM28 AM30 AN37 AL01 AA01 AA37 AC01 AC37 AE01 AE37 AG01 AG37 AJ11 AJ19 AJ29 AN09 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29
NOTE: shaded VCC/VSS/NC pins definitions (additions) Pentium OverDrive® processor with MMXtechnology with exception B02.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
2.3.
Quick Reference
Table Quick Reference
Symbol A20M#
Type
Name Function When address mask asserted, Pentium® OverDrive® processor with MMXtechnology emulates address wraparound Mbyte which occurs 8086. When A20M# asserted, Pentium OverDrive processor with technology masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A3. address status indicates that valid cycle currently being driven Pentium OverDrive processor with technology. ADSC# functionally identical ADS#. response assertion address hold, Pentium OverDrive processor with technology will stop driving address lines (A31-A3), next clock. rest will remain active data returned driven previously issued cycles. Address parity driven Pentium OverDrive processor with technology with even parity information Pentium OverDrive processor with technology generated cycles same clock that address driven. Even parity must driven back Pentium OverDrive processor with technology during inquire cycles this same clock EADS# ensure that correct parity check status indicated Pentium OverDrive processor with technology address parity check status asserted clocks after EADS# sampled active Pentium OverDrive processor with technology detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected (including during dual processing private snooping). APIC supported Pentium OverDrive processor with technology. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-3). Frequency determines bus-to-core frequency ratio Pentium processor. These Internal Connects Pentium OverDrive processor with technology which preset fraction 166MHz OverDrive Processor 200-MHz OverDrive Processor core/bus ratio.
A31-A3
ADS# ADSC# AHOLD
APCHK#
[APICEN] PICD1 BE7#-BE5# BE4#-BE0#
[BF] [BF1]
Symbol BOFF# Type BP[3:2] PM/BP[1:0] BRDY#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Continued) Name Function backoff input used abort outstanding cycles that have completed. response BOFF#, Pentium OverDrive processor with technology will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time Pentium OverDrive processor with technology restarts aborted cycle(s) their entirety. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted Pentium OverDrive processor with technology data response write request. This signal sampled states. This signal same functionality BRDY#. request output indicates external system that Pentium OverDrive processor with technology internally generated request. This signal always driven whether Pentium OverDrive processor with technology driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, Pentium OverDrive processor with technology will latch address control signals machine check registers. addition, set, Pentium OverDrive processor with technology will vector machine check exception. Pentium OverDrive processor with technology-initiated cycles cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, Pentium OverDrive processor with technology will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing Pentium OverDrive processor with technology. clock frequency operating frequency Pentium OverDrive processor with technology external requires levels. external timing parameters except TDI, TDO, TMS, TRST#, PICD0-1 specified with respect rising edge CLK. CPUTYP internally tied ground Internal No-Connect (INC) package Pentium OverDrive processor with technology.
BRDYC# BREQ
BUSCHK#
CACHE#
CPUTYP
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Continued) Symbol D/C# Type Name Function data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. Pentium OverDrive processor with technology does support dual processing. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during T12, clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven Pentium OverDrive processor with technology with even parity information writes same clock write data. Even parity information must driven back Pentium OverDrive processor with technology these pins same clock data ensure that correct parity check status indicated Pentium OverDrive processor with technology. applies D63-D56, applies D7-D0. Pentium OverDrive processor with technology does support dual processing. This signal indicates that valid external address been driven onto Pentium OverDrive processor with technology address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When Pentium OverDrive processor with technology generates write, EWBE# sampled inactive, Pentium OverDrive processor with technology will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating-point error reporting. When asserted, cache flush input forces Pentium OverDrive processor with technology writeback modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated Pentium OverDrive processor with technology indicating completion writeback invalidation. FLUSH# sampled when RESET transitions from high low, tristate test mode entered. FRCMC# Pentium OverDrive processor with technology does support functional redundancy checking.
D/P# D63-D0
DP7-DP0
[DPEN#] PICD0 EADS#
EWBE#
FERR#
FLUSH#
Symbol HIT# Type HITM# HLDA
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Continued) Name Function indication driven reflect outcome inquire cycle. inquire cycle hits valid line either Pentium OverDrive processor with technology data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses Pentium OverDrive processor with technology cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that Pentium OverDrive processor with technology floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive Pentium OverDrive processor with technology will resume driving bus. Pentium OverDrive processor with technology cycle pending, will driven same clock that HLDA de-asserted. response hold request, Pentium OverDrive processor with technology will float most output input/output pins assert HLDA after completing outstanding cycles. Pentium OverDrive processor with technology will maintain this state until HOLD deasserted. HOLD recognized during LOCK cycles. Pentium OverDrive processor with technology will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, Pentium OverDrive processor with technology will assert IERR# clock then shutdown. This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, Pentium OverDrive processor with technology will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, Pentium OverDrive processor with technology will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, Pentium OverDrive processor with technology will stop execution wait external interrupt.
HOLD
IERR#
IGNNE#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Continued) Symbol INIT Type Name Function Pentium OverDrive processor with technology initialization input forces Pentium OverDrive processor with technology begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floatingpoint registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, Pentium OverDrive processor with technology will perform built-in self test prior start program execution. INTR/LINT0 active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, Pentium OverDrive processor with technology will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When Pentium OverDrive processor with technology generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. lock indicates that current cycle locked. Pentium OverDrive processor with technology will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed deasserted least clock between back back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. Pentium OverDrive processor with technology will issue ADS# pending cycle clocks after asserted. Pentium OverDrive processor with technology supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. Pentium OverDrive processor with technology does support dual processing.
KEN#
LOCK#
M/IO#
NMI/LINT1 PBGNT#
Symbol Type PCHK# PEN#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference Name Function page cache disable reflects state CR3, Page Directory Entry, Page Table Entry. purpose provide external cacheability indication page page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock data parity error detected, Pentium OverDrive processor with technology will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", Pentium OverDrive processor with technology will vector machine check exception before beginning next instruction. Pentium OverDrive processor with technology does support dual processing. Pentium OverDrive processor with technology does support dual processing. Pentium OverDrive processor with technology does support dual processing. Pentium OverDrive processor with technology does support dual processing. Pentium OverDrive processor with technology does support dual processing. These pins function part performance monitoring feature. breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. PRDY probe ready output indicates that processor stopped normal execution response R/S# going active, Probe Mode being entered. page write through reflects state CR3, Page Directory Entry, Page Table Entry. used provide external writeback indication page page basis. stop input asynchronous, edge sensitive interrupt used stop normal execution processor place into idle state. high transition R/S# will interrupt processor cause stop execution next instruction boundary.
PHIT# PHITM# PICCLK PICD0-1 [DPEN#] [APICEN] PBREQ# PM/BP[1:0]
R/S#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference Symbol RESET Type Name Function RESET forces Pentium OverDrive processor with technology begin execution known state. Pentium OverDrive processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH#, INIT sampled when RESET transitions from high determine tristate test mode mode will entered, BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode (SMM). Assertion stop clock input signifies request stop internal clock Pentium OverDrive processor with technology thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate stop grant acknowledge cycle. When STPCLK# asserted, Pentium OverDrive processor with technology will still respond external snoop requests. testability clock input provides clocking function Pentium OverDrive processor with technology boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into Pentium OverDrive processor with technology during boundary scan. test data input serial input test logic. instructions data shifted into Pentium OverDrive processor with technology rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted Pentium OverDrive processor with technology TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. These power inputs defined separately they used split voltage plane motherboard design. These pins must supplied with 3.3V Pentium OverDrive processor with technology function.
SCYC
SMI#
SMIACT# STPCLK#
TRST# VCC2
Symbol VCC3 VCC5 W/R# Type WB/WT#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Continued) Name Function These power inputs must connected 3.3V either single split voltage systems. Pentium OverDrive processor with technology power inputs. Pentium OverDrive processor with technology ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line line basis. result, determines whether cache line initially state data cache.
NOTE: Highlighted items Table signals supported Pentium® OverDrive® processor with MMXtechnology.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
2.4.
2.4.1.
Descriptions
INPUT PINS Table Input Pins Name A20M# AHOLD BOFF# BRDY# BRDYC# BUSCHK# CPUTYP EADS# EWBE# FLUSH# FRCMC# HOLD IGNNE# INIT INTR KEN# PICCLK PEN# R/S# Active Level High High High High High High Synchronous/RESET Synchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous Pullup Pullup Pullup Pulldown Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Synchronous Pullup Pullup Pulldown Pullup Internal Resistor
Qualified State T2,T12,T2P State T2,T12,T2P BRDY#
BRDY#
EADS# First BRDY#/NA# State T2,TD,T2P
BRDY#
Name RESET SMI# STPCLK# TRST# WB/WT#
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Input Pins (Continued) Active Level High Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous/ Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Internal Resistor Qualified
NOTE: Highlighted signals original Pentium® processor 75/90/100/120/133/150/166 signals supported Pentium OverDrive® processor with MMXtechnology.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
2.4.2. OUTPUT PINS Table Output Pins Name ADS# ADSC# APCHK# BE7#-BE5# BREQ CACHE# D/P# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO# D/C# W/R# PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# Active Level High High High High High High Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated Hold, BOFF# Hold, BOFF#
states except Shift-DR Shift-IR
NOTES: output pins floated during tristate test mode (except TDO). Signals original Pentium® processor signals used Pentium OverDrive® processor with MMXtechnology.
2.4.3. Name
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
INPUT/OUTPUT PINS Table Input/Output Pins Active Level When Floated Address hold, Hold, BOFF# Address hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (When Input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown Internal Resistor
A31-A3
BE4#-BE0# D63-D0 DP7-DP0 PICD0[DPEN#] PICD1[APICEN]
NOTES: input/output pins floated during tristate test. Signals original Pentium processor signals used Pentium OverDrive processor with MMXtechnology.
Table Interprocessor Pins Name PHIT# PHITM# PBGNT# PBREQ# Active Level Internal Resistor Pullup Pullup Pullup Pullup
NOTE: Signals original Pentium processor signals used Pentium OverDrive processor with MMXtechnology.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
2.4.4. GROUPING ACCORDING FUNCTION
Pins
Table organizes pins with respect their function. Table Functional Grouping Function Clock Initialization Address Address Mask Data Address Parity Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating-Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Probe Mode RESET, INIT A31-A3, BE7# BE0# A20M# D63-D0 APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# R/S#, PRDY
Function APIC Support Miscellaneous Dual Processing Execution Tracing
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Functional Groupings Supported Pentium® OverDrive® Processor with MMXTechnology Pins PICCLK, PICD0-1 PBGNT#, PBREQ#, PHIT#, PHITM# FRCMC# CPUTYP, D/P# BT3-BT0,
Dual Processing Private Control Functional Redundancy Checking
3.0. 3.1.
COMPONENT OPERATION Core Ratio Higher Speed
3.2.
Hardware Interface Differences
Pentium OverDrive processor with technology incorporates internal Phase Lock Loop (PLL) clock multiplier generate higher internal speeds. This allows internal processor core operate synchronously higher frequencies than external bus. 200/180-MHz Pentium OverDrive processor with technology, fraction configuration will preset internally 166-MHz 5/2. Table details. Table Core/Bus Frequencies Internal Speed 150-MHz 180-MHz Speed 50-MHz 60-MHz Replaces (Core/Bus) 75/50-MHz 90/60-MHz 120/60-MHz 150/60-MHz 166-MHz 66-MHz 100/66-MHz 133/66-MHz 200-MHz 66-MHz 100/66-MHz 133/66-MHz 166/66-MHz
Pentium OverDrive processor with technology pin-for-pin compatible with respective original Pentium processors, except additional pins defined Socket Pentium OverDrive processor with technology. Some minor differences discussed this section referenced tables previous section. These differences represent features that required end-user upgrade. 3.2.1. CPUTYP SIGNAL
Pentium OverDrive processor with technology CPUTYP signal internally tied ground signal package internal no-connect (INC). original Pentium processor must removed Pentium OverDrive processor with technology function properly.
3.3.
3.3.1.
Processor Initialization
POWER SPECIFICATION
Pentium OverDrive processor with technology will boot like respective original Pentium processors. Pentium OverDrive processor with technology installed second socket dual socket system primary must removed system will boot properly.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
3.3.2. TEST CONFIGURATION FEATURES (BIST, FRC, TRISTATE TEST MODE)
64-bit quadword type. 64-bit data type holds packed integer values. These packed integer values bytes, words, double-words. Pentium OverDrive processor with technology includes instruction defined Intel Architecture MMXTechnology Programmers Reference Manual (Order #243007) Intel Architecture MMXTechnology Developer's Manual (Order #243006). Software determine that system been upgraded Intel Architecture processor that supports technology CPUID instruction. 3.4.2. RDPMC (READ PERFORMANCE MONITORING COUNTER)
Pentium OverDrive processor with technology will execute Built Self Test (BIST) Tristate Test Mode same respective original Pentium processor. Functional Redundancy Checking supported. 3.3.3. INITIALIZATION WITH RESET, INIT BIST
Pentium OverDrive processor with technology handling RESET, INIT, Built Self Test (BIST) same original Pentium processors. register states after RESET, INIT, BIST same original Pentium processors. further information refer Section this datasheet.
RDPMC will enable user only READ performance monitoring counters.
3.4.
Instruction Differences
3.5.
CPUID
Pentium OverDrive processor with technology 100% compatible with Pentium processor (75-200). additions have been made. instructions that comprise Technology Instruction RDPMC (Read Performance Monitoring Counter) instruction. These instructions added feature will impact upgraded system anyway unless specifically used. 3.4.1. MMXTECHNOLOGY EXTENSIONS INTEL ARCHITECTUR
CPUID instruction allows software determine type features microprocessor. When executing CPUID instruction Pentium OverDrive processor with technology behaves like original Pentium processors: value then 12-byte ASCII string "GenuineIntel" (little endian) returned EBX, EDX, ECX. Also, returned EAX. value then processor version returned processor capabilities returned EDX. values Pentium® OverDrive® processor with MMXtechnology given below. value neither `1', Pentium OverDrive processor with technology writes registers undefined.
Intel's technology extension Intel architecture which provides additional performance multimedia communications applications. Intel processors that include this technology still 100% compatible with "scalar" Intel processors. This means that existing software that runs existing Intel processors will continue (without modification) Intel processor that incorporates technology. Intel's technology uses SIMD (Single Instruction, Multiple Data) tecnique speedup multimedia communications software processing multiple data elements parallel. instruction opcodes
stepping field same format original Pentium processor will same Pentium OverDrive processor with technology. Pentium OverDrive processor with technology will have unique CPUID from original Pentium processor Pentium processor with technology (154xH 052xH 054xH). type field defined Table
Field Definition
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Values Definition CPUID 31.14 (reserved) (reserved) (reserved) (reserved) 13.12 type Table Table Table 11.8 family model stepping varies varies varies
Pentium® processor (75, 100) Pentium processor with MMXtechnology (166, 200, 233-MHz) Pentium OverDrive® processor with technology
Table Values Definition Processor Type Processor Type Primary Pentium® processor
Primary Pentium processor with technology Pentium OverDrive® processor with technology Dual Pentium processor Reserved
NOTE: Pentium® OverDrive® processor with MMXtechnology does support Dual Processing mode.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-6
HEATSINK CERAMIC SPGA
Figure Pentium® OverDrive® Processor with MMXTechnology with Fan/Heatsink
3.6.
On-Package Fan/Heatsink
3.9.
Code Prefetch Queue Branch Target Buffers
on-package fan/heatsink included with Pentium OverDrive processor with technology requires different stress ratings than original Pentium processor. detachable unit, storage temperature stated separately Table Operation Pentium OverDrive processor with technology defined 10°C 45°C. fan/heatsink shown Figure
Code should written rely specific code prefetch queue branch target buffer mechanism particular processor. With each generation family processors, these mechanisms subject change.
3.10.
Buffers
3.7.
On-Package Voltage Regulator
Pentium OverDrive processor with technology on-package voltage regulator supply volts processor core. This allows Pentium OverDrive processor with technology function volt only system.
3.8.
Cache Support
Pentium OverDrive processor with technology buffer models comply with specifications buffer model respective original Pentium processor. circuit topology same ranges values Pentium OverDrive processor with technology model within original Pentium processor ranges. buffer models used Pentium OverDrive processor with technology accurately model flight time signal quality.
Pentium OverDrive processor with technology enhanced internal cache (2x16KB Total, set-associative Code Data caches, each with improved TLBs) will support caches supported Pentium processor (75200). Pentium OverDrive processor with technology supports Intel 82430 chipsets. Chipsets with signal levels, 82497/82492 cache controller, 82498/82493 cache controller supported Pentium OverDrive processor with technology.
3.11.
Test Register Access
Pentium OverDrive processor with technology have test registers which allow testing different areas processor. These test registers called Model Specific Registers (MSR). These MSR's accessed using RDMSR WRMSR instructions.
4.0. 5.0.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
pins should connected volts regardless system design.
BIOS SOFTWAR
Pentium OverDrive processor with technology drop-in replacement respective original Pentium processor. BIOS changes normally necessary might required. Please call Intel Technical Support hotline assistance required. Pentium OverDrive processor with technology 100% backward software compatible with their respective original Pentium processors.
5.2.
Decoupling Recommendations
ELECTRICAL SPECIFICATIONS
This section describes electrical differences between Pentium processor (75-200) Pentium OverDrive processor with technology. Pentium OverDrive processor with technology requires volts power processor. voltage socket volt converted on-package voltage regulator proper voltage processor's internal core voltage plane. internal volt plane powered from socket processor. Pentium OverDrive processor with technology looks like volt device externally.
Decoupling recommendation original Pentium processor apply Pentium OverDrive processor with technology upgradable systems capacitors should placed near Pentium OverDrive processor with technology. Pentium OverDrive processor with technology cause transient power surges, particularly when driving large capacitive loads. Pentium OverDrive processor with technology shipped with adequate decoupling capacitors package limit transients excess Pentium processors tolerance. recommended follow original Pentium processor specification decoupling recommendations.
5.3.
Other Connection Recommendations
5.1.
Power Ground
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC. Unused active high inputs should connected ground. pins must remain unconnected.
clean on-chip power distribution, Pentium OverDrive processor with technology SPGA package (power) (ground) inputs. VCC2 pins connected internally power plane that provides power on-package voltage regulator core supply. VCC3 pins connected internally separate power plane that provides power buffers. Power ground connections must made external pins Pentium OverDrive processor with technology. circuit board pins must connected 3.3V plane. pins must connected plane. Pentium OverDrive processor with technology pinout contains pins (VCC5) used provide power fan/heatsink. These
5.4.
Absolute Maximum Ratings
tables this section provide environmental stress ratings Pentium OverDrive processor with technology. Functional operation absolute maximum minimum implied guaranteed. Extended exposure maximum ratings affect device reliability. Furthermore, precautions should taken avoid high static voltages electric fields prevent static electric discharge. Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. tables contain stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" effect device reliability.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Unit
Table Absolute Maximum Ratings without Fan/Heatsink Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC5 Supply Voltage with respect Supply Voltage with respect Only Buffer Input Voltage -0.5 -0.5 -0.5 +125 +110 +4.6 VCC3+0.5V exceed 4.6V +6.5 Notes
VINSB
5.0V Safe Buffer Input Voltage
-0.5
NOTES: Applies PICCLK. Applies Pentium® OverDrive® processor with MMXtechnology inputs except PICCLK. overshoot/undershoot transient specification Pentium® Family User's Manual, Volume
Table Absolute Maximum Ratings Fan/Heatsink Only Parameter Fan: Storage Temperature Case Temperature Under Bias VCC5 Supply Voltage with Respect -0.5 Unit Notes
5.5.
Symbol VIL5 VIH5 ICC5 ICC3
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
D.C. Specifications
technology voltage specification VCC3 3.135V 3.6V VCC5 ±5%. Table lists D.C. specifications which apply Pentium OverDrive processor with technology. Pentium OverDrive processor with technology requires 3.3V power supply 3.3V input signals with exception signals which tolerant.
Pentium OverDrive processor with technology will have compatible D.C. specifications original Pentium processor, except (Power Supply Current) ICC5 (Fan/Heatsink Current). Pentium OverDrive processor with
Table 3.3V D.C. Specifications 3.135V 3.6V (See Notes 45°C Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Input Voltage Input High Voltage Fan/Heatsink Current Power Supply Current -0.3 5.55 4330 4330 4330 4330 5000 ICC5 ICCSB Fan/Heatsink Current Standby -0.3 @50/125 (4)(5) @60/150 (4)(5) @60/180 (4)(5) @66/166 (4)(5) @66/200 (4)(5) Unit Notes Level Level Level Level Level Level
NOTES: Parameter measured Parameter measured volt levels apply signals except PICCLK. worst case conditions: VCC3+5% TCASE Power supply transient response decoupling capacitors must sufficient handle current transients required when transitioning from standby full power mode. Refer Chapter Pentium® Family User's Manual, Volume listing remaining D.C. Specifications. worst case ambient temperature Applies safe inputs: PICCLK.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
5.6.
5.6.1.
A.C. Specifications
TABLES 50-MHZ
hold requirements 50-MHz external bus. A.C. specifications (with exception those signals) relative rising edge input. timings referenced volts both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct 150-MHz Pentium OverDrive processor with technology running 125-MHz operation.
Notes
specifications 180/150-Pentium OverDrive processor with technology consist setup times, hold times, valid delays 0pF. A.C. specifications given Table consist output delays, input setup requirements input
Table 50-MHz A.C. Specifications 3.135 3.6V, 45°C, Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time ADS#, ADSC#, PWT, PCD, BE0-7#, M/IO#, D/C#, CACHE#, SCYC, W/R# Valid Delay Valid Delay A3-A31, LOCK# Valid Delay ADS#, ADSC#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay PCHK#, APCHK#, IERR#, FERR# Valid Delay BREQ, HLDA, SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay 0.15 0.15 Parameter 25.0 20.0 50.0 40.0 ±250 Unit Adjacent Clocks, (1), (25) @2V, @0.8V, (2.0V-0.8V), (0.8V-2.0V), Figure
core Freq
10.0
t10a t10b t11a
10.0
Symbol t11b t16a t16b t18a t18b t22a t25a t25b PRDY Valid Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time KEN# Setup Time
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 50-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Parameter 10.0 Unit CLKs Figure (11), (15) (12) (11), (15), (16) (12) (14), (16) (11), (15), (16) (12) Notes
D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay
EADS#, INV, Hold Time
NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time BOFF# Setup Time AHOLD Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time
INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Figure Notes (14), (16) (11), (15) (12) (16) Power (11), (15), (16) (12) RESET falling edge (15) RESET falling edge (20) RESET falling edge (20) RESET falling edge (1), (27)
Table 50-MHz A.C. Specifications 3.135 3.6V, 45°C, Symbol t42a t42b Parameter R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDYC#, BUSCHK#) Hold Time, Async. Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. Reset Configuration Signals (BRDYC#) Hold Time, RESET Driven Synchronously. Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay 40.0 13.0 20.0 15.0 Unit CLKs CLKs CLKs CLKs
t42c t42d
CLKs
62.5 25.0 25.0
16.0
@2V, @0.8V, (2.0V-0.8V), (1), (8), (0.8V-2.0V), (1), (8), (1), Asynchronous
Symbol Float Delay
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 50-MHz A.C. Specifications 3.135 3.6V, 45°C, Parameter 25.0 20.0 25.0 13.0 Unit Figure Notes (1), (3), (8), (10) (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time
NOTES: Notes general apply standard signals used with Pentium® OverDrive processor with MMXtechnology. 100% tested. Guaranteed design/characterization. input test waveforms assumed Volt transitions with 1Volt/nS rise fall times. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch free outputs. Glitch free signals monotonically transition without false transitions (i.e., glitches). V/ns input rise/fall time V/ns. V/ns Input rise/fall time V/ns. Referenced rising edge. Referenced falling edge. added rise fall times every frequency below MHz. During probe mode operation, boundary scan timings (t55-58). Setup time required guarantee recognition specific clock. This applicable Pentium OverDrive processor with technology. Hold time required guarantee recognition specific clock. timings referenced from guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. However, when operating Pentium® OverDrive® processor with MMXtechnology, FLUSH# RESET must asserted synchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must deasserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A5-A31 signals sampled only that ADS# active. BF1, CPUTYP should strapped VSS. These signals measured rising edge adjacent CLKs 1.5V. ensure relationship between amplitude input jitter internal external clocks, jitter frequency specturm should have power spectrum peaking between 500KHz operating frequency. amount jitter present must accounted component skew between devices. BRDYC# BUSCHK# used Reset configuration signals select buffer size. value this signal have been changed, check latest Pentium Processor Data Book updated values. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
5.6.2. TABLES 60-MHZ
A.C. specifications given Table consist output delays, input setup requirements input hold requirements 60-MHz external bus. A.C. specifications (with exception those signals) relative rising edge input.
timings referenced volts both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct 180-MHz Pentium OverDrive processor with technology operation.
Table 60-MHz A.C. Specifications 3.135 3.6V, 45°C, Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time ADS#, ADSC#, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC Valid Delay Valid Delay A3-A31, LOCK# Valid Delay ADS#, ADSC#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ, HLDA Valid Delay SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay 0.15 0.15 Parameter 60.0 Unit Adjacent Clocks, (1), (25) @2V, @0.8V, (2.0V-0.8V), (0.8V-2.0V), Figure Notes core Freq
16.67 33.33 ±250
10.0
t10a t10b t11a t11b
10.0
D0-D63, DP0-7 Write Data Valid Delay
Symbol t16a t16b t18a t18b t25a A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time KEN# Setup Time
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 60-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Parameter D0-D63, DP0-3 Write Data Float Delay 10.0 Unit CLKs CLKs Figure (11), (15) (12) (11), (15), (16) (12) (14), (16) (11), (15), (16) (12) (14), (16) Notes
EADS#, INV, Hold Time
NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async.
D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Notes (11), (15) (12) (16) Power (11), (15), (16) (12) (15) (20)
Table 60-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Symbol t42a t42b Parameter RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Unit CLKs CLKs CLKs Figure
Reset Configuration Signals (FLUSH#, BRDYC#, INIT, BUSCHK#) Hold Time, Async. Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. Reset Configuration Signals (BRDYC#) Hold Time, RESET Driven Synchronously. Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay 40.0 13.0 20.0 25.0 20.0 25.0
t42c t42d
CLKs
(20) RESET falling edge (1), (27)
62.5 25.0 25.0
16.0
@2V, @0.8V, (2.0V-0.8V), (1), (8), (0.8V-2.0V), (1), (8), Asynchronous, (1), (3), (8), (10) (1), (3), (8), (10)
Symbol
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 60-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Parameter Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 Unit Figure Notes (3), (7), (10) (3), (7), (10)
NOTES: Notes general apply standard signals used with Pentium® OverDrive processor with MMXtechnology. 100% tested. Guaranteed design/characterization. input test waveforms assumed Volt transitions with 1Volt/nS rise fall times. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch free outputs. Glitch free signals monotonically transition without false transitions (i.e., glitches). V/ns input rise/fall time V/ns. V/ns Input rise/fall time V/ns. Referenced rising edge. Referenced falling edge. added rise fall times every frequency below MHz. During probe mode operation, boundary scan timings (t55-58). Setup time required guarantee recognition specific clock. This applicable Pentium OverDrive processor with technology. Hold time required guarantee recognition specific clock. timings referenced from guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. However, when operating Pentium® OverDrive® processor with MMXtechnology, FLUSH# RESET must asserted synchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must deasserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A5-A31 signals sampled only that ADS# active. BF1, CPUTYP should strapped VSS. These signals measured rising edge adjacent CLKs 1.5V. ensure relationship between amplitude input jitter internal external clocks, jitter frequency specturm should have power spectrum peaking between 500KHz operating frequency. amount jitter present must accounted component skew between devices. BRDYC# BUSCHK# used Reset configuration signals select buffer size. value this signal have been changed, check latest Pentium Processor Data Book updated values. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
5.6.3. TABLES 66-MHZ
A.C. specifications given Table consist output delays, input setup requirements input hold requirements 66-MHz external bus. A.C. specifications (with exception those signals) relative rising edge input.
timings referenced volts both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct 200-MHz Pentium OverDrive processor with technology operation.
Table 66-MHz A.C. Specifications 3.135 3.6V, 45°C, Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time ADSC#, PWT, PCD, BE0-7#, D/C#, W/R#, CACHE#, SCYC, Valid Delay Valid Delay A3-A31, LOCK# Valid Delay ADS#, MIO# Valid Delay ADS#, ADSC#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ, HLDA Valid Delay SMIACT# Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay 0.15 0.15 10.0 Parameter Unit Adjacent Clocks, (1), (25) @2V, (1), @0.8V, (1), (2.0V-0.8V),(1),(5) (0.8V-.0V),(1),(5) Figure Notes core Freq
33.33 66.6 15.0 30.0 ±250
t10a t10b t11a t11b
10.0
(4), (21) (4), (21) (21)
D0-D63, DP0-7 Write Data Valid Delay
(21)
Symbol t16a t16b t18a t18b t25a t25b A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time KEN# Setup Time
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 66-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Parameter D0-D63, DP0-3 Write Data Float Delay 10.0 Unit CLKs CLKs Figure (11), (15) (12) (11), (15), (16) (12) (14), (16) (11), (15), (16) (12) (14), (16) (21) (21) Notes
EADS#, INV, Hold Time
NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async.
D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Notes (11), (15) (12) (16) Power (11), (15), (16) (12) RESET falling edge (15) RESET falling edge (20) RESET falling edge (20) RESET falling edge (1), (27)
Table 66-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Symbol t42a t42b Parameter RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#,BRDYC#, BUSCHK#) Hold Time, Async. Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. Reset Configuration Signals (BRDYC#) Hold Time, RESET Driven Synchronously. Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay 40.0 13.0 20.0 25.0 20.0 15.0 Unit CLKs CLKs CLKs Figure
t42c
CLKs
t42d
62.5 25.0 25.0
16.0
@2V, @0.8V, (2.0V-0.8V), (1), (8), (0.8V-2.0V), (1), (8), Asynchronous, (1), (3), (8), (10)
Symbol
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table 66-MHz A.C. Specifications (Continued) 3.135 3.6V, 45°C, Parameter Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 25.0 Unit Figure Notes (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
NOTES: Notes general apply standard signals used with Pentium® OverDrive processor with MMXtechnology. 100% tested. Guaranteed design/characterization. input test waveforms assumed Volt transitions with 1Volt/nS rise fall times. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch free outputs. Glitch free signals monotonically transition without false transitions (i.e., glitches). V/ns input rise/fall time V/ns. V/ns Input rise/fall time V/ns. Referenced rising edge. Referenced falling edge. added rise fall times every frequency below MHz. During probe mode operation, boundary scan timings (t55-58). Setup time required guarantee recognition specific clock. This applicable Pentium OverDrive processor with technology. Hold time required guarantee recognition specific clock. timings referenced from guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. However, when operating Pentium® OverDrive® processor with MMXtechnology, FLUSH# RESET must asserted synchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must deasserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A5-A31 signals sampled only that ADS# active. BF1, CPUTYP should strapped VSS. These signals measured rising edge adjacent CLKs 1.5V. ensure relationship between amplitude input jitter internal external clocks, jitter frequency specturm should have power spectrum peaking between 500KHz operating frequency. amount jitter present must accounted component skew between devices. BRDYC# BUSCHK# used Reset configuration signals select buffer size. value this signal have been changed, check latest Pentium Processor Data Book updated values. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
5.6.4. TIMING WAVEFORMS
290607-7
Figure Clock Waveform
290607-8
Figure Valid Delay Timing
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-9
Figure Float Delay Timing
290607-10
Figure Setup Hold Timing
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-11
Figure Reset Configuration Timing
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-12
Figure Test Timing
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-13
Figure Reset Configuration Timing
6.0. 6.1.
MECHANICAL SPECIFICATIONS Package Dimensions
Table Pentium® OverDrive® Processor with MMXTechnology Package Summary
Package Total Type Pins Array Package Size
Pentium OverDrive processor with technology, upgrade 100-MHz Pentium processor-based systems, uses 320-pin ceramic staggered grid array (SPGA) package. pins will arranged matrix package dimensions will 1.95 1.95 (4.95cm 4.95cm). Table
Pentium® OverDrive® Processor with MMXTechnology
SPGA
1.95" 1.95" 4.95cm 4.95cm
NOTE: mechanical specifications provided Table Figure shows package dimensions Pentium® OverDrive® processor with MMXtechnology.
Symbol 10.16 0.43 49.28 45.47 2.41 1.14 3.05 1.52 0.33 2.62
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Table Package Dimensions Family: Ceramic Staggered Grid Array Package Millimeters 33.88 0.43 2.97 20.32 Space 0.51 49.91 45.97 2.67 1.40 3.30 SPGA pins 2.54 0.400 0.017 1.940 1.790 0.095 0.045 0.120 0.060 0.100 0.020 1.965 1.810 0.105 0.055 0.130 SPGA pins Notes Solid Solid 0.013 0.103 Inches 1.334 0.017 0.117 0.800 Space Notes Solid Solid
NOTES: Assumes minimum space above fan/heatsink. clearance around three four sides package also required allow free airflow through fan/heatsink.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
SEATING PLANE
heat sink space
REF. CHAMFER (INDEX CORNER) 2.29 REF. 1.52
AAAAAAAAAA AAAA AAAA AAAAAA AAAA AAAAAA AAAA AAAA AAAAAA AAAA AAAA AAAAAA AAAA AAAA
AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
PP0077
290607-14
Figure Pentium® OverDrive® Processor with MMXTechnology Package Dimensions
6.2.
Spatial Requirements
Pentium OverDrive processor with technology employs fan/heatsink thermal management device. Clearance requirements must around fan/heatsink ensure unimpeded flow proper cooling. Figure shows Pentium OverDrive processor with technology's fan/heatsink space requirements. Pentium OverDrive processor with technology spatial requirements defined respective socket specification that must met. shown Figure acceptable allow device (i.e., add-in cards, surface mount device,
chassis, etc.) enter within free space distance 0.2" from Pentium OverDrive processor with technology package taller than level heatsink base. other words, component taller than height "B," cannot closer Pentium OverDrive processor with technology package than distance "A". This applies three four sides Pentium OverDrive processor with technology package, although back handle sides socket will generally automatically meet this specification since they have widths larger than distance "A." Compliance this requirement will ensure systems upgraded Pentium OverDrive processor with technology.
NOTE:
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
290607-15
Pentium® OverDrive® processor with MMXtechnology. Figure Illustrates Physical Space Requirements Pentium® OverDrive® Processor with MMXTechnology
TEMP
Figure Required Free Space from Sides SPGA Package
6.3.
6.3.1.
Socket
SOCKET COMPATIBILITY
proper operation Pentium OverDrive processor with technology, power ground pins should connected defined respective socket definitions. 6.3.2. SOCKET PINOUT
Socket (320 pins) Socket (321 pins) defined specifically requirements Pentium OverDrive processor with technology. Socket Socket define fifth pins inside 296-pin SPGA socket. rows "AJ" rows pins defined Socket Socket Socket Socket superset original 100-MHz Pentium processor (296 pins) pinout. Pentium OverDrive processor with technology sockets compatible with their respective original Pentium processors. insure
Socket 320-pin (Zero Insertion Force) socket recommended 150/166-Pentium OverDrive processor with technology. Socket pinout defined with additional power ground pins ensure proper functionality Pentium OverDrive processor with technology. pinout also specifically defined ensure proper orientation Pentium OverDrive processor with technology.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
PICCLK PICD1 TMS# TRST# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 D/P# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
VCC3 VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3 VCC3
VCC3
VCC3
VCC3
IERR#
VCC3
VCC3
PICD0
VCC3
VCC3
VCC3
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
PM0BP0
FERR#
CPUTYP
PM1BP1 MI/O#
VCC3 VCC3
CACHE#
AHOLD KEN#
STPCLK#
EWBE#
BRDY#
BRDYC#
FRCMC# PEN#
BOFF# PHIT# WB/WT# INIT
IGNNE# SMI# INTR
HOLD PHITM# PRDY
PBGNT#
PBREQ# APCHK# PCHK#
SMIACT#
BREQ
LOCK# HLDA ADS# D/C# HIT# A20M# BE0# VCC3 VCC3 VCC3 BE1# BE2# VCC3 BE3# BE5# BE4# VCC3 BE6# VCC3 BE7# SCYC VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
RESET
HITM# BUSCHK# W/R#
ADSC#
VCC5
EADS#
VCC5
FLUSH#
290607-17
Figure 320-Pin Socket
6.3.3.
SOCKET PINOUT
Socket 321-pin (Zero Insertion Force) socket recommended future Pentium Pentium
OverDrive processors should used designs. Socket compatible with 320-pin Socket with addition pin. Contact Intel further information.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
HLDA
FLUSH
290607-18
NOTE: Shaded pins internal connects Pentium® OverDrive® processor with MMXtechnology.
Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Top Side View
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 RESET VCC2 SCYC VCC2 VCC2 BE7# BE5# BE6# VCC2 VCC2 BE3# BE1# BE2# VCC2 VCC2 A20M# VCC3 D/P# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 PICD1 TMS# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 IERR# PM1BP1 VCC2 MI/O#
PICCLK PICD0
CPUTYP TRST# VCC3 VCC3
FERR# PM0BP0
CACHE#
STPCLK#
AHOLD KEN#
EWBE#
BRDY#
VCC2
FRCMC#
BRDYC#
PEN# INIT
BOFF# WB/WT#
IGNNE# INTR SMI#
PHIT#
HOLD PRDY
PHITM#
PBGNT#
APCHK# PBREQ# PCHK#
SMIACT#
LOCK# ADS# HIT# D/C# HLDA
BREQ
BE4#
BE0# BUSCHK# HITM# W/R#
EADS#
ADSC# VCC5
FLUSH#
VCC5
290607-19
Figure Pentium® OverDrive® Processor with MMXTechnology Pinout-Pin Side View
7.0. 8.0. 8.1.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
THERMAL SPECIFICATIONS
8.2.
Built Self Test (BIST)
Pentium OverDrive processor with technology shipped with attached fan/heatsink complete thermal solution processor upgrade. fan/heatsink cooling solution will properly cool Pentium OverDrive processor with technology provided space requirements Section maximum temperature entering fan/heatsink (TA) does exceed 45°C. fan/heatsink inlet temperature (TA) measured 0.3" above centerline system maximum ambient operating temperature (see Figure 15).
Self test initiated driving INIT high when RESET transitions from high low. cycles Pentium OverDrive processor with technology during self test. duration self test approximately clocks. BIST used test approximately devices Pentium OverDrive processor with technology. Pentium OverDrive processor with technology BIST consists parts: hardware self test microcode self test. During hardware portion BIST, microcode large PLAs tested. possible input combinations microcode PLAs tested. microcode self test done comparing stored value check sums with result self test. mismatch occurs errors detected during BIST, Pentium OverDrive processor with technology will assert IERR# attempt shutdown.
TESTABILITY Introduction
This section describes features which included Pentium OverDrive processor with technology purposes testability part. testability features provided original Pentium processor also available Pentium OverDrive processor with technology. Pentium OverDrive processor with technology however, does support IEEE Standard 1149.1 boundary scan using Test Access Port (TAP) Controller described Chapters Pentium Family User's Manual, Volume Contact your Intel representative further details. Some features testability described below.
8.3.
Tri-State Test Mode
When FLUSH# sampled clock prior RESET going from high low, Pentium OverDrive processor with technology enters tristate test mode. Pentium OverDrive processor with technology floats output pins bi-directional pins including pins which never floated during normal operation (except TD0). Tristate test mode initiated order facilitate testing board connections. Pentium OverDrive processor with technology remains tristate test mode until RESET toggled again.
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
APPENDIX
Pentium® OverDrive® Processor with MMXTechnology UPGRADABILITY DESIGN CONSIDERATIONS
Intel designed family Pentium OverDrive processors that they easily installed enduser. manufactures support this implementing design considerations listed Table Table Design Considerations Design Consideration Visible Pentium® OverDrive® Processor with MMXTechnology Socket Implementation Pentium OverDrive processor socket should easily visible when PC's cover removed. Label Pentium OverDrive processor socket location silk screening this information board. Make Pentium processor easily accessible user (i.e., place Intel Pentium OverDrive processor socket under hard disk). insertion force (LIF) used, position Pentium OverDrive processor socket board such that there ample clearance around socket. Intel packages Pentium OverDrive processors with "keyed configuration" that insures that Pentium OverDrive processors fits into respective sockets correct orientation. high count Pentium OverDrive processors often require more than insertion force Insertion Force (LIF) sockets. Zero Insertion Force (ZIF) socket insures that chip insertion force does damage Board. socket handle, sure allow enough clearance socket handle. socket used, additional board support recommended. Jumper switch changes should needed electrically configure system Pentium OverDrive processor. Describe Pentium OverDrive processor's installation procedure PC's User's Manual.
Accessible Pentium OverDrive Processor Socket
Foolproof Chip Orientation
Zero Insertion Force Upgrade Socket
"Plug Play"
Thorough Documentation
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
APPENDIX
Part 916513 916560 916655 916656 916671 916672 916637 916657 916658 SLR-S19-320-LN2 SLR-S19-321-LN2
Pentium® OverDrive® Processor with MMXTechnology SOCKET VENDORS
following list provides examples sockets which used Pentium processor-based systems. NOTE This comprehensive list, Intel tested Vendor's sockets listed below cannot guarantee that these will meet every manufacturer's specific requirement. Socket (800) 522-6752 Socket Socket Socket Socket Socket Socket Socket Socket Socket Appros (408) 567-1234 Socket Socket Style SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, Drawing C-916513 C-916560 C-916655 C-916656 C-916671 C-916672 C-916637 C-916657 C-916658 KEA391129 KEA391130
Average plating thickness used qualification testing: 11.2 micro inches gold.
Augat (800) 999-7646 Socket Socket Socket Socket Socket Socket SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, MP-AX159BCD20 MP-AX159BCD20A MP-AX159BCD20B MP-AX164BCD21X MP-AX164BCD21XA MP-AX164BCD21XB MP-AX159BCD203 MP-AX159BCD203A MP-AX159BCD203B MP-AX164BCD213 MP-AX164BCD213A MP-AX164BCD213B
Average plating thickness used qualification testing sockets: micro inches gold.
Berg/Mckenzie (510) 654-2700 Socket Socket Socket Socket Foxconn (408) 749-1228 Socket Socket Socket Socket Socket Socket
Pentium OverDrive PROCESSOR WITH MMXTECHNOLOGY
Socket
Style SLAZ, SLAZ, SLAZ, SLAZ,
Drawing 270086-000 270086-000 270088-000 270088-000
Part 97050-4020 97050-4120 97054-4020 97054-4120
Average plating thickness used qualification testing sockets: micro inches gold
SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, 309-0000-049 309-0000-049 309-0000-049 309-0000-049 309-0000-062 309-0000-062 PZ32023-0120 PZ32033-0120 PZ32043-0120 PZ32053-0120 PZ32143-0120 PZ32153-0120
Average plating thickness used qualification testing: 10.0 micro inches gold
(714) 753-2628 Socket Socket SLAZ, SLAZ, SJ029842-E SJ029842-E PCPS-ZL320-A9 PCPS-ZL321-A9
Average plating thickness used qualification testing: Socket micro inched gold Flash/31.4 microinches Palladium Nickel, Socket micro inched gold Flash/34 micro inches Palladium Nickel.
Producer 886-2-202-3578 Yamaichi (800) 769-0797 Socket SLAZ, PD104-3202 PD104-32025
Average plating thickness used qualification testing: micro inches gold.
Socket Socket Socket Socket Socket Socket Socket Socket SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, SLAZ, KL-13790 KL-13425 KL-13518 KL-13930 KL-13625 KL-13823 KL-13620 KL-13938 NP210-320-0100-CC0 NP210-320-0100-CC1 NP210-320-0100-CC2 NP210-320-0100-CC3 NP210-320K13625(D) NP210-321-0100-CC1 NP210-321-0100-CC2 NP210-321-0100-CC3
Average plating thickness used qualification testing: micro inches gold.
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