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Pentium® OverDrive® PROCESSOR WITH MMX TECHNOLOGY FOR Pentium PROCESSOR-BASED SYSTEMS

Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY

200-MHz Pentium® OverDrive® Processor with MMX Technology to upgrade 100 / 133 / 166-MHz Pentium Processor-Based Systems 180-MHz Pentium OverDrive Processor with MMX Technology to upgrade 90 / 120 / 150-MHz Pentium Processor-Based Systems and upgrades 75-MHz Pentium Processor-Based Systems to 150-MHz 166-MHz Pentium OverDrive Processor with MMX Technology to upgrade 100 / 133MHz Pentium Processor-Based Systems
PRELIMINARY
Pentium® OverDrive® PROCESSOR WITH MMX TECHNOLOGY FOR Pentium PROCESSOR-BASED SYSTEMS
Support for MMX Technology Powerful Processor Upgrades for Upgradable Pentium® Processor-Based Systems Superscalar Architecture Enhanced pipelines Two Pipelined Integer Units Capable of 2 Instructions / Clock Pipelined MMX Unit Pipelined Floating-Point Unit Separate Code and Data Caches Deeper Write Buffers, "Pool" Configuration Enhanced Branch Prediction Virtual Mode Extensions 32-Bit CPU with 64-Bit Data Bus .35µM CMOS Silicon Technology
On-package Voltage Regulation and Voltage Filtering Integrated Fan / Heatsink Thermal Solution Compatible with Installed Software Base MS-DOS, Windows, Windows 95, Windows NT, OS / 2, UNIX Product Line Supports Socket 5 & Socket 7 Designs 320 pin SPGA Package Bus / Core Ratio, Hard-Bonded in 2 / 5 and 1 / 3 Modes Easy Installation Supports 50, 60, 66-MHz Bus Speeds Single 3.3 Volt Supply
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
PRELIMINARY
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
CONTENTS
PAGE PAGE 3.7. On-Package Voltage Regulator..........30 3.8. Cache Support.......................30 3.9. Code Prefetch Queue and Branch Target Buffers .............................30 3.10. I / O Buffers .........................30 3.11. Test Register Access .................30 4.0. BIOS AND SOFTWARE.................31 5.0. ELECTRICAL SPECIFICATIONS..........31 5.1. Power and Ground ....................31 5.2. Decoupling Recommendations...........31 5.3. Other Connection Recommendations .....31 5.4. Absolute Maximum Ratings.............31 5.5. D.C. Specifications ....................33 5.6. A.C. Specifications ....................34 5.6.1. A. C. TABLES FOR A 50-MHZ BUS...34 5.6.2. A. C. TABLES FOR A 60-MHZ BUS...38 5.6.3. A. C. TABLES FOR A 66-MHZ BUS...42 5.6.4. TIMING AND WAVEFORMS ........46 6.0. MECHANICAL SPECIFICATIONS .........50 6.1. Package Dimensions..................50 6.2. Spatial Requirements ..................52 6.3. Socket..............................53 6.3.1. SOCKET COMPATIBILITY ..........53 6.3.2. SOCKET 5 PINOUT...............53 6.3.3. SOCKET 7 PINOUT...............54 7.0. THERMAL SPECIFICATIONS ............57 8.0. TESTABILITY .........................57 8.1. Introduction ..........................57 8.2. Built in Self Test (BIST) ................57 8.3. Tri-State Test Mode...................57
1.0. INTRODUCTION ........................5 1.1. Product Overview......................5 1.2. Product Description ....................8 1.3. Purpose of this Document ...............8 1.4. Compatibility Note .....................8 2.0. PINOUT AND PIN DESCRIPTION..........8 2.1. Pinout...............................8 2.2. Pin Cross Reference ..................11 2.3. Quick Pin Reference ..................14 2.4. Pin Descriptions ......................22 2.4.1. INPUT PINS .....................22 2.4.2. OUTPUT PINS ...................24 2.4.3. INPUT / OUTPUT PINS .............25 2.4.4. PIN GROUPING ACCORDING TO FUNCTION ......................26 3.0. COMPONENT OPERATION..............27 3.1. Core to Bus Ratio for Higher Speed.......27 3.2. Hardware Interface Differences ..........27 3.2.1. CPUTYP SIGNAL .................27 3.3. Processor Initialization .................27 3.3.1. POWER UP SPECIFICATION.......27 3.3.2. TEST AND CONFIGURATION FEATURES (BIST, FRC, TRISTATE TEST MODE)....................28 3.3.3. INITIALIZATION WITH RESET, INIT AND BIST .......................28 3.4. Instruction Differences.................28 3.4.1. MMX TECHNOLOGY EXTENSIONS TO THE INTEL ARCHITECTURE....28 3.4.2. RDPMC (READ PERFORMANCE MONITORING COUNTER) .........28 3.5. CPUID .............................28 3.6. On-Package Fan / Heatsink ..............30
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
FIGURES Figure 1. Pentium® OverDrive® Processor with MMX Technology Block Diagram...6 Figure 2. Pentium® OverDrive® Processor with MMX Technology Key Features....7 Figure 3. Pentium® OverDrive® Processor with MMX Technology Upgrade Choices .7 Figure 4. Pentium® OverDrive® Processor with MMX Technology Pinout-Top Side View ...........................9 Figure 5. Pentium® OverDrive® Processor with MMX Technology Pinout-Pin Side View ..........................10 Figure 6. Pentium® OverDrive® Processor with MMX Technology with Fan / Heatsink30 Figure 7. Clock Waveform.................46 Figure 8. Valid Delay Timing ...............46 Figure 9. Float Delay Timing ...............47 Figure 10. Setup and Hold Timing...........47 Figure 11. Reset and Configuration Timing....48 Figure 12. Test Timing....................49 Figure 13. Reset and Configuration Timing....50 Figure 14. Pentium® OverDrive® Processor with MMX Technology Package Dimensions .....................52 Figure 15. Illustrates Physical Space Requirements for the Pentium® OverDrive® Processor with MMX Technology.....................53 Figure 16. Required Free Space from Sides of SPGA Package..................53 Figure 17. 320-Pin Socket 5................54 Figure 18. Pentium® OverDrive® Processor with MMX Technology Pinout-Top Side View ..........................55
Figure 19. Pentium® OverDrive® Processor with MMX Technology Pinout-Pin Side View...........................56
TABLES Table 1. 320-Pin SPGA Pin Cross Reference by Pin Name.....................11 Table 2. Quick Pin Reference ...............14 Table 3. Input Pins........................22 Table 4. Output Pins......................24 Table 5. Input / Output Pins..................25 Table 6. Interprocessor I / O Pins.............25 Table 7. Pin Functional Grouping ............26 Table 8. Pin Functional Groupings Not Supported by Pentium® OverDrive® Processor with MMX Technology ...........27 Table 9. Core / Bus Frequencies..............27 Table 10. EAX Bit Values Definition for CPUID..29 Table 11. EAX Bit Values Definition for Processor Type ...........................29 Table 12. Absolute Maximum Ratings without Fan / Heatsink ....................32 Table 13. Absolute Maximum Ratings for Fan / Heatsink Only................32 Table 14. 3.3V D.C. Specifications...........33 Table 15. 50-MHz Bus A.C. Specifications .....34 Table 16. 60-MHz Bus A.C. Specifications .....38 Table 17. 66-MHz Bus A.C. Specifications .....42 Table 18. Pentium® OverDrive® Processor with MMX Technology Package Summary .......................50 Table 19. Package Dimensions..............51 Table 20. Design Considerations ............59
PRELIMINARY
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Pentium processor-based systems that are compatible with the Pentium OverDrive processor with MMX technology must be designed to both the original processor specifications and the Pentium OverDrive processor with MMX technology specifications.
INTRODUCTION
Product Overview
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Figure 1. Pentium® OverDrive® Processor with MMX Technology Block Diagram
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Based on Advanced Pentium® Processor with MMX Technology q Superscalar Architecture q Pipelined Floating-Point Unit q Separate 16K Code and 16K Data caches q 64 Bit Data Bus q Address Parity q Virtual Mode Extensions q System Management Mode q Fractional Bus Operation 200, 180, and 166-MHz Pentium OverDrive® Processors with MMX Technology
q .35µM q
CMOS Silicon Technology Dynamic Branch prediction q Improved Execution Time q Writeback MESI Protocol in the Data Cache q Bus Cycle Pipelining q Internal Parity Checking q Performance Monitoring q Execution Tracing q Active Fan / Heatsink
For 75, 90, and 100-MHz Pentium Processor-Based Systems 320 Pin SPGA Pinout On-package Voltage Regulation
Figure 2. Pentium® OverDrive® Processor with MMX Technology Key Features
Current Processor 75-MHz Pentium Processor
Pentium® OverDrive® Processor with MMX Technology Upgrade 150-MHz Pentium OverDrive Processor with MMX Technology 180-MHz Pentium OverDrive Processor with MMX Technology
90 / 120 / 150-MHz Pentium Processor
100 / 133 / 166-MHz Pentium Processor
200 & 166-MHz Pentium OverDrive Processor with MMX Technology
Figure 3. Pentium® OverDrive® Processor with MMX Technology Upgrade Choices
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Product Description
always load the
The Pentium OverDrive processor with MMX technology comes in a 320-pin SPGA package and is a drop-in replacement for the 75, 90, 100, 120, 133, 150 and 166-MHz Pentium processor. It comes with on-package voltage regulation to provide the required 2.8 volts for the core and a fan / heatsink for a complete thermal solution. The internal core operates at 3.0 and 2.5 times the speed of the system bus for respective 200MHz and 166-MHz Pentium OverDrive processor with MMX technology. For dual socket systems the original processor must be removed and the Pentium OverDrive processor with MMX technology should be installed in the secondary socket since it does not support dual processing.
1. Do not depend on the states of any undefined bits when testing the values of defined register. Mask them out when testing. 2. Do not depend on the states of any undefined bits when storing them to memory or another register. 3. Do not depend on the ability to retain information written into any undefined bits. 4. When loading registers undefined bits as zeros.
5. Never connect signals to device pins marked "NC" or "RES". 6. INC pins are Internal No-Connects. This means that the pin is not connected to the processor internally. For example the CPUTYP signal pin on the Pentium OverDrive processor with MMX technology is internally not connected to the package pin. The core is internally tied to VSS. The pin on the package is defined as INC. Any external connections to the package pin will not affect the processor core because the core is physically disconnected from the package pin.
Purpose of this Document
This document describes the system architecture and physical environment of Pentium OverDrive processor with MMX technology. It also outlines differences between the originally installed Pentium processor and the Pentium OverDrive processor with MMX technology.
2.0. 1.4. Compatibility Note 2.1.
In this document some register bits are shown as "Intel Reserved" (RES) and some pins are marked as "No Connects" (NC) or "Reserved" (RES). When reserved bits are called out, treat them as fully undefined. This is essential for software compatibility with current and future processors. When a pin is marked as a "NC" or "RES" it is important to not connect any other signals to such pins to ensure proper operation. Intel strongly recommends following the guidelines below:
PINOUT AND PIN DESCRIPTION Pinout
The Pentium OverDrive processor with MMX technology has a 320-pin SPGA pinout and is designed to be installed into Socket 5 or Socket 7. See Section 6.3 for more details on Socket 5 and Socket 7. Figure 4 and Figure 5 are illustrations of each side of the SPGA package.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
VCC 2 VSS D36 D39 D3 7 VSS VSS D3 4 VCC 2
VCC 2 VSS D3 1 D3 3 NC DP3 VSS VSS D2 9 VCC 3
VSS D38 D40 D4 2
PICCLK PICD0
PM0BP0
CPU TYP NC VSS NC
VSS VCC 2 VSS
PM1BP1 BP2 MI / O# INV BP3 NC
CAC HE# VSS
AHOLD KEN#
STPC LK# NC INC INC NC
EW BE#
VSS VCC 2
BRD Y# NA#
BRD YC# VSS
FR CMC# PEN# VSS
BOFF # PHIT# W B / WT # INIT
IGNNE# SMI# VSS RS# INTR
HOLD PRD Y NMI
PHITM# VSS
PBREQ# APCH K# VSS PCH K# PCD
SMIACT#
VSS BREQ AP
LO CK# HLDA ADS# D / C# PW T HIT# VSS VSS VCC 2 BE1# BE2# VSS VCC 2 VSS VCC 2 VSS BE3# BE5 # BE6 # VSS VCC 2 VCC 2 VSS NC BE7 # SCYC VSS VCC 2 VSS VCC 3 CLK NC VSS VCC 2 VSS A1 9 A1 8 VSS VCC 3 VSS VCC 3 VCC 3 NC A1 7 A1 6 VSS VCC 3 VSS A1 5 A1 4 VSS VCC 3 VSS VCC 3 A1 3 A1 2 VSS A9 A1 1 VSS A5 A3 1
A2 0M#
RESET A2 0
HITM# BUSC HK# BE0# W / R# VSS
ADSC # VCC 5
EADS# INC
FLUSH#
Figure 4. Pentium® OverDrive® Processor with MMX Technology Pinout-Top Side View
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
VCC2 VSS VSS D38 D39 D42 D40 D46 DP5 DP4 D44 D49 D51 D53 D56 D58 D59 D57 VSS D61 D62 VCC2 VSS D63 VSS VCC2 VCC2 L M N P Q R S T VCC2 U V VCC2 W X Y Z VCC2 AA AB AC AD VCC2 AE AF VCC2 AG AH AJ AK INC AL AM AN D55 VSS VCC2
A NC B C D E F G H J K L M N P Q VCC3 R S T U V W X Y Z AA VCC3 AB AC AD AE AF AG AH AJ VSS AK AL AM AN VSS VSS A30 NC A28 A3 A4 A6 VCC3 A22 A25 A29 A7 A8 A10 VCC3 VSS A24 A26 A31 A5 A11 VSS VCC3 VSS A9 A12 VCC3 VCC3 VSS D / P# A21 A27 VCC3 VCC3 VSS VCC3 VSS VCC3 VSS VSS VCC3 VSS VCC3 VCC3 VSS PICD1 VSS TDI TMS# VCC3 VSS D2 D0 VCC3 D9 DP0 VCC3 D4 D1 D6 D5 D3 D11 D10 D8 D7 D15 D13 D14 D12 VSS D18 D16 D17 DP1 VSS D22 VCC3 D20 D21
VCC3 VSS D24 D19 VCC3 D23 NC VSS DP2 D26 VSS VCC3 VCC3 VSS D25 D28 VSS
VCC3 VSS D27 D30 VCC3 VSS D29 DP3 NC VCC3 VSS D31 D33 VCC2 VCC2 VSS D32 D35 VCC2 VSS
VCC2 VCC2 VSS D34 D37 VSS D36
VSS D45
VCC2 D47 INC D50 D52 DP6 VCC2 D54
PICCLK PICD0
TCK TDO DP7
IERR# FERR#
CPUTYP TRST# VSS NC VCC3 VCC3 NC NC
PM0BP0
PM1BP1 BP3 MI / O# INV BP2
VSS VCC2 VSS
CACHE# VSS
STPCLK# NC INC INC NC
AHOLD KEN#
EWBE#
BRDY# NA#
VSS VCC2
FRCMC# VSS
BRDYC# VSS
PEN# INIT
BOFF# WB / WT#
IGNNE# VSS RS# INTR SMI#
PHIT#
HOLD NMI PRDY
VSS VCC2
PHITM# VSS
PBGNT# A23
APCHK# PBREQ# PCHK# PCD VSS
SMIACT#
LOCK# VSS A13 A14 VSS VCC3 VSS VCC3 A15 A16 VSS VCC3 VSS A17 A18 VSS VCC3 NC VSS A19 VCC3 RESET A20 VSS VCC2 NC VSS VCC2 CLK SCYC VSS VCC2 VSS BE7# NC VSS BE5# VCC2 BE3# BE1# BE2# VSS VCC2 VSS VCC2 VSS VSS A20M# ADS# HIT# D / C# PWT HLDA
VSS BREQ AP
BE4# VSS
BE0# BUSCHK# HITM# VSS W / R#
EADS# INC
ADSC# VCC5
FLUSH#
Figure 5. Pentium® OverDrive® Processor with MMX Technology Pinout-Pin Side View
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Signal A3 A4 A5 A6 A7 A8 Signal D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Pin Cross Reference
Table 1. 320-Pin SPGA Pin Cross Reference by Pin Name Address Location AL35 AM34 AK32 AN33 AL33 AM32 Signal A9 A10 A11 A12 A13 A14 Location AK30 AN31 AL31 AL29 AK28 AL27 Signal A15 A16 A17 A18 A19 A20 Data Location K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 Signal D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 Location B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 Signal D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 Location D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C09 Signal D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 Location D10 D08 A05 E09 B04 D06 C05 E07 C03 D04 E05 D02 F04 Signal D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 Location E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03 Location AK26 AL25 AK24 AL23 AK22 AL21 Signal A21 A22 A23 A24 A25 A26 Location AF34 AH36 AE33 AG35 AJ35 AH34 Signal A27 A28 A29 A30 A31 Location AG33 AK36 AK34 AM36 AJ33
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Signal PEN# PM0 / BP0 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT# Location Z34 Q03 R04 AC05 AL03 AC35 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 AM06 AA05
Table 1. 320-Pin SPGA Pin Cross Reference by Pin Name (Continued) Control Signal A20M# ADS# ADSC# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# Location AK08 AJ05 AM02 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 S05 X04 APIC Signal PICCLK PICD0 DPEN# PICD1 APICEN L35 Location H34 J33 Signal BRDYC# BREQ BUSCHK# CACHE# CPUTYP D / C# D / P# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# Location Y03 AJ01 AL07 U03 Q35 AK04 AE35 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05 Signal FLUSH# FRCMC# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# Location AN07 Y35 AK06 AL05 AJ03 AB04 P04 AA35 AA33 AD34 U05 W05 AH04 T04 Y05 AC33 AG05 AF04 Dual Processor Private Interface Signal PBGNT# PBREQ# PHIT# PHITM# Location AD04 AE03 AA03 AC03
Clock Control Signal CLK BF BF1 STPCLK# Location AK18 Y33 X34 V34
NOTES: The shaded pin definitions on the Pentium® OverDrive® processor with MMX technology are dual processing pins and are not supported by the Pentium OverDrive processor with MMX technology in Table 2. · The D / P# signal in the 75, 90, 100, 120, 133, 150, and 166-MHz Pentium processor is always driven. Low indicates primary processor has the bus and high indicates the secondary processor is driving the bus. In the Pentium OverDrive processor with MMX technology this pin is defined internal no connect. These signals are internally set and are not connected to the Pentium OverDrive processor with MMX technology pins. The pins are defined as Internal No-Connects.
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A07 A09 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 B02 E15 E21 E27 E37 G01 A03 B06 B08 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 E11 E13 E19
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Table 1. 320-Pin SPGA Pin Cross Reference by Pin Name (Continued) VCC G37 J01 J37 L01 L33 L37 N01 N37 Q01 Q37 S01 S37 VSS E23 E29 E31 H02 H36 K02 K36 M02 M36 P02 P36 R02 R36 T02 T36 U35 NC / INC A37 E17 E25 R34 S33 S35 W33 W35 C01 AJ15 AJ23 AL19 AN35 AN05 V02 V36 X02 X36 Z02 Z36 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ07 AJ09 AJ13 AJ17 AJ21 AJ25 AJ27 AJ31 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 VCC5 AN01 AN03 AM26 AM28 AM30 AN37 AL01 T34 U01 U33 U37 W01 W37 Y01 Y37 AA01 AA37 AC01 AC37 AE01 AE37 AG01 AG37 AJ11 AJ19 AJ29 AN09 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25 AN27 AN29
NOTE: The shaded VCC / VSS / NC pins are new pin definitions (additions) on the Pentium ® OverDrive® processor with MMX technology with the exception of A03 and B02.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Quick Pin Reference
Table 2. Quick Pin Reference
Symbol A20M# I
A31-A3
ADS# ADSC# AHOLD
APCHK#
APICEN PICD1 BE7#-BE5# BE4#-BE0#
BF BF1
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Symbol BOFF# I Type BP3:2 PM / BP1:0 O BRDY# I
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
BRDYC# BREQ
BUSCHK#
CACHE#
CPUTYP
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
D / P# D63-D0
DP7-DP0
DPEN# PICD0 EADS#
EWBE#
FERR#
FLUSH#
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Symbol HIT# O Type HITM# O HLDA O
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
IERR#
IGNNE#
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
LOCK#
NMI / LINT1 PBGNT#
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Symbol PCD O Type PCHK# O PEN# I
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
PHIT# PHITM# PICCLK PICD0-1 DPEN# APICEN PBREQ# PM / BP1:0
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
SMIACT# STPCLK#
TMS TRST# VCC2
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Symbol VCC3 VCC5 VSS W / R# I I I O Type WB / WT# I
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Table 2. Quick Pin Reference (Continued) Name and Function These 32 power inputs must be connected to 3.3V in either single or split voltage systems. The Pentium OverDrive processor with MMX technology has two 5V power inputs. The Pentium OverDrive processor with MMX technology has 68 ground inputs. Write / read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W / R# distinguishes between write and read cycles. The writeback / writethrough input allows a data cache line to be defined as writeback or writethrough on a line by line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
NOTE: Highlighted items in Table 2 are signals not supported on the Pentium® OverDrive® processor with MMX technology.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Pin Descriptions
INPUT PINS Table 3. Input Pins Name A20M# AHOLD BF BF1 BOFF# BRDY# BRDYC# BUSCHK# CLK CPUTYP EADS# EWBE# FLUSH# FRCMC# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PICCLK PEN# R / S# Active Level Low High N / A N / A Low Low Low Low n / a N / A Low Low Low N / A High Low High High High Low Low High N / A Low n / a Synchronous / RESET Synchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous Pullup Pullup Pullup Pulldown Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous / RESET Synchronous Synchronous Synchronous Synchronous Pullup Pullup Pulldown Pullup Internal Resistor
Qualified Bus State T2, T12, T2P Bus State T2, T12, T2P BRDY#
BRDY#
EADS# First BRDY# / NA# Bus State T2, TD, T2P
BRDY#
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Name RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT#
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Table 3. Input Pins (Continued) Active Level High Low Low n / a n / a n / a Low n / a Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous / Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY# / NA# TCK TCK Internal Resistor Qualified
NOTE: Highlighted signals are original Pentium® processor 75 / 90 / 100 / 120 / 133 / 150 / 166 MHz signals and are not supported by the Pentium OverDrive® processor with MMX technology.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
2.4.2. OUTPUT PINS Table 4. Output Pins Name ADS# ADSC# APCHK# BE7#-BE5# BREQ CACHE# D / P# FERR# HIT# HITM# HLDA IERR# LOCK# M / IO# , D / C# , W / R# PCHK# BP3-2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO Active Level Low Low Low Low High Low n / a Low Low Low High Low Low n / a Low High High High High Low n / a Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF# Bus Hold, BOFF#
All states except Shift-DR and Shift-IR
NOTES: All output pins are floated during tristate test mode (except TDO). Signals are original Pentium® processor signals and are not used by the Pentium OverDrive® processor with MMX technology.
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2.4.3. Name AP
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
INPUT / OUTPUT PINS Table 5. Input / Output Pins Active Level n / a n / a Low n / a n / a When Floated Address hold, Bus Hold, BOFF# Address hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (When an Input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown Internal Resistor
A31-A3
BE4#-BE0# D63-D0 DP7-DP0 PICD0DPEN# PICD1APICEN
NOTES: All input / output pins are floated during tristate test. ® ® Signals are original Pentium processor signals and are not used by the Pentium OverDrive processor with MMX technology.
Table 6. Interprocessor I / O Pins Name PHIT# PHITM# PBGNT# PBREQ# Active Level n / a n / a n / a n / a Internal Resistor Pullup Pullup Pullup Pullup
NOTE: ® ® Signals are original Pentium processor signals and are not used by the Pentium OverDrive processor with MMX technology.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
2.4.4. PIN GROUPING ACCORDING TO FUNCTION
Table 7 organizes the pins with respect to their function. Table 7. Pin Functional Grouping Function Clock Initialization Address Bus Address Mask Data Bus Address Parity Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating-Point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Probe Mode CLK RESET, INIT A31-A3, BE7# - BE0# A20M# D63-D0 AP, APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-2 STPCLK# R / S#, PRDY
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Function APIC Support Miscellaneous Dual Processing Execution Tracing
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Table 8. Pin Functional Groupings Not Supported by Pentium® OverDrive® Processor with MMX Technology Pins PICCLK, PICD0-1 PBGNT#, PBREQ#, PHIT#, PHITM# FRCMC# CPUTYP, D / P# BT3-BT0, IU, IV, IBT
Dual Processing Private Bus Control Functional Redundancy Checking
COMPONENT OPERATION Core to Bus Ratio for Higher Speed
Hardware Interface Differences
The Pentium OverDrive processor with MMX technology incorporates an internal Phase Lock Loop (PLL) and clock multiplier to generate the higher internal speeds. This allows the internal processor core to operate synchronously and at higher frequencies than the external bus. On the 200 / 180-MHz Pentium OverDrive processor with MMX technology, the bus fraction configuration will be preset to 3 / 1 internally and 166-MHz to 5 / 2. See Table 9 for details. Table 9. Core / Bus Frequencies Internal Speed 150-MHz 180-MHz Bus Speed 50-MHz 60-MHz Replaces (Core / Bus) 75 / 50-MHz 90 / 60-MHz 120 / 60-MHz 150 / 60-MHz 166-MHz 66-MHz 100 / 66-MHz 133 / 66-MHz 200-MHz 66-MHz 100 / 66-MHz 133 / 66-MHz 166 / 66-MHz
The Pentium OverDrive processor with MMX technology is pin-for-pin compatible with the respective original Pentium processors, except for the additional pins defined by Socket 5 and 7 for the Pentium OverDrive processor with MMX technology. Some minor differences are discussed in this section and are referenced in tables in previous section. These differences represent features that are not required for an end-user CPU upgrade. 3.2.1. CPUTYP SIGNAL
The Pentium OverDrive processor with MMX technology CPUTYP signal is internally tied to ground and the signal pin on the package is an internal no-connect (INC). The original Pentium processor must be removed for the Pentium OverDrive processor with MMX technology to function properly.
Processor Initialization
POWER UP SPECIFICATION
The Pentium OverDrive processor with MMX technology will boot like the respective original Pentium processors. If the Pentium OverDrive processor with MMX technology is installed in a second socket of dual socket system the primary CPU must be removed or the system will not boot properly.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
3.3.2. TEST AND CONFIGURATION FEATURES (BIST, FRC, TRISTATE TEST MODE)
The Pentium OverDrive processor with MMX technology will execute the Built In Self Test (BIST) and Tristate Test Mode same as the respective original Pentium processor. Functional Redundancy Checking is not supported. 3.3.3. INITIALIZATION WITH RESET, INIT AND BIST
The Pentium OverDrive processor with MMX technology handling of RESET, INIT, and the Built In Self Test (BIST) is the same as the original Pentium processors. The register states after RESET, INIT, and BIST are same as the original Pentium processors. For further information refer to Section 8 in this datasheet.
RDPMC will enable the user to only READ the performance monitoring counters.
Instruction Differences
CPUID
The stepping field has the same format as the original Pentium processor and will be the same for the Pentium OverDrive processor with MMX technology. The Pentium OverDrive processor with MMX technology will have a unique CPUID from the original Pentium processor and the Pentium processor with MMX technology (154xH Vs. 052xH and 054xH). The type field is defined in Table 11.
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CPU Field Definition Bit 13 0 0 0 1 1 Bit 12 0 0 1 0 1
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Table 10. EAX Bit Values Definition for CPUID 31..14 (reserved) (reserved) (reserved) (reserved) 13..12 type Table 11 Table 11 Table 11 11..8 family 5H 5H 5H 7..4 model 2H 4H 4H 3..0 stepping varies varies varies
Pentium® processor (75, 90, 100) Pentium processor with MMX technology (166, 200, 233-MHz) Pentium OverDrive® processor with MMX technology
Table 11. EAX Bit Values Definition for Processor Type Processor Type Primary Pentium® processor
Primary Pentium processor with MMX technology Pentium OverDrive® processor with MMX technology Dual Pentium processor Reserved
NOTE: The Pentium® OverDrive® processor with MMX technology does not support Dual Processing mode.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
FAN HEATSINK CERAMIC PGA or SPGA
Figure 6. Pentium® OverDrive® Processor with MMX Technology with Fan / Heatsink
On-Package Fan / Heatsink
Code Prefetch Queue and Branch Target Buffers
Code should not be written to rely on the specific code prefetch queue or branch target buffer mechanism of a particular processor. With each new generation and family of processors, these mechanisms are subject to change.
I / O Buffers
On-Package Voltage Regulator
The Pentium OverDrive processor with MMX technology has an on-package voltage regulator to supply 2.8 volts to the processor core. This allows the Pentium OverDrive processor with MMX technology to function in a 3.3 volt only system.
Cache Support
The Pentium OverDrive processor with MMX technology buffer models comply with the specifications for the buffer model for the respective original Pentium processor. The circuit topology is the same and the ranges of values in the Pentium OverDrive processor with MMX technology model are within the original Pentium processor ranges. The buffer models used by the Pentium OverDrive processor with MMX technology accurately model flight time and signal quality.
The Pentium OverDrive processor with MMX technology has an enhanced internal cache (2x16KB Total, 4 way set-associative Code and Data caches, each with improved TLBs) and will support the L2 caches supported by the Pentium processor (75200). The Pentium OverDrive processor with MMX technology supports the Intel 82430 chipsets. Chipsets with 5V signal levels, 82497 / 82492 cache controller, and the 82498 / 82493 cache controller are not supported by the Pentium OverDrive processor with MMX technology. 30
Test Register Access
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
BIOS AND SOFTWARE
Decoupling Recommendations
ELECTRICAL SPECIFICATIONS
Decoupling recommendation for the original Pentium processor apply to the Pentium OverDrive processor with MMX technology upgradable systems and capacitors should be placed near the Pentium OverDrive processor with MMX technology. The Pentium OverDrive processor with MMX technology can cause transient power surges, particularly when driving large capacitive loads. The Pentium OverDrive processor with MMX technology are shipped with adequate decoupling capacitors on the package to limit transients in excess of Pentium processors tolerance. It is recommended to follow the original Pentium processor specification for decoupling recommendations.
Other Connection Recommendations
Power and Ground
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC. Unused active high inputs should be connected to ground. All NC pins must remain unconnected.
For clean on-chip power distribution, the Pentium OverDrive processor with MMX technology in an SPGA package has 60 VCC (power) and 68 VSS (ground) inputs. The 28 VCC2 pins are connected internally to a power plane that provides power to the on-package voltage regulator for the core supply. The 32 VCC3 pins are connected internally to a separate power plane that provides power to the I / O buffers. Power and ground connections must be made to all external VCC and VSS pins of the Pentium OverDrive processor with MMX technology. On the circuit board all VCC pins must be connected to a 3.3V VCC plane. All VSS pins must be connected to a VSS plane. The Pentium OverDrive processor with MMX technology pinout contains two 5V VCC pins (VCC5) used to provide power to the fan / heatsink. These
Absolute Maximum Ratings
The tables in this section provide environmental stress ratings for the Pentium OverDrive processor with MMX technology. Functional operation at the absolute maximum and minimum is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. Furthermore, precautions should be taken to avoid high static voltages and electric fields to prevent static electric discharge. Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. The tables contain stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability.
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Max Unit
Table 12. Absolute Maximum Ratings without Fan / Heatsink Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC5 VIN 3.3 V Supply Voltage with respect to VSS 5 V Supply Voltage with respect to VSS 3.3 V Only Buffer DC Input Voltage -40 -40 -0.5 -0.5 -0.5 Min +125 +110 +4.6 6.5 VCC3+0.5V not to exceed 4.6V MAX +6.5 Notes
VINSB
5.0V Safe Buffer DC Input Voltage
Table 13. Absolute Maximum Ratings for Fan / Heatsink Only Parameter Fan: Storage Temperature Case Temperature Under Bias VCC5 5V Fan Supply Voltage with Respect to VSS -40 -5 -0.5 70 60 6.5 °C °C V Min Max Unit Notes
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Symbol VIL VIH VOL VOH VIL5 VIH5 ICC5 ICC3
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
D.C. Specifications
The Pentium OverDrive processor with MMX technology will have compatible D.C. specifications to the original Pentium processor, except for ICC (Power Supply Current) and ICC5 (Fan / Heatsink Current). The Pentium OverDrive processor with
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
A.C. Specifications
A. C. TABLES FOR A 50-MHZ BUS
hold requirements for a 50-MHz external bus. All A.C. specifications (with the exception of those for the TAP signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5 volts for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct 150-MHz Pentium OverDrive processor with MMX technology running 125-MHz operation.
Notes
The AC specifications of the 180 / 150-Pentium OverDrive processor with MMX technology consist of setup times, hold times, and valid delays at 0pF. The A.C. specifications given in Table 15 consist of output delays, input setup requirements and input
t6b t6c t7
t8 t9 t10a t10b t11a
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Symbol t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t22a t23 t24 t25a t25b t26 t27 t28 t29 t30 t31 t32 PRDY Valid Delay A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time KEN# Setup Time
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay
EADS#, INV, AP Hold Time
NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time BOFF# Setup Time AHOLD Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time
INIT, FLUSH#, NMI, SMI#, IGNNE# Hold 1.0 Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time 2.0 5.0 1.0
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Figure Notes (14), (16) 10 10 11 11 11 11 11 11 11 11 (11), (15) (12) (16) Power up (11), (15), (16) (12) To RESET falling edge (15) To RESET falling edge (20) To RESET falling edge (20) To RESET falling edge (1), (27)
t42c t42d
CLKs nS
t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 36
MHz nS nS nS 7 7 7 7 7 13 12 12 12 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (8), (9) (0.8V-2.0V), (1), (8), (9) (1), Asynchronous (7) (7) (8)
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Symbol t54 t55 t56 t57 t58 TDO Float Delay
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
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5.6.2. A. C. TABLES FOR A 60-MHZ BUS
The A.C. specifications given in Table 16 consist of output delays, input setup requirements and input hold requirements for a 60-MHz external bus. All A.C. specifications (with the exception of those for the TAP signals) are relative to the rising edge of the CLK input.
All timings are referenced to 1.5 volts for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct 180-MHz Pentium OverDrive processor with MMX technology operation.
t6b t6c t7
t8a t8b t9a t9b t10a t10b t11a t11b t12
D0-D63, DP0-7 Write Data Valid Delay 1.3
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Symbol t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24 t25 t25a t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time KEN# Setup Time
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
EADS#, INV, AP Hold Time
NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time R / S# Pulse Width, Async.
D0-D63, DP0-7 Read Data Setup Time 3.0 D0-D63, DP0-7 Read Data Hold Time 1.5
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Notes (11), (15) (12) (16) Power up (11), (15), (16) (12) (15) (20)
Reset Configuration Signals (FLUSH#, 2.0 BRDYC#, INIT, BUSCHK#) Hold Time, Async. Reset Configuration Signals (BRDYC#, 3.0 BUSCHK#) Setup Time, Async. Reset Configuration Signals (BRDYC#) Hold Time, RESET Driven Synchronously. TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay 3.0 40.0 5.0 13.0 3.0 20.0 25.0 20.0 25.0 1.0
t42c t42d
CLKs nS
(20) To RESET falling edge (1), (27)
t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 40
MHz nS nS nS 7 7 7 7 7 13 12 12 12 12 12 12 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (8), (9) (0.8V-2.0V), (1), (8), (9) Asynchronous, (1) (7) (7) (8) (1), (8) (3), (8), (10) (1), (3), (8), (10)
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Symbol t57 t58
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
5.6.3. A. C. TABLES FOR A 66-MHZ BUS
The A.C. specifications given in Table 17 consist of output delays, input setup requirements and input hold requirements for a 66-MHz external bus. All A.C. specifications (with the exception of those for the TAP signals) are relative to the rising edge of the CLK input.
All timings are referenced to 1.5 volts for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct 200-MHz Pentium OverDrive processor with MMX technology operation.
t8a t8b t9a t9b t10a t10b t11a t11b t12
D0-D63, DP0-7 Write Data Valid Delay 1.3
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Symbol t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24 t25a t25b t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time KEN# Setup Time
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
EADS#, INV, AP Hold Time
NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time R / S# Pulse Width, Async.
D0-D63, DP0-7 Read Data Setup Time 3.0 D0-D63, DP0-7 Read Data Hold Time 2.0
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Notes (11), (15) (12) (16) Power up (11), (15), (16) (12) To RESET falling edge (15) To RESET falling edge (20) To RESET falling edge (20) To RESET falling edge (1), (27)
t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55
MHz nS nS nS 7 7 7 7 7 13 12 12 12 12 12 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (8), (9) (0.8V-2.0V), (1), (8), (9) Asynchronous, (1) (7) (7) (8) (1), (8) (3), (8), (10)
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Symbol t56 t57 t58
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
5.6.4. TIMING AND WAVEFORMS
Figure 7. Clock Waveform
Figure 8. Valid Delay Timing
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Figure 9. Float Delay Timing
Figure 10. Setup and Hold Timing
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Figure 11. Reset and Configuration Timing
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Figure 12. Test Timing
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Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Figure 13. Reset and Configuration Timing
MECHANICAL SPECIFICATIONS Package Dimensions
Table 18. Pentium® OverDrive® Processor with MMX Technology Package Summary
Package Total Type Pins Pin Array Package Size
The Pentium OverDrive processor with MMX technology, an upgrade for the 75, 90, 100-MHz Pentium processor-based systems, uses a 320-pin ceramic staggered pin grid array (SPGA) package. The pins will be arranged in a 37 x 37 matrix and the package dimensions will be 1.95 x 1.95 (4.95cm x 4.95cm). See Table 18.
Pentium® OverDrive® Processor with MMX Technology
1.95" x 1.95" 4.95cm x 4.95cm
NOTE: The mechanical specifications are provided in Table 19. Figure 14 shows the package dimensions for the Pentium® OverDrive® processor with MMX technology.
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Symbol Min A A1 A2 A4 A5 B D D1 E1 E2 L N S1 10.16 0.43 49.28 45.47 2.41 1.14 3.05 320 1.52 0.33 2.62
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Table 19. Package Dimensions Family: Ceramic Staggered Pin Grid Array Package Millimeters Max 33.88 0.43 2.97 20.32 Air Space 0.51 49.91 45.97 2.67 1.40 3.30 SPGA pins 2.54 0.400 0.017 1.940 1.790 0.095 0.045 0.120 320 0.060 0.100 0.020 1.965 1.810 0.105 0.055 0.130 SPGA pins Notes Solid Lid Solid Lid 0.013 0.103 Min Inches Max 1.334 0.017 0.117 0.800 Air Space Notes Solid Lid Solid Lid
NOTES: Assumes the minimum air space above the fan / heatsink. A 0.2 clearance around three of four sides of the package is also required to allow free airflow through the fan / heatsink.
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SEATING PLANE L
heat sink fan air space
D D1 S1 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 01.65AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA REF. AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Pin C3 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 45° CHAMFER (INDEX CORNER) 2.29 REF. 1.52
AAAAAAAAAA AAAA AAAA AAA AAAAAA AAAA AAA AAAAAA AAAA AAAA AAA AAAAAA AAAA AAAA AAA AAAAAA AAAA AAAA
AA AAAA AA AA AAAA AA AA AAAA AA AA AA AAAA AA AA AAAA AA AA AAAA AA AA AAAA AA AA AAAA AA AA AAAA AA AA AAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
PP0077
Figure 14. Pentium® OverDrive® Processor with MMX Technology Package Dimensions
Spatial Requirements
chassis, etc.) to enter within the free space distance of 0.2" from the Pentium OverDrive processor with MMX technology package if it is not taller than the level of the heatsink base. In other words, if a component is taller than height "B, " it cannot be closer to the Pentium OverDrive processor with MMX technology package than distance "A". This applies to three of the four sides of the Pentium OverDrive processor with MMX technology package, although the back and handle sides of a ZIF socket will generally automatically meet this specification since they have widths larger than distance "A." Compliance to this requirement will ensure systems can be upgraded to the Pentium OverDrive processor with MMX technology.
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NOTE:
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
Figure 16. Required Free Space from Sides of SPGA Package
Socket
SOCKET COMPATIBILITY
proper operation of Pentium OverDrive processor with MMX technology, all power and ground pins should be connected as defined by the respective socket definitions. 6.3.2. SOCKET 5 PINOUT
Socket 5 (320 pins) and Socket 7 (321 pins) are defined specifically for the requirements of the Pentium OverDrive processor with MMX technology. Socket 5 and Socket 7 define a fifth row of pins in the inside of the 296-pin SPGA socket. The rows "E" and "AJ" are the new rows of pins defined by Socket 5 and Socket 7. Socket 5 and Socket 7 are a superset of the original 75, 90, and 100-MHz Pentium processor (296 pins) pinout. The Pentium OverDrive processor with MMX technology sockets are compatible with their respective original Pentium processors. To insure
Socket 5 is the 320-pin ZIF (Zero Insertion Force) socket recommended for the 150 / 166-Pentium OverDrive processor with MMX technology. The Socket 5 pinout is defined with additional power and ground pins to ensure proper functionality of the Pentium OverDrive processor with MMX technology. The pinout is also specifically defined to ensure proper orientation for the Pentium OverDrive processor with MMX technology.
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D22 D20 D16 D17 DP1 D12 VSS D7 D5 D3 PICCLK D1 VSS D2 D0 VSS PICD1 TCK VSS TDI TMS# TRST# VSS VCC3 R VCC3 VSS VSS VSS VCC3 VSS VCC3 VCC3 S T U V W X Y Z AA VCC3 AB VCC3 VSS D / P# A21 A27 A26 A24 A22 A25 A29 A7 A8 A10 A6 A4 NC A3 A30 VSS A28 VSS VSS AK AL AM AN VSS VCC3 AH AJ VCC3 AC AD AE AF AG VCC3 VCC3 VCC3 D14 D8 D6 D4 VCC3
D18 D13
VCC3 VSS VSS DP4 D44 D40 D46 DP5
VCC3 VSS D38 D39 D42
VCC3 VSS D36 D37 VSS
VCC3 VSS D34 D35 VSS
VCC3 VSS D32 D33 VCC3
VCC3 VSS D31 DP3 NC
VCC3 VSS D29 D30 VSS
VCC3 INC D50 D52 DP6 D55 VSS D57 VSS D47
D43 D45 D48 D49 D51 D53 D56 D58 D59 D61 D62 D63 IERR# DP7 D60
VSS D27 D28 VCC3 VSS D25
VSS DP2 D26 NC
VSS D24 D23 VCC3
VSS D21 D19 VSS
PICD0
VSS VCC3
N P Q VCC3 R S VCC3 T U VCC3 V W VCC3 X Y VCC3 Z AA VCC3 AB AC VCC3 AD AE VCC3 AF AG VCC3 AH AJ AK AL AM AN INC VSS VSS VSS
PM0BP0
FERR#
CPUTYP NC VSS NC
PM1BP1 BP2 MI / O# INV BP3 NC
VCC3 VCC3
CACHE# VSS
AHOLD KEN#
STPCLK# NC BF1 BF NC
EWBE#
BRDY# NA#
BRDYC# VSS
FRCMC# PEN# VSS
BOFF# PHIT# WB / WT# INIT
IGNNE# SMI# VSS RS# INTR
HOLD PHITM# PRDY NMI
PBGNT# A23
PBREQ# APCHK# PCHK# PCD
SMIACT#
VSS BREQ AP
LOCK# HLDA ADS# D / C# PWT HIT# VSS VSS A20M# BE0# VSS VCC3 VCC3 VCC3 BE1# BE2# VSS VCC3 VSS BE3# BE5# BE4# VSS VCC3 BE6# VSS VCC3 NC BE7# SCYC VSS VSS VCC3 CLK NC VSS VCC3 VCC3 VSS A19 A20 VSS VCC3 A18 VSS VCC3 NC A17 A16 VSS VCC3 VSS A15 A14 VSS VCC3 VSS VCC3 A13 A12 VSS A9 A11 VSS A5 A31
RESET
HITM# BUSCHK# W / R# INC VSS
ADSC#
EADS#
FLUSH#
Figure 17. 320-Pin Socket 5
SOCKET 7 PINOUT
Socket 7 is a 321-pin ZIF (Zero Insertion Force) socket recommended for future Pentium and Pentium
OverDrive processors and should be used for all new designs. Socket 7 is pin compatible with the 320-pin Socket 5 with the addition of a key pin. Contact Intel for further information.
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VCC 2 VSS
VCC 3 VSS
D22 D20
D43 D45
VSS DP4 D44 D46
VSS D38 D40 D42
VSS D36 D39 VSS
VSS D34 D37 VSS
VSS D32 D35 VCC 2
VSS D31 D29 DP3 NC VSS
VSS D27 D25 D28 VCC 3 VSS
VSS DP2 D26 NC
VSS D24 D23 VCC 3
VSS D21 D19 VSS
D16 D17 D14 D12 VSS D7
CPU TYP NC VSS NC
VCC 3 VSS
VCC 3 VCC 3 VSS
VCC 3 VSS VCC 3 VSS VCC 3
FR CM C# PEN # VSS
HO LD PRD Y NMI
RES ET
FLUSH #
NOTE: Shaded pins are internal no connects on the Pentium® OverDrive® processor with MMX technology.
Figure 18. Pentium® OverDrive® Processor with MMX Technology Pinout-Top Side View
PRELIMINARY
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
A NC B C D E F G H J K L M N P Q R S T U V W X Y Z AA VCC3 AB AC AD AE AF AG AH AJ AK AL AM AN VSS VSS A30 NC VSS A28 A3 A4 A6 VCC3 A22 A25 A29 A7 A8 A10 VCC3 VSS A24 A26 A31 A5 A11 VSS VCC3 VSS A9 A12 VSS VCC3 VCC3 A13 A14 VSS VCC3 VSS A15 A16 VSS VCC3 VSS A17 A18 VSS VCC3 NC VSS A19 VCC3 RESET A20 VSS VCC2 NC CLK SCYC VSS VCC2 VSS VCC2 VSS BE7# NC BE5# BE6# VSS VCC2 VSS VCC2 BE3# BE1# BE2# VSS VCC2 VSS VCC2 VSS VSS A20M# VCC3 VSS D / P# A21 A27 VCC3 VCC3 VSS VCC3 VSS VCC3 VSS VSS VCC3 VCC3 VSS VCC3 VCC3 VSS PICD1 VSS TDI TCK TDO TMS# VCC3 VSS D2 D0 VCC3 VCC3 D4 D1 D9 DP0 D6 D5 D3 D11 D10 D8 D7 D15 D13 D14 D12 VSS D18 D16 D17 DP1 VSS D22 VCC3 D20 D21 D19 VCC3 VCC3 VSS D24 D23 NC VSS DP2 D26 VSS VCC3 VSS D25 D28 VCC3 VCC3 VSS D27 D30 VSS VCC3 VSS D29 DP3 NC VCC3 VSS D31 D33 VCC2 VCC2 VSS D32 D35 VSS VCC2 VSS D34 D37 VSS VCC2 VCC2 VSS D36 D39 D42 VSS D38 D40 D46 DP5 VCC2 VSS DP4 D44 VCC2 VSS
VSS D43 VCC2 D47 D48 D50 D52 D51 DP6 D55 D56 VSS D57 D59 VSS D61 D62 VCC2 VSS D63 VSS VCC2 VCC2 L M N P Q R S T VCC2 U V VCC2 W X Y Z VCC2 VSS VCC2 AA AB AC AD VCC2 AE AF VCC2 AG AH AJ AK INC AL AM AN VCC2 VCC2 D54 INC A B C D E F G H J K IERR# PM1BP1 VSS VCC2 VSS BP2 MI / O#
PICCLK PICD0 D58
CPUTYP TRST# VSS NC VCC3 VCC3 NC NC
FERR# PM0BP0
CACHE# VSS
STPCLK# NC INC INC NC
AHOLD KEN#
EWBE#
BRDY# NA#
VSS VCC2
FRCMC# VSS
BRDYC# VSS
PEN# INIT
BOFF# WB / WT#
IGNNE# VSS RS# INTR SMI#
PHIT#
HOLD NMI PRDY
PHITM# VSS
PBGNT# A23
APCHK# PBREQ# PCHK# PCD VSS
SMIACT#
LOCK# ADS# HIT# D / C# PWT HLDA
VSS BREQ AP
BE0# BUSCHK# HITM# VSS W / R#
EADS# INC
ADSC# VCC5
FLUSH#
Figure 19. Pentium® OverDrive® Processor with MMX Technology Pinout-Pin Side View
PRELIMINARY
Pentium OverDrive PROCESSOR WITH MMX TECHNOLOGY
THERMAL SPECIFICATIONS
Built in Self Test (BIST)
The Pentium OverDrive processor with MMX technology is shipped with an attached fan / heatsink for a complete thermal solution for the processor upgrade. The fan / heatsink cooling solution will properly cool the Pe