AK2540 Quad Transceiver FEATURE short haul transceiver with jitte

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AK2540 Quad Transceiver FEATURE short haul transceiver with jitte

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[AK2540]
AK2540 Quad Transceiver
FEATURE short haul transceiver with jitter attenuator Jitter Tolerance: Compliant with GR-499 Category I,II 62411 Transmitter Pulse Shape: Compliant with GR-499 ANSI T1.102 (1993) Loss Signal Detection Local/Remote Loopback Mode Driver Failure Monitor Current limiter transmit drivers short circuits protection Hardware/Host Control Mode Single 3.3V±5% 5.0V±5% Operation Power Consumption Package: 144LQFP BLOCK DIAGRAM
TRANSCEIVER
Remote Loopback Local Loopback
TCLK1 TPOS1 TNEG1
PULSE SHAPER
DFM1
TTIP1 TRING1
TAOS
JITTER
RCLK1 RPOS1 RNEG1
CLOCK &DATA RECOVERY
RTIP1 RRING1 LOS1
RCLK2-4 RPOS2-4 RNEG2-4 TCLK2-4 TPOS2-4 TNEG2-4
TRANSCEIVER
DFM2-4 TTIP2-4 TRING2-4 RTIP2-4 RRING2-4 LOS2-4 MCLK
CONTROL
CLKGEN
MCLKSEL
Quad Transceiver Block Diagram
MS0012-E-00
2000/1
[AK2540]
GENERAL DESCRIPTIONS AK2540 quad short haul transceiver asynchronous applications, such MUX, etc. includes Transmitter, Clock Data Recovery, Jitter Attenuator, Detector, Driver Failure Monitor, Control Circuits, etc. LQFP-144 package. Internally generated transmit pulse provides appropriate pulse shape line length ranging from feet from DSX-1 cross connect.
ASSIGNMENTS
MS0012-E-00
R/W(WR)_LENG03 AS(ALE)_LENG24 DS(RD)_LENG14 CS_LENG04 BTS_AIS1SEL INT_LOMC HWMODE RESET SEL5V CLKE TEST8 RRING4 RTIP4 TEST7 TEST6 RRING3 RTIP3 TEST5 PVSS MCLK MCLKSEL PVDD BVDD BGREF BVSS TEST4 RRING2 RTIP2 TEST3 TEST2 RRING1 RTIP1 TEST1
DFM3 AIS3 TPOS3 TNEG3 TCLK3 LOS3 RPOS3 RNEG3 RCLK3 DFM4 AIS4 TAVDD1 TAVSS1 TPOS4 TNEG4 TCLK4 LOS4 RPOS4 RNEG4 RCLK4 DAVSS2 IOVDD IOVSS AD0_LENG21 AD1_LENG11 AD2_LENG01 AD3_LENG22 AD4_LENG12 AD5_LENG02 AD6_LENG23 AD7_LENG13
LLOOP4 RLOOP4 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 LLOOP3 RLOOP3 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 LLOOP2 RLOOP2 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 LLOOP1 RLOOP1 TTIP1 TVSS1 TVDD1 TRING1 AVSS1
(TOP VIEW)
DFM1 AIS1 TPOS1 TNEG1 TCLK1 LOS1 RPOS1 RNEG1 RCLK1 DFM2 AIS2 TAVDD2 TAVSS2 DVSS DVDD DAVSS1 TPOS2 TNEG2 TCLK2 LOS2 RPOS2 RNEG2 RCLK2 JASELT JASELR RAVDD RAVSS
2000/1
[AK2540]
CONDITION
Name DFM3 AIS3 TPOS3 TNEG3 TCLK3 LOS3 RPOS3 RNEG3 RCLK3 DFM4 AIS4 TAVDD1 TAVSS1 TPOS4 TNEG4 TCLK4 LOS4 RPOS4 RNEG4 RCLK4 DAVSS2 IOVDD IOVSS AD0_LENG21 AD1_LENG11 AD2_LENG01 AD3_LENG22 AD4_LENG12 AD5_LENG02 AD6_LENG23 AD7_LENG13
Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power
Load 15pF
Load
Comments Note2)
15pF 15pF 15pF 15pF 15pF Note2)
15pF 15pF 15pF 15pF
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
50pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF
MS0012-E-00
2000/1
[AK2540]
Name R/W(WR)_LENG03 AS(ALE)_LENG24 DS(RD)_LENG14 CS_LENG04 BTS_AIS1SEL INT_LOMC HWMODE RESET SEL5V CLKE TEST8 RRING4 RTIP4 TESE7 TEST6 RRING3 RTIP3 TEST5 PVSS MCLK MCLKSEL PVDD BVDD BGREF BVSS TEST4 RRING2 RTIP2 TEST3 TEST2 RRING1 RTIP1 TEST1
Type CMOS CMOS CMOS CMOS CMOS Open drain CMOS CMOS CMOS CMOS CMOS Analog Analog CMOS CMOS Analog Analog CMOS Power CMOS CMOS Power Power Analog Power CMOS Analog Analog CMOS CMOS Analog Analog CMOS
Load
Load
Comments
PMOS Open drain
Note1)
Note1) Note1)
Note1)
accuracy Note1)
Note1) Note1)
Note1)
MS0012-E-00
2000/1
[AK2540]
Name RAVSS RAVDD JASELR JASELT RCLK2 RNEG2 RPOS2 LOS2 TCLK2 TNEG2 TPOS2 DAVSS1 DVDD DVSS TAVSS2 TAVDD2 AIS2 DFM2 RCLK1 RNEG1 RPOS1 LOS1 TCLK1 TNEG1 TPOS1 AIS1 DFM1
Type Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power Power
Load
Load
Comments
Note2) Note2) 15pF 15pF 15pF 15pF
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 15pF 15pF 15pF 15pF 15pF 15pF
Note2)
Note2)
MS0012-E-00
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[AK2540]
Name AVSS1 TRING1 TVDD1 TVSS1 TTIP1 RLOOP1 LLOOP1 AVSS2 TRING2 TVDD2 TVSS2 TTIP2 RLOOP2 LLOOP2 AVSS3 TRING3 TVDD3 TVSS3 TTIP3 RLOOP3 LLOOP3 AVSS4 TRING4 TVDD4 TVSS4 TTIP4 RLOOP4 LLOOP4
Type Power Analog Power Power Analog CMOS CMOS
Load
Load
Comments
driver output
driver output Note2) Note2)
Power Analog Power Power Analog CMOS CMOS Power Analog Power Power Analog CMOS CMOS Power Analog Power Power Analog CMOS CMOS driver output Note2) Note2) driver output driver output Note2) Note2) driver output driver output Note2) Note2) driver output
Note1 )Should connected externally. Note2 )Should connected externally host mode. Note3 )All pins recommended connected externally. MS0012-E-00 2000/1
ASAHI KASEI DESCRIPTIONS
Name Transceiver TTIP1-4 TRING1-4 TPOS1-4 TNEG1-4 TCLK1-4 RTIP1-4 RRING1-4 RPOS1-4 RNEG1-4 RCLK1-4 RLOOP1-4 LLOOP1-4 LENG01-04 LENG11-14 LENG21-24 AIS1-4 AIS1SEL JASELR JASELT DFM1-4 LOS1-4 Transmit Tip/Ring Output pins Bipolar output over transmit transformer Transmit Positive/Negative Data Input pins Input falling edge TCLK Transmit Clock Input pins Receive Tip/Ring Input pins Bipolar Input over receive transformer Receive Positive/Negative Data Output pins Output rising/falling edge RCLK (determined CLKE pin) Receive Clock Output recovered from receive data input pins Remote Loopback Control input pins Local Loopback Control input pins Line Length Control input pins Line Length Control input pins Line Length Control input pins Transmit Enable input pins Transmit Ones/Zero Selection input pins when enabled Jitter Attenuator Select input pin, placed Receiver Jitter Attenuator Select input pin, placed Transmitter Driver Failure Monitor output pins Loss signal output pins Output "high" when detect loss signal LOSx output masked MLOSx register. Positive Power Supply Transmit Driver Negative Power Supply Transmit Driver Analog ground. 1.544MHz 24.704MHz External Reference Clock input Loss master clock output pin. Output "high" when detect loss master clock LOMC output masked MLOMC register. AS(ALE) Address Select(Address Latch Enable) input Interrupt Output pin(PMOS open drain), Active High, output goes "high" when alarm reported LOSx, LOTCx LOMC registers. This masked MLOSx, MLOTCx MLOMC registers. DS(RD) (WR) Data Strobe(Read Enable) input Read/Write(Write Enable) input Function
[AK2540]
Comments
Note1) Note1) Note1) Note1) Note1) Note1) Note1) Note1) Note1)
TVDD1-4 TVSS1-4 AVSS1-4 Common Block MCLK LOMC
Note1)
Note2) Note2)
Note2) Note2)
MS0012-E-00
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[AK2540]
Name
Chip Select input Type Select input BTS="H" Motorola Mode BTS="L" Intel Mode
Function
Comments Note2) Note2)
Common block (Cont.)
AD0-AD7 MCLKSEL
Address/Data Input/Output pins Used read/write internal registers. MCLK Select input CLKSEL="H":1.544MHz CLKSEL="L":24.704MHz
Note2)
HWMODE
Hardware/ Host Mode Select input HWMODE="H": Hardware Mode HWMODE="L": Host Mode
SEL5V
5.0V /3.3V Select input SEL5V="H": operation SEL5V="L": 3.3V operation
CLKE RESET
RCLK clock edge select input Reset Input Active "High" input pulse over 200ns initializes internal circuit forces RPOSx/RNEGx output "low" LOSx output "high".
TEST1 TAVDD1,2 TAVSS1,2 RAVDD RAVSS DVDD DVSS DAVSS1,2 IOVDD IOVSS BVDD BVSS PVDD PVSS BGREF
Factory Use. Should connected "VSS" externally. Positive Power Supply analog circuitry transmitters Negative Power Supply analog circuitry transmitters Positive Power Supply digital circuitry transmitters Negative Power Supply digital circuitry transmitters Positive Power Supply Digital Negative Power Supply Digital Ground Digital Positive Power Supply Negative Power Supply Positive Power Supply Reference Circuit Negative Power Supply Reference Circuit Positive Power Supply Negative Power Supply Bandgap Reference Output 12k±1% external register should connected across this VSS.
Note1) Hardware Mode Note2) Host Mode
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ASAHI KASEI ABSOLUTE MAXIMUM RATINGS
Parameter Supply Input Voltage Symbol VIN1 VIN2 Input Current Storage Temperature Tstg -0.3 -0.3 -3.2 VDD+0.3 VDD+0.3 Units
[AK2540]
Conditions
Apply except RTIPx, RRINGx Apply RTIPx,RRINGx Pins
RECOMMENDED OPERATING COMDITIONS
Parameter Supply Supply Ambient Operating Temperature Symbol 3.135 4.75 3.465 5.25 Units Conditions 3.3V± 5.0V±
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
Parameter Power Consumption(/ch) Power Consumption(/ch) Digital High-Level Output Voltage Digital Low-Level Output Voltage Digital High-Level Input Voltage Digital Low-Level Input Voltage Input Leak Current Output Current (VOH=VDD-0.5) Symbol 0.7VDD 0.3VDD 0.9VDD Units Conditions Note1 Note2 PMOS Open Drain IOH=-500µA IOL=500µA
Note typ: mark, Room temp., 3.3V, line length 399feet, Load 100ohm max: 100% mark, Temp./VDD range, line length 655feet, Load 100ohm other loads (ex. external pull register, etc.) included except lines. Note typ: mark, Room temp., 5.0V, line length 399feet, Load 100ohm max: 100% mark, Temp./VDD range, line length 655feet, Load 100ohm other loads (ex. external pull register, etc.) included except lines.
MS0012-E-00
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[AK2540]
RECEIVER Receiver characteristics guaranteed under conditions shown below. VDD=3.3V±5% 5.0V±5%, VSS=0V, GND=0V, Ta=-40 85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm, input data rate:1.544bps±130ppm(reference input level: 3V0p±20%)
Parameter Sensitivity Loss Signal Threshold Jitter Tolerance Consecutive Zeros before Loss Signal Input Impedance Symbol 0.35 Units Conditions Note Note Note kohm Note
GR-499 CategoryI,II, 62411
Note Relative value reference level. Compare 772kHz with mark pattern. Note Level line side transformer. Loss signal logical between analog loss signal, which monitors input level, digital loss signal, which checks recovered data stream. Note device will tolerate consecutive zeros until loss signal reported with QRSS (PN20 Modified) pattern. Note subject tested production. Guaranteed design.
JITTER TOLERANCE
JITTER TOLERANCE 1000 1000 10000 100000 Jiiter Frequency(Hz)
TR62411
MS0012-E-00
Jitter Amplitude(UIpp)
2000/1
[AK2540]
TRANSMITTER Transmitter characteristics guaranteed under conditions shown below. VDD=3.3V±5% 5.0V±5%, VSS=0V, GND=0V, Ta=-40 85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm
Parameter Output Pulse Shape Output Pulse Amplitude Output Pulse Imbalance Output Jitter 10Hz-8kHz 10Hz-40kHz 8kHz-40kHz Broad Band Power Levels @772kHz Power Levels @1.544MHz Consecutive Zeros before Alarm Note Measured terminated with 100ohm. Note Turns Ratio transmission transformer recommended value. Note Measured 2kHz bandwidth about specified frequency. Transmit mark pattern. Note Referenced power 772kHz. 12.6 0.02 0.025 0.025 0.05 17.9 Note3 Note3, Note4 UIpp Symbol Units Conditions
GR-499,Note1
Note1, Note2
ISOLATED PULSE MASK (GR-499)
Normalized Amplitude -0.5 -0.5 Time, Unit Intervals
MS0012-E-00
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[AK2540]
JITTER ATTENUATOR Jitter Attenuator characteristics guaranteed under conditions shown below. VDD=3.3V±5% 5.0V±5%, VSS=0V, GND=0V, Ta=-40 85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm
Parameter Jitter attenuator curve corner frequency Jitter attenuation 10kHz Attenuator input jitter tolerance before FIFO overflow/underflow protection Intrinsic Jitter 0.03 0.06 UIpp Symbol Units UIpp Input Jitter: UIpp Conditions
MS0012-E-00
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[AK2540]
CHARACTERISTICS(Clock/Data)
Parameter Clock Frequency Clock Pulse Width MCLK1 MCLK2 MCLK1 MCLK2 Clock Pulse Width Clock Pulse Width Duty Cycle Setup/Hold Time TCLK RCLK RCLK TCLK RCLK RPOS RNEG Setup/Hold Time TCLK TPOS TNEG Rise Time RCLK, TCLK RPOS, TOPS RNEG, TNEG Fall Time RCLK, TCLK RPOS, TPOS RNEG, TNEG Note AK2540 specifications within limit with ±100ppm MCLK. However, MCLK needs within ±32ppm range order transmit accuracy during loss TCLK. Note Duty Cycle:(tpwho/( tpwho tpwlo)) 100% Note Drive 15pF Load Capacitance Refer Fig.3 Note3 Refer Fig.3 Note3 tsu2 Refer Fig.2 tsu1 tpwhi tpwli tpwho tpwlo Refer Fig.1 Note Note Note Refer Fig.1 Symbol fci1 fci2 tpwhi tpwli Units Conditions ±100ppm Note Refer Fig.4 1.544MHz Refer Fig.4 24.704MHz Refer Fig.2
1.543846 1.544000 1.544154 24.70153 24.70400 24.70647
MS0012-E-00
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[AK2540]
tpwho
tpwlo tsur tsur When CLKE=0
RCLK
RPOS/RNEG
When CLKE Fig. Receiver Timing
tpwhi
tpwli
TCLK
tsut
TPOS/TNEG
Fig. Transmitter Timing
Fig. Rise Fall Times tpwhi tpwli
MCLK
Fig.4 Master Clock Timing
MS0012-E-00
2000/1
[AK2540]
CHARACTERISTICS(Parallel Port)
Parameter Motrola Mode Address Setup Time Address Hold Time ASDS Delay Time DSAS Delay Time Read Data Delay Time Read Data Hold Time Setup Time Hold Time Setup Time Hold Time Write Data Setup Time Write Data Hold Time Pulse Width Pulse Width Address InvalidDS Delay Time Intel Mode Address Setup Time Address Hold Time ALEWR Delay Time WRALE Delay Time RDALE Delay Time Read Data Delay Time Read Data Hold Time Setup Time Hold Time Write Data Setup Time Write Data Hold Time Pulse Width Pulse Width Pulse Width Address InvalidRD Delay Time Symbol Units Conditions
Notes: 50pF AD0-AD7. timing specified 50%VDD.
MS0012-E-00
2000/1
[AK2540]
Motorola Mode(READ)
Data
AD7-0
Address
Motorola Mode(WRITE)
Data
AD7-0
Address
MS0012-E-00
2000/1
[AK2540]
Intel Mode(READ)
AD7-0 Data
Address
Intel Mode(WRITE)
AD7-0 Data
Address
MS0012-E-00
2000/1
ASAHI KASEI THEORY OPERATION
[AK2540]
Mode Operation There mode operation selected HWMODE pin. hardware mode other host mode. device hardware mode when HWMODE pulled high host mode when HWMODE pulled low. Minimum information available hardware mode. Hardware Mode, device controlled appropriate pins. Host Mode, device controlled appropriate registers described after through parallel interface. Host Mode, interrupt masked appropriate mask register. However, status registers hard flag pins show current status regardless mask register setting. Pulse Shape Control (Hardware Mode Host Mode) Hardware Mode, transmit pulse shape channel 1,2,3 determined Line Length control pins LENG0x through LENG2x shown Table Table Line Length Control LENG2x X=1,2,3 Host Mode, transmission pulse shape determined appropriate register described Register Description section later LENG1x LENG0x Line Length Reserved 0-133feet 133-266feet 266-399feet 399-533feet 533-655feet Reserved Reserved
MS0012-E-00
2000/1
[AK2540]
Jitter Attenuator (Hardware Mode Host Mode) Jitter Attenuator placed either transmitter path receiver path, bypassed according JASELR JASELT both Hardware Mode Host Mode described table Jitter Attenuators placed same place channel through channel Table Jitter Attenuator Place Selection JASELR JASELT Location Jitter Attenuator Bypassed Transmitter Receiver Reserved (NA)
(Hardware Mode Host Mode) channel selected when AISx "high". mode TPOS TNEG inputs ignored, transmitter remains locked TCLK input. enabled simultaneously with Local Loopback. overdrives Remote Loopback. this mode, either ones zeros transmitted according AIS1SEL selection. (see table Table Control AISx AIS1SEL X=1,2,3 TTIP/TRING Normal Normal
MS0012-E-00
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[AK2540]
Loopbacks (Hardware Mode Host Mode) Local Loopback (LLOOP) channel selected when LLOOPx "high" RLOOPx "low". LLOOP mode, receiver circuits inhibited. transmitter circuits unaffected LLOOP. Remote Loopback (RLOOP) channel selected when RLOOPx "high" LLOOPx "low". However, RLOOP ignored selected. RLOOP mode, transmit clock data inputs (TCLK TPOS/TNEG) ignored. RPOS/RNEG outputs looped back transmit circuits output TTIP TRING RCLK frequency. Receiver circuits unaffected RLOOP continue output data clock signals received from line. Table Loopback mode Selection RLOOPx LLOOPx Function Normal Local Loop back Remote Loop back Reserved (NA) transmit clock data inputs (TCLK TOPS/TNEG) looped back output RCLK RPOS/RNEG.
Driver Performance Monitor (Host Mode) device incorporates internal Driver Performance Monitor (DPM) parallel with TTIP TRING. DPMx "high" when detect bits consecutive space channel becomes "high" when DPMx "high", MDPMx "low". DPMx registers represent current status regardless MDPMx status. DPMx returns "low", when mark detected. However, DPMx kept "high" TCLK cycle after first detection event. output ignored when being transmitted Line Short Protection Circuit transmit driver includes line short protection circuit. When line short protection circuit detect line short, transmit signal fixed "space". line short protection circuit monitor line short every 160bits cycle. (This alarm outputted. Line short shown Driver Failure described below.)
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[AK2540]
Driver Failure Monitor (Hardware Mode Host Mode) Driver Failure Monitor asserts detection consecutive space line short. When DPMx "high" line short circuit channel detected, DFMx(Driver Failure Monitor) register "high" DFMx becomes "high". becomes "high" when DFMx "high" MDFMx "low". DFMx registers DFMx pins represent current status regardless MDFMx status.
Loss signal (Hardware Mode Host Mode) receiver will indicate loss signal upon receiving consecutive zeros (DLOS) detecting input level being below threshold (ALOS). LOSx returns "low" when received signal returns 12.5% ones density including consecutive zeros. (GR-820) When Loss Signal detected channel LOSx register "high" LOSx becomes "high". When LOSx "high", interrupt will issued MLOSx "low". LOSx becomes high regardless MLOSx status. MLOSx active-high masks LOSx interrupt. LOSx registers LOSx pins represent current status received signal regardless MLOSx status. There also ALOSx registers current status each channel available.
Loss TCLK (Host Mode Only) Loss TCLKx reported setting LOTCx "high". When LOTCx "high", output becomes "high" MLOTCx "low". MLOTCx active-high masks LOTCx interrupt. LOTCx represents current status TCLKx read regardless MLOTCx status. When Loss TCLKx detected, TTIPx/TRINGx will forced "0"(except Remote loopback AIS), channel sent synchronized with MCLK AISx selected. INT_LOMC output (Hardware Mode Host Mode) Host Mode, INT_LOMC(Interrupt Output) output becomes "high" when alarm reported ALOSx, LOSx, LOTCx, DFMx DPMx registers. MALOSx, MLOSx, MLOTCx, MDFM MDPM registers. Hardware Mode, INT_LOMC assert LOMC(Loss MCLK alarm). INT_LOMC masked
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ASAHI KASEI REGISTER DESCRIPTIONS
[AK2540]
REGISTER
*A7-A4="0" Address
Bit7 <AD7> Bit6 <AD6> Bit5 <AD5>
Function
Bit4 <AD4> Bit3 <AD3> Bit2 <AD2> Bit1 <AD1> Bit0 <AD0>
Status Register (READ ONLY)
DPM4 LOTC4 ALOS4
DPM3 LOTC3 ALOS3 MDPM3 MLOTC3 MALOS3 MSK3 LENG11 LENG12 LENG13 LENG14 JASELT
DPM2 LOTC2 ALOS2 MDPM2 MLOTC2 MALOS2 MSK2 LENG01 LENG02 LENG03 LENG04
DPM1 LOTC1 ALOS1 MDPM1 MLOTC1 MALOS1 MSK1 RLOOP1 RLOOP2 RLOOP3 RLOOP4 RDEN
DFM4 LOS4 MDFM4 MLOS4
DFM3 LOS3 MDFM3 MLOS3
DFM2 LOS2 MDFM2 MLOS2
DFM1 LOMC LOS1 MDFM1 MLOS1
Mask Control Register (WRITE/READ)
MDPM4 MLOTC4 MALOS4 MSK4
MLOMC
Channel Control Register (WRITE/READ)
LENG21 LENG22 LENG23 LENG24
LLOOP1 LLOOP2 LLOOP3 LLOOP4 AIS1SEL
AIS1 AIS2 AIS3 AIS4
Global Control Register (WRITE/READ)
JASELR
other addresses reserved. Initial value "<>" shows name. Address A0-A3 should input AD0-AD3 pins.
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[AK2540]
STATUS REGISTER
Symbol LOSx (x=1 LOTCx (x=1 DPMx (x=1 DFMx (x=1 ALOSx (x=1 LOMC Description Loss signal alarm channel Read only register. When loss signal detected, LOSx High. Loss TCLK alarm channel Read only register. When loss TCLKx detected, LOTCx High. Driver Performance Monitor alarm channel Read only register. When bits consecutive space detected channel DPMx high. Driver Failure Monitor alarm channel Read only register. When short circuit detected channel DFMx high. Analog loss signal alarm channel Read only register. When analog loss signal detected, ALOSx High. Loss MCLK alarm. Read only register. When loss MCLK detected, LOMC High.
MASK CONTROL REGISTER Symbol MLOSx (x=1 Description Mask loss signal alarm channel (LOSx). MLOSx active-high prevents LOSx from setting output "high". LOSx register read regardless MLOSx status. Initial value "high". Mask loss TCLK alarm channel (LOTCx). MLOTCx active high prevents LOTCx from setting output "high". LOTCx register read regardless MLOTCx status. Initial value "high". Mask alarm channel (DPMx). MDPMx active high Initial value "high". Mask alarm channel (DFMx). MDFMx active high Initial value "high". MSKx active-high prevents LOSx, LOTCx, DFMx DPMx channel from setting output "high". Initial value "high". Mask analog loss signal alarm channel (ALOSx). MALOSx active-high prevents ALOSx from setting output "high". ALOSx register read regardless MALOSx status. Initial value "high". Mask loss MCLK alarm (LOMC). MLOMC active high prevents LOMC from setting output "high". LOMC register read regardless MLOMC status. Initial value "high".
MLOTCx (x=1
MDPMx (x=1 MDFMx (x=1 MSKx (x=1 MALOSx (x=1
MLOMC
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[AK2540]
CHANNEL CONTROL REGISTER
Symbol LENGyx Description generated transmit pulse channel provides appropriate pulse shape line length from DSX-1 cross connect through setting this register shown below Table Loopback mode channel activated through setting these registers shown below Table AISx active-high transmit corresponding channel. active-high corresponding transceiver power down mode. TTIPx TRINGx goes "low". LOSx goes "high" power down mode. Initial value "high".
RLOOPx/ LLOOPx AISx
GLOBAL CONTROL REGISTER
Symbol JASELR/JA SELT RDEN Description Jitter Attenuator placed these resisters shown Table Initial values "low" This register shown Table controls TIP/RING output polarity. Initial value "high". RDEN active-high enabling RCLK, RPOS, RNEG output upon Loss signal. RCLK, RPOS RNEG forced "high" "low" upon Loss Signal when RDEN "low". (Please refer output control) Initial value "low". mark transmitted when AIS1SEL "high". transmitted when AIS1SEL "low". space
AIS1SEL
Table Line Length Control LENG2x LENG1x LENG0x Line Length Reserved 0-133feet 133-266feet 266-399feet 399-533feet 533-655feet Reserved Reserved
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ASAHI KASEI Table Loopback mode Selection RLOOPx LLOOPx Function Normal (Initial value) Local Loop back Remote Loop back Reserved (NA)
[AK2540]
Table Jitter Attenuator Place Selection JASELR JASELT Location Jitter Attenuator Bypassed (Initial value) Transmitter Receiver Reserved (NA)
Table TIPx/RINGx Polarity Control POSx/NEGx TIPx/RINGx space mark mark space
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[AK2540]
OUTPUT CONTROL don't care LOS: LOSx output LOSx register
Reset, Loss MCLK, Power down (Host Mode)
RESET MCLK Loopback Local loss loss clocked clocked clocked clocked clocked clocked Remote RDEN CLKE TTIP TRING High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) RCLK RPOS RNEG
Reset, Loss MCLK (Hardware Mode)
RESET MCLK Loopback Local loss Remote CLKE TTIP TRING RCLK RPOS RNEG
Hardware Mode, fixed RDEN fixed "0".
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[AK2540]
Normal Operation(RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=RLOOP=0)
RDEN TCLK clocked clocked loss loss clocked loss clocked clocked loss loss clocked loss Receive signal clocked loss clocked loss loss loss clocked loss clocked loss loss loss TTIP TRING TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG
RCLK RCLK RCLK RCLK RCLK
RCLK
RPOS RNEG RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING
active active active active active active
RCLK
RCLK
RCLK
Normal Operation: Transmit space (RESET=0, AIS=1,AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=RLOOP=0)
RDEN TCLK clocked clocked loss loss clocked loss clocked clocked loss loss clocked loss Receive signal clocked loss clocked loss loss loss clocked loss clocked loss loss loss TTIP TRING
RCLK
RCLK
RPOS RNEG RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING
RCLK
RCLK
RCLK
RCLK
RCLK
RCLK
RCLK
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[AK2540]
Normal Operation: Transmit mark (RESET=0, AIS=1,AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=RLOOP=0)
RDEN TCLK clocked clocked loss loss clocked loss clocked clocked loss loss clocked loss Receive signal clocked loss clocked loss loss loss clocked loss clocked loss loss loss TTIP TRING Mark Mark Mark (Note2) Mark (Note2) Mark Mark (Note2) Mark Mark Mark (Note2) Mark (Note2) Mark Mark (Note2)
RCLK RCLK RCLK RCLK
RCLK
RPOS RNEG RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING
active active active active active active active active active active active active
RCLK
RCLK
RCLK
RCLK
Remote Loopback (RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1)
RDEN TCLK Receive signal clocked loss loss clocked loss loss TTIP TRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING
RCLK RCLK RCLK RCLK
RCLK
RPOS RNEG RTIP RRING RTIP RRING RTIP RRING RTIP RRING
active active active active active active
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[AK2540]
Remote Loopback: Transmit space (RESET=0, AIS=1, AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1)
RDEN TCLK Receive signal clocked loss loss clocked loss loss TTIP TRING
RCLK
RCLK
RPOS RNEG RTIP RRING RTIP RRING RTIP RRING RTIP RRING
RCLK
RCLK
RCLK
Remote Loopback: Transmit mark (RESET=0, AIS=1, AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1)
RDEN TCLK Receive signal clocked loss loss clocked loss loss TTIP TRING Mark Mark Mark Mark Mark Mark
RCLK
RCLK
RPOS RNEG RTIP RRING RTIP RRING RTIP RRING RTIP RRING
active active active active active active
RCLK
RCLK
RCLK
Local Loopback(RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0)
RDEN TCLK clocked clocked loss loss clocked clocked loss loss Receive signal clocked loss clocked loss clocked loss clocked loss TTIP TRING TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG TCLK (Note4) TCLK (Note4) (Note3) (Note3) TCLK (Note4) TCLK (Note4) (Note3) (Note3) TPOS TNEG TPOS TNEG active active RCLK RPOS RNEG TPOS TNEG TPOS TNEG active active
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[AK2540]
Local Loopback: Transmit space (RESET=0, AIS=1, AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0)
RDEN TCLK clocked clocked loss loss clocked clocked loss loss Receive signal clocked loss clocked loss clocked loss clocked loss TTIP TRING TCLK (Note4) TCLK (Note4) (Note3) (Note3) TCLK (Note4) TCLK (Note4) (Note3) (Note3) TPOS TNEG TPOS TNEG RCLK RPOS RNEG TPOS TNEG TPOS TNEG
Local Loopback: Transmit mark (RESET=0, AIS=1, AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0)
RDEN TCLK clocked clocked loss loss clocked clocked loss loss Receive signal clocked loss clocked loss clocked loss clocked loss TTIP TRING Mark Mark Mark (Note2) Mark (Note2) Mark Mark Mark (Note2) Mark (Note2) TCLK (Note4) TCLK (Note4) (Note3) (Note3) TCLK (Note4) TCLK (Note4) (Note3) (Note3) active TPOS TNEG TPOS TNEG active active active active RCLK RPOS RNEG TPOS TNEG TPOS TNEG active active active
Note1) impedance between TTIP TRING 30kohm(typ) Note2) Transmit signal synchronize with MCLK Note3) When CLKE "1", RCLK fixed "1". Note4) phase TCLK satisfy receive output timing.
MS0012-E-00
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ASAHI KASEI RECOMMENDED EXTERNAL CIRCUITS
[AK2540]
Transmit Circuit AK2540 TTIPx (3.3V) 1:1.14 (5V)
TRINGx C1=0.47µF Received Circuit (3.3V) 1:0.57 (5V)
AK2540 RTIPx
RRINGx
R1=R2= 50ohms (3.3V) 154ohms (5V) Rp=100ohms(Protection resistance, Example value)
Recommended Transformer Specification 3.3V Turns Ratio (Typ) Turns Ratio (Typ) 1:1.14 1:1.14(CT) Primary Inductance (Min) 1.5mH 1.5mH Leakage Inductance (Max) 0.3uF 0.3uF Interwinding Capacitance (Max) 30pF 30pF (Max) 1:2(CT) Primary Inductance (Min) 1.5mH 1.5mH Leakage Inductance (Max) 0.3uF 0.3uF Interwinding Capacitance (Max) 30pF 30pF (Max)
0.6ohms 0.6ohms 0.6ohms 0.6ohms
0.6ohms 0.6ohms 0.6ohms 0.6ohms
MS0012-E-00
2000/1
ASAHI KASEI Reference current circuit determine input reference current, connect 12kohm±1% resistor. recommended connect AK2540 short possible avoid noise. AK2540 BGREF
[AK2540]
R1=12kohm±1% Power Supply attenuate power supply noise, connect capacitors between respectively. value capacitance AK2540 need depend condition power supply line. Please decide value capacitance after your evaluation. recommended connect AK2540 short possible avoid noise. AK2540
name RAVDD-RAVSS, BVDD-BVSS, TAVDD1-TAVSS1, TAVDD2-TAVSS2 TVDD1-TVSS1, IOVDD-IOVSS, TVDD2-TVSS2, DVDD-DVSS, TVDD3-TVSS3, TVDD4-TVSS4, PVDD-PVSS
0.01uF
Recommended Transformers Selection Power Supply 3.3V Operation Operation Turns Ratio 1:1.14 Manufacturer Pulse Engineering Pulse Engineering Part Number WBTT-0425B T1104 WBTT-0425 T1105 4101 Description Single, SMT,1.5kV Octal, SMT,1.5kV Single, SMT,1.5kV Octal, SMT,1.5kV Single, SMT,1.5kV
MS0012-E-00
2000/1
[AK2540]
PACKAGE
144pin LQFP Outline Dimensions
22.0 20.0
AK2540 XXXXXXX JAPAN
20.0 0.17±0.040.07
1.70 1.40
0.50 0.20
0.10
22.0
0.10
0.10
0.50±0.1
MS0012-E-00
2000/1

AK2540 Quad Transceiver FEATURE short haul transceiver with jitte

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