Publication 27532 Rev: Issue Date: October 2003 2003 Advanced Mic

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Publication 27532 Rev: Issue Date: October 2003 2003 Advanced Mic

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AthlonProcessor Model Revision Guide
Publication 27532 Rev: Issue Date: October 2003
2003 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. products described herein contain design defects errors ("Product Errata") that cause products deviate from published specifications. Currently characterized Product Errata available upon request. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, Arrow logo, Athlon, Duron, combinations thereof, trademarks Advanced Micro Devices, Inc. Other product names used this publication identification purposes only trademarks their respective companies.
27532C-October 2003
AthlonProcessor Model Revision Guide
Revision History
Date October 2003 June 2003 Revised erratum #27. Initial public release. Description
Preliminary Information AthlonProcessor Model Revision Guide
27532C-October 2003
AthlonProcessor Model Revision Guide
purpose AthlonXP Processor Model Revision Guide communicate updated product information AthlonXP processor model designers computer systems software developers. This revision guide applies Athlon processor model mobile Athlon processor model Athlon processor model low-power desktop, Athlon processor model This guide consists three sections:
Product Errata: This section, which starts page provides detailed description product errata, including potential effects system operation suggested workarounds. erratum defined deviation from product's specification. product errata cause behavior Athlon processor model deviate from published specifications. Revision Determination: This section, which starts page shows Athlon processor model identification numbers returned CPUID instruction each revision processor. Technical Documentation Support: This section, which starts page provides listing available technical support resources. also lists corrections, modifications, clarifications listed documents. Please refer data sheets listed this section product marking information.
Revision Guide Policy
Occasionally identifies deviations from changes specification Athlon processor model These changes documented AthlonXP Processor Model Revision Guide errata. Descriptions written assist system software designers using Athlon processor model corrections AMD's documentation Athlon processor model included. This release documents currently characterized product errata.
27532C-October 2003
AthlonProcessor Model Revision Guide
Product Errata
This section documents Athlon processor model product errata. errata divided into categories assist referencing particular errata. unique tracking number each erratum been assigned within this document user convenience tracking errata within specific revision levels. Table cross-references revisions processor each erratum. indicates that erratum applies stepping. absence indicates that erratum does apply stepping. Table page cross-references erratum each processor segment. indicates that erratum applies processor segment. Note: There missing errata numbers. Errata that have been resolved from early revisions processor have been deleted, errata that have been reconsidered have been deleted renumbered.
Table
Cross-Reference Product Revision Errata
Errata Numbers Description Revision Numbers
Deadlock Occur Two-Processor System Presence Probe Memory- Mapped Processor Performance Counters Count Some Instructions Speculative Store Followed Actual Store Cause One-Time Stale Execution Processor Does Support Reliable Microcode Patch Mechanism Single Step Across Skips Debug Trap Software Prefetches Report Page Fault
Preliminary Information AthlonProcessor Model Revision Guide
27532C-October 2003
Table
Errata Number
Notes:
Cross-Reference Erratum Processor Segments
Workstation/Server1
Desktop2
Low-Power Desktop3
Mobile4
workstation/server segment currently includes AthlonMP processor. desktop segment currently includes Athlon processor. low-power desktop segment currently includes Athlon processor. mobile segment currently includes mobile Athlon processor.
27532C-October 2003
AthlonProcessor Model Revision Guide
Deadlock Occur Two-Processor System Presence Probe MemoryMapped
Products Affected. Normal Specified Operation. Processor should hang. Non-conformance. multiprocessor system, processor continuously writing cacheable memory-mapped block while other processor trying read same cacheable block, same time both processors also trying write different memory-based cache block, then processor hang. Should this occur processor fields interrupt, deadlock resolved. Potential Effect System. System will hang exhibit performance degradation. Suggested Workaround. current processor design assumes that memory-mapped incoherent does handle deadlock cases. System logic should generate probes memory-mapped addresses. Resolution Status. planned.
Preliminary Information AthlonProcessor Model Revision Guide
27532C-October 2003
Processor Performance Counters Count Some Instructions
Products Affected. Normal Specified Operation. processor should count instructions when programmed Non-conformance. There types uncounted instructions. instructions always uncounted. Another instructions uncounted only certain data dependency exists. Instructions never counted are: RDMSR, WRMSR, FSTENV, FSAVE, FLDENV, FPTAN, FYL2XP1, FCLEX, LLDT, LTR, CRx, LGDT, LIDT, INVLPG, INVD, WBINVD, DRx, CPUID, SFENCE. Instructions that uncounted only when certain data dependencies exist are:
LAR, LSL, VERR, VERW they clear Zero Flag FXSAVE, FXRSTOR FERR changed instructions with exceptional data conditions instructions that detect interrupt POPF with trap flag POPFD PUSHFD with IOPL equal Virtual Mode enabled POPFD when Alignment Check being enabled with trap flag Segment Loads that generate accessed exceptions with trap flag interrupt flag already CLTS with CR0.TS flag LMSW that changes
Potential Effect System. Performance counter under count actual number instructions. Suggested Workaround. Versions Athlonprocessor affected this erratum used gather instruction counts. Resolution Status. planned.
27532C-October 2003
AthlonProcessor Model Revision Guide
Speculative Store Followed Actual Store Cause One-Time Stale Execution
Products Affected. Normal Specified Operation. Self-modifying code sequences should correctly detected handled manner consistent with canonical results; stale code should executed. Non-conformance. following scenario result one-time execution stale instructions: speculative store instruction initiates request modify 64-byte cache line with address which currently resides within instruction cache. speculative store instruction ultimately executed because branch misprediction. However, store still flight attempting bring line into data cache modified state. instruction cache, which fetches instructions bytes time, redirected branch into cache line with address fetches portion line into instruction buffer. then invalidates instruction cache line with address brings line into data cache, marking modified. However, instruction buffer, which also contains some bytes from address invalidated. instruction fetch mechanism attempts read next 16-byte chunk code must issue request bring 64-byte line back into instruction cache. This instruction cache request address hits modified line cache, evicts from data cache second store instruction from instruction buffer issued into execution units. self-modifying code reference another instruction that currently exists 64-byte cache block address also instruction buffer. execution detects that instruction request fetch address flight. However, store request given priority. Since hits state modified, assumes that line cannot instruction cache instruction buffer. Potential Effect System. processor will execute stale code instructions. Suggested Workaround. None. This failure only been observed internally generated synthetic code. Resolution Status. planned.
Preliminary Information AthlonProcessor Model Revision Guide
27532C-October 2003
Processor Does Support Reliable Microcode Patch Mechanism
Products Affected. Normal Specified Operation. processor should function properly after microcode patch loaded. Non-conformance. processor patch BIST function disabled. Since BIST patch RAM, reliable operation patch cannot guaranteed. Therefore should used. Potential Effect System. When microcode patch loaded, system behave properly. Suggested Workaround. load microcode patch. Resolution Status. planned.
27532C-October 2003
AthlonProcessor Model Revision Guide
Single Step Across Skips Debug Trap
Products Affected. Normal Specified Operation. When single stepping (with EFLAGS.TF) across instruction that detects SMI, processor correctly defers taking debug trap instead enters SMM. Upon (without restart), processor should immediately enter debug trap handler. Non-conformance. Under this scenario, processor does enter debug trap handler instead returns instruction following instruction. Potential Effect System. When using single step debug mode, following operation that detects SMI, instruction appear skipped. Suggested Workaround. None required this debug limitation only. workaround desired, modify handler detect this case enter debug handler directly. Resolution Status. planned.
Preliminary Information AthlonProcessor Model Revision Guide
27532C-October 2003
Software Prefetches Report Page Fault
Products Affected. Normal Specified Operation. Software prefetches should report page faults they encounter them. Non-conformance. Software prefetch instructions defined ignore page faults. Under highly specific detailed internal circumstances, prefetch instruction report page fault both following conditions true:
target address prefetch would cause page fault address accessed actual memory load store instruction under current privilege mode; prefetch instruction followed execution-order actual speculative byte-sized memory access same modify-intent same address.
PREFETCH PREFETCHNTA/0/1/2 have same modify-intent memory load access. PREFETCHW same modify-intent memory store access. page fault exception error code bits faulting prefetch will identical that bytesized memory access same-modify intent same address. Note that some misaligned accesses broken processor into multiple accesses where least accesses byte-sized access. target address subsequent memory access same modify-intent aligned byte-sized, this errata does occur workaround needed. Potential Effect System. unexpected page fault occur infrequently prefetch instruction. Suggested Workaround. workarounds described this erratum. Kernel Workaround Operating System kernel work around erratum allowing page fault handler satisfy page fault "accessible" page regardless whether fault load, store, prefetch operation. faulting instruction permitted access page, return usual. "accessible" page which memory accesses allowed under current privilege mode once page resident memory). faulting instruction trying access "inaccessible" page, scan instruction stream bytes faulting Instruction Pointer determine instruction prefetch. "inaccessible" page which memory accesses allowed under current privilege mode.) faulting instruction prefetch instruction, simply return back internal hardware conditions that caused prefetch fault should removed operation should continue normally. prefetch instruction, generate appropriate memory access control violation appropriate. performance impact doing scan small because actual errata infrequent does produce excessive number page faults that affect system performance. General Workaround page-fault handler kernel patched described preceding kernel workaround, further action software required. following general workarounds should only considered kernels where page-fault handler patched prefetch instruction could targeting address "inaccessible" page.
27532C-October 2003
AthlonProcessor Model Revision Guide
Because actual errata infrequent, does produce excessive number page faults that affect system performance. Therefore page fault from prefetch instruction address within "accessible" page does require general workaround. Software minimize occurrence errata issuing only prefetch instruction cacheline naturally-aligned 64-byte quantity) ensuring following:
many cases, particular target address prefetch known encounter this errata, simply change prefetch target next byte. Avoid prefetching inaccessible memory locations, when possible. general case, ensure that address used prefetch offset into middle aligned quadword near cache-line. example, address desired prefetched "ADDR", offset 0x33 compute address used actual prefetch instruction "(ADDR ~0x3f) 0x33".
Resolution Status. planned.
Preliminary Information AthlonProcessor Model Revision Guide
27532C-October 2003
Revision Determination
Table shows Athlon processor model identification number returned CPUID instruction each revision processor.
Table
CPUID Value Revision AthlonXP Processor Model
Revision
CPUID
27532C-October 2003
AthlonProcessor Model Revision Guide
Technical Documentation Support
following documents provide additional information regarding operation AthlonXP processor model Please refer data sheets listed this section product marking information.
AthlonXP Processor Model Data Sheet, order# 26237 Mobile AthlonXP Processor Model Data Sheet, order# 26200 Athlonand DuronProcessors BIOS, Software, Debug Developers Guide, order# 21656
latest updates, refer www.amd.com download appropriate files. documents under NDA, please contact your local sales representative updates.

Publication 27532 Rev: Issue Date: October 2003 2003 Advanced Mic

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