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FC-PGA Intel® Pentium® Processor Intel® Chipset
Order Number: 273332-002
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® Pentium® processor Intel chipset contain design defects errors known errata which cause products deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 *Third-party brands names property their respective owners.
FC-PGA Intel® Pentium® Processor Chipset
Contents
Contents
Design Guide Introduction .1-1
Text Conventions .1-2 Technical Support .1-3 1.2.1 Electronic Support Systems .1-3 1.2.1.1 Online Documents .1-3 1.2.1.2 Intel Product Forums .1-3 1.2.2 Telephone Technical Support .1-3 Product Literature.1-4 Related Information .1-4 Intel® Chipset Components .2-2 2.1.1 Memory Controller (MCH).2-2 2.1.2 Controller (ICH) .2-2 2.1.3 Firmware (FWH) .2-3 2.1.4 Memory Repeater RDRAM (MRH-R) .2-3 2.1.5 64-bit (P64H) .2-3 Bandwidth Summary .2-3 System Configuration .2-4 2.3.1 Platform Configuration.2-4 Memory Expansion Card Connector .3-1 Direct RDRAM.3-1 Accelerated Graphics Port (AGP) .3-1 3.3.1 .3-1 3.3.2 .3-2 Interface.3-2 Security: Intel® Random Number Generator.3-2 Clocks.3-4 Form Factor.3-4 Manageability .3-4 3.8.1 Timer.3-4 3.8.2 Present Indicator.3-5 3.8.3 Error Reporting .3-5 3.8.4 Function Disable.3-5 3.8.5 Intruder Detect.3-5 3.8.6 SMBus.3-5 3.8.7 Alert-On-LAN.3-5 '97.3-6 Count (LPC) Interface.3-7 Ultra DMA.3-7 Universal Serial (USB) .3-8 Component Quadrant Layout .4-1
System Overview.2-1
Platform Initiatives .3-1
3.10 3.11 3.12
System Manufacturing .4-1
FC-PGA Intel® Pentium® Processor Chipset
Contents
Board Layout Routing Guidelines .5-1
General Recommendations .5-1 Stack-up Requirement .5-1 5.2.1 Overview .5-1 5.2.2 Material .5-2 5.2.3 Inner Layer Routing.5-2 5.2.4 Impedance Calculation Tools .5-3 5.2.5 Board Stack-Up .5-3 Power Distribution .5-5 5.3.1 Reference Planes Stackup .5-6 5.3.1.1 High Frequency Decoupling .5-8 Decoupling Guidelines PGA370 Designs .5-9 5.4.1 VCC_CORE Decoupling Design.5-9 5.4.2 Decoupling Design .5-9 5.4.3 VREF Decoupling Design .5-9 Thermal/EMI Differences .5-10 5.5.1 Debug Port Changes.5-10 SMI# Layout Guidelines .5-11 (FC-PGA) Intel® Pentium® Processors .6-1
Dual
Two-Way FC-PGA Pentium® Processors Intel® Chipset Layout .6-1 Definition Terms .6-2 6.2.1 AGTL+ Design Guideline .6-4 6.2.2 Initial Timing Analysis.6-5 6.2.3 Dual Processor General Topology .6-8 6.2.4 Cross-talk Routing Guidelines.6-9 Processor Overshoot/Undershoot Limits .6-9 Wired-OR Signals .6-9 Signal Return Path Considerations .6-9 Intel Pentium Processor (FC-PGA) Pull-Up Values .6-10 APIC CMOS Bus.6-11 6.7.1 Two-way FC-PGA Intel Chipset APIC Layout Guidelines.6-11 Processor THERMTRIP# Connection.6-12 BSEL[1:0] Implementation .6-12 6.10 CLKREF Circuit Implementation .6-13 6.11 On-die Considerations .6-13 6.11.1 Connecting RESET# Dual Processor PGA370 Designs .6-13 6.11.2 AGTL+ Reset Layout Topology .6-14 Single (FC-PGA) Intel® Pentium® Processors .7-1 One-Way FC-PGA Pentium® Processors Intel® Chipset Layout .7-1 Definition Terms .7-2 AGTL+ Design Methodology .7-3 Initial Timing Analysis.7-4 7.4.1 Flight Time Calculation.7-6 General Topology.7-6 Changes Signal Connectivity Uniprocessor Systems .7-7 Connecting RESET# Uniprocessor PGA370 Designs .7-8 SMI# Layout Guidelines .7-9
FC-PGA Intel® Pentium® Processor Chipset
Contents
Memory Interface.8-1
Memory Design with MEC/MECC (Outer Layer Routing) .8-2 RIMMs Motherboard.8-2 8.2.1 Signals.8-3 8.2.2 Signal Layer Alternation .8-4 8.2.3 Signal Termination .8-5 8.2.4 RDRAM Connector Compensation .8-6 8.2.5 Direct RDRAM Ground Plane Reference .8-10 8.2.6 Length Matching Method .8-10 8.2.6.1 Signals Length Match Requirement.8-11 8.2.6.2 Compensated Trace Length Calculation .8-11 8.2.6.3 Normalized Trace Length Calculation.8-11 8.2.7 Compensation .8-12 8.2.8 Direct RDRAM Reference .8-13 8.2.9 High Speed CMOS Routing .8-13 8.2.10 Routing .8-14 8.2.11 Suspend-to-RAM Shunt Transistor .8-15 General Routing Guidelines.9-2 9.1.1 Decoupling .9-2 9.1.2 Ground Reference.9-3 Timing Domain Routing Guidelines .9-3 2X/4X Timing Domain Routing Guidelines .9-3 9.3.1 Interfaces Signals Routing Guidelines.9-4 9.3.2 Interface Signals 7.25" Routing Guidelines .9-5 9.3.3 Routing Summary .9-5 9.3.4 Clock Skew .9-6 9.3.5 VDDQ TYPEDET# .9-6 9.3.6 VREF Generation .9-8 9.3.7 Compensation .9-10 9.3.8 Pull-ups/Pull-down Signals.9-10 9.3.9 Signal Voltage Tolerance List .9-12 9.3.10 Connector .9-12 9.3.11 Unused interface.9-12 Interface (8-bit) ICH.10-2 10.1.1 Interface Data Signals .10-2 10.1.2 Interface Strobe Signals .10-2 10.1.3 Interface (HLAREF) Generation/Distribution .10-2 10.1.4 Interface Compensation .10-3 Interface (16-bit) P64H .10-3 10.2.1 Data Signals .10-3 10.2.2 Strobe Signals .10-4 10.2.3 Interface HUBREF Generation/Distribution .10-4 10.2.4 HLB_RCOMP Signal .10-5 10.2.5 Unused Interface .10-5
.9-1
Interface .10-1
10.1
10.2
FC-PGA Intel® Pentium® Processor Chipset
Contents
Ultra ATA/66 .11-1
11.1 11.2 Cable Requirement .11-1 Ultra ATA/66 Cable Detection .11-1 11.2.1 Host Side Detection-BIOS Detects Cable Type Using GPIOs .11-2 11.2.2 Device Side Detection-BIOS Queries Drive Cable Type.11-3 Layout Host Side Driver Side Cable Detection .11-4 Guidelines .11-4 Codec-only .12-1 Audio/Modem Riser Specification .12-2 Signal Quality Requirements.12-3 Motherboard Implementation .12-3
11.3 11.4
.12-1
12.1 12.2 12.3 12.4
Universal Serial (USB) .13-1 Count Interface (LPC)/FWH .14-1
14.1 14.2 Circuit Programming .14-1 Design Guidelines.14-1 Crystal.15-1 External Capacitors.15-2 External Battery Connection .15-2 External RTCRST Circuit.15-3 VBIAS Clarification.15-4 15.5.1 Routing Guidelines.15-4 15.5.2 VBIAS Voltage Noise Measurements .15-4 Guidelines.16-1 Guidelines.16-2 CK133W.17-1 17.1.1 FC-PGA Intel® Pentium® Processor .17-2 17.1.2 CK133W FC-PGA Intel Pentium Processor Intel Chipset Clock Skew.17-3 17.1.3 BCLK Skew Between Chipset .17-4 17.1.4 Processor Platform Clocks Ganging Solution.17-4 Series Termination Resistor CK133W Clock Outputs.17-5 Topology Under Investigation Source Series Termination with Receiver Termination.17-5 Unused CK133W Clock Outputs .17-6 DRCG.17-7 Component Placement Layout Requirements .17-7 17.6.1 14.318 Crystal CK133W .17-7 17.6.2 CK133W DRCG .17-7 17.6.3 Intel® 82840-MCH DRCG .17-8 17.6.4 DRCG RDRAM Channels .17-8
.15-1
15.1 15.2 15.3 15.4 15.5
.16-1
16.1 16.2
Clocking .17-1
17.1
17.2 17.3 17.4 17.5 17.6
FC-PGA Intel® Pentium® Processor Chipset
Contents
17.7
17.8 17.9
17.6.5 Trace Lengths .17-10 17.6.6 DRCG Impedance Matching Circuit .17-11 17.6.7 DRCG Layout Example .17-13 17.6.8 Decoupling Recommendation CK133W DRCG .17-14 DRCG Frequency Selection DRCG+ .17-14 17.7.1 DRCG Frequency Selection Table .17-14 17.7.2 DRCG+ Frequency Selection Schematic .17-14 Clock Routing Guidelines .17-15 17.8.1 P64H Clock Routing Guidelines.17-15 P64H Clock Routing Guidelines.17-17 Power Delivery .18-1 18.1.1 Definitions.18-1 18.1.2 Intel® Chipset Board Power Delivery.18-2 Power Management .18-5 ACPI Hardware Model.18-5 Thermal Design Power.18-6 64/72-Mbit RDRAM Excessive Power Consumption.18-7 18.5.1 Option Reduce Clock Frequency During Initialization .18-7 18.5.2 Option Increase Current Capability Voltage Regulator .18-7 VTERM/VDD Power Sequencing Requirement .18-8 VDDQ/VCC1.8 Power Sequencing.18-8 ICH/P64H 5VREF VCC3.3 Sequencing Requirement .18-9 General Design Considerations .19-1 Design Consideration .19-1 19.2.1 FC-PGA Intel® Pentium® Processors.19-1 82840 Memory Controller (MCH).19-2 19.3.1 System Interface .19-2 19.3.2 RDRAM Interface .19-2 19.3.2.1 Ground Isolation .19-2 19.3.2.2 VTERM Layout Guidelines Noise .19-3 19.3.2.3 CTM/CTM# Routing.19-3 19.3.2.4 DRCG Power Supply .19-3 19.3.2.5 DRCG Output Network Layout .19-4 19.3.2.6 Transmission Line.19-4 19.3.2.7 VREF Routing .19-4 19.3.2.8 Routing .19-5 19.3.2.9 RDRAM Clock Routing .19-5 19.3.2.10 Interface A.19-5 19.3.2.11 Interface .19-5 19.3.3 Controller (ICH) .19-6 19.3.3.1 AC'97 Interface .19-6 19.3.3.2 APIC Interface .19-6 19.3.3.3 Interface.19-6 19.3.3.4 Interface A.19-6 19.3.3.5 IDE.19-6 19.3.3.6 SIO.19-7 19.3.3.7 Interface.19-7
System Design Considerations .18-1
18.1
18.2 18.3 18.4 18.5
18.6 18.7 18.8
Design Considerations/Checklist .19-1
19.1 19.2 19.3
FC-PGA Intel® Pentium® Processor Chipset
Contents
19.4
19.3.3.8 Power Ground .19-7 19.3.3.9 .19-9 19.3.3.10 SMBus/Alert .19-9 19.3.3.11 Interface .19-9 19.3.3.12 Firmware (FWH) .19-10 19.3.4 64-bit (P64H) .19-10 19.3.4.1 APIC Interface .19-10 19.3.4.2 Interface B.19-10 19.3.4.3 Interface.19-10 19.3.4.4 Clocks .19-10 19.3.4.5 Power Ground .19-10 19.3.5 CK133W/S Clock Synthesizer.19-11 Design Checklist .19-12 19.4.1 FC-PGA Intel® Pentium® Processors.19-12 19.4.2 82840 Memory Controller (MCH).19-16 19.4.3 Controller (ICH).19-19 19.4.4 Firmware (FWH)- 40Lead TSOP .19-22 19.4.5 64-bit (P64H) .19-23 Pre-Layout Simulation. A.1.1 Methodology. A.1.1.1. Simulation Criteria A.1.2 Place Route Board A.1.2.1. Estimate Component Component Spacing AGTL+ Signals. A.1.2.2. Layout Route Board A.1.2.3. Host Clock Routing. A.1.3 Post-Layout Simulation A.1.3.1. Intersymbol Interference. A.1.3.2. Cross-talk Analysis. A.1.3.3. Monte Carlo Analysis A.1.4 Validation A.1.4.1. Measurements. A.1.5 Timing Requirements A.1.5.1. Flight Time Simulation. A.1.5.2. Flight Time Hardware Validation Theory A.2.1 AGTL+. A.2.2 Cross-Talk Theory. A.2.2.1. Potential Termination Cross-talk Problems More Details Insights. A-10 A.3.1 Textbook Timing Equations. A-10 A.3.2 Effective Impedance Tolerance/Variation. A-11 A.3.3 Clock Routing. A-11 Conclusion A-12
AGTL+ Design Guidelines
Schematics Index Index-1
viii
FC-PGA Intel® Pentium® Processor Chipset
Contents
Figures
5-10 5-11 5-12 8-10 8-11 8-12 8-13 8-14 8-15 10-1 Intel® Chipset Configuration .2-4 with Audio/Modem Codec.3-6 with Audio Modem Codec.3-7 View MBGA Quadrant Layout.4-1 View MBGA Quadrant Layout.4-2 View Package .4-2 View P64H MBGA Quadrant Layout.4-3 View- MRH-R MBGA Quadrant Layout.4-3 Trace Geometry.5-2 Microstrip Cross Section Trace .5-3 8-Layer Board Stack-up Example .5-4 12-Layer Board Stack-up Example .5-5 Signal Layer Reference Plane .5-6 Layer Switch with Reference Plane.5-7 Layer Switch with Multiple Reference Planes (same type) .5-7 Layer with Multiple Reference Planes .5-7 Layer Switch with Multiple Reference Planes .5-8 Capacitor Placement Motherboard.5-9 Connector Comparison .5-10 Topology Simulated.5-11 Intel® Pentium® Processor Dual Processor Configuration .6-8 PICD[1:0] Two-way Topology.6-11 BSEL[1:0] Circuit Implementation PGA370 Designs.6-12 Examples CLKREF Divider Circuit.6-13 AGTL+ Reset Schematic PGA370 Designs .6-14 Uniprocessor Topology Processor System Frequency .7-6 Uniprocessor Reset Topology .7-8 Uniprocessor SMI# Topology .7-9 MECC Layout (Outer Layer Routing) .8-2 Routing Dimension RIMMs.8-3 Example Routing Diagram .8-4 Signal Layer Alternation .8-4 Direct RDRAM Termination.8-5 Rambus Termination Example .8-6 C-Tab Example, Layer .8-8 C-Tab Example, Bottom Layer .8-9 Close-up C-TABs .8-10 RDRAM Trace Length Matching Example .8-11 Dummy Real Vias .8-12 RAMREF Generation Example Circuit .8-13 High Speed CMOS Termination.8-14 Routing Example.8-15 RDRAM CMOS Shunt Transistor .8-16 2X/4X Routing Example Interfaces .9-4 VDDQ Generation Example.9-7 VREF Generation Distribution Cards.9-9 VREF Generation Distribution Cards.9-10 Interface (8-Bit) Routing Example .10-1
FC-PGA Intel® Pentium® Processor Chipset
Contents
10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 12-1 12-2 12-3 13-1 15-1 15-2 15-3 16-1 16-2 16-3 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 19-1
Interface (16-Bit) Routing Example .10-1 MCH/ICH Single Interface Reference Divider Circuit .10-2 MCH/ICH Locally Generated Interface Reference Divider Circuit .10-3 MCH/P64H Single Interface Reference Divider Circuit .10-4 MCH/P64H Locally Generated Interface Reference Divider Circuit .10-5 Host Side Cable Detection .11-2 Driver Side Cable Detection #2.11-3 Driver-side Detection Layout.11-4 Resistor Placement Primary Secondary Connector.11-5 Codec-only Topology Trace Length Requirements.12-1 Topology Trace Length Requirements.12-2 Daisy-Chain Topology Trace Length Requirements .12-2 Data Signals .13-2 External Circuitry .15-1 Diode Circuit Connect External Battery .15-2 RTCRST External Circuit .15-3 Layout Example.16-1 Slots Only.16-2 Slots Device Down .16-2 CK133W Clock Diagram .17-2 CK133W Intel® Pentium® Processor/Intel® Chipset Guidelines .17-4 Transmission Line Termination .17-5 VDDIR CPU_DIV2 Routing .17-7 DRCG Routing Diagram .17-8 RDRAM Clock Routing Dimension.17-9 Board Stack-up: Signals.17-10 Board Stack-up: Differential Signals .17-10 CFM/CFM# Termination.17-11 DRCG Impedance Matching Network .17-11 DRCG Layout Example.17-13 DRCG+ Frequency Selection.17-15 P64H Clock Routing .17-16 P64H Clock Trace.17-16 P64H Clock Routing .17-17 P64H Clock Trace.17-17 FC-PGA Intel® Pentium® Processor Intel® Chipset RIMMs Power Delivery Architecture.18-2 FC-PGA Intel® Pentium® Processors Intel® Chipset Power Delivery .18-3 Intel® Chipset System Power Delivery .18-4 Global System Power States Transition.18-5 Using Reduce DRCG Frequency .18-7 Power Sequence (Schottky Diode) .18-8 VDDQ Power Sequencing Example .18-9 5VREF Sequencing Circuit .18-9 PWRGOOD PWROK Generation Logic.19-8 Test Load Actual System Load. Aggressor Victim Networks Transmission Line Geometry: Microstrip Stripline
FC-PGA Intel® Pentium® Processor Chipset
Contents
Tables
13-1 17-1 17-2 17-3 17-4 17-5 17-6 18-1 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 Related Documents.1-4 Related Specifications.1-4 Intel® Chipset Platform Bandwidth Summary.2-3 Field Solver ZCALC*.5-3 Definition Terms .6-2 AGTL+ Component Timings.6-5 Example TFLT_MAX Calculations Bus1 .6-7 Example TFLT_MIN Calculations (Frequency Independent) .6-7 Segment Descriptions Lengths Figure 6-1.6-8 Pull-Up Values.6-10 PICD[1:0] Two-way Topology Segment Lengths .6-11 Resistor Values CLKREF Divider (3.3V Source) .6-13 Definition Terms .7-2 AGTL+ Component Timings.7-4 Example TFLT_MAX Calculations Bus1 .7-5 Example TFLT_MIN Calculations (Frequency Independent) .7-6 Recommendations .7-7 Signal Differences Uniprocessor Intel® Chipset Systems .7-7 RDRAM Channel Signal Groups .8-1 Routing Trace Lengths .8-3 Signal Layer Alteration .8-5 Copper Area Calculation .8-7 Signal Groups .9-2 Routing Summary .9-6 TYPEDET# VDDQ Relationship .9-7 Pull-up/Pull-down Resistors .9-11 2X/4X Pull-up Pull-down Resistors .9-11 Connector/Add-in Card Interoperability .9-12 Voltage/Data Rate Interoperability .9-12 Recommended Trace Characteristics.13-2 Intel® Chipset System Clocks CK133W .17-1 Intel® Chipset Clock Skew .17-3 Sample Trace Length Calculation .17-6 Unused Clock Output Connection Guidelines .17-6 RDRAM* Clock Routing Guidelines .17-9 DRGC+ DRGC Multiplier Ratios .17-14 Thermal Design Power.18-6 Pins Special Functions .19-11 FC-PGA Intel® Pentium® Processor Intel Chipset Connectivity1 .19-12 CMOS Connectivity Checklist 370-Pin Socket Processors.19-13 Checklist 370-Pin Socket Processors1, .19-13 Miscellaneous Checklist 370-Pin Socket Processors .19-14 Clock Generator Checklist.19-15 Signal Differences Uniprocessor Intel® Chipset Systems .19-16 Connectivity.19-16
FC-PGA Intel® Pentium® Processor Chipset
Contents
19-9 19-10 19-11
Connectivity .19-19 Connectivity .19-22 P64H Connectivity.19-23 Trace Width:Space Guidelines.
Revision History
Date 2000 2000 Revision Description Removed MRH-S references. Integrated uniprocessor design guide supplement (273334) into this document. First public release.
FC-PGA Intel® Pentium® Processor Chipset
Design Guide Introduction
This design guide organizes Intel's design recommendations implementing single- dualprocessor systems using Intel® Pentium® processor (100/133 system bus) FlipChip Grid Array (FC-PGA) package together with Intel® chipset. addition providing motherboard design recommendations such layout routing guidelines, this document also addresses possible system design issues such thermal requirements Intel chipset systems. This document presents design recommendations, board schematics, debug recommendations, system checklist that should used system design. These design guidelines have been developed ensure maximum flexibility board designers while reducing risk board related issues. Intel schematics used reference board designers. While schematics cover specific dual processor designs, core schematics will remain same most FC-PGA Pentium processor/Intel chipset platforms. reference schematic features includes following features:
Dual processor, FC-PGA Socket Intel chipset MCH, ICH, FWH, P64H channels RDRAM, RIMMs channel universal connector 4x33 MHz/32-bit (ICH) 2x66 MHz/64-bit (P64H) UltraDMA/66 audio 82559 Super CK133W DRCG Rambus*
FC-PGA Intel® Pentium® Processor Chipset
Design Guide Introduction
Text Conventions
following notations used throughout this manual. Variables Instructions pound symbol appended signal name indicates that signal active low. Variables shown italics. Variables must replaced with correct values. Instruction mnemonics shown uppercase. When programming, instructions case-sensitive. either uppercase lowercase. Hexadecimal numbers represented string hexadecimal digits followed character zero prefix added numbers that begin with through (For example, shown 0FFH.) Decimal binary numbers represented their customary notations. (That decimal number 1111 1111 binary number. some cases, letter added clarity.) following abbreviations used represent units measure: Gbyte Kbyte Mbyte Signal Names amps, amperes gigabytes kilobytes kilo-ohms milliamps, milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps, microamperes microfarads microseconds microwatts
Numbers
Units Measure
Signal names shown uppercase. When several signals share common name, individual signal represented signal name followed number, while group represented signal name followed variable (n). example, lower chip-select signals named CS0#, CS1#, CS2#, they collectively called CSn#. pound symbol appended signal name identifies active-low signal. Port pins represented port abbreviation, period, number (e.g., P1.0).
FC-PGA Intel® Pentium® Processor Chipset
Design Guide Introduction
1.2.1
Technical Support
Electronic Support Systems
Intel's site World Wide (http://www.intel.com/) provides up-to-date technical information product support. This information available hours day, days week, providing technical information whenever need
1.2.1.1
Online Documents
Product documentation provided online variety Web-friendly formats
1.2.1.2
Intel Product Forums
Intel provides technical expertise through electronic messaging. With publicly accessible forums, have benefits e-mail technical support, with added benefit option viewing previous messages written other participants, providing suggestions tips that help others. Each Intel's technical support forums based single product product family. Questions replies limited topic particular forum. Intel also provides several non-technical support related forums. Complete information Intel forums available
1.2.2
Telephone Technical Support
U.S. Canada, technical support representatives available answer your questions between a.m. p.m. PST. also your questions (Please include your voice telephone number indicate whether prefer response phone fax.) Outside U.S. Canada, please contact your local distributor. 800-628-8686 916-356-7599 916-356-6100 (fax) U.S. Canada U.S. Canada U.S. Canada
FC-PGA Intel® Pentium® Processor Chipset
Design Guide Introduction
Product Literature
order product literature from following Intel literature centers. 800-548-4725 708-296-9333 44(0)1793-431155 44(0)1793-421333 44(0)1793-421777 81(0)120-47-88-32 U.S. Canada U.S. (from overseas) Europe (U.K.) Germany France Japan (fax only)
Related Information
Table 1-1. Related Documents
Document Title Order Number 245264 244453 273325 298020 290655 298025 244001 243190 243191 243192 245125
Pentium® Processor PGA370 1GHz datasheet Intel® Pentium® Processor Specification Update Intel® Pentium® Processor Thermal Design Guide Intel® Chipset: 82840 Memory Controller (MCH) datasheet Intel® 82801AA (ICH) Intel® 82801AB (ICH0) Controller datasheet Intel® 82806AA PCI64 (P64H) datasheet Family Processors Hardware Developer's Manual Intel Architecture Software Developer's Manual, Volume Basic Architecture Intel Architecture Software Developer's Manual, Volume Instruction Reference Intel Architecture Software Developer's Manual, Volume System Programming Guide Intel Processor Serial Number application note
Table 1-2. Related Specifications
Specification ac97/ agp_index.htm industry/lpc.htm http://www.pcisig.com http://www.pcisig.com http://www.pcisig.com http://www.pcisig.com
Component Specification, Revision Accelerated Graphics Port Interface Specification, Revision Count Interface Specification, Revision Local Specification, Revision Local Specification, Revision ECNs PCI-PCI Bridge Specification, Revision Power Management Interface Specification, Revision Universal Serial Specification, Revision
FC-PGA Intel® Pentium® Processor Chipset
System Overview
Intel® chipset designed Intel's Pentium® Pentium III, Pentium Xeonprocessor-based architectures. This chipset allows flexibility dual single FC-PGA Pentium processor configurations with system bus. Intel chipset consists three main components: Memory Controller (MCH), Controller (ICH) Firmware (FWH). Architectural expansion provided with memory expansion card 64-bit (P64H). Intel chipset components interconnected interface called interface. interface designed into Intel chipset provide efficient communication between chipset components. Additional hardware platform features supported Intel chipset include RDRAM, Ultra DMA/66, Count interface (LPC), Universal Serial (USB). Intel chipset architecture eliminates requirement expansion bus, which traditionally integrated into subsystem PCIsets/AGPsets. This removes many conflicts experienced when installing legacy hardware drivers. Intel chipset architecture enables security manageability infrastructure through Firmware component. custom features provides consistent pre-boot environment enables protected infrastructure storing updating platform code data. Intel chipset also ACPI-compliant supports Full-on, Stop Grant, Suspend RAM, Suspend Disk, Soft-off power management states. Through appropriate device, Intel chipset also supports Wake-on-LAN remote administration troubleshooting.
FC-PGA Intel® Pentium® Processor Chipset
System Overview
Intel® Chipset Components
Intel chipset consists Memory Controller (MCH), Controller (ICH) Firmware (FWH). Additional functionality provided using memory expansion (memory repeater MRH-R) P64H.
2.1.1
Memory Controller (MCH)
component contains interface, DRAM controller, P64H interface, interface interface. communicates with Intel chipset controller (ICH) P64H over interface. supports dual channels Direct RDRAM data transfers. also contains advanced power management logic. Intel chipset contains following functionality:
Provides Dual Channel Pre-Fetched Architecture Supports single dual FC-PGA Pentium processor configurations 100/133 AGTL host supporting 32-bit 36-bit host addressing Dual direct RDRAM channels support operation Support 4-Gbyte RDRAM device support interface with SBA/Data Transfer 2X/4X Fast Write capability 8-bit/66 interface 16-bit/66 interface P64H Fully optimized data paths buffering Distributed arbitration highly concurrent operation
2.1.2
Controller (ICH)
Controller provides subsystem access rest system. Additionally, integrates many functions. integrates following features:
Upstream link access Two-channel Ultra ATA/66 Master controller controller APIC SMBus controller interface Count interface interface interface Integrated System Management controller Alert-on-LAN
also contains arbitration buffering needed efficiently utilize these interfaces.
FC-PGA Intel® Pentium® Processor Chipset
System Overview
2.1.3
Firmware (FWH)
component element enabling security manageability infrastructure platform. device operates under interface protocol. hardware features this device include unique Random Number Generator (RNG), register-based locking, hardware-based locking.
2.1.4
Memory Repeater RDRAM (MRH-R)
MRH-R component provides capability support multiple RDRAM channels from "expansion channel." expansion channel interconnect between Intel chipset MRH-R. Each MRH-R support "stick" channels. MRH-R acts pass-through logic with fixed delay read write accesses from expansion channels RDRAM channels. MRH-R features also include:
Maximum 1-Gbyte memory channel Entry/Exit, Power Down Exit, Refresh Precharge channel upon request from
memory controller Core logic gating minimize power consumption Clock generation Direct Rambus* Clock Generator (DRCG) Integrated SMBus controller read/write data from/to EEPROM RIMMs
2.1.5
64-bit (P64H)
PCI-64 (P64H) peripheral chip that performs bridging functions between interface used integral part Intel chipset. P64H 16-bit primary interface Memory Controller (MCH) secondary 64-bit interface. 64-bit interfaces inter-operate transparently with either 64-bit 32-bit devices. P64H fully complies with Local Specification, Revision 2.2. P64H integrated functions include:
Integrated skew clock driver APIC
Bandwidth Summary
Clock Speed (MHz) Samples Clock Data Rate (Msamples/s) Data Width (Bytes) Bandwidth (Mbyte/s) 1066 1066
Table 2-1. Intel® Chipset Platform Bandwidth Summary
Interface interface interface (32-bit) (64-bit)
FC-PGA Intel® Pentium® Processor Chipset
System Overview
2.3.1
System Configuration
Platform Configuration
Figure 2-1. Intel® Chipset Configuration
100/133 System MECC
21154
MRH-R
RDRAM
RDRAM MRH-R Interface ports) RDRAM
P64H
Interface
drives)
Slot Slot Slot Slot
Modem Codec (optional) Audio Codec (optional)
Note: Denotes core Intel® chipset Denotes expandability components
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FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
Memory Expansion Card Connector
memory expansion card (MEC) concept intended provide flexibility scalability memory Intel® chipset-based platforms. Specific design information memory expansion card connector will described future releases this document.
Direct RDRAM
Direct RDRAM initiative will provide necessary memory bandwidth achieving optimal processor performance enabling implementation high performance controller. RDRAM interface supports 300-MHz 400-MHz operations; 300-MHz operation provides Gbyte/s theoretical memory bandwidth twice memory bandwidth SDRAM systems. Coupled with greater bandwidth, RDRAM protocol provides substantially more efficient data transfer. RDRAM memory interface achieve greater than utilization Gbyte/s theoretical maximum bandwidth. addition RDRAM's performance features, this memory architecture provides enhanced power management capabilities. powerdown mode operation will enable Intel chipset-based system cost-effectively support suspend-to-RAM. Industry leading DRAM vendors have agreed develop RDRAMs, module vendors will developing RDRAM Inline Memory Modules (RIMMs). RIMMs provide approximately same form factor SDRAM DIMMs.
3.3.1
Accelerated Graphics Port (AGP)
Accelerated Graphics Port (AGP) high performance, component-level interconnect targeted graphical display applications. based performance extensions enhancements bus. interface optimized point-to-point topology using either signaling. baseline performance level utilizes clock provide peak bandwidth Mbyte/s. There options higher performance levels: mode mode. mode provides peak bandwidth Mbyte/s mode provides peak bandwidth 1066 Mbyte/s. Refer Accelerated Graphics Port Interface Specification, Revision Design Guide (1x, Modes Signaling), Revision further details.
FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
3.3.2
specifies extension graphics connection high-performance workstation market segment. specifications include electrical, mechanical thermal requirements connector, card chassis. will also include examples possible thermal solutions. expected deliver four times electrical power standard interface through extension connector provision sufficient space dissipating this increased power. also allows multiple slot implementations where Card coupled with more cards. specification allows flexible utilization thermal space provided cards that dissipate significantly less than maximum power-envelope. will retain mechanical functional compatibility with implying that card plug into connector, though reverse will allowed. Refer Specification complete details http://www.agp.org.
Interface
speed increases, demand placed becomes significant. With addition '97, ATA/66 existing USB, requirement could impact performance. Intel chipset's interface architecture ensures that subsystem will receive adequate bandwidth. placing bridge interface, allows functions obtain necessary bandwidth peak performance. addition, interface's lower count allows smaller package memory controller.
Security: Intel® Random Number Generator
Intel chipset features first Intel's platform security features, Intel Random Number Generator (RNG). Intel component 82802 Firmware (FWH) that supplies applications security middleware products with true non-deterministic random numbers, through Intel Security Driver. Better random numbers provide better security. Most cryptographic functions, especially those that provide authentication encryption services, require random numbers purposes such generation. means attacking those cryptographic functions predict random numbers being used generate those keys. Current methods that system user input seed pseudo-random number generator have shown susceptible those attacks. Intel uses thermal noise across resistor generate true non-deterministic, unpredictable random numbers. Applications often access cryptographic functions through security middleware products such Microsoft's CAPI*, RSA's BSAFE*, OpenGroup's CDSA*. Intel working ensure that middleware products applications enabled take advantage this capability. Implementing BIOS requirements, testing loading Intel Security Driver, ensures that Intel enabled your platform design.
FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
system BIOS must contain System Device Node (devnode) device order plug-and-play operating systems Intel Random Number Generator through Intel Security Driver. devnode required order find enumeration time, specific devnode number associates with Intel Security Driver. BIOS Specification (FM-1604) contains complete details BIOS requirements enable Intel RNG.
BIOS must report single device node FWH:
Intel Specific EISA (devnode number must INT0800) Device Type: System peripherals/other Device Attribute: Non-configurable cannot disabled ANSI String: "Intel FWH" Memory Range Descriptor: Describing feature space
plug-and-play operating systems, BIOS ranges allocated through E820h ACPI
structures, current BIOS.
plug-and-play operating systems, ranges should reserved through
E820h function. complete Intel chipset system must have Intel Security Driver loaded order applications take advantage Intel Random Number Generator. Intel Security Driver implements interface that middleware some applications call access Intel RNG. Intel Security Driver obtained from Intel Chipset Software Driver site Intel Security Driver tests Intel hardware each time driver initialized. Driver obtains random numbers from Intel hardware verifies that they meet federal FIPS 140-1 randomness standard. self-test application that explicitly verifies that Intel output meeting FIPS 140-1 standard bundled with Intel Security Driver above site. Running self-test continuous mode gets numbers from Intel runs FIPS 140-1 randomness test those numbers. install driver self-test, InstallShield* executable, unzip floppy version 3.5" disks SETUP.EXE from disk. default setup options Intel Security Driver folder, which contains Self Test application, Windows Programs menu. Self Test application targeted user; should used verify operation Intel Intel Security Driver.
FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
Clocks
clock synthesizer/generator specification, CK133W, been defined Intel chipset platform. CK133W shares same pinout CK133. features include:
14.31818 Xtal Oscillator Input Four copies 100/133 clocks (cycle jitter=150 CPU/2 outputs Four copies fixed @3.3 clocks Eight copies clocks Three copies APIC clocks @16.667 copy clock copies 14.31818 reference clocks Power Management Control Input pins Spread Spectrum Clocking support
Reference CK98W/S Clock Synthesizer/Driver Specification complete details.
Form Factor
board-set system form factor developed mid-range workstation market. This specification defines board-set volume, interface between board-set chassis, openings, thermal requirements. also provides design suggestions motherboard chassis development. Several major Intel architecture workstation vendors worldwide worked jointly define form factor, incorporating flexibility accommodate best designs current future mid-range workstations. specification other information available http://www.wtx.org
Manageability
Intel platform integrates several functions designed manage system lower total cost ownership (TCO) system. These system management functions designed report errors, diagnose system, recover from system lockups without external microcontroller.
3.8.1
Timer
integrates programmable Timer. This timer used detect system locks. first expiration timer generates SMI# that system recover from software lock. second expiration timer causes system reset recovery from hardware lock.
FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
3.8.2
Present Indicator
looks fetch first instruction after reset. does fetch first instruction, reboots system safe-mode frequency multiplier.
3.8.3
Error Reporting
Upon detecting error, ability send several messages ICH. tell generate either SMI#, NMI#, SERR#, interrupt.
3.8.4
Function Disable
provides ability disable following functions: Modem, Audio, IDE, SMBus. Once disabled, these functions longer decode I/O, memory, configuration space. interrupts power management events generated from disabled functions.
3.8.5
Intruder Detect
provides input signal, INTRUDER#, that attached switch that activated when system case opened. programmed generate SMI# interrupt active INTRUDER# signal.
3.8.6
SMBus
integrates SMBus controller. SMBus provides interface manage peripherals such serial presence detection (SPD) RIMMs thermal sensors.
3.8.7
Alert-On-LAN
supports Alert-On-LAN. response event (intruder detect, thermal event, booting) will send hard coded message over SMBus. controller decode this SMBus message send message over network alert network manager. Refer Wired Management (WfM) Design Guide complete details this URL:
FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
Audio Codec '97) Specification defines digital link that used attach audio codec (AC), modem codec (MC), audio/modem codec (AMC), both Figure Figure illustrate these digital links. Specification defines interface between system logic audio/modem codec known Digital Link. ability cost-effective audio modem solutions platform migrates away from important. addition, audio modem components software configurable. replaces audio modem functionality, improves overall platform integration, eases migration from architecture, reduces cost. using audio codec, digital link enables cost-effective, high-quality, integrated audio Intel chipset platform. addition, soft modem implemented with modem codec. integrated digital link allows external codecs connected ICH. system designer provide audio with audio codec modem with modem codec. systems requiring both audio modem, there solutions: audio codec modem codec integrated into separate audio modem codecs connected ICH. Modem implementation different countries must considered varying telephone standards. Using single integrated codec AMC, both audio modem routed connector near rear panel where external ports located. digital link Rev. 2.1-compliant, supporting codecs with independent functions audio modem. Microphone input left/right audio channels supported high quality twospeaker audio solution. Wake ring from suspend also supported with appropriate modem codec.
Figure 3-1. with Audio/Modem Codec
Modem Port
Digital Link
Audio/ Modem Codec
Audio Port
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FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
Figure 3-2. with Audio Modem Codec
Modem Port
Modem Codec
Digital Link Audio Codec
Audio Port
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Specification, Revision 2.1, complete details.
3.10
Count (LPC) Interface
Intel chipset platform, Super component migrated Count (LPC) interface. Migration interface allows lower cost Super designs. Super component requires same feature traditional Super components. generally includes keyboard mouse controller, floppy disk controller, serial parallel ports. addition standard Super features, integrated game port recommended because interface does provide support game port. systems with audio, game port typically existed audio card. 15-pin game port connector provides joysticks two-wire MPU-401 MIDI interface. Refer Count Interface Specification, Revision 1.0, (http://developer.intel.com/ complete details. Consult your Super vendor comprehensive list devices offered features supported.
3.11
Ultra
Ultra widens path hard drive transferring twice much data clock cycle. maximum disk drive burst data transfer rate increases from 16.6 Mbyte/s Mbyte/s. Hard disk drive manufacturers bring higher performance products market that scale with rest platform (faster hard drives feed faster processors, memory, graphics). Ultra protocol lets host computers (PCs) send retrieve data faster, removing bottlenecks associated with data transfers especially during sequential operations. Users will need less time boot their systems open applications, direct result improved throughput provided Ultra DMA. Current disk drive technology been optimized perform
FC-PGA Intel® Pentium® Processor Chipset
Platform Initiatives
within limits legacy protocol (16.6 Mbyte/s). Raising data transfer headroom results moderate performance gains with today's drive technology. Greater performance improvements will emerge drive manufacturers introduce products that generate faster data stream. supports both Ultra DMA/33 Ultra DMA/66 protocols. Ultra DMA/66 similar Ultra DMA/33 scheme intended device driver compatible. Ultra DMA/66 logic operates move 16-bits data every clocks, maximum Mbyte/s.
3.12
Universal Serial (USB)
Universal Serial (USB) simplifies process attaching peripherals computer accessing them. also eases system configuration process from end-user's perspective. specification outlines single connector-type peripherals, automatic detection/ configuration devices, transfer types allowed bus. Intel chipset-based platform, integrated Host Controller, includes root with separate ports. Host Controller supports standard Universal Host Controller Interface (UHCI), Revision 1.0. Refer Specification, Revision http://www.usb.org further details.
FC-PGA Intel® Pentium® Processor Chipset
System Manufacturing
Component Quadrant Layout
preliminary quadrant layouts shown approximate. Only exact ball assignment should used conduct routing analysis. Please reference specific component's datasheet other specification document this information. Figure 4-1. View MBGA Quadrant Layout
Interface
µBGA
Interface
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FC-PGA Intel® Pentium® Processor Chipset
System Manufacturing
Figure 4-2. View MBGA Quadrant Layout
Interface
SMBus
µBGA
A8155-01
Figure 4-3. View Package
Interface 40-Lead TSOP
Interface 32-Lead PLCC
A8166-01
FC-PGA Intel® Pentium® Processor Chipset
System Manufacturing
Figure 4-4. View P64H MBGA Quadrant Layout
P64H µBGA
Interrupt
Plug
Interface
A8236-01
Figure 4-5. View- MRH-R MBGA Quadrant Layout
MISC
Channel RDRAM Interface (Master Interface)
Channel RDRAM Interface (Master Interface)
MRH-R µBGA
Expansion Channel (Slave Channel)
A8156-01
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
This section documents motherboard layout routing guidelines Intel® chipset-based system. component functionality information, refer each component's respective specification. Although layout routing guidelines provided, recommended that OEMs simulate signals ensure proper signal integrity flight time. Complete signal integrity timing simulation important whether design deviates from following layout routing guidelines.
General Recommendations
nominal trace impedance used ±10%. When calculating flight times, important consider minimum maximum impedance trace based switching neighboring traces. Wider spaces between traces used since this minimize trace-to-trace coupling, reduce crosstalk. recommendations described this document assume wide signal trace unless otherwise specified. wider traces used, trace spacing must adjusted accordingly (linearly). example, recommended that signals routed with minimum traces spaces (ratio 1:4). increase trace width, requires trace spacing adjusted mil, maintaining ratio. These guidelines were generated based eight- 12-layer board stack-ups. Other stack-ups used, thorough simulation highly recommended.
5.2.1
Stack-up Requirement
Overview
Intel chipset requires board stack-up with prepreg outer layer. This change dimension (previously, typically mil) required because signaling environment used Direct RDRAM*, link. RDRAM channel designed mismatched impedance will cause signal reflections that will reduce voltage timing margins. example, with clock operation, which equals 1.25 sampling window, only allotted total channel timing error. Channel error results only from impedance, also process variation. Therefore, critical attain required impedance.
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
5.2.2
Material
tolerances determine variation. Those tolerances include trace width, prepreg thickness, plating thickness, dielectric constant. Figure 5-1. prepreg type impacts tolerance tolerance, which includes single ply, two-ply, resin content. design correct variation, PCBs typically need meet following:
Height tolerance mil) Width tolerance 2.5% mil) tolerance (~0.2)
stack-up impedance requirement must 10%. Figure 5-1. Trace Geometry
A8238-01
Steps design meet tight tolerance requirements include:
Specify material used. Calculate board geometry desired impedance example stack-up provided. Build test boards coupons. Measure board impedance using follow procedures Impedance Test Methodology document. This document available Intel developer's site: http://developer.intel.com/
Measure board geometry with cross-section. Adjust design parameters and/or material required. Build board, measure parameters again prepared generate
board iterations.
5.2.3
Inner Layer Routing
Inner layer routing many possible stack-up combinations. initial should fall within acceptable limits, 10%, with these parameters. important consider ground floods stitching well. Figure provides example Stripline Microstrip cross sections:
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Figure 5-2. Microstrip Cross Section Trace
mils mils
mils
mils
mils
A8174-01
5.2.4
Impedance Calculation Tools
Field Solvers, such those Ansoft, Sonnet, Polar most accurate impedance calculations. calculators, based equations (ZCALC*), also reasonably accurate. differences shown:
Table 5-1. Field Solver ZCALC*
Example 18.1 Example 18.1 Example 18.1 Example 18.1 Example 17.1 Example 19.1
Results with (3D) Results with (ZCALC)
29.0 29.1
28.4 28.7
27.6 27.7
30.4 30.4
30.2 3.02
27.9 28.0
5.2.5
Board Stack-Up
There board stack-ups shown, eight-layer platforms, shown Figure 5-3, other 12-layer platforms, shown Figure 5-4. additional prepreg thickness recommended accommodate high-speed signal environment. example: Direct RDRAM, interface, interfaces. There popular prepreg types:
7628 Cloth, .007" when cured with resin 2116 Cloth, .0045" when cured with resin
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Although 7628 Cloth more common, recommended that 2116 Cloth used because better accommodates high speed signals impedance layout requirements. Other board stack-ups achieved important maintain traces inner outer layers close possible. also important maintain prepreg that needed keep RDRAM traces impedance. Figure 5-3. 8-Layer Board Stack-up Example
Signal Layer (1/2 Foil) Prepreg Ground Layer Foil) Core Signal Layer Foil) Prepreg Power Plane Foil) Core Power Plane Foil) Prepreg Signal Layer Foil) Core Ground Layer Foil) Prepreg Signal Layer (1/2 Foil)
A8167-01
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Figure 5-4. 12-Layer Board Stack-up Example
Signal Signal VCC1 VCC2 Signal Signal Bottom Layer
A8168-01
Power Distribution
Designs using Pentium processor require several different voltages. following paragraphs describe some impact common methods used distribute required voltages. Refer Flexible Motherboard Power Distribution Guidelines more information power distribution. most conservative method distributing these voltages each them have dedicated plane. When these planes used ground" reference traces control trace impedance board, then plane needs coupled system ground plane. This method require more total layers than other methods. ounce/ft2 thick copper recommended power reference planes. second method power distribution partial planes immediate area needing power, place these planes routing layer as-needed basis. These planes still need decoupled ground ensure stable voltages components being supplied. This method disadvantage reducing area that used route traces. These partial planes also change impedance adjacent trace layers. (For instance, impedance calculations have been done microstrip geometry, adding partial plane other side trace layer turn microstrip into stripline.)
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
5.3.1
Reference Planes Stackup
type number layers need chosen balance many requirements. Many these requirements include:
maximum trace resistance AGTL+ signal paths should exceed Depending
trace width chosen vendor's process tolerance, this require ounce/ft2 thick copper instead ounce/ft2 thickness. higher trace resistivity increases voltage drop along trace, which reduces falling edge noise margin. requirements components
Providing enough routing channels support minimum maximum timing Providing stable voltage distribution each components Providing uniform impedance processor other signals needed Providing ground plane under principal component side baseboard, preferably
under both sides when active components mounted both sides
Minimizing coupling/cross-talk between networks Minimizing emissions Maximizing yield Minimizing cost Minimizing cost assemble
following baseboard layout requirements should help processor signal integrity requirements reduce amount Simultaneous Switching Output (SSO) effects experienced. strongly recommended that baseboard stackup arranged such that AGTL+ signals referenced ground (VSS) plane, that AGTL+ signals traverse multiple signal layers. Deviating from either guideline create discontinuities signal's return path that lead large effects that degrade timing noise margin. Designing AGTL+ platform incorporating discontinuities will expose platform risk that very hard predict prelayout simulation. Figure shows ideal case where particular signal routed entirely within same signal layer, with ground layer single reference plane. Figure 5-5. Signal Layer Reference Plane
Signal Layer Ground Plane
A8144-01
When possible route entire AGTL+ signal single referenced layer, there methods reduce effects layer switches. best alternative allow signals change layers while staying referenced same plane (see Figure 5-6). Figure shows another method minimizing layer switch discontinuities, less effective than Figure 5-7. this case, signal still references same type reference plane (ground). such case, important connect ground planes together with vias vicinity signal transition via.
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Figure 5-6. Layer Switch with Reference Plane
Signal Layer Ground Plane
Signal Layer
A8145-01
Figure 5-7. Layer Switch with Multiple Reference Planes (same type)
Signal Layer
Ground Layer Layer Ground
Plane
Plane
Signal Layer
A8146-01
When routing stackup constraints require that AGTL+ signal reference multiple planes, special care must given minimize impact timing noise margin. best method reducing adverse effects high-frequency decoupling wherever transitions occur. Such decoupling should, again, vicinity signal transition capacitors with minimal effective series resistance (ESR) effective series inductance (ESL). When placing caps recommended space vias close possible and/or dual vias since inductance sometimes higher than actual capacitor inductance. Figure 5-8. Layer with Multiple Reference Planes
Signal Layer Ground Power
A8143-01
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Figure 5-9. Layer Switch with Multiple Reference Planes
Signal Layer Power Layer Layer Plane
Ground
Plane
Signal Layer
A8142-01
5.3.1.1
High Frequency Decoupling
This section contains several high frequency decoupling recommendations that will improve return path AGTL+ signal. These design recommendations will very likely reduce amount effects. Just layer switching multiple reference planes create discontinuities AGTL+ signal return path, discontinuities also occur when signal transitions between baseboard cartridge. Therefore, providing adequate high-frequency decoupling across CC_CORE ground interface baseboard will minimize discontinuity signal's reference plane this junction. Please note that these additional high-frequency decoupling capacitors addition high-frequency decoupling already processor. Transmission line geometry also influences return path reference plane. following decoupling recommendations that take this into consideration:
signal that transitions from stripline another stripline should have close proximity
decoupling between four reference planes.
signal that transitions from stripline microstrip vice versa) should have close
proximity decoupling between three reference planes.
signal that transitions from stripline microstrip through vias pins component
(Intel MCH, etc.) should have close proximity decoupling across involved reference planes ground device.
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Decoupling Guidelines PGA370 Designs
These decoupling guidelines PGA370 designs estimated meet VRM8.4 flexible motherboard requirements (VCC=1.6 ~18.4
5.4.1
VCC_CORE Decoupling Design
more capacitors 1206 packages.
capacitors should placed within PGA370 socket cavity mounted primary side motherboard. capacitors arranged minimize overall inductance between VCC_CORE/VSS power pins, shown Figure 5-10 below.
Figure 5-10. Capacitor Placement Motherboard
5.4.2
Decoupling Design
Decoupling guidelines: minimum capacitors 1206 package minimum 0603 package.
5.4.3
VREF Decoupling Design
Four capacitors 0603 package placed near VREF pins (within mils).
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
Thermal/EMI Differences
Heatsink requirements will different FC-PGA processors from previous processors using PPGA packaging. current flexible motherboard specification 256K FC-PGA Pentium processor calls 37.4
Increased power density Pentium processor (approximately 51.5 W/cm2) Different thermal design verification FC-PGA compared PPGA packaged processors.
Pentium processors specified using versus TCASE (used with Intel® Celeronprocessors). processors.
heatsink FC-PGA package which backwards compatible with PPGA heatsink clips FC-PGA processor heatsinks.
5.5.1
Debug Port Changes
lower voltage technology employed with FC-PGA Pentium processor, changes required support debug port. Previously, test access port (TAP) signals used logic. This case with Intel Celeron processor PPGA package. Pentium processor utilizes logic levels TAP. result, connector used flexible PGA370 designs. connector mirror image older connector. Either connector will into same printed circuit board layout. Just numbers would change, seen drawing below.
Figure 5-11. Connector Comparison
Connector, 104068-3 Vertical Plug, View
RESET#
Connector, 104078-4 Vertical Receptacle, View
RESET#
A8169-01
Caution:
FC-PGA Pentium processor requires in-target probe (ITP) with tolerant buffer. Previous ITPs designed work with higher voltages damage processor they connected FC-PGA Pentium processor. processor EMTS more information regarding debug port.
5-10
FC-PGA Intel® Pentium® Processor Chipset
Board Layout Routing Guidelines
SMI# Layout Guidelines
design assistance with reducing eliminating non-monotonic rising edge SMI# signal, refer simulated topologies UP/DP FC-PGA, shown Figure 5-12. Pentium processor SMI# erratum documented latest specification update erratum will fixed B-step silicon. Please refer Pentium processor specification update additional information steppings affected this anomaly.
Figure 5-12. Topology Simulated
Vcmos
CPUlen1 stub Chipset stub CSlen CPUlen2 CPU2 CPU1
A8170-01
Parameter stub stub CSlen CPUlen1 CPUlen2 0.25" 0.25" 0.25" 0.25"
Minimum 1.5" 1.5"
Maximum
simulations assume:
±10% motherboard manufacturing impedance 5:15 trace width spacing ratio
FC-PGA Intel® Pentium® Processor Chipset
5-11
Dual (FC-PGA) Intel® Pentium® Processors
This chapter discusses using FC-PGA Intel® Pentium® processor dual processor system design. Chapter discusses single processor design.
Two-Way FC-PGA Pentium® Processors Intel® Chipset Layout
Intel Pentium processor most powerful advanced member Intel's family processors. Intel chipset been designed provide high-performance memory, Advanced Graphics Port (AGP), subsystem support Intel processors interfacing SC242 connector FC-PGA Pentium processors. processors implement synchronous, latched protocol that allows full clock cycle signal transmission full clock cycle signal interpretation generation. This protocol simplifies interconnect timing requirements supports system designs using conventional interconnect technology. processor system operates using Assisted Gunning Transceiver Logic, AGTL+. This chapter provides information needed design dual FC-PGA Pentium processor (133 system bus) system using Intel chipset. This layout guideline does support designs using other chipsets. This section provides guidelines methodologies that used with good engineering practices. Pentium® Processor PGA370 Socket datasheet Intel chipset documents component-specific electrical details. Intel strongly recommends running analog simulations using available buffer models together with layout information extracted from your specific design. additional details, reference following documents:
Pentium® Processor PGA370 Socket datasheet (order
number 245264)
CK98 Clock Synthesizer/Driver Specification CK133 Clock Synthesizer/Driver Specification Pentium® Processor Developer's Manual (order number 243341)
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
Definition Terms
Table 6-1. Definition Terms (Sheet
Aggressor network that transmits coupled signal another network called aggressor network. processor system uses technology called AGTL+, Assisted Gunning Transceiver Logic. AGTL+ buffers open-drain require pull-up resistors providing high logic level termination. processor AGTL+ output buffers differ from GTL+ buffers with addition active pMOS pull-up transistor "assist" pull-up resistors during first clock low-to-high voltage transition. component group components that, when combined, represent single load AGTL+ bus. Describes component performs when parameters that could impact performance adjusted have same impact performance. Examples these parameters include variations manufacturing process, operating temperature, operating voltage. This results performance electronic component that change result corners include (but limited to): clock-to-output time, output driver edge rate, output drive current, input drive current. Discussion "slow" corner would mean having component operating slowest, weakest drive strength performance. Similar discussion "fast" corner would mean having component operating fastest, strongest drive strength performance. Operation simulation component slow corner fast corner expected bound extremes between slowest, weakest performance fastest, strongest performance. reception victim network signal imposed aggressor network(s) through inductive capacitive coupling between networks. Backward Cross-talk coupling that creates signal victim network that travels opposite direction aggressor's signal. Cross-talk Forward Cross-talk coupling that creates signal victim network that travels same direction aggressor's signal. Even Mode Cross-talk coupling from multiple aggressors when aggressors switch same direction that victim switching. Mode Cross-talk coupling from multiple aggressors when aggressors switch opposite direction that victim switching. term timing equation that includes signal propagation delay, effects system driver, plus adjustments signal receiver needed guarantee setup time receiver. More precisely, flight time defined time difference, between signal input receiving agent crossing VREF (adjusted meet receiver manufacturer's conditions required timing specification; i.e., ringback, etc.) output driving agent crossing VREF, driver driving TEST load used specify driver's timings. technology used Pentium processor. This incident wave switching, open-drain with pull-up resistors that provide both high logic level termination. enhancement (Gunning Transceiver Logic) technology. Pentium® Processor Developer's Manual more details GTL+. Multi-bit timing adjustment factor. This term accounts additional delay that occurs when multiple data bits switch same cycle. adjustment factor includes such mechanisms package crosstalk, high inductance current return paths, simultaneous switching noise. trace Printed Circuit Board (PCB) that completes electrical connection between more components. Distance between extreme agents network does include distance connecting agents termination resistors. voltage range, receiver, located above below VREF signal integrity analysis. Pentium® Processor Developer's Manual more details.
AGTL+
Agent
Corner
Flight Time
GTL+
MADJ
Network Network Length Overdrive Region
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
Table 6-1. Definition Terms (Sheet
Overshoot Ringback Maximum voltage allowed signal processor core pad. each processor's datasheet overshoot specification. feature logic package used connect package 370-pin FC-PGA socket. voltage that signal rings back after achieving maximum absolute value. Ringback reflections, driver oscillations, etc. each processor's datasheet ringback specifications. Defines maximum amount ringing receiving that signal must reach before next transition. each processor's datasheet settling limit specifications. time between beginning Setup Clock (TSU_MIN) arrival valid clock edge. This window different each type agent system. Refers difference electrical timing parameters degradation signal quality caused multiple signal outputs simultaneously switching voltage levels (e.g., high- tolow) opposite direction from single signal (e.g., low-to-high) same direction (e.g., high-to-low). These respectively called odd-mode switching evenmode switching. This simultaneous switching multiple outputs creates higher current swings that cause additional propagation delay "pushout"), decrease propagation delay "pull-in"). These effects impact setup and/or hold times always taken into account simulations. System timing budgets should include margin effects. branch from trunk terminating agent. Intel uses test load specifying components. main connection, excluding interconnect branches, terminating agent pads. Maximum voltage allowed signal extend below processor core pad. each processor's datasheet undershoot specifications. network that receives coupled cross-talk signal from another network called victim network. guardband (VREF) defined above below VREF provide more realistic model accounting noise such cross-talk, noise, VREF noise.
Settling Limit Setup Window
Simultaneous Switching Output (SSO) Effects
Stub Test Load Trunk Undershoot Victim VREF Guardband
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
6.2.1
AGTL+ Design Guideline
following step-by-step guideline developed systems based processor loads Intel load. guideline recommended this section based experience developed Intel while developing many different family (Pentium Pro, Pentium Pentium III) processor-based systems. Begin with initial timing analysis topology definition. Perform pre-layout analog simulations detailed picture working "solution space" design. These pre-layout simulations help define routing rules prior placement routing. After routing, extract interconnect database perform post-layout simulations refine timing signal integrity analysis. Validate analog simulations when actual systems become available. validation section describes method determining flight time actual system. Begin with initial timing analysis topology definition. Perform pre-layout analog simulation detailed picture working "solution space" design. These pre-layout simulations help define routing rules prior placement routing. After routing, extract interconnect database perform post-layout simulations refine timing signal integrity analysis. Validate analog simulations when actual systems become available. validation section describes method determining flight time actual system. Guideline Methodology:
Initial timing analysis Determine general topology, layout, routing Pre-layout simulation
Sensitivity sweep Monte Carlo analysis
Place route board
Estimate component-to-component spacing AGTL+ signals Layout route board
Post-layout simulation
Interconnect extraction Inter-symbol interference (ISI), cross-talk, Monte Carlo analysis
Validation
Measurements Determining flight time
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
6.2.2
Initial Timing Analysis
Intel highly recommends performing simulations part board design process. This includes pre-layout simulations provide passing robust solution space. post-layout simulations based extracted board layout verify that layout meets timing noise requirements. Simulations required designs that deviate from recommended layout guidelines. Table lists AGTL+ component timings processors Intel defined pins. These timings reference only; obtain processor chipset component specifications from datasheets.
Table 6-2. AGTL+ Component Timings
Parameters Clock Output maximum (TCO_MAX) Clock Output minimum (TCO_MIN) Setup time (TSU_MIN) Hold time (THOLD) Intel® Pentium® Processor (FC-PGA) Core 3.25 0.95 Intel® 3.00 0.25 1.85 0.60 Notes
NOTES: Numbers table reference only. These timing parameters subject change. Please check appropriate component documentation valid timing parameter values. TSU_MIN 1.85 assumes Intel sees minimum edge rate equal V/ns.
Table Table show recommended setup hold margin timing budget system supporting two-way FC-PGA Pentium processor operation with Intel chipset. recommended topologies should support maximum minimum flight times suggested these tables. processor chipset timing values used these tables reference only should taken from latest component datasheet. maximum minimum flight times suggested this topology make certain assumptions described below. deviations from these assumptions must analyzed verify that recommended topology flight times still valid. These flight times also assume that component AGTL+ signal quality requirements derated properly. appropriate component documentation more details. These timing tables make assumptions about clock skew jitter meant clock-specific; e.g., clock driver skew minimized ganging outputs together clock driver device that supports this operation. Clock skew jitter values dependent components clock distribution method chosen particular design must budgeted into these timing equations appropriate each design. Note that MADJ factor accounts multi-bit switching effects that worsen flight time and/or signal quality always seen simulation. This factor highly dependent high-speed design practices implemented baseboard (e.g., decoupling, signal return paths) should budgeted accordingly each design.
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
following timing equations were used calculate minimum maximum flight times: Processor driving: TFLT_MAX Period TCO_MAX TSU_MIN CLKSKEW CLKJITTER MADJ CLKSHFT TFLT_MIN THOLD CLKSKEW TCO_MIN MADJ CLKSHFT Chipset driving: TFLT_MAX Period TCO_MAX TSU_MIN CLKSKEW CLKJITTER MADJ CLKSHFT TFLT_MIN THOLD CLKSKEW TCO_MIN MADJ CLKSHFT Table gives example AGTL+ initial maximum flight time Table gives example minimum flight time calculation MHz, two-way FC-PGA Pentium processor Intel chipset system bus. Note that assumed values clock skew clock jitter used. Note: Clock skew clock jitter values dependent clock components distribution method chosen particular design must budgeted into initial timing equations appropriate each design. Table Table assume:
CLKSKEW 0.15 CLKJITTER 0.25 CLKSHIFT 0.26
Note: These values derived from assumption that three host clocks tied together (ganged), resulting pin-to-pin skew clock driver output pins. clock routing skew assumed System timing budget must assume 0.175 clock driver skew output tied together clock driver that meets CK98W/S CK133 Clock Synthesizer/Driver Specification being used. Some clock driver components support ganging outputs together. sure verify with your clock component vendor before ganging outputs. respective processor's datasheet, appropriate Intel chipset documentation, CK133 Clock Synthesizer/Driver Specification details clock skew jitter specifications. Exact details host clock routing topology still under investigation will documented future release this document. CK98W/S specification, with tighter clock jitter 0.150 also available designs that need tighter control jitter.
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
Table 6-3. Example TFLT_MAX Calculations Bus1
Driver Receiver Period2 TCO_MAX TSU_MIN CLKSKEW CLKJITTER CLKSHIFT MADJ Recommended TFLT_MAX3
Processor Processor
Processor Processor
3.25 3.25 3.00
0.95 1.85 0.95
0.15 0.15 0.15
0.25 0.25 0.25
0.26 0.26
0.40 0.40 0.40
1.86 2.49
NOTES: times nanoseconds. BCLK period MHz. flight times this column include margin account following phenomena that Intel observed when multiple bits switching simultaneously. These multi-bit effects adversely affect flight time signal quality sometimes accounted simulation. Accordingly, maximum flight times depend baseboard design additional adjustment factors margins recommended. push-out pull-in. Rising falling edge rate degradation receiver caused inductance current return path, requiring extrapolation that causes additional delay. Cross-talk internal package cause variation signals.
There additional effects that necessarily covered multi-bit adjustment factor should budgeted appropriate baseboard design. Examples include effective board propagation constant (SEFF), which function
Dielectric constant material. trace type connecting components (stripline microstrip). length trace load components trace. Note that board
propagation constant multiplied trace length component flight time necessarily equal flight time. Table 6-4. Example TFLT_MIN Calculations (Frequency Independent)
Driver Processor Processor Receiver Processor Processor THOLD 0.60 CLKSKEW 0.15 0.15 0.15 TCO_MIN 0.25 CLKSHIFT 0.26 0.26 Recommended TFLT_MIN 0.75 0.61 0.64
NOTE: times nanoseconds.
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
6.2.3
Dual Processor General Topology
Table below provides segment descriptions length recommendations simulated topology shown Figure 6-1. Segment lengths defined pins devices components. signal routing assumes four-signal layer (six eight-layer motherboard) form factor platform. dual processor FC-PGA/Intel chipset designs, termination device must placed unused socket when only processor populated. ensure signal integrity requirements, required that system signal segments (CPUlen, CSlen) referenced ground plane entire route. multiple ground plane references used, then ground planes should stitched together with vias between ground planes.
Figure 6-1. Intel® Pentium® Processor Dual Processor Configuration
Chipset
CPUlen
CPUlen
CSlen
Chipset
A8171-01
Table 6-5. Segment Descriptions Lengths Figure
Parameter CPUlen CSlen length (inches) 2.75 2.25 length (inches) 3.75 2.75
simulations assume following:
maintained VREF maintained Motherboard impedance, Signal propagation delay between 1.93 ns/ft 2.057 ns/ft baseboard dielectric constant, tracewidth-to-spacing ration 5:15 stub length same must matched with 0.25" processor
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
6.2.4
Cross-talk Routing Guidelines
ensure adequate levels cross-talk, follow these trace width spacing recommendations baseboard:
Intragroup AGTL+ Intergroup AGTL+ AGTL+ non-AGTL+ 5:15 5:15 5:20 6:24
Intragroup AGTL+ refers AGTL+ signals same group. Intergroup AGTL+ refers AGTL+ signals different groups. signal listing AGTL+ groups, Section Pentium® Family Developer's Manual, Volume example non-AGTL+ signal CMOS.
Processor Overshoot/Undershoot Limits
FC-PGA Pentium processor, maximum absolute overshoot voltage limit been increased from 2.18 However, this value still based very preliminary studies subject change. Refer processor datasheet more information overshoot specifications. There also time dependent, non-linear overshoot undershoot requirement that dependent amplitude duration overshoot/undershoot. deviations from layout guidelines recommended this chapter require additional overshoot/undershoot verification order ensure that these specifications met.
Wired-OR Signals
There "wired-OR" AGTL+ signals that driven more than agent simultaneously. When signal asserted (driven electrically low) agents same clock edge, falling wave fronts will meet some point bus. This create large undershoot ringback. special attention during layout validation these signals prevent signal quality violations. signals AERR#, BERR#, BINIT#, BNR#, HIT#, HITM#.
Signal Return Path Considerations
Adequate signal return path very important maintaining signal quality timing margin high-speed such AGTL+. Failure address these effects result excessive signal flight time push-out, overshoot/undershoot, ringback violations. best maintain high-speed signal return path reference single ground plane (preferred) single power plane that continuous entire length signal route. Avoid routing layer switches multiple reference planes these create discontinuities signal return path. When routing layer switches unavoidable, minimize possible adverse effects return path making sure signal still references either same plane same type reference plane. When layer switch occurs where signal references same type plane located another layer, then vias should inserted immediate vicinity layer switch allow return current traverse from plane another. When layer switch occurs where signal references different type plane located another layer, then place fast-response decoupling capacitors immediate
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
vicinity layer switch. Fast-response decoupling caps should also placed immediate vicinity partial plane breaks when being used signal's reference plane. Ideally, signal should have reference plane breaks cutting across entire signal path. additional details return path considerations, refer "Power Distribution" page 5-5.
Intel Pentium Processor (FC-PGA) Pull-Up Values
Table documents pull-up resistor values Pentium processor signals design should used guideline. specific value should calculated each design. twoway system, dual pull-ups required each PICD[1:0] signals, should placed near extreme ends trace. Pull-up resistors CMOS outputs should near CPU. dual processor designs, terminate PICD[1:0] signals trace.
Table 6-6. Pull-Up Values
Signal BSEL[1:0] FERR# A20M# IGNNE# LINT0/INTR LINT1/NMI Resistor1 Signal STPCLK# INIT# PREQ# PICD[1:0] PWRGOOD
Resistor1 200-330 300-330 150-330
NOTE: Unless noted, signals listed should pulled-up BSEL[1:0] must pulled PWRGOOD must pulled-up
6-10
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
6.7.1
APIC CMOS
Two-way FC-PGA Intel Chipset APIC Layout Guidelines
Figure shows layout guidelines two-way Pentium processor 256K FC-PGA systems based Intel chipset. These guidelines still preliminary, simulations suggest that this daisy-chain, dual-ended termination topology corresponding segment lengths will support timing signal quality requirements 16.67 frequency. Intel recommends APIC CMOS simulation good layout practices.
Figure 6-2. PICD[1:0] Two-way Topology
VCC_CMOS
FC-PGA
VCC_CMOS
FC-PGA
Note: denotes component
P64H
A7580-01
Table 6-7. PICD[1:0] Two-way Topology Segment Lengths
Length inches) 0.25 inches) 19.5
FC-PGA Intel® Pentium® Processor Chipset
6-11
Dual (FC-PGA) Intel® Pentium® Processors
Processor THERMTRIP# Connection
PGA370 socket design implements following connection THERMTRIP# between processors. Platform designs that THERMTRIP# sensing leave processor THERMTRIP# pins unconnected. corresponding THRM# must pulled-up resistor. THRM# must connected processor's THERMTRIP# pins directly.
BSEL[1:0] Implementation
Pentium processor utilizes BSEL1 select either host frequency setting from clock synthesizer. While BSEL0 signal still connected PGA370 socket, Pentium processor does utilize Only Intel® Celeronprocessor utilizes BSEL0 signal. Pentium processors tolerant these signals, chipset. clock synthesizer been designed support selections MHz. input been redefined frequency selection strap (BSEL1) during power-on then becomes reference clock output. Figure details BSEL[1:0] circuit design flexible PGA370 designs. Note: BSEL[1:0] pulled using resistors.
Figure 6-3. BSEL[1:0] Circuit Implementation PGA370 Designs
Processor
BSEL0 BSEL1
Processor
BSEL0
BSEL1
REFCLK
CK133
SEL0
SEL1
LMD29
LMD13
A7579-01
6-12
FC-PGA Intel® Pentium® Processor Chipset
Dual (FC-PGA) Intel® Pentium® Processors
6.10
CLKREF Circuit Implementation
CLKREF input requires 1.25 source. generated from voltage divider VCC2.5 VCC3.3 sources utilizing tolerance resistors. decoupling capacitor should included this input. Figure Figure example CLKREF circuits. source this reference!
Figure 6-4. Examples CLKREF Divider Circuit
VCC2.5
Processor
CLKREF
VCC3.3
Processor
CLKREF
A7578-01
Table 6-8. Resistor Values CLKREF Divider (3.3V Source)
CLKREF Voltage 1.243 1.243 1.226 1.242
6.11
6.11.1
On-die Considerations
Connecting RESET# Dual Processor PGA370 Designs
dual processor PGA370-processor designs, route AGTL+ signal from chipset RESET# (AH4) processor well connector. RESET2# (X4) provided backwards compatibility only, should connected ground. Finally, AGTL+ reset signal must always terminated motherboard. Figure 6-5.
FC-PGA Intel® Pentium® Processor Chipset
6-13
Dual (FC-PGA) Intel® Pentium® Processors
6.11.2
AGTL+ Reset Layout Topology
Figure 6-5. AGTL+ Reset Schematic PGA370 Designs
RESET# RESET2#
RESET#
Connector
Processor
RESET#
RESET# RESET2#
Processor
A7630-01
6-14
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
This chapter discusses using FC-PGA Intel® Pentium® processor single processor system design. Chapter discusses dual processor design.
One-Way FC-PGA Pentium® Processors Intel® Chipset Layout
Intel Pentium processor most powerful advanced member Intel's family processors. Intel chipset been designed provide high-performance memory, Accelerated Graphics Port (AGP), subsystem support Intel Pentium processors. Pentium processor implements synchronous, latched protocol that allows full clock cycle signal transmission full clock cycle signal interpretation generation. This protocol simplifies interconnect timing requirements supports system designs using conventional interconnect technology. processor system operates using Assisted Gunning Transceiver Logic (AGTL+). goal this chapter provide information needed design uniprocessor systems with Intel chipset. This layout guideline does support designs using other chipsets. This chapter provides guidelines methodologies that used with good engineering practices. Pentium® Processor PGA370 Socket datasheet (order number 245264) Intel Chipset component datasheets specific electrical details. Intel strongly recommends running analog simulations using available buffer models together with layout information extracted from your specific design.
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
Definition Terms
Table 7-1. Definition Terms (Sheet
Aggressor network that transmits coupled signal another network called aggressor network. processor system uses technology called AGTL+, Assisted Gunning Transceiver Logic. AGTL+ buffers open-drain require pull-up resistors providing high logic level termination. processor AGTL+ output buffers differ from GTL+ buffers with addition active pMOS pull-up transistor "assist" pull-up resistors during first clock low-to-high voltage transition. component group components that, when combined, represent single load AGTL+ bus. Clock timing offset between chipset CPU, used maximize timing margins. Describes component performs when parameters that could impact performance adjusted have same impact performance. Examples these parameters include variations manufacturing process, operating temperature, operating voltage. This results performance electronic component that change result corners include (but limited to): clock output time, output driver edge rate, output drive current, input drive current. Discussion "slow" corner would mean having component operating slowest, weakest drive strength performance. Similar discussion "fast" corner would mean having component operating fastest, strongest drive strength performance. Operation simulation component slow corner fast corner expected bound extremes between slowest, weakest performance fastest, strongest performance. reception victim network signal imposed aggressor network(s) through inductive capacitive coupling between networks. Backward Cross-talk coupling which creates signal victim network that travels opposite direction aggressor's signal. Cross-talk Forward Cross-talk coupling which creates signal victim network that travels same direction aggressor's signal. Even Mode Cross-talk coupling from multiple aggressors when aggressors switch same direction that victim switching. Mode Cross-talk coupling from multiple aggressors when aggressors switch opposite direction that victim switching. term timing equation that includes signal propagation delay, effects system driver, adjustments signal receiver needed guarantee setup time receiver. More precisely, flight time defined time difference, between signal input receiving agent crossing VREF (adjusted meet receiver manufacturer's conditions required timing specification; i.e., ringback, etc.) output driving agent crossing VREF, driver driving TEST load used specify driver's timings. technology used Pentium® processor. This incident wave switching, open-drain with pull-up resistors that provide both high logic level termination. enhancement Gunning Transceiver Logic) technology. Pentium® Processor Developer's Manual more details GTL+. Multi-bit timing adjustment factor. This term accounts additional delay that occurs when multiple data bits switch same cycle. adjustment factor includes such mechanisms package crosstalk, high inductance current return paths, simultaneous switching noise. trace printed circuit board (PCB) that completes electrical connection between more components. Distance between extreme agents network, including distance connecting agents termination resistors.
AGTL+
Agent CLKSHIFT
Corner
Flight Time
GTL+
MADJ
Network Network Length
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
Table 7-1. Definition Terms (Sheet
Overdrive Region Overshoot Ringback Voltage Settling Limit Setup Window voltage range, receiver, located above below VREF signal integrity analysis. Pentium® Processor Developer's Manual more details. Maximum voltage allowed signal processor core pad. processor's datasheet overshoot specification. feature logic package used connect package 370-pin FC-PGA socket. voltage that signal rings back during rising falling edge. Ringback reflections, driver oscillations, etc. each processor's datasheet ringback specifications. Defines maximum amount ringing receiving that signal must reach before next transition. respective processor's datasheet settling limit specifications. time between beginning Setup Clock (TSU_MIN) arrival valid clock edge. This window different each type agent system. Refers difference electrical timing parameters degradation signal quality caused multiple signal outputs simultaneously switching voltage levels opposite direction from single signal (e.g., low-to-high) same direction (e.g., high-to-low). These respectively called odd-mode switching even-mode switching. This simultaneous switching multiple outputs creates higher current swings that cause additional propagation delay "pushout"), decrease propagation delay "pullin"). These effects impact setup and/or hold times always taken into account simulations. System timing budgets should include margin effects. branch from trunk terminating agent. Intel uses test load specifying components. main connection, excluding interconnect branches, terminating agent pads. Maximum voltage allowed signal extend below processor core pad. each processor's datasheet undershoot specifications. network that receives coupled cross-talk signal from another network called victim network. guardband (VREF) defined above below VREF provide more realistic model accounting noise such cross-talk, noise, VREF noise.
Simultaneous Switching Output (SSO) Effects
Stub Test Load Trunk Undershoot Victim VREF Guardband
AGTL+ Design Methodology
guideline recommended this document based experience Intel developing many different family (Pentium Pro, Pentium Pentium III) processor-based systems. Begin with initial timing analysis topology definition. Perform pre-layout analog simulation detailed picture working "solution space" design. These pre-layout simulations help define routing rules prior placement routing. After routing, extract interconnect database perform post-layout simulations refine timing signal integrity analysis. Validate analog simulations when actual systems become available. validation section (see Appendix describes method determining flight time actual system.
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
Guideline Methodology:
Initial timing analysis Determine general topology, layout, routing Pre-Layout Simulation
Sensitivity sweep Monte Carlo analysis
Place route board
Estimate component-to-component spacing AGTL+ Signals Layout route board
Post-layout simulation
Interconnect extraction Inter-symbol interference (ISI), cross-talk, Monte Carlo analysis Verify BCLK skew meets design specifications
Validation
Measurements Determining flight time
Initial Timing Analysis
Intel highly recommends performing simulations part board design process. This includes pre-layout simulations define passing robust solution space. Intel also recommends running post-layout simulations based extracted board layout verify that layout meets timing noise requirements. Simulations required designs that deviate from recommended layout guidelines. Table lists AGTL+ component timings Pentium processor Intel defined pins. These timings reference only; obtain each component's specifications from datasheet.
Table 7-2. AGTL+ Component Timings
Parameters Clock Output maximum (TCO_MAX) Clock Output minimum (TCO_MIN) Setup time (TSU_MIN) Hold time (THOLD) Intel® Pentium® Processor Processor System Frequency 3.25 0.95 Intel® Notes
3.00 0.25 1.85 0.60
NOTES: Numbers table reference only subject change. Please check appropriate component documentation current timing parameter values. TSU_MIN 1.85 assumes Intel sees minimum edge rate equal V/ns.
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
Table gives example AGTL+ initial maximum flight time Table gives example minimum flight time calculation MHz, FC-PGA Pentium processor/Intel chipset system bus. Table Table show recommended setup hold margin timing budget system supporting FC-PGA Pentium processor operation with Intel chipset. recommended topologies should support maximum minimum flight times suggested these tables. processor chipset timing values used these tables reference only should taken from latest component datasheet. maximum minimum flight times suggested this topology make certain assumptions described below. deviations from these assumptions must analyzed verify that recommended topology flight times still valid. These flight times also assume that component AGTL+ signal quality requirements derated properly.
timing tables make assumptions about clock skew jitter meant
clock-specific (e.g., clock driver skew minimized ganging outputs together clock driver device that supports this operation). Clock skew jitter values dependent components clock distribution method chosen particular design must budgeted into these timing equations appropriate each design.
System timing budget must assume 0.175 clock driver skew outputs tied
together clock driver that meets CK98W/S CK133 Clock Synthesizer/Driver Specification being used. sure verify with your clock component vendor that ganging together clock outputs supported. respective processor's datasheet, appropriate Intel chipset documentation, CK133 clock synthesizer/driver documentation details clock skew jitter specifications. Refer Chapter "Clocking."
MADJ factor accounts multi-bit switching effects that worsen flight time
signal quality always seen simulation. This factor highly dependent high-speed design practices implemented baseboard (e.g., decoupling, signal return paths) should budgeted accordingly each design. There additional effects that necessarily covered multi-bit adjustment factor (MADJ) should budgeted appropriate baseboard design. Examples include effective board propagation constant (SEFF), which function Dielectric constant material trace type connecting components (stripline microstrip) length trace load components trace. board propagation constant multiplied trace length component flight time necessarily equal flight time.
Table 7-3. Example TFLT_MAX Calculations Bus1
Driver Receiver Period2 TCO_MAX TSU_MIN CLKSKEW CLKJITTER CLKSHIFT MADJ Recommended TFLT_MAX3
Processor
Processor
3.25 3.00
1.85 0.95
0.15 0.15
0.25 0.25
0.26 0.26
0.40 0.40
1.86 2.49
NOTES: times nanoseconds. BCLK period MHz. flight times this column include margin account timing degradation multi-bit adjustment factor (MADJ). following factors influence MADJ factor: timing push-out pull-in Rising falling edge rate degradation receiver caused inductance current return path Cross-talk internal chipset packages
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
Table 7-4. Example TFLT_MIN Calculations (Frequency Independent)
Driver Processor Receiver Processor THOLD 0.60 CLKSKEW 0.15 0.15 TCO_MIN 0.25 CLKSHIFT 0.26 0.26 Recommended TFLT_MIN 0.61 0.64
NOTE: times nanoseconds.
7.4.1
Flight Time Calculation
following timing equations were used calculate minimum maximum flight times: Processor driving: TFLT_MAX Period TCO_MAX TSU_MIN CLKSKEW CLKJITTER MADJ CLKSHFT TFLT_MIN THOLD CLKSKEW TCO_MIN MADJ CLKSHFT Chipset driving: TFLT_MAX Period TCO_MAX TSU_MIN CLKSKEW CLKJITTER MADJ CLKSHFT TFLT_MIN THOLD CLKSKEW TCO_MIN MADJ CLKSHFT
General Topology
Segment descriptions length recommendations provided below simulated topology shown Figure 7-1. Segment lengths defined pins devices components. signal routing assumes four-signal layer (six eight-layer motherboard) form factor platform. uniprocessor FC-PGA/Intel chipset designs, termination resistor required chipset. satisfy signal integrity requirements, required that system signal segments (MB_LEN, CS_STUB, CS_LEN) referenced ground plane entire route. multiple ground plane references used, then ground planes should stitched together with vias between ground planes.
Figure 7-1. Uniprocessor Topology Processor System Frequency
CS_RTT
MB_LEN
CS_LEN
CS_STUB
A7838-01
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
chipset distance minimum maximum calculated using Table 7-5. requirement keep CS_RTT located close chipset follow topology, shown Figure 7-1. Table 7-5. Recommendations
Parameter CS_RTT CS_LEN CS_STUB MB_LEN CPURTT simulations assume following: maintained VREF maintained Motherboard impedance, Signal propagation delay between 1.93 ns/ft 2.057 ns/ft baseboard dielectric constant, 3.7-4.7 tracewidth-to-spacing ratio 5:15 (i.e., trace with space) 0.2" 5.25" 0.5" 6.25" Comments Terminator Resistor Value Recommended: Terminator Resistor Stub Resistor Stub ball point On-die nominal processor
Changes Signal Connectivity Uniprocessor Systems
Four signals implemented differently uniprocessor systems, shown Table 7-6. other signals defined Table 19-2 page 19-12.
Table 7-6. Signal Differences Uniprocessor Intel® Chipset Systems
BREQ0# BREQ1# RESET# Comments Connect Connect pull-up VTT. Connect MCH. (Optional Debug) series resistor ITP. RTT_CTRL input signal provides AGTL+ termination control. uniprocessor implementations, both on-die on-board termination required. Placing resistor RTT_CTRL ground will appropriate on-die value uniprocessor topology.
RTT_CTRL
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
Connecting RESET# Uniprocessor PGA370 Designs
Route AGTL+ signal from chipset RESET# (AH4) processor well connector. RESET2# (X4) provided backwards compatibility only, should connected ground. Finally, AGTL+ reset signal must always terminated (using pull-up resistor.) motherboard. Figure 7-2.
Figure 7-2. Uniprocessor Reset Topology
RTT_STUB
Chipset
RESET#
MB_LEN
CPU_STUB
Processor
RESET# RESET2#
ITP_STUB
Connector
A7833-01
Parameter MB_LEN (chipset point) CPU_STUB RTT_STUB ITP_STUB
(inches) 5.25
(inches) 6.25
FC-PGA Intel® Pentium® Processor Chipset
Single (FC-PGA) Intel® Pentium® Processors
SMI# Layout Guidelines
design assistance with reducing eliminating non-monotonic rising edge SMI# signal, refer simulated topologies shown Figure 7-3. Pentium processor SMI# erratum documented latest specification update. Please refer specification update additional information steppings affected.
Figure 7-3. Uniprocessor SMI# Topology
VCC_CMOS RTT_STUB
SMI#
CS_STUB
MB_LEN AJ35
Processor
SMI#
CTT_STUB
A7832-01
Parameter CS_STUB RTT_STUB CTT_STUB MB_LEN (CPU point)
(inches)
(inches) 20.0
Comments point point termination resistor point termination Series resistor
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
perfect matching transmission line impedance uniform trace length essential Direct RDRAM interface work properly. Maintaining (+/- 10%) loaded impedance every (Rambus* Signaling Level) signal requires some changes standard trace width board prepreg thickness. Typically, achieving nominal impedance with prepreg requires mil-wide traces. mils-wide traces wide break rows signals 82840 MCH. order reduce trace width, prepreg required. This thinner prepreg allows wide traces meet (+/- 10%) nominal impedance requirement. Refer Figure Figure board stackup details. signals RDRAM Channels broken into three groups: RSL, CMOS Clock signals, shown Table 8-1. Table 8-1. RDRAM Channel Signal Groups
Signals DQA[8:0] DQB[8:0] RQ[7:0] CCTM# CFM#
CMOS Signals
Clock Signals
Denotes high speed CMOS signals.
Characterization understanding trace impedance critical delivering reliable systems increased frequencies. Incorporating test coupon design into motherboard makes testing simpler more accurate. test coupon pattern must match probe type being used. Providing test coupon memory section will provide greatest accuracy, board impedance varies with location. location test coupon listed order preference below: First Choice (Ideal Location) Second Choice Third Choice Memory section motherboard section motherboard Separate location panel
Intel Impedance Test Methodology Document should used ensure that boards within requirement. Intel Controlled Impedance Design Test Document should used test coupon design implementation. These documents found (select "Application Notes")
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
Memory Design with MEC/MECC (Outer Layer Routing)
Memory Expansion Card (MEC) concept intended provide flexibility scalability memory Intel® chipset-based platform. Intel chipset supports both RIMMs down MECC configurations. Additional details will published future revisions this document. Figure illustrates connection MCH.
Figure 8-1. MECC Layout (Outer Layer Routing)
4.0" 4.5"
A8174-01
signals between 82840 MECC should maintained between 4.0" (min) 4.5" (max). Although channels required match another, difference between channels should minimized must meet levelization requirements. order maintain trace impedance, signals must nominally wide. exact width determined board stack-up. control crosstalk odd/even mode velocity deltas, there must ground isolation trace between adjacent signals. ground isolation traces must connected ground with every 0.5". required between signals ground isolation traces. ensure uniform traces, trace width variation must uniform signals every neck down. signals within each channel must length matched mils line section between first device (MRH-R) using trace length matching methods. Also, signals must have same number vias. necessary place additional vias (dummy vias) signals, even vias needed, meet loading requirement (equal number vias).
RIMMs Motherboard
following RDRAM layout guidelines applicable outer-layer routing each channel. Additional layout guidelines will available future releases this design guide.
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
8.2.1
Signals
signals enter first RIMM left side, propagate through RIMM, then exit right. signal continues through rest existing RIMMs until terminated VTERM. unpopulated slot must have continuity modules place ensure that signals propagate termination. Refer following site more information regarding Direct Rambus* technology: http://www.rambus.com
Figure 8-2. Routing Dimension RIMMs
Termination First RIMM RIMM RIMM RIMM Termination
A8175-01
With Intel MCH, possible achieve longer trace length (MCH first RIMM connector) RIMMs-per-RDRAM channel implementation. Although channels minimized required match another, difference between channels should minimized must meet levelization requirements, shown Table 8-2. Table 8-2. Routing Trace Lengths
Reference Section Trace Description first RIMM connector (Microstrip) first RIMM connector (Stripline) RIMM connector RIMM connector RIMM Termination Trace Length 3.75" 0.4" 0.45"
order maintain nominal trace impedance, signals must mils wide. control crosstalk odd/even mode velocity deltas, there must ground isolation trace between adjacent signals through sections "A," "C". ground isolation traces must connected ground with every 0.5". required between signals ground isolation trace. ensure uniform trace lines, trace width variation must uniform signals every neck-down each line section. signals within each channel must length matched mils line sections labelled mils both line sections labeled using trace length matching methods described next section. Also, signals must have same number vias. necessary place additional
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
vias (dummy vias) certain signals, even vias needed, meet loading requirement (equal number vias). There trace length matching requirement traces section "C". Figure 8-3. Example Routing Diagram
Space Space Space Space
Signal Trace
Ground
Signal Trace
Ground
A8176-01
8.2.2
Signal Layer Alternation
signals must alternate layers they routed through channel. example, signal routed primary side from first RIMM socket must routed secondary side from first RIMM second RIMM (signal When signal routed secondary layer from first RIMM socket, must then routed primary side from first RIMM second (signal Signals routed either layer from last RIMM termination resistors. Figure Table 8-3.
Figure 8-4. Signal Layer Alternation
82840
Signal Signal
routed either layer. Ground isolation REQUIRED!
Notes: Signal Secondary Side Signal Primary Side
A8177-01
FC-PGA Intel® Pentium® Processor Chipset
Termination
Memory Interface
Table 8-3. Signal Layer Alteration
First RIMM Primary Side Secondary Side First RIMM Second RIMM Secondary Side Primary Side
8.2.3
Signal Termination
signals must terminated (VTERM) using resistors channel opposite MCH. Resistor packs acceptable. VTERM must decoupled using very high-speed bypass capacitors (one ceramic chip capacitor lines) near terminating resistors. Additionally, bulk capacitance required. Assuming linear regulator with approximate response time, tantalum other capacitors recommended. capacitors should minimum vias each connection ground layer. trace length between last RIMM termination resistors should less than Length matching this section channel required. VTERM power island should least mils wide. This voltage required during Suspend-to-RAM (STR).
Figure 8-5. Direct RDRAM Termination
Terminator R-packs
Signals
Vterm
A8178-01
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
Figure 8-6. Rambus Termination Example
necessary compensate electrical characteristic difference between "dummy" "real" vias. Refer "Via Compensation" page 8-12 more details.
8.2.4
RDRAM Connector Compensation
RIMM connector inductance causes impedance discontinuity Rambus* channel. This reduce voltage timing margin. order compensate inductance connector, approximately 0.65 pF-0.85 compensating capacitive (C-TAB) required each connector pin. This compensating capacitance must added following connector pins each connector: LCLCTM# RCRCTM# LCFM LCFM# RCFM RCFMRE LRQ[7:0] RRQ[7:0] RDQA[8:0] LDQA[8:0] RDQB[8:0] LDQB[8:0]
FC-PGA Intel® Pentium® Processor Chipset
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This achieved motherboard adding copper specified pins each connector. target value approximately 0.65 pF-0.85 copper area recommended stackup determined through simulation. placement copper tabs signal layer, independent layer which signal routed. Equation approximation that used calculating copper area outer layer. Equation 8-1. Length*Width Area Cplate Thickness prepreg [(0) (r)] (1.1)
Cplate Capacitance plates 2.25 10-16 F/mil Relative dielectric constant prepreg material Thickness prepreg Stackup dependent Length, Width Dimensions mils copper plate added Factor accounts fringe capacitance
Based stackup requirement outlined Intel® Chipset Platform Design Guide, copper area should 2800 3600 mils. Different stackups require different copper area. Table shows suggested copper area: Table 8-4. Copper Area Calculation
Dielectric Thickness Separation Between Signal Traces Copper Minimum Ground Flood between Signal Flood Compensating Capacitance Cplate (pF) 0.65 CTAB Area mils CTAB Shape
2800
Based Equation 8-1, area 2800 mils, where 4.5. These values based 2116 prepreg material. Note that more than copper shape used shown Figure 8-7. dimensions based copper area over ground plane. actual length width tabs different routing constraints (e.g., must extend center hole anti-pad); however each copper should have equivalent area. copper tabs Figure Figure have following dimensions: Inner CTAB (CA)= (length) (width) Outer CTAB (CB)= (length) (width) following figures show routing example compensation capacitors. Note that ground floods around RIMM pins must interrupted capacitor tabs, they must connected avoid discontinuity ground plane shown. Also, compensating capacitive tabs (C-TAB) required connector pins signals.
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
Figure 8-7. C-Tab Example, Layer
Inner C-tab
Outer C-tab
*Ground floods were removed picture clarity.
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
Figure 8-8. C-Tab Example, Bottom Layer
*Ground floods were removed picture clarity.
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
Figure 8-9. Close-up C-TABs
Inner C-TAB Outer C-TAB Fill Signal
8.2.5
Direct RDRAM Ground Plane Reference
ground reference island under signals must continuous from last RIMM back termination capacitors resistors. return current flows through VTERM capacitors into ground island under traces. split ground island will cause sub-optimal return path, resulting impedance variation. four-layer board, this requires VTERM island outer layer. VTERM island should always placed layer shown Figure 8-6.
8.2.6
Length Matching Method
Package dimension (LPKG): representation length from ball. Board trace length (LMB): trace length board. Nominal length: length which signals matched. Nominal length arbitrary value which signals will matched (within mils). LPKG Package dimension LPCB Board trace length
8-10
FC-PGA Intel® Pentium® Processor Chipset
Memory Interface
Figure 8-10. RDRAM Trace Length Matching Example
Intel® 82840 Package 82840 ball
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allow greater routing flexibility, signals require pad-to-pin length matching between 82840 first RIMM connector 82840 MECC. When only trace lengths between balls 82840 pins RIMM connector matched, length mismatch between die) ball been compensated. signals, channel, required have matching trace lengths from pad-to-pin within mils.
8.2.6.1
Signals Length Match Requirement
must length matched within mils.
8.2.6.2
Compensated Trace Length Calculation
LPCB (LPKG Package TRACE VELOCITY) PCBTRACE VELOCITY trace length each signal calculated value vary with designs. actual package trace velocity between ps/in ps/in. nominal trace velocity ps/in used when calculating compensated trace length. PCBTRACE VELOCITY board-dependent. signal lengths (LPKG) normalized either shortest longest trace using equation next section. Please refer RS-Intel® Chipset Ballout Mechanical document specific package traces. Note that this ballout document provides signal lengths NORMALIZED LONGEST trace length. Additional length matching with MRH-R available Intel Chipset: Workstation/Server Design Guide.
8.2.6.3
Normalized Trace Length Calculation
LPKG LPKG LNORMALIZED RDRAM clocks (CTM, CTM#, CFM#) must longer than RDRAM signals their increased trace velocity (because they differential routed pair). calculate length each clock, following formula should used:
FC-PGA Intel® Pentium® Processor Chipset
8-11
Memory Interface
Clock Length Nominal Signal Length (package board)* 1.021 lengthening clock signals, compensate their trace velocity change, applies only routing between first RIMM. clock signals should matched length signals between RIMMs. necessary account CMOS signals package compensation. routing, mismatch between CMOS signals (CMD, SCK) signals should minimized; i.e., route CMOS signals trace length equal nominal trace length.
8.2.7
Compensation
signals must have same number vias. result, each trace will have (near pad) because some signals must routed bottom motherboard. necessary place du
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